| T1593 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.1617349327 |
|
|
Aug 25 04:05:42 PM UTC 24 |
Aug 25 04:20:50 PM UTC 24 |
5722361469 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.2511874611 |
|
|
Aug 25 04:15:34 PM UTC 24 |
Aug 25 04:20:57 PM UTC 24 |
21819102587 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.2035732790 |
|
|
Aug 25 04:14:29 PM UTC 24 |
Aug 25 04:21:02 PM UTC 24 |
6965756579 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.2273130294 |
|
|
Aug 25 04:20:51 PM UTC 24 |
Aug 25 04:21:03 PM UTC 24 |
47414961 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.2526851773 |
|
|
Aug 25 04:20:49 PM UTC 24 |
Aug 25 04:21:06 PM UTC 24 |
225179568 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.3352300989 |
|
|
Aug 25 04:19:05 PM UTC 24 |
Aug 25 04:21:06 PM UTC 24 |
5371688447 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.680864275 |
|
|
Aug 25 04:19:21 PM UTC 24 |
Aug 25 04:21:09 PM UTC 24 |
919343413 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.88348695 |
|
|
Aug 25 04:19:05 PM UTC 24 |
Aug 25 04:21:17 PM UTC 24 |
8828485446 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.4284621333 |
|
|
Aug 25 04:05:46 PM UTC 24 |
Aug 25 04:21:24 PM UTC 24 |
9559765624 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.567585255 |
|
|
Aug 25 04:20:26 PM UTC 24 |
Aug 25 04:21:34 PM UTC 24 |
697633162 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.2257027286 |
|
|
Aug 25 04:21:20 PM UTC 24 |
Aug 25 04:21:37 PM UTC 24 |
282151759 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.2804201687 |
|
|
Aug 25 04:21:26 PM UTC 24 |
Aug 25 04:21:42 PM UTC 24 |
69522668 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.4188878550 |
|
|
Aug 25 04:20:22 PM UTC 24 |
Aug 25 04:21:46 PM UTC 24 |
1372315953 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.1577077542 |
|
|
Aug 25 03:59:43 PM UTC 24 |
Aug 25 04:21:55 PM UTC 24 |
79324687992 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.2136373707 |
|
|
Aug 25 04:14:53 PM UTC 24 |
Aug 25 04:21:56 PM UTC 24 |
3533669040 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.2951533595 |
|
|
Aug 25 04:21:26 PM UTC 24 |
Aug 25 04:22:04 PM UTC 24 |
197508903 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.3466230624 |
|
|
Aug 25 04:21:57 PM UTC 24 |
Aug 25 04:22:10 PM UTC 24 |
49587567 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.3249186283 |
|
|
Aug 25 04:22:00 PM UTC 24 |
Aug 25 04:22:11 PM UTC 24 |
45551922 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.709370260 |
|
|
Aug 25 04:20:59 PM UTC 24 |
Aug 25 04:22:12 PM UTC 24 |
472944626 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.2074973061 |
|
|
Aug 25 04:21:03 PM UTC 24 |
Aug 25 04:22:15 PM UTC 24 |
2697626082 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.3055504599 |
|
|
Aug 25 04:21:13 PM UTC 24 |
Aug 25 04:22:18 PM UTC 24 |
504176322 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.475991545 |
|
|
Aug 25 03:49:49 PM UTC 24 |
Aug 25 04:22:24 PM UTC 24 |
80199056399 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.552173719 |
|
|
Aug 25 04:20:59 PM UTC 24 |
Aug 25 04:22:25 PM UTC 24 |
1395817514 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.668385377 |
|
|
Aug 25 04:21:29 PM UTC 24 |
Aug 25 04:22:27 PM UTC 24 |
36835461 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.595061215 |
|
|
Aug 25 04:22:18 PM UTC 24 |
Aug 25 04:22:38 PM UTC 24 |
102351985 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.1430162260 |
|
|
Aug 25 04:22:18 PM UTC 24 |
Aug 25 04:22:46 PM UTC 24 |
178030754 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.4087584941 |
|
|
Aug 25 04:21:06 PM UTC 24 |
Aug 25 04:22:48 PM UTC 24 |
835386423 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.1000843616 |
|
|
Aug 25 04:10:19 PM UTC 24 |
Aug 25 04:23:06 PM UTC 24 |
12754787530 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.1800462942 |
|
|
Aug 25 04:20:54 PM UTC 24 |
Aug 25 04:23:24 PM UTC 24 |
5929917058 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.4109289370 |
|
|
Aug 25 04:16:51 PM UTC 24 |
Aug 25 04:23:25 PM UTC 24 |
3922796515 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.3420009806 |
|
|
Aug 25 04:20:53 PM UTC 24 |
Aug 25 04:23:38 PM UTC 24 |
9168069079 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.1743266840 |
|
|
Aug 25 04:22:48 PM UTC 24 |
Aug 25 04:23:42 PM UTC 24 |
995303107 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.3950811126 |
|
|
Aug 25 04:22:49 PM UTC 24 |
Aug 25 04:23:42 PM UTC 24 |
1058023823 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.4277962102 |
|
|
Aug 25 04:22:40 PM UTC 24 |
Aug 25 04:23:46 PM UTC 24 |
492950380 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.3537344628 |
|
|
Aug 25 04:23:49 PM UTC 24 |
Aug 25 04:24:00 PM UTC 24 |
43009731 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.2412549518 |
|
|
Aug 25 04:23:49 PM UTC 24 |
Aug 25 04:24:05 PM UTC 24 |
267619768 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.1414712098 |
|
|
Aug 25 04:10:32 PM UTC 24 |
Aug 25 04:24:21 PM UTC 24 |
5754904356 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.1151565847 |
|
|
Aug 25 04:22:09 PM UTC 24 |
Aug 25 04:24:22 PM UTC 24 |
5435335484 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.1222735365 |
|
|
Aug 25 04:22:39 PM UTC 24 |
Aug 25 04:24:23 PM UTC 24 |
2326630339 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.3369549973 |
|
|
Aug 25 04:22:06 PM UTC 24 |
Aug 25 04:24:23 PM UTC 24 |
7916568787 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.1215952702 |
|
|
Aug 25 04:20:22 PM UTC 24 |
Aug 25 04:24:33 PM UTC 24 |
424979250 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.1290481667 |
|
|
Aug 25 04:24:10 PM UTC 24 |
Aug 25 04:24:36 PM UTC 24 |
170475060 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.3045966396 |
|
|
Aug 25 03:59:10 PM UTC 24 |
Aug 25 04:24:36 PM UTC 24 |
12464093040 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.2690909582 |
|
|
Aug 25 04:20:34 PM UTC 24 |
Aug 25 04:24:39 PM UTC 24 |
563156421 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.859738492 |
|
|
Aug 25 04:22:34 PM UTC 24 |
Aug 25 04:24:40 PM UTC 24 |
936546170 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.2697239341 |
|
|
Aug 25 04:18:13 PM UTC 24 |
Aug 25 04:25:08 PM UTC 24 |
6697106205 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.2771677439 |
|
|
Aug 25 04:25:01 PM UTC 24 |
Aug 25 04:25:17 PM UTC 24 |
200001162 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.3586280683 |
|
|
Aug 25 04:24:06 PM UTC 24 |
Aug 25 04:25:19 PM UTC 24 |
2758286989 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.3470869905 |
|
|
Aug 25 04:24:45 PM UTC 24 |
Aug 25 04:25:20 PM UTC 24 |
195966129 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.1937653827 |
|
|
Aug 25 04:24:07 PM UTC 24 |
Aug 25 04:25:23 PM UTC 24 |
516569531 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.2222032987 |
|
|
Aug 25 04:24:58 PM UTC 24 |
Aug 25 04:25:23 PM UTC 24 |
301486776 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.1939175748 |
|
|
Aug 25 04:24:03 PM UTC 24 |
Aug 25 04:25:24 PM UTC 24 |
5101270109 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.4174533688 |
|
|
Aug 25 04:24:47 PM UTC 24 |
Aug 25 04:25:34 PM UTC 24 |
355893793 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.425864511 |
|
|
Aug 25 04:25:43 PM UTC 24 |
Aug 25 04:25:54 PM UTC 24 |
39425580 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.874728922 |
|
|
Aug 25 04:25:45 PM UTC 24 |
Aug 25 04:25:55 PM UTC 24 |
51028163 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.421141846 |
|
|
Aug 25 04:24:48 PM UTC 24 |
Aug 25 04:25:55 PM UTC 24 |
494915105 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.2116005307 |
|
|
Aug 25 03:55:42 PM UTC 24 |
Aug 25 04:25:56 PM UTC 24 |
70788327693 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.527232216 |
|
|
Aug 25 04:21:03 PM UTC 24 |
Aug 25 04:26:04 PM UTC 24 |
20409830291 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.3882457285 |
|
|
Aug 25 04:25:32 PM UTC 24 |
Aug 25 04:26:16 PM UTC 24 |
153275936 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.3329035945 |
|
|
Aug 25 03:48:48 PM UTC 24 |
Aug 25 04:26:18 PM UTC 24 |
15965609921 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.1862368895 |
|
|
Aug 25 04:25:58 PM UTC 24 |
Aug 25 04:26:34 PM UTC 24 |
314130884 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.663388677 |
|
|
Aug 25 04:26:20 PM UTC 24 |
Aug 25 04:26:45 PM UTC 24 |
286221069 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.1104660048 |
|
|
Aug 25 04:26:29 PM UTC 24 |
Aug 25 04:26:46 PM UTC 24 |
277262129 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.2303475371 |
|
|
Aug 25 04:18:07 PM UTC 24 |
Aug 25 04:26:48 PM UTC 24 |
3917096689 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.1648297973 |
|
|
Aug 25 03:46:27 PM UTC 24 |
Aug 25 04:26:56 PM UTC 24 |
15418976959 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.172792018 |
|
|
Aug 25 04:13:34 PM UTC 24 |
Aug 25 04:26:57 PM UTC 24 |
37502166889 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.969683741 |
|
|
Aug 25 04:27:22 PM UTC 24 |
Aug 25 04:27:33 PM UTC 24 |
40582957 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.3370702061 |
|
|
Aug 25 04:18:08 PM UTC 24 |
Aug 25 04:27:35 PM UTC 24 |
2748682046 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.873966596 |
|
|
Aug 25 04:26:44 PM UTC 24 |
Aug 25 04:27:38 PM UTC 24 |
707110215 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.1155117671 |
|
|
Aug 25 04:25:47 PM UTC 24 |
Aug 25 04:27:38 PM UTC 24 |
4397364558 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.3580579077 |
|
|
Aug 25 04:26:58 PM UTC 24 |
Aug 25 04:27:40 PM UTC 24 |
715437547 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.3918866768 |
|
|
Aug 25 04:09:16 PM UTC 24 |
Aug 25 04:27:42 PM UTC 24 |
53689581008 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.2398089403 |
|
|
Aug 25 04:26:41 PM UTC 24 |
Aug 25 04:27:46 PM UTC 24 |
596872352 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.483231352 |
|
|
Aug 25 04:25:48 PM UTC 24 |
Aug 25 04:27:50 PM UTC 24 |
2576327461 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.4290517817 |
|
|
Aug 25 04:25:48 PM UTC 24 |
Aug 25 04:27:52 PM UTC 24 |
7930971110 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.754892853 |
|
|
Aug 25 03:47:44 PM UTC 24 |
Aug 25 04:27:54 PM UTC 24 |
110119651729 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.1652991879 |
|
|
Aug 25 04:21:07 PM UTC 24 |
Aug 25 04:28:07 PM UTC 24 |
21584075290 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.4112330898 |
|
|
Aug 25 04:27:58 PM UTC 24 |
Aug 25 04:28:08 PM UTC 24 |
46446195 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.676956469 |
|
|
Aug 25 04:24:29 PM UTC 24 |
Aug 25 04:28:08 PM UTC 24 |
8592396185 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.3157990247 |
|
|
Aug 25 04:06:31 PM UTC 24 |
Aug 25 04:28:12 PM UTC 24 |
55638533510 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.3720049592 |
|
|
Aug 25 04:27:09 PM UTC 24 |
Aug 25 04:28:13 PM UTC 24 |
490740244 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.2775139149 |
|
|
Aug 25 04:01:08 PM UTC 24 |
Aug 25 04:28:20 PM UTC 24 |
12094392367 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.965971696 |
|
|
Aug 25 04:28:02 PM UTC 24 |
Aug 25 04:28:22 PM UTC 24 |
111875954 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.620404318 |
|
|
Aug 25 04:27:13 PM UTC 24 |
Aug 25 04:28:37 PM UTC 24 |
966248197 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.49396715 |
|
|
Aug 25 04:23:13 PM UTC 24 |
Aug 25 04:28:39 PM UTC 24 |
2474670956 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.2019376926 |
|
|
Aug 25 04:28:31 PM UTC 24 |
Aug 25 04:28:43 PM UTC 24 |
115775022 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.2298004716 |
|
|
Aug 25 04:28:04 PM UTC 24 |
Aug 25 04:28:49 PM UTC 24 |
298628151 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.4017174268 |
|
|
Aug 25 04:23:11 PM UTC 24 |
Aug 25 04:28:51 PM UTC 24 |
6946090725 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.2837836804 |
|
|
Aug 25 04:28:58 PM UTC 24 |
Aug 25 04:29:11 PM UTC 24 |
60954047 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.4208042513 |
|
|
Aug 25 04:29:00 PM UTC 24 |
Aug 25 04:29:12 PM UTC 24 |
42666921 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.1324723234 |
|
|
Aug 25 04:03:59 PM UTC 24 |
Aug 25 04:29:12 PM UTC 24 |
9359026325 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.1857295125 |
|
|
Aug 25 04:04:49 PM UTC 24 |
Aug 25 04:29:15 PM UTC 24 |
63761534773 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.2772879919 |
|
|
Aug 25 04:28:32 PM UTC 24 |
Aug 25 04:29:19 PM UTC 24 |
229684735 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.2382655446 |
|
|
Aug 25 04:12:56 PM UTC 24 |
Aug 25 04:29:29 PM UTC 24 |
15333358285 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.3864501324 |
|
|
Aug 25 04:28:00 PM UTC 24 |
Aug 25 04:29:30 PM UTC 24 |
4952473372 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.511831047 |
|
|
Aug 25 04:28:32 PM UTC 24 |
Aug 25 04:29:32 PM UTC 24 |
1315610858 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.2101558085 |
|
|
Aug 25 04:28:18 PM UTC 24 |
Aug 25 04:29:38 PM UTC 24 |
1620104858 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.4050414473 |
|
|
Aug 25 04:29:13 PM UTC 24 |
Aug 25 04:29:46 PM UTC 24 |
193936975 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.741290602 |
|
|
Aug 25 04:21:47 PM UTC 24 |
Aug 25 04:29:57 PM UTC 24 |
4346400474 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.3987321449 |
|
|
Aug 25 04:26:19 PM UTC 24 |
Aug 25 04:30:12 PM UTC 24 |
14756906939 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.1338647948 |
|
|
Aug 25 04:29:55 PM UTC 24 |
Aug 25 04:30:16 PM UTC 24 |
75589444 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.3722378324 |
|
|
Aug 25 04:22:33 PM UTC 24 |
Aug 25 04:30:20 PM UTC 24 |
18332479993 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.4194153840 |
|
|
Aug 25 04:28:02 PM UTC 24 |
Aug 25 04:30:21 PM UTC 24 |
6023876902 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.1135286500 |
|
|
Aug 25 04:28:15 PM UTC 24 |
Aug 25 04:30:22 PM UTC 24 |
2281649555 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.2212925644 |
|
|
Aug 25 04:29:35 PM UTC 24 |
Aug 25 04:30:22 PM UTC 24 |
389997087 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.2126222230 |
|
|
Aug 25 04:21:41 PM UTC 24 |
Aug 25 04:30:23 PM UTC 24 |
6089213903 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.1824773539 |
|
|
Aug 25 04:11:26 PM UTC 24 |
Aug 25 04:30:24 PM UTC 24 |
74277782397 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.4124905947 |
|
|
Aug 25 04:29:15 PM UTC 24 |
Aug 25 04:30:27 PM UTC 24 |
453478681 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.1308785419 |
|
|
Aug 25 04:29:54 PM UTC 24 |
Aug 25 04:30:29 PM UTC 24 |
230206603 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.230915550 |
|
|
Aug 25 04:29:43 PM UTC 24 |
Aug 25 04:30:30 PM UTC 24 |
361837314 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.2978192453 |
|
|
Aug 25 04:28:37 PM UTC 24 |
Aug 25 04:30:33 PM UTC 24 |
178460789 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.2737668423 |
|
|
Aug 25 04:23:02 PM UTC 24 |
Aug 25 04:30:36 PM UTC 24 |
4402625080 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.3951385308 |
|
|
Aug 25 04:29:56 PM UTC 24 |
Aug 25 04:30:39 PM UTC 24 |
657654842 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.1206994583 |
|
|
Aug 25 04:22:35 PM UTC 24 |
Aug 25 04:30:41 PM UTC 24 |
18084791281 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.2115986146 |
|
|
Aug 25 04:29:07 PM UTC 24 |
Aug 25 04:30:43 PM UTC 24 |
4104785732 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.552349406 |
|
|
Aug 25 04:18:45 PM UTC 24 |
Aug 25 04:30:45 PM UTC 24 |
4391946500 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.3272463300 |
|
|
Aug 25 04:30:39 PM UTC 24 |
Aug 25 04:30:52 PM UTC 24 |
166061944 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.508379563 |
|
|
Aug 25 04:04:41 PM UTC 24 |
Aug 25 04:30:55 PM UTC 24 |
93773649265 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.807399007 |
|
|
Aug 25 04:30:45 PM UTC 24 |
Aug 25 04:30:57 PM UTC 24 |
52676654 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.1894701542 |
|
|
Aug 25 04:06:22 PM UTC 24 |
Aug 25 04:30:57 PM UTC 24 |
87439922597 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.75563337 |
|
|
Aug 25 04:30:46 PM UTC 24 |
Aug 25 04:31:02 PM UTC 24 |
261463010 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.2951265153 |
|
|
Aug 25 04:20:36 PM UTC 24 |
Aug 25 04:31:10 PM UTC 24 |
4491991472 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.2771214024 |
|
|
Aug 25 04:25:03 PM UTC 24 |
Aug 25 04:31:14 PM UTC 24 |
3142752949 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.3486130015 |
|
|
Aug 25 04:25:01 PM UTC 24 |
Aug 25 04:31:15 PM UTC 24 |
3409718637 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.3376045810 |
|
|
Aug 25 04:30:54 PM UTC 24 |
Aug 25 04:31:18 PM UTC 24 |
111004590 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.1149876751 |
|
|
Aug 25 04:02:19 PM UTC 24 |
Aug 25 04:31:20 PM UTC 24 |
99625272126 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.752552349 |
|
|
Aug 25 04:31:00 PM UTC 24 |
Aug 25 04:31:28 PM UTC 24 |
402978618 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.1690213088 |
|
|
Aug 25 04:31:03 PM UTC 24 |
Aug 25 04:31:30 PM UTC 24 |
128562532 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.2315713022 |
|
|
Aug 25 04:29:03 PM UTC 24 |
Aug 25 04:31:31 PM UTC 24 |
9669192403 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.1510580465 |
|
|
Aug 25 04:31:21 PM UTC 24 |
Aug 25 04:31:32 PM UTC 24 |
50742248 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.2707162782 |
|
|
Aug 25 04:30:57 PM UTC 24 |
Aug 25 04:31:33 PM UTC 24 |
656469880 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.737817141 |
|
|
Aug 25 04:31:21 PM UTC 24 |
Aug 25 04:31:33 PM UTC 24 |
44816580 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.2945612145 |
|
|
Aug 25 04:28:36 PM UTC 24 |
Aug 25 04:31:51 PM UTC 24 |
3639305681 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.3330289558 |
|
|
Aug 25 04:30:47 PM UTC 24 |
Aug 25 04:31:55 PM UTC 24 |
478870633 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.3778045118 |
|
|
Aug 25 04:31:05 PM UTC 24 |
Aug 25 04:32:08 PM UTC 24 |
1001509683 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.4255788954 |
|
|
Aug 25 04:31:19 PM UTC 24 |
Aug 25 04:32:17 PM UTC 24 |
888024694 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.4105859442 |
|
|
Aug 25 04:21:28 PM UTC 24 |
Aug 25 04:32:17 PM UTC 24 |
4435182281 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.4263130017 |
|
|
Aug 25 04:08:07 PM UTC 24 |
Aug 25 04:32:22 PM UTC 24 |
7965033670 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.2176624223 |
|
|
Aug 25 04:31:56 PM UTC 24 |
Aug 25 04:32:29 PM UTC 24 |
146153696 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.1978843971 |
|
|
Aug 25 04:31:08 PM UTC 24 |
Aug 25 04:32:31 PM UTC 24 |
681275691 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.3770596406 |
|
|
Aug 25 04:43:12 PM UTC 24 |
Aug 25 04:44:23 PM UTC 24 |
1497415582 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.3609058196 |
|
|
Aug 25 04:31:57 PM UTC 24 |
Aug 25 04:32:32 PM UTC 24 |
496110284 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.1669579837 |
|
|
Aug 25 04:28:16 PM UTC 24 |
Aug 25 04:32:38 PM UTC 24 |
10817149811 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.4053974654 |
|
|
Aug 25 04:31:39 PM UTC 24 |
Aug 25 04:32:42 PM UTC 24 |
559614015 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.430280967 |
|
|
Aug 25 04:30:45 PM UTC 24 |
Aug 25 04:32:47 PM UTC 24 |
5042497868 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.1425872718 |
|
|
Aug 25 04:31:26 PM UTC 24 |
Aug 25 04:32:50 PM UTC 24 |
5123622629 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.2435848629 |
|
|
Aug 25 04:30:46 PM UTC 24 |
Aug 25 04:32:52 PM UTC 24 |
7359195632 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.1719307566 |
|
|
Aug 25 04:21:33 PM UTC 24 |
Aug 25 04:32:52 PM UTC 24 |
12986361562 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.3139365211 |
|
|
Aug 25 04:32:43 PM UTC 24 |
Aug 25 04:32:55 PM UTC 24 |
161307788 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.2788485352 |
|
|
Aug 25 04:32:47 PM UTC 24 |
Aug 25 04:32:57 PM UTC 24 |
44800357 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.2199525429 |
|
|
Aug 25 04:31:40 PM UTC 24 |
Aug 25 04:33:03 PM UTC 24 |
1593736336 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.1236786939 |
|
|
Aug 25 04:31:56 PM UTC 24 |
Aug 25 04:33:03 PM UTC 24 |
1174351987 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.3909473018 |
|
|
Aug 25 04:17:42 PM UTC 24 |
Aug 25 04:33:14 PM UTC 24 |
38720095159 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.4198904628 |
|
|
Aug 25 04:33:16 PM UTC 24 |
Aug 25 04:33:27 PM UTC 24 |
14552944 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.1452629846 |
|
|
Aug 25 04:28:45 PM UTC 24 |
Aug 25 04:33:32 PM UTC 24 |
689397458 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.1151815045 |
|
|
Aug 25 04:33:02 PM UTC 24 |
Aug 25 04:33:33 PM UTC 24 |
201182136 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.1930692544 |
|
|
Aug 25 04:32:57 PM UTC 24 |
Aug 25 04:33:38 PM UTC 24 |
277217787 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.18882069 |
|
|
Aug 25 03:39:51 PM UTC 24 |
Aug 25 04:33:39 PM UTC 24 |
142410111115 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.2374617739 |
|
|
Aug 25 04:31:32 PM UTC 24 |
Aug 25 04:33:42 PM UTC 24 |
5916705292 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.2607148773 |
|
|
Aug 25 04:33:15 PM UTC 24 |
Aug 25 04:33:51 PM UTC 24 |
261381408 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.309188527 |
|
|
Aug 25 04:31:56 PM UTC 24 |
Aug 25 04:33:54 PM UTC 24 |
2575750044 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.265030998 |
|
|
Aug 25 04:31:53 PM UTC 24 |
Aug 25 04:33:54 PM UTC 24 |
933533931 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.417392497 |
|
|
Aug 25 04:28:45 PM UTC 24 |
Aug 25 04:34:07 PM UTC 24 |
3171903062 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.571372363 |
|
|
Aug 25 04:33:56 PM UTC 24 |
Aug 25 04:34:07 PM UTC 24 |
44909697 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.1213263256 |
|
|
Aug 25 04:32:40 PM UTC 24 |
Aug 25 04:34:09 PM UTC 24 |
149511687 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.212475040 |
|
|
Aug 25 04:34:02 PM UTC 24 |
Aug 25 04:34:12 PM UTC 24 |
48294880 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.352675401 |
|
|
Aug 25 04:33:21 PM UTC 24 |
Aug 25 04:34:22 PM UTC 24 |
904106600 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.2008204230 |
|
|
Aug 25 04:02:36 PM UTC 24 |
Aug 25 04:34:23 PM UTC 24 |
88255292739 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.2049949889 |
|
|
Aug 25 04:22:54 PM UTC 24 |
Aug 25 04:34:28 PM UTC 24 |
5160459912 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.153290291 |
|
|
Aug 25 04:33:20 PM UTC 24 |
Aug 25 04:34:35 PM UTC 24 |
604294224 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.1358200437 |
|
|
Aug 25 03:38:33 PM UTC 24 |
Aug 25 04:34:38 PM UTC 24 |
17462133652 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.2309264407 |
|
|
Aug 25 04:27:20 PM UTC 24 |
Aug 25 04:34:38 PM UTC 24 |
3886697543 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.853535195 |
|
|
Aug 25 03:53:47 PM UTC 24 |
Aug 25 04:34:38 PM UTC 24 |
116304788157 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.1409581688 |
|
|
Aug 25 04:29:33 PM UTC 24 |
Aug 25 04:34:41 PM UTC 24 |
12826932349 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.2534311682 |
|
|
Aug 25 04:33:28 PM UTC 24 |
Aug 25 04:34:55 PM UTC 24 |
530294805 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.3338571755 |
|
|
Aug 25 04:25:42 PM UTC 24 |
Aug 25 04:34:56 PM UTC 24 |
4393760920 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.1380334573 |
|
|
Aug 25 04:34:47 PM UTC 24 |
Aug 25 04:34:56 PM UTC 24 |
69433752 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.2374894141 |
|
|
Aug 25 04:33:28 PM UTC 24 |
Aug 25 04:34:57 PM UTC 24 |
1230560761 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.259358748 |
|
|
Aug 25 04:34:36 PM UTC 24 |
Aug 25 04:35:01 PM UTC 24 |
170127645 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.99094355 |
|
|
Aug 25 04:34:17 PM UTC 24 |
Aug 25 04:35:03 PM UTC 24 |
352840755 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.3974346219 |
|
|
Aug 25 04:32:56 PM UTC 24 |
Aug 25 04:35:05 PM UTC 24 |
5195513281 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.261640571 |
|
|
Aug 25 04:32:54 PM UTC 24 |
Aug 25 04:35:17 PM UTC 24 |
9151638988 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.1653144387 |
|
|
Aug 25 04:35:05 PM UTC 24 |
Aug 25 04:35:19 PM UTC 24 |
157082408 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.3270339518 |
|
|
Aug 25 04:34:52 PM UTC 24 |
Aug 25 04:35:30 PM UTC 24 |
217142981 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.956458819 |
|
|
Aug 25 04:35:19 PM UTC 24 |
Aug 25 04:35:30 PM UTC 24 |
40925121 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.2753239841 |
|
|
Aug 25 04:35:20 PM UTC 24 |
Aug 25 04:35:35 PM UTC 24 |
157278638 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.1952017443 |
|
|
Aug 25 04:34:16 PM UTC 24 |
Aug 25 04:35:36 PM UTC 24 |
568191785 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.2244050579 |
|
|
Aug 25 04:35:41 PM UTC 24 |
Aug 25 04:36:03 PM UTC 24 |
156351915 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.2059715405 |
|
|
Aug 25 03:56:33 PM UTC 24 |
Aug 25 04:36:07 PM UTC 24 |
14540788934 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.2449479394 |
|
|
Aug 25 04:35:53 PM UTC 24 |
Aug 25 04:36:23 PM UTC 24 |
489897114 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.3056871255 |
|
|
Aug 25 04:35:53 PM UTC 24 |
Aug 25 04:36:24 PM UTC 24 |
224658354 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.792420588 |
|
|
Aug 25 04:35:16 PM UTC 24 |
Aug 25 04:36:25 PM UTC 24 |
3267702015 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.2127680760 |
|
|
Aug 25 04:34:32 PM UTC 24 |
Aug 25 04:36:26 PM UTC 24 |
2314034982 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.4290351858 |
|
|
Aug 25 04:34:31 PM UTC 24 |
Aug 25 04:36:30 PM UTC 24 |
4635586450 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3120923966 |
|
|
Aug 25 04:36:00 PM UTC 24 |
Aug 25 04:36:33 PM UTC 24 |
162029969 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.4249238542 |
|
|
Aug 25 04:34:06 PM UTC 24 |
Aug 25 04:36:38 PM UTC 24 |
5978507806 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.3632815707 |
|
|
Aug 25 04:35:26 PM UTC 24 |
Aug 25 04:36:39 PM UTC 24 |
543902817 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.3418151074 |
|
|
Aug 25 04:34:46 PM UTC 24 |
Aug 25 04:36:39 PM UTC 24 |
1951814839 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.415346569 |
|
|
Aug 25 04:33:38 PM UTC 24 |
Aug 25 04:36:46 PM UTC 24 |
310649524 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.1224836189 |
|
|
Aug 25 04:30:10 PM UTC 24 |
Aug 25 04:36:46 PM UTC 24 |
2860007577 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.237323090 |
|
|
Aug 25 04:24:25 PM UTC 24 |
Aug 25 04:36:50 PM UTC 24 |
44949957349 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.3841290061 |
|
|
Aug 25 04:19:23 PM UTC 24 |
Aug 25 04:36:55 PM UTC 24 |
46597018366 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.1055946092 |
|
|
Aug 25 04:23:32 PM UTC 24 |
Aug 25 04:36:57 PM UTC 24 |
4678057175 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.1223253221 |
|
|
Aug 25 04:36:50 PM UTC 24 |
Aug 25 04:37:00 PM UTC 24 |
47691880 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.2564845921 |
|
|
Aug 25 04:36:50 PM UTC 24 |
Aug 25 04:37:05 PM UTC 24 |
221771165 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.3563521192 |
|
|
Aug 25 04:34:02 PM UTC 24 |
Aug 25 04:37:05 PM UTC 24 |
10008165651 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.730384906 |
|
|
Aug 25 04:35:57 PM UTC 24 |
Aug 25 04:37:11 PM UTC 24 |
1293486207 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.4234483551 |
|
|
Aug 25 04:30:01 PM UTC 24 |
Aug 25 04:37:18 PM UTC 24 |
10078957745 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.2593635353 |
|
|
Aug 25 04:37:02 PM UTC 24 |
Aug 25 04:37:26 PM UTC 24 |
275810967 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.2896681175 |
|
|
Aug 25 04:37:17 PM UTC 24 |
Aug 25 04:37:29 PM UTC 24 |
70379492 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.516307540 |
|
|
Aug 25 04:37:11 PM UTC 24 |
Aug 25 04:37:33 PM UTC 24 |
107609958 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.1469318405 |
|
|
Aug 25 04:32:32 PM UTC 24 |
Aug 25 04:37:43 PM UTC 24 |
2498654797 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.3259381517 |
|
|
Aug 25 04:37:21 PM UTC 24 |
Aug 25 04:37:57 PM UTC 24 |
255555225 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.1097413857 |
|
|
Aug 25 04:31:15 PM UTC 24 |
Aug 25 04:38:04 PM UTC 24 |
9240105757 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.1527045986 |
|
|
Aug 25 04:37:56 PM UTC 24 |
Aug 25 04:38:06 PM UTC 24 |
45088373 ps |
| T1763 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.120533955 |
|
|
Aug 25 03:42:43 PM UTC 24 |
Aug 25 04:38:08 PM UTC 24 |
15546970214 ps |
| T1764 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.1351510550 |
|
|
Aug 25 04:37:53 PM UTC 24 |
Aug 25 04:38:08 PM UTC 24 |
238655710 ps |
| T1765 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.2883605629 |
|
|
Aug 25 04:35:19 PM UTC 24 |
Aug 25 04:38:13 PM UTC 24 |
9572962322 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.3501965410 |
|
|
Aug 25 04:15:35 PM UTC 24 |
Aug 25 04:38:18 PM UTC 24 |
66750135448 ps |
| T1766 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.3097086150 |
|
|
Aug 25 04:37:03 PM UTC 24 |
Aug 25 04:38:22 PM UTC 24 |
575119365 ps |
| T1767 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.2858320796 |
|
|
Aug 25 04:37:27 PM UTC 24 |
Aug 25 04:38:27 PM UTC 24 |
1106278219 ps |
| T1768 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.152446244 |
|
|
Aug 25 04:36:31 PM UTC 24 |
Aug 25 04:38:30 PM UTC 24 |
147386603 ps |
| T1769 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.560843538 |
|
|
Aug 25 04:36:57 PM UTC 24 |
Aug 25 04:38:49 PM UTC 24 |
4199678612 ps |
| T1770 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.1689112568 |
|
|
Aug 25 04:37:24 PM UTC 24 |
Aug 25 04:38:56 PM UTC 24 |
1525689522 ps |
| T1771 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.1125052563 |
|
|
Aug 25 04:38:49 PM UTC 24 |
Aug 25 04:39:00 PM UTC 24 |
42719496 ps |
| T1772 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.684289038 |
|
|
Aug 25 04:38:30 PM UTC 24 |
Aug 25 04:39:04 PM UTC 24 |
215356912 ps |
| T1773 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.191372256 |
|
|
Aug 25 04:38:46 PM UTC 24 |
Aug 25 04:39:09 PM UTC 24 |
520862685 ps |
| T1774 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.2998939893 |
|
|
Aug 25 04:36:28 PM UTC 24 |
Aug 25 04:39:15 PM UTC 24 |
3774758937 ps |
| T1775 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.199431863 |
|
|
Aug 25 04:33:51 PM UTC 24 |
Aug 25 04:39:17 PM UTC 24 |
2674738415 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.1863049692 |
|
|
Aug 25 04:04:57 PM UTC 24 |
Aug 25 04:39:20 PM UTC 24 |
78640539449 ps |
| T1776 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.313242117 |
|
|
Aug 25 04:31:09 PM UTC 24 |
Aug 25 04:39:24 PM UTC 24 |
632272942 ps |
| T1777 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.1106479804 |
|
|
Aug 25 04:38:29 PM UTC 24 |
Aug 25 04:39:26 PM UTC 24 |
521866954 ps |
| T1778 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.4243269967 |
|
|
Aug 25 04:31:43 PM UTC 24 |
Aug 25 04:39:40 PM UTC 24 |
30848353130 ps |
| T1779 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.69876392 |
|
|
Aug 25 04:39:12 PM UTC 24 |
Aug 25 04:39:43 PM UTC 24 |
211446720 ps |
| T1780 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.1080135338 |
|
|
Aug 25 04:39:38 PM UTC 24 |
Aug 25 04:39:50 PM UTC 24 |
57128139 ps |
| T1781 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.3863790680 |
|
|
Aug 25 04:39:41 PM UTC 24 |
Aug 25 04:39:53 PM UTC 24 |
54419079 ps |
| T1782 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.1129540354 |
|
|
Aug 25 04:36:55 PM UTC 24 |
Aug 25 04:39:53 PM UTC 24 |
10193600603 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.3161181898 |
|
|
Aug 25 04:25:03 PM UTC 24 |
Aug 25 04:40:10 PM UTC 24 |
11348611984 ps |
| T1783 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.4073773896 |
|
|
Aug 25 04:38:51 PM UTC 24 |
Aug 25 04:40:15 PM UTC 24 |
1233210659 ps |
| T1784 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.1052660989 |
|
|
Aug 25 04:35:01 PM UTC 24 |
Aug 25 04:40:17 PM UTC 24 |
7416808597 ps |
| T1785 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.3450911756 |
|
|
Aug 25 04:38:06 PM UTC 24 |
Aug 25 04:40:19 PM UTC 24 |
7965153928 ps |
| T1786 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.638870417 |
|
|
Aug 25 04:38:37 PM UTC 24 |
Aug 25 04:40:19 PM UTC 24 |
1642711451 ps |
| T1787 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.3169199778 |
|
|
Aug 25 04:31:44 PM UTC 24 |
Aug 25 04:40:23 PM UTC 24 |
20732613434 ps |
| T1788 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.3571853617 |
|
|
Aug 25 04:38:21 PM UTC 24 |
Aug 25 04:40:23 PM UTC 24 |
4988363687 ps |
| T1789 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.1712386764 |
|
|
Aug 25 04:40:04 PM UTC 24 |
Aug 25 04:40:24 PM UTC 24 |
131766052 ps |
| T1790 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.535446577 |
|
|
Aug 25 04:39:49 PM UTC 24 |
Aug 25 04:40:35 PM UTC 24 |
784439222 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.1978401844 |
|
|
Aug 25 04:15:41 PM UTC 24 |
Aug 25 04:40:48 PM UTC 24 |
66789862604 ps |
| T1791 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.3426042383 |
|
|
Aug 25 04:40:35 PM UTC 24 |
Aug 25 04:40:53 PM UTC 24 |
100656537 ps |
| T1792 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.789301490 |
|
|
Aug 25 04:40:42 PM UTC 24 |
Aug 25 04:40:59 PM UTC 24 |
63139857 ps |
| T1793 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.1295943829 |
|
|
Aug 25 04:39:20 PM UTC 24 |
Aug 25 04:41:01 PM UTC 24 |
2360548989 ps |