| T178 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1077406498 |
|
|
Sep 09 11:28:47 PM UTC 24 |
Sep 10 12:45:46 AM UTC 24 |
25332394405 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sival_flash_info_access.3249642649 |
|
|
Sep 10 12:41:09 AM UTC 24 |
Sep 10 12:46:53 AM UTC 24 |
3372272640 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.1000175868 |
|
|
Sep 10 12:42:52 AM UTC 24 |
Sep 10 12:46:58 AM UTC 24 |
2989515700 ps |
| T20 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.4167627519 |
|
|
Sep 10 12:42:35 AM UTC 24 |
Sep 10 12:47:15 AM UTC 24 |
3587456756 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1180334306 |
|
|
Sep 09 11:42:07 PM UTC 24 |
Sep 10 12:48:11 AM UTC 24 |
14992290390 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2173003534 |
|
|
Sep 09 11:47:53 PM UTC 24 |
Sep 10 12:49:39 AM UTC 24 |
15030140356 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.661550414 |
|
|
Sep 09 11:38:46 PM UTC 24 |
Sep 10 12:49:41 AM UTC 24 |
15675014596 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3131881964 |
|
|
Sep 10 12:41:05 AM UTC 24 |
Sep 10 12:49:47 AM UTC 24 |
4903093430 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1350303989 |
|
|
Sep 09 11:37:19 PM UTC 24 |
Sep 10 12:50:00 AM UTC 24 |
15689539312 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pattgen_ios.1879917886 |
|
|
Sep 10 12:46:04 AM UTC 24 |
Sep 10 12:50:16 AM UTC 24 |
2477449180 ps |
| T27 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.1879937505 |
|
|
Sep 10 12:42:36 AM UTC 24 |
Sep 10 12:50:44 AM UTC 24 |
5745829106 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.1800739254 |
|
|
Sep 10 12:41:11 AM UTC 24 |
Sep 10 12:50:48 AM UTC 24 |
3914159090 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1045357801 |
|
|
Sep 09 11:38:00 PM UTC 24 |
Sep 10 12:50:58 AM UTC 24 |
15271624304 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.146191445 |
|
|
Sep 09 11:43:00 PM UTC 24 |
Sep 10 12:51:20 AM UTC 24 |
13872126232 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2532636471 |
|
|
Sep 09 11:45:12 PM UTC 24 |
Sep 10 12:51:22 AM UTC 24 |
14624621455 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.2021051469 |
|
|
Sep 10 12:41:43 AM UTC 24 |
Sep 10 12:52:17 AM UTC 24 |
5616961408 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3437853688 |
|
|
Sep 09 11:43:25 PM UTC 24 |
Sep 10 12:52:20 AM UTC 24 |
14960109080 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.155163747 |
|
|
Sep 09 11:42:42 PM UTC 24 |
Sep 10 12:52:46 AM UTC 24 |
14982703365 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_rma.770087660 |
|
|
Sep 10 12:03:51 AM UTC 24 |
Sep 10 12:54:12 AM UTC 24 |
32408753973 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.4251209721 |
|
|
Sep 09 11:38:59 PM UTC 24 |
Sep 10 12:54:35 AM UTC 24 |
15390409416 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx2.1917098043 |
|
|
Sep 10 12:46:08 AM UTC 24 |
Sep 10 12:54:41 AM UTC 24 |
4362937646 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2070364975 |
|
|
Sep 09 11:46:41 PM UTC 24 |
Sep 10 12:54:48 AM UTC 24 |
13856407422 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx3.900308331 |
|
|
Sep 10 12:46:02 AM UTC 24 |
Sep 10 12:54:59 AM UTC 24 |
3793416696 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.2691181718 |
|
|
Sep 10 12:51:00 AM UTC 24 |
Sep 10 12:55:37 AM UTC 24 |
2197568320 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx.1177297320 |
|
|
Sep 10 12:46:04 AM UTC 24 |
Sep 10 12:55:40 AM UTC 24 |
3721973388 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.1149998089 |
|
|
Sep 10 12:51:00 AM UTC 24 |
Sep 10 12:55:45 AM UTC 24 |
3478400229 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_tpm.322734757 |
|
|
Sep 10 12:51:08 AM UTC 24 |
Sep 10 12:56:44 AM UTC 24 |
3492150895 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx1.2738824151 |
|
|
Sep 10 12:46:09 AM UTC 24 |
Sep 10 12:57:23 AM UTC 24 |
4746259178 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.2543863479 |
|
|
Sep 10 12:48:54 AM UTC 24 |
Sep 10 12:58:07 AM UTC 24 |
3647282060 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.4172530925 |
|
|
Sep 09 11:40:40 PM UTC 24 |
Sep 10 12:59:10 AM UTC 24 |
15305178696 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod_end.3125062173 |
|
|
Sep 09 11:50:04 PM UTC 24 |
Sep 10 12:59:14 AM UTC 24 |
16279800030 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1859542279 |
|
|
Sep 10 12:53:05 AM UTC 24 |
Sep 10 12:59:15 AM UTC 24 |
3156268900 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through_collision.826579495 |
|
|
Sep 10 12:51:04 AM UTC 24 |
Sep 10 12:59:25 AM UTC 24 |
4225285989 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3532559014 |
|
|
Sep 09 11:40:08 PM UTC 24 |
Sep 10 12:59:50 AM UTC 24 |
15683793372 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2677744647 |
|
|
Sep 10 12:56:40 AM UTC 24 |
Sep 10 12:59:51 AM UTC 24 |
3157807738 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.4169138073 |
|
|
Sep 10 12:47:58 AM UTC 24 |
Sep 10 12:59:56 AM UTC 24 |
4074314950 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.1841301893 |
|
|
Sep 10 12:47:56 AM UTC 24 |
Sep 10 12:59:56 AM UTC 24 |
4862203448 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.2384584622 |
|
|
Sep 10 12:55:53 AM UTC 24 |
Sep 10 01:00:21 AM UTC 24 |
2754970680 ps |
| T42 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.234587404 |
|
|
Sep 10 12:52:17 AM UTC 24 |
Sep 10 01:00:29 AM UTC 24 |
4248710822 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_rma.1238754515 |
|
|
Sep 09 11:52:23 PM UTC 24 |
Sep 10 01:00:50 AM UTC 24 |
15525309273 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.266135223 |
|
|
Sep 10 12:55:52 AM UTC 24 |
Sep 10 01:00:52 AM UTC 24 |
3192064520 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2233501850 |
|
|
Sep 10 12:52:20 AM UTC 24 |
Sep 10 01:01:07 AM UTC 24 |
5751287592 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.633309501 |
|
|
Sep 10 12:48:01 AM UTC 24 |
Sep 10 01:01:29 AM UTC 24 |
4236809876 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.3539237291 |
|
|
Sep 10 12:57:24 AM UTC 24 |
Sep 10 01:01:44 AM UTC 24 |
3348507703 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.3757069039 |
|
|
Sep 09 11:59:32 PM UTC 24 |
Sep 10 01:02:17 AM UTC 24 |
41109190043 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.524141825 |
|
|
Sep 10 12:52:25 AM UTC 24 |
Sep 10 01:02:29 AM UTC 24 |
3672749072 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod.723132028 |
|
|
Sep 09 11:48:40 PM UTC 24 |
Sep 10 01:02:45 AM UTC 24 |
15304150705 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1396053489 |
|
|
Sep 10 12:46:27 AM UTC 24 |
Sep 10 01:02:49 AM UTC 24 |
8929543279 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1052432540 |
|
|
Sep 10 12:52:16 AM UTC 24 |
Sep 10 01:02:56 AM UTC 24 |
4434594404 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.118798633 |
|
|
Sep 10 12:58:48 AM UTC 24 |
Sep 10 01:03:31 AM UTC 24 |
2988120361 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.78862120 |
|
|
Sep 10 12:51:05 AM UTC 24 |
Sep 10 01:03:40 AM UTC 24 |
6604522189 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1931823746 |
|
|
Sep 10 01:02:35 AM UTC 24 |
Sep 10 01:04:23 AM UTC 24 |
2359987471 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1133078292 |
|
|
Sep 10 01:02:42 AM UTC 24 |
Sep 10 01:04:59 AM UTC 24 |
1711172418 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1237402567 |
|
|
Sep 10 12:55:52 AM UTC 24 |
Sep 10 01:05:06 AM UTC 24 |
4544604420 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_dev.3003413878 |
|
|
Sep 09 11:48:35 PM UTC 24 |
Sep 10 01:05:13 AM UTC 24 |
15108596811 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.4272325042 |
|
|
Sep 10 12:58:04 AM UTC 24 |
Sep 10 01:05:37 AM UTC 24 |
4932433530 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.3895475843 |
|
|
Sep 10 01:02:54 AM UTC 24 |
Sep 10 01:06:23 AM UTC 24 |
2992463750 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.3903023544 |
|
|
Sep 10 12:45:50 AM UTC 24 |
Sep 10 01:06:25 AM UTC 24 |
8361041684 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.621439884 |
|
|
Sep 10 01:02:44 AM UTC 24 |
Sep 10 01:07:31 AM UTC 24 |
3952120106 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.160534255 |
|
|
Sep 10 01:02:57 AM UTC 24 |
Sep 10 01:08:30 AM UTC 24 |
4661972386 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.56491178 |
|
|
Sep 10 12:52:25 AM UTC 24 |
Sep 10 01:09:05 AM UTC 24 |
5365308750 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pincfg.4137639657 |
|
|
Sep 09 10:43:10 PM UTC 24 |
Sep 10 01:09:26 AM UTC 24 |
31879382814 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2046298036 |
|
|
Sep 10 01:04:14 AM UTC 24 |
Sep 10 01:10:35 AM UTC 24 |
4979331460 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1874028606 |
|
|
Sep 10 01:05:04 AM UTC 24 |
Sep 10 01:10:48 AM UTC 24 |
3504754600 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2661235928 |
|
|
Sep 10 12:54:54 AM UTC 24 |
Sep 10 01:10:55 AM UTC 24 |
5149703229 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1276401388 |
|
|
Sep 10 12:52:26 AM UTC 24 |
Sep 10 01:11:04 AM UTC 24 |
5742579988 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.438183545 |
|
|
Sep 10 01:06:02 AM UTC 24 |
Sep 10 01:11:05 AM UTC 24 |
2973996136 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1681642085 |
|
|
Sep 10 01:02:50 AM UTC 24 |
Sep 10 01:11:17 AM UTC 24 |
8996683640 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.2110823483 |
|
|
Sep 10 12:46:24 AM UTC 24 |
Sep 10 01:11:19 AM UTC 24 |
8720961000 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.440364074 |
|
|
Sep 10 01:06:18 AM UTC 24 |
Sep 10 01:11:28 AM UTC 24 |
3069638481 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.999397669 |
|
|
Sep 10 01:04:09 AM UTC 24 |
Sep 10 01:11:38 AM UTC 24 |
6635785385 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_dev.1051670404 |
|
|
Sep 10 12:02:41 AM UTC 24 |
Sep 10 01:12:28 AM UTC 24 |
34985505311 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.287208364 |
|
|
Sep 10 12:46:05 AM UTC 24 |
Sep 10 01:12:39 AM UTC 24 |
9440202251 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2878592840 |
|
|
Sep 09 11:42:28 PM UTC 24 |
Sep 10 01:12:53 AM UTC 24 |
17687837416 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_outputs.2622882200 |
|
|
Sep 10 01:09:12 AM UTC 24 |
Sep 10 01:14:25 AM UTC 24 |
3149994560 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_smoketest.3633566346 |
|
|
Sep 10 12:35:39 AM UTC 24 |
Sep 10 01:14:39 AM UTC 24 |
9954969830 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.1207471922 |
|
|
Sep 10 01:02:45 AM UTC 24 |
Sep 10 01:15:12 AM UTC 24 |
5746880490 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1435489208 |
|
|
Sep 09 11:40:21 PM UTC 24 |
Sep 10 01:15:24 AM UTC 24 |
18252237352 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3164334275 |
|
|
Sep 10 01:07:16 AM UTC 24 |
Sep 10 01:15:31 AM UTC 24 |
6140519984 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1878525408 |
|
|
Sep 10 01:05:59 AM UTC 24 |
Sep 10 01:16:07 AM UTC 24 |
3942050690 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3478013499 |
|
|
Sep 10 01:03:58 AM UTC 24 |
Sep 10 01:16:11 AM UTC 24 |
7843751500 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1355456166 |
|
|
Sep 10 12:56:43 AM UTC 24 |
Sep 10 01:16:25 AM UTC 24 |
9010265132 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.426490185 |
|
|
Sep 10 12:56:40 AM UTC 24 |
Sep 10 01:16:30 AM UTC 24 |
9319529592 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.41502625 |
|
|
Sep 10 12:08:30 AM UTC 24 |
Sep 10 01:17:20 AM UTC 24 |
14630110386 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.43859533 |
|
|
Sep 10 01:13:30 AM UTC 24 |
Sep 10 01:17:40 AM UTC 24 |
2928462470 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.1200048084 |
|
|
Sep 10 01:10:12 AM UTC 24 |
Sep 10 01:17:45 AM UTC 24 |
4310319378 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.3479363210 |
|
|
Sep 10 01:13:35 AM UTC 24 |
Sep 10 01:18:13 AM UTC 24 |
2369957430 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1005022944 |
|
|
Sep 10 01:10:13 AM UTC 24 |
Sep 10 01:18:21 AM UTC 24 |
6821516608 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.1916336613 |
|
|
Sep 10 01:15:07 AM UTC 24 |
Sep 10 01:18:48 AM UTC 24 |
2688017036 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2388042042 |
|
|
Sep 10 01:07:16 AM UTC 24 |
Sep 10 01:18:57 AM UTC 24 |
5445194734 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2683167566 |
|
|
Sep 10 12:05:30 AM UTC 24 |
Sep 10 01:19:08 AM UTC 24 |
15816474900 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.3959728170 |
|
|
Sep 10 12:04:38 AM UTC 24 |
Sep 10 01:19:12 AM UTC 24 |
17505699438 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1280609023 |
|
|
Sep 10 12:55:56 AM UTC 24 |
Sep 10 01:19:17 AM UTC 24 |
9949671976 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.340470800 |
|
|
Sep 10 01:23:05 AM UTC 24 |
Sep 10 01:28:07 AM UTC 24 |
2616946780 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.610444415 |
|
|
Sep 10 12:04:49 AM UTC 24 |
Sep 10 01:19:40 AM UTC 24 |
15163270070 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.984483250 |
|
|
Sep 10 01:02:19 AM UTC 24 |
Sep 10 01:19:46 AM UTC 24 |
10448446182 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1335605169 |
|
|
Sep 10 01:12:46 AM UTC 24 |
Sep 10 01:20:49 AM UTC 24 |
4012800008 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.1686067296 |
|
|
Sep 10 01:15:22 AM UTC 24 |
Sep 10 01:21:22 AM UTC 24 |
3708720545 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1961758583 |
|
|
Sep 10 01:12:08 AM UTC 24 |
Sep 10 01:21:23 AM UTC 24 |
5867484760 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1846760633 |
|
|
Sep 10 01:11:35 AM UTC 24 |
Sep 10 01:21:24 AM UTC 24 |
7145312068 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_mem_scramble.4199441353 |
|
|
Sep 10 01:13:17 AM UTC 24 |
Sep 10 01:21:53 AM UTC 24 |
3444228060 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2871952146 |
|
|
Sep 10 01:02:40 AM UTC 24 |
Sep 10 01:22:25 AM UTC 24 |
7566411120 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.2640072432 |
|
|
Sep 10 01:16:17 AM UTC 24 |
Sep 10 01:23:11 AM UTC 24 |
2956188884 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.1277830478 |
|
|
Sep 10 01:19:04 AM UTC 24 |
Sep 10 01:24:15 AM UTC 24 |
2969976712 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.612706440 |
|
|
Sep 10 01:12:56 AM UTC 24 |
Sep 10 01:24:16 AM UTC 24 |
19341968642 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.3074871411 |
|
|
Sep 10 01:19:04 AM UTC 24 |
Sep 10 01:24:31 AM UTC 24 |
3340417988 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1182212848 |
|
|
Sep 10 01:17:28 AM UTC 24 |
Sep 10 01:24:40 AM UTC 24 |
3638399460 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_timeout.1056802305 |
|
|
Sep 10 01:16:21 AM UTC 24 |
Sep 10 01:25:05 AM UTC 24 |
4736102030 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.4160042644 |
|
|
Sep 10 01:18:31 AM UTC 24 |
Sep 10 01:25:18 AM UTC 24 |
3303471383 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.1581875976 |
|
|
Sep 10 01:16:18 AM UTC 24 |
Sep 10 01:25:35 AM UTC 24 |
5198607000 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3941115935 |
|
|
Sep 10 01:22:41 AM UTC 24 |
Sep 10 01:26:28 AM UTC 24 |
2612003968 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.4185033932 |
|
|
Sep 10 01:13:35 AM UTC 24 |
Sep 10 01:26:34 AM UTC 24 |
5449838376 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_kat_test.2098930788 |
|
|
Sep 10 01:20:47 AM UTC 24 |
Sep 10 01:26:42 AM UTC 24 |
2416939390 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.3718994208 |
|
|
Sep 10 01:02:45 AM UTC 24 |
Sep 10 01:27:14 AM UTC 24 |
11946460300 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en.3518883487 |
|
|
Sep 10 01:23:52 AM UTC 24 |
Sep 10 01:27:14 AM UTC 24 |
3146154719 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_randomness.3954135114 |
|
|
Sep 10 01:12:50 AM UTC 24 |
Sep 10 01:27:19 AM UTC 24 |
5956263342 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.577724811 |
|
|
Sep 10 12:53:02 AM UTC 24 |
Sep 10 01:27:57 AM UTC 24 |
20671690312 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.3805039015 |
|
|
Sep 10 01:12:50 AM UTC 24 |
Sep 10 01:28:44 AM UTC 24 |
5568321288 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.1873800914 |
|
|
Sep 10 01:20:12 AM UTC 24 |
Sep 10 01:28:54 AM UTC 24 |
2718414860 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1806786903 |
|
|
Sep 10 01:04:14 AM UTC 24 |
Sep 10 01:28:55 AM UTC 24 |
13399533135 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2658919332 |
|
|
Sep 10 01:21:31 AM UTC 24 |
Sep 10 01:29:12 AM UTC 24 |
3839390856 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.1697507003 |
|
|
Sep 10 01:20:41 AM UTC 24 |
Sep 10 01:30:05 AM UTC 24 |
3127693522 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.1917621495 |
|
|
Sep 10 01:25:29 AM UTC 24 |
Sep 10 01:30:11 AM UTC 24 |
2873586432 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.11257772 |
|
|
Sep 10 01:25:45 AM UTC 24 |
Sep 10 01:31:03 AM UTC 24 |
2688823648 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.2507311467 |
|
|
Sep 10 01:20:46 AM UTC 24 |
Sep 10 01:31:10 AM UTC 24 |
5287741460 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.3278462531 |
|
|
Sep 10 01:27:37 AM UTC 24 |
Sep 10 01:32:05 AM UTC 24 |
2582307526 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_app_rom.2504714730 |
|
|
Sep 10 01:28:16 AM UTC 24 |
Sep 10 01:32:24 AM UTC 24 |
2744982472 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1918462587 |
|
|
Sep 09 11:43:10 PM UTC 24 |
Sep 10 01:32:45 AM UTC 24 |
22516119662 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1743600912 |
|
|
Sep 10 01:03:59 AM UTC 24 |
Sep 10 01:33:07 AM UTC 24 |
12948910539 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3948381217 |
|
|
Sep 10 01:02:58 AM UTC 24 |
Sep 10 01:33:48 AM UTC 24 |
10660273564 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1387984574 |
|
|
Sep 09 11:42:40 PM UTC 24 |
Sep 10 01:33:53 AM UTC 24 |
23723062298 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3295396339 |
|
|
Sep 10 01:28:19 AM UTC 24 |
Sep 10 01:33:54 AM UTC 24 |
2572116493 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.196492506 |
|
|
Sep 10 01:28:16 AM UTC 24 |
Sep 10 01:34:06 AM UTC 24 |
2616825440 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.1524200547 |
|
|
Sep 10 01:28:45 AM UTC 24 |
Sep 10 01:34:27 AM UTC 24 |
3106905244 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1030111346 |
|
|
Sep 09 11:40:13 PM UTC 24 |
Sep 10 01:34:59 AM UTC 24 |
24267392496 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3020254067 |
|
|
Sep 09 11:43:08 PM UTC 24 |
Sep 10 01:35:11 AM UTC 24 |
24000387060 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.2373538613 |
|
|
Sep 10 01:31:55 AM UTC 24 |
Sep 10 01:35:55 AM UTC 24 |
2758955086 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3815877182 |
|
|
Sep 10 01:17:24 AM UTC 24 |
Sep 10 01:36:05 AM UTC 24 |
11065833538 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.3262552723 |
|
|
Sep 10 01:20:27 AM UTC 24 |
Sep 10 01:36:56 AM UTC 24 |
4898245720 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3248099894 |
|
|
Sep 10 01:02:48 AM UTC 24 |
Sep 10 01:44:24 AM UTC 24 |
34754229008 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.802596665 |
|
|
Sep 10 01:08:12 AM UTC 24 |
Sep 10 01:37:03 AM UTC 24 |
23373371902 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2865150296 |
|
|
Sep 10 01:28:48 AM UTC 24 |
Sep 10 01:37:24 AM UTC 24 |
10298309489 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.796624658 |
|
|
Sep 10 01:17:22 AM UTC 24 |
Sep 10 01:37:37 AM UTC 24 |
7578987440 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3162269303 |
|
|
Sep 10 01:02:54 AM UTC 24 |
Sep 10 01:38:24 AM UTC 24 |
22074622734 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.3883365003 |
|
|
Sep 10 01:35:20 AM UTC 24 |
Sep 10 01:38:58 AM UTC 24 |
3092605542 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.3960853404 |
|
|
Sep 10 01:22:43 AM UTC 24 |
Sep 10 01:39:06 AM UTC 24 |
5189355792 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs.3848369164 |
|
|
Sep 10 01:22:42 AM UTC 24 |
Sep 10 01:39:27 AM UTC 24 |
6909114840 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3511184427 |
|
|
Sep 10 01:18:30 AM UTC 24 |
Sep 10 01:39:32 AM UTC 24 |
6126264760 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.3809173009 |
|
|
Sep 10 01:30:03 AM UTC 24 |
Sep 10 01:39:32 AM UTC 24 |
6695414499 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.4289235572 |
|
|
Sep 10 01:18:01 AM UTC 24 |
Sep 10 01:39:41 AM UTC 24 |
6414000012 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3693599423 |
|
|
Sep 10 01:31:56 AM UTC 24 |
Sep 10 01:39:49 AM UTC 24 |
5363509704 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3819147197 |
|
|
Sep 10 01:29:58 AM UTC 24 |
Sep 10 01:40:26 AM UTC 24 |
5426247272 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2640825427 |
|
|
Sep 10 01:30:05 AM UTC 24 |
Sep 10 01:41:25 AM UTC 24 |
5247876651 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.37867302 |
|
|
Sep 10 01:30:58 AM UTC 24 |
Sep 10 01:41:27 AM UTC 24 |
7364125812 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.1492904939 |
|
|
Sep 10 01:33:26 AM UTC 24 |
Sep 10 01:41:43 AM UTC 24 |
3772667604 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.654980021 |
|
|
Sep 10 01:30:59 AM UTC 24 |
Sep 10 01:42:03 AM UTC 24 |
6528014940 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.211573527 |
|
|
Sep 09 11:40:23 PM UTC 24 |
Sep 10 01:43:09 AM UTC 24 |
24591613244 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.569133935 |
|
|
Sep 10 01:22:42 AM UTC 24 |
Sep 10 01:43:32 AM UTC 24 |
6409856086 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1042133270 |
|
|
Sep 10 01:35:14 AM UTC 24 |
Sep 10 01:43:34 AM UTC 24 |
5366139000 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.558814942 |
|
|
Sep 10 01:39:51 AM UTC 24 |
Sep 10 01:43:59 AM UTC 24 |
2679693468 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3570509049 |
|
|
Sep 09 11:40:02 PM UTC 24 |
Sep 10 01:44:16 AM UTC 24 |
24214432886 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3461010034 |
|
|
Sep 09 11:41:14 PM UTC 24 |
Sep 10 01:44:31 AM UTC 24 |
23366484486 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3417138950 |
|
|
Sep 10 01:35:18 AM UTC 24 |
Sep 10 01:44:51 AM UTC 24 |
4904894810 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_reset_frequency.1488111132 |
|
|
Sep 10 01:38:26 AM UTC 24 |
Sep 10 01:44:55 AM UTC 24 |
3550288632 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3774836244 |
|
|
Sep 10 01:35:19 AM UTC 24 |
Sep 10 01:45:18 AM UTC 24 |
4263082756 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2242403359 |
|
|
Sep 10 01:36:48 AM UTC 24 |
Sep 10 01:45:23 AM UTC 24 |
3969309490 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.941595344 |
|
|
Sep 09 11:39:40 PM UTC 24 |
Sep 10 01:45:32 AM UTC 24 |
24718166242 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2467334985 |
|
|
Sep 10 01:30:04 AM UTC 24 |
Sep 10 01:46:16 AM UTC 24 |
8351317400 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.803711128 |
|
|
Sep 10 01:39:06 AM UTC 24 |
Sep 10 01:46:39 AM UTC 24 |
3166911624 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3452115276 |
|
|
Sep 10 01:26:17 AM UTC 24 |
Sep 10 01:46:50 AM UTC 24 |
6231081494 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3973443865 |
|
|
Sep 10 01:35:48 AM UTC 24 |
Sep 10 01:47:02 AM UTC 24 |
6165156628 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.4028700447 |
|
|
Sep 10 01:44:48 AM UTC 24 |
Sep 10 01:47:23 AM UTC 24 |
2666542970 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.32193808 |
|
|
Sep 10 01:38:19 AM UTC 24 |
Sep 10 01:47:38 AM UTC 24 |
3908320888 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.1980637833 |
|
|
Sep 10 01:45:34 AM UTC 24 |
Sep 10 01:47:40 AM UTC 24 |
2732939809 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.986928097 |
|
|
Sep 10 01:38:17 AM UTC 24 |
Sep 10 01:47:47 AM UTC 24 |
5123399556 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.132610242 |
|
|
Sep 10 01:36:49 AM UTC 24 |
Sep 10 01:47:52 AM UTC 24 |
4780862056 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.576864232 |
|
|
Sep 10 01:33:49 AM UTC 24 |
Sep 10 01:47:56 AM UTC 24 |
4932560110 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1312482318 |
|
|
Sep 10 01:40:39 AM UTC 24 |
Sep 10 01:48:28 AM UTC 24 |
6886216434 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.361509189 |
|
|
Sep 10 01:41:08 AM UTC 24 |
Sep 10 01:48:32 AM UTC 24 |
4050906202 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.3236767660 |
|
|
Sep 10 01:25:58 AM UTC 24 |
Sep 10 01:48:43 AM UTC 24 |
6565165768 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2746121630 |
|
|
Sep 10 01:38:27 AM UTC 24 |
Sep 10 01:48:49 AM UTC 24 |
4436080168 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1106437951 |
|
|
Sep 10 01:39:51 AM UTC 24 |
Sep 10 01:49:02 AM UTC 24 |
4717780180 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3637791877 |
|
|
Sep 10 01:38:27 AM UTC 24 |
Sep 10 01:49:36 AM UTC 24 |
5332447796 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_program_error.2246327346 |
|
|
Sep 10 01:40:39 AM UTC 24 |
Sep 10 01:50:22 AM UTC 24 |
6136152116 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.524238691 |
|
|
Sep 10 01:43:49 AM UTC 24 |
Sep 10 01:50:32 AM UTC 24 |
4535968946 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1154181327 |
|
|
Sep 10 01:44:25 AM UTC 24 |
Sep 10 01:50:33 AM UTC 24 |
3539843900 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3828082354 |
|
|
Sep 10 01:42:48 AM UTC 24 |
Sep 10 01:50:40 AM UTC 24 |
5429639880 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.4244604345 |
|
|
Sep 10 01:46:22 AM UTC 24 |
Sep 10 01:50:48 AM UTC 24 |
2902410840 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.999140502 |
|
|
Sep 10 01:45:39 AM UTC 24 |
Sep 10 01:51:07 AM UTC 24 |
3245339164 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_aes.2572957696 |
|
|
Sep 10 01:27:32 AM UTC 24 |
Sep 10 01:51:12 AM UTC 24 |
8944762512 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3560235339 |
|
|
Sep 10 01:47:43 AM UTC 24 |
Sep 10 01:51:16 AM UTC 24 |
2337808533 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.1820530616 |
|
|
Sep 10 01:20:26 AM UTC 24 |
Sep 10 01:51:27 AM UTC 24 |
8767737652 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.3610647228 |
|
|
Sep 10 01:33:07 AM UTC 24 |
Sep 10 01:51:31 AM UTC 24 |
6217147680 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.4030003157 |
|
|
Sep 10 01:44:56 AM UTC 24 |
Sep 10 01:51:35 AM UTC 24 |
4833604712 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1118521730 |
|
|
Sep 10 01:35:52 AM UTC 24 |
Sep 10 01:51:52 AM UTC 24 |
13448419664 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.832521238 |
|
|
Sep 10 01:44:34 AM UTC 24 |
Sep 10 01:52:18 AM UTC 24 |
5740308824 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.829053154 |
|
|
Sep 10 01:46:58 AM UTC 24 |
Sep 10 01:52:59 AM UTC 24 |
3357888250 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.3424322588 |
|
|
Sep 10 01:45:04 AM UTC 24 |
Sep 10 01:53:12 AM UTC 24 |
6427739066 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2546252234 |
|
|
Sep 10 01:42:43 AM UTC 24 |
Sep 10 01:53:13 AM UTC 24 |
6937312530 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1041656031 |
|
|
Sep 10 01:49:22 AM UTC 24 |
Sep 10 01:53:22 AM UTC 24 |
2721115795 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1797721400 |
|
|
Sep 10 01:49:00 AM UTC 24 |
Sep 10 01:53:44 AM UTC 24 |
3340993095 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.250078366 |
|
|
Sep 10 01:49:55 AM UTC 24 |
Sep 10 01:53:59 AM UTC 24 |
3371310635 ps |
| T1037 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.3102520681 |
|
|
Sep 10 01:40:32 AM UTC 24 |
Sep 10 01:54:14 AM UTC 24 |
7978870600 ps |
| T1038 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.1970107011 |
|
|
Sep 10 01:26:18 AM UTC 24 |
Sep 10 01:55:10 AM UTC 24 |
9164788748 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3448557828 |
|
|
Sep 10 01:44:39 AM UTC 24 |
Sep 10 01:55:22 AM UTC 24 |
5808266444 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.19722140 |
|
|
Sep 10 01:50:46 AM UTC 24 |
Sep 10 01:56:03 AM UTC 24 |
3827050872 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.3339515722 |
|
|
Sep 10 01:39:51 AM UTC 24 |
Sep 10 01:56:20 AM UTC 24 |
10121430435 ps |
| T1039 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_volatile_raw_unlock.3214470686 |
|
|
Sep 10 01:55:16 AM UTC 24 |
Sep 10 01:57:04 AM UTC 24 |
2700377256 ps |
| T1040 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.1891558037 |
|
|
Sep 10 01:46:23 AM UTC 24 |
Sep 10 01:57:17 AM UTC 24 |
4990868144 ps |
| T1041 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1336194613 |
|
|
Sep 10 01:47:48 AM UTC 24 |
Sep 10 01:57:31 AM UTC 24 |
5399851004 ps |
| T1042 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3348588821 |
|
|
Sep 10 01:26:14 AM UTC 24 |
Sep 10 01:58:06 AM UTC 24 |
10318908160 ps |
| T1043 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.4139327737 |
|
|
Sep 10 01:50:23 AM UTC 24 |
Sep 10 01:58:25 AM UTC 24 |
3894102054 ps |
| T1044 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.3218357234 |
|
|
Sep 10 01:55:31 AM UTC 24 |
Sep 10 01:58:32 AM UTC 24 |
2606102430 ps |
| T1045 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.40570615 |
|
|
Sep 10 01:35:20 AM UTC 24 |
Sep 10 01:59:18 AM UTC 24 |
12436790320 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_raw_unlock.225656220 |
|
|
Sep 10 01:55:07 AM UTC 24 |
Sep 10 01:59:25 AM UTC 24 |
5714143820 ps |
| T1046 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.1973075711 |
|
|
Sep 10 01:55:20 AM UTC 24 |
Sep 10 01:59:46 AM UTC 24 |
2812746440 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2737063011 |
|
|
Sep 10 01:50:25 AM UTC 24 |
Sep 10 01:59:54 AM UTC 24 |
4737842459 ps |
| T1047 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.3471338672 |
|
|
Sep 10 01:55:33 AM UTC 24 |
Sep 10 01:59:56 AM UTC 24 |
2539243568 ps |
| T1048 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.3065100317 |
|
|
Sep 10 01:56:12 AM UTC 24 |
Sep 10 02:00:18 AM UTC 24 |
3537100412 ps |
| T1049 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.118826211 |
|
|
Sep 10 01:55:13 AM UTC 24 |
Sep 10 02:00:31 AM UTC 24 |
2940565400 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.2846959509 |
|
|
Sep 10 01:39:56 AM UTC 24 |
Sep 10 02:01:17 AM UTC 24 |
13410706592 ps |
| T1050 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.4162210614 |
|
|
Sep 10 01:56:42 AM UTC 24 |
Sep 10 02:01:49 AM UTC 24 |
2865966525 ps |
| T1051 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.3127536305 |
|
|
Sep 10 01:58:13 AM UTC 24 |
Sep 10 02:02:51 AM UTC 24 |
3571573370 ps |
| T1052 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.3393573303 |
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Sep 10 02:00:54 AM UTC 24 |
Sep 10 02:03:03 AM UTC 24 |
2299309920 ps |
| T1053 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_plic_smoketest.3934381518 |
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Sep 10 01:59:16 AM UTC 24 |
Sep 10 02:03:11 AM UTC 24 |
2811232418 ps |
| T1054 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.923765107 |
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Sep 10 02:00:11 AM UTC 24 |
Sep 10 02:03:46 AM UTC 24 |
3020153296 ps |
| T1055 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation.579526713 |
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Sep 10 01:25:59 AM UTC 24 |
Sep 10 02:03:48 AM UTC 24 |
11274516016 ps |
| T1056 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.3920246174 |
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Sep 10 01:57:01 AM UTC 24 |
Sep 10 02:04:19 AM UTC 24 |
2970022134 ps |
| T1057 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.3872649223 |
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Sep 10 01:57:55 AM UTC 24 |
Sep 10 02:04:31 AM UTC 24 |
3103984060 ps |
| T1058 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_smoketest.680439414 |
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Sep 10 01:56:19 AM UTC 24 |
Sep 10 02:04:32 AM UTC 24 |
4013090764 ps |
| T1059 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2178455888 |
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Sep 10 01:59:15 AM UTC 24 |
Sep 10 02:04:56 AM UTC 24 |
5378497938 ps |
| T1060 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.1494404944 |
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Sep 10 01:58:47 AM UTC 24 |
Sep 10 02:04:59 AM UTC 24 |
5528213652 ps |
| T1061 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2911281623 |
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Sep 10 01:09:47 AM UTC 24 |
Sep 10 02:05:10 AM UTC 24 |
21242211027 ps |
| T1062 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.3372976415 |
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Sep 10 02:00:52 AM UTC 24 |
Sep 10 02:05:31 AM UTC 24 |
3172549880 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.4119591463 |
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Sep 10 02:00:53 AM UTC 24 |
Sep 10 02:05:37 AM UTC 24 |
2846572728 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.3856669410 |
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Sep 10 02:00:10 AM UTC 24 |
Sep 10 02:05:46 AM UTC 24 |
3507145004 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.1462939252 |
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Sep 10 02:01:11 AM UTC 24 |
Sep 10 02:05:57 AM UTC 24 |
2414063980 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.618245012 |
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Sep 10 01:56:20 AM UTC 24 |
Sep 10 02:06:17 AM UTC 24 |
4114537110 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_smoketest.693629761 |
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Sep 10 02:00:51 AM UTC 24 |
Sep 10 02:06:20 AM UTC 24 |
2933610320 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3833999745 |
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Sep 10 01:47:48 AM UTC 24 |
Sep 10 02:06:26 AM UTC 24 |
7387645252 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.3945285352 |
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Sep 10 02:01:58 AM UTC 24 |
Sep 10 02:06:56 AM UTC 24 |
2864342840 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1594525197 |
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Sep 10 01:49:30 AM UTC 24 |
Sep 10 02:07:49 AM UTC 24 |
8605745310 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.994728088 |
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Sep 10 02:02:32 AM UTC 24 |
Sep 10 02:08:10 AM UTC 24 |
3586055918 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1000390244 |
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Sep 10 01:53:13 AM UTC 24 |
Sep 10 02:08:33 AM UTC 24 |
4796477596 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.319633357 |
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Sep 10 01:42:42 AM UTC 24 |
Sep 10 02:08:34 AM UTC 24 |
21408079118 ps |
| T28 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.3919340924 |
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Sep 10 02:04:39 AM UTC 24 |
Sep 10 02:09:49 AM UTC 24 |
4963101100 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.3133112320 |
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Sep 10 02:05:47 AM UTC 24 |
Sep 10 02:10:18 AM UTC 24 |
3073059944 ps |
| T21 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2313363782 |
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Sep 10 02:04:38 AM UTC 24 |
Sep 10 02:10:23 AM UTC 24 |
3276571587 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3564238707 |
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Sep 10 01:32:48 AM UTC 24 |
Sep 10 02:10:27 AM UTC 24 |
27962975042 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.1375902614 |
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Sep 10 02:05:22 AM UTC 24 |
Sep 10 02:10:40 AM UTC 24 |
3286000714 ps |