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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.17 95.52 94.02 95.39 94.99 97.53 99.59


Total test records in report: 2926
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T2023 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.110098566 Sep 10 06:45:01 AM UTC 24 Sep 10 06:45:36 AM UTC 24 868817325 ps
T2024 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.3258677769 Sep 10 06:44:31 AM UTC 24 Sep 10 06:45:38 AM UTC 24 4801850419 ps
T2025 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.735512804 Sep 10 05:52:11 AM UTC 24 Sep 10 06:45:44 AM UTC 24 29012120758 ps
T2026 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.2597338494 Sep 10 06:32:40 AM UTC 24 Sep 10 06:45:45 AM UTC 24 52823662371 ps
T2027 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.881591711 Sep 10 06:45:38 AM UTC 24 Sep 10 06:45:45 AM UTC 24 53154373 ps
T2028 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.743559628 Sep 10 06:45:10 AM UTC 24 Sep 10 06:45:46 AM UTC 24 258412827 ps
T2029 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.1193090744 Sep 10 06:44:56 AM UTC 24 Sep 10 06:45:50 AM UTC 24 1054778006 ps
T2030 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.3978371661 Sep 10 06:45:35 AM UTC 24 Sep 10 06:45:50 AM UTC 24 232685476 ps
T2031 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.2422377993 Sep 10 06:29:06 AM UTC 24 Sep 10 06:45:52 AM UTC 24 106011994853 ps
T2032 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.1094811190 Sep 10 06:42:30 AM UTC 24 Sep 10 06:45:52 AM UTC 24 4666554397 ps
T2033 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.2001117564 Sep 10 06:42:36 AM UTC 24 Sep 10 06:45:56 AM UTC 24 2923381017 ps
T2034 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.3504073839 Sep 10 06:44:29 AM UTC 24 Sep 10 06:45:57 AM UTC 24 7851529906 ps
T2035 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.3778838809 Sep 10 06:27:43 AM UTC 24 Sep 10 06:46:01 AM UTC 24 106867383316 ps
T2036 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.1182962297 Sep 10 06:45:56 AM UTC 24 Sep 10 06:46:09 AM UTC 24 68019371 ps
T2037 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.1158568947 Sep 10 06:46:01 AM UTC 24 Sep 10 06:46:20 AM UTC 24 379789448 ps
T2038 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.42700477 Sep 10 06:46:09 AM UTC 24 Sep 10 06:46:20 AM UTC 24 74978501 ps
T2039 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.2038264198 Sep 10 06:46:23 AM UTC 24 Sep 10 06:46:30 AM UTC 24 47075562 ps
T2040 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.2289126584 Sep 10 06:36:39 AM UTC 24 Sep 10 06:46:31 AM UTC 24 6073380882 ps
T2041 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.2583318748 Sep 10 06:46:26 AM UTC 24 Sep 10 06:46:34 AM UTC 24 48334408 ps
T2042 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.4115145728 Sep 10 06:46:14 AM UTC 24 Sep 10 06:46:40 AM UTC 24 156052473 ps
T2043 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.444383909 Sep 10 06:46:13 AM UTC 24 Sep 10 06:46:46 AM UTC 24 687087762 ps
T2044 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.4259877707 Sep 10 06:35:43 AM UTC 24 Sep 10 06:46:51 AM UTC 24 37831994002 ps
T2045 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.163280256 Sep 10 06:45:51 AM UTC 24 Sep 10 06:46:54 AM UTC 24 583066398 ps
T2046 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.574804839 Sep 10 06:47:21 AM UTC 24 Sep 10 06:47:31 AM UTC 24 77206977 ps
T2047 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.2214622241 Sep 10 06:45:49 AM UTC 24 Sep 10 06:47:02 AM UTC 24 3978029921 ps
T2048 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.4240537899 Sep 10 06:46:12 AM UTC 24 Sep 10 06:47:02 AM UTC 24 875054369 ps
T2049 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.3287583254 Sep 10 06:45:23 AM UTC 24 Sep 10 06:47:03 AM UTC 24 1401443766 ps
T2050 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.1324674899 Sep 10 06:46:44 AM UTC 24 Sep 10 06:47:03 AM UTC 24 497160274 ps
T2051 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.3295579990 Sep 10 06:30:17 AM UTC 24 Sep 10 06:47:05 AM UTC 24 99221888520 ps
T2052 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.2009194722 Sep 10 06:45:46 AM UTC 24 Sep 10 06:47:05 AM UTC 24 8308074484 ps
T2053 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.1538220046 Sep 10 06:31:21 AM UTC 24 Sep 10 06:47:06 AM UTC 24 91196359922 ps
T2054 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.1985632691 Sep 10 06:46:15 AM UTC 24 Sep 10 06:47:14 AM UTC 24 554246017 ps
T2055 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.3655029077 Sep 10 06:46:44 AM UTC 24 Sep 10 06:47:31 AM UTC 24 416402716 ps
T2056 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.1784499174 Sep 10 06:47:35 AM UTC 24 Sep 10 06:47:44 AM UTC 24 45601911 ps
T2057 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.4164459836 Sep 10 06:46:34 AM UTC 24 Sep 10 06:47:54 AM UTC 24 5318154156 ps
T2058 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.3233152469 Sep 10 06:47:12 AM UTC 24 Sep 10 06:48:02 AM UTC 24 1211875851 ps
T2059 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.3921051935 Sep 10 06:46:20 AM UTC 24 Sep 10 06:48:03 AM UTC 24 377517424 ps
T2060 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.13764005 Sep 10 06:47:31 AM UTC 24 Sep 10 06:48:07 AM UTC 24 452579224 ps
T2061 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.2493225585 Sep 10 06:47:28 AM UTC 24 Sep 10 06:48:08 AM UTC 24 780609964 ps
T2062 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.1804570429 Sep 10 06:46:27 AM UTC 24 Sep 10 06:48:13 AM UTC 24 9011121278 ps
T2063 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.3337956536 Sep 10 06:46:03 AM UTC 24 Sep 10 06:48:13 AM UTC 24 6949917644 ps
T2064 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.907459654 Sep 10 06:47:31 AM UTC 24 Sep 10 06:48:20 AM UTC 24 472246349 ps
T2065 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.38277725 Sep 10 06:40:35 AM UTC 24 Sep 10 06:48:24 AM UTC 24 53771452596 ps
T2066 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.895275112 Sep 10 06:48:00 AM UTC 24 Sep 10 06:48:28 AM UTC 24 269729185 ps
T2067 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.2283457133 Sep 10 06:48:23 AM UTC 24 Sep 10 06:48:36 AM UTC 24 111304783 ps
T2068 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.2234404063 Sep 10 06:47:13 AM UTC 24 Sep 10 06:48:38 AM UTC 24 2066388229 ps
T2069 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.2391154435 Sep 10 06:46:59 AM UTC 24 Sep 10 06:48:48 AM UTC 24 7178080491 ps
T2070 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.2475006965 Sep 10 06:39:10 AM UTC 24 Sep 10 06:48:50 AM UTC 24 15718346331 ps
T2071 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.2259044783 Sep 10 06:48:34 AM UTC 24 Sep 10 06:48:50 AM UTC 24 231384641 ps
T2072 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.3222234202 Sep 10 06:48:08 AM UTC 24 Sep 10 06:48:51 AM UTC 24 334749819 ps
T2073 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.3998902239 Sep 10 06:48:34 AM UTC 24 Sep 10 06:48:53 AM UTC 24 110863626 ps
T2074 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_aliasing.3908719892 Sep 10 05:08:10 AM UTC 24 Sep 10 06:48:54 AM UTC 24 31100701660 ps
T2075 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.569170805 Sep 10 06:42:35 AM UTC 24 Sep 10 06:48:55 AM UTC 24 663939191 ps
T2076 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2721969495 Sep 10 06:47:33 AM UTC 24 Sep 10 06:48:59 AM UTC 24 322599133 ps
T2077 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.2406801630 Sep 10 06:44:01 AM UTC 24 Sep 10 06:49:02 AM UTC 24 5890870758 ps
T2078 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.252251455 Sep 10 06:48:41 AM UTC 24 Sep 10 06:49:04 AM UTC 24 146525830 ps
T2079 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.2800334418 Sep 10 06:46:57 AM UTC 24 Sep 10 06:49:07 AM UTC 24 3038784759 ps
T2080 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.3175965762 Sep 10 06:49:03 AM UTC 24 Sep 10 06:49:13 AM UTC 24 49246550 ps
T2081 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.4215359956 Sep 10 06:45:33 AM UTC 24 Sep 10 06:49:15 AM UTC 24 3583768684 ps
T2082 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.3055212725 Sep 10 06:49:02 AM UTC 24 Sep 10 06:49:16 AM UTC 24 226734064 ps
T2083 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.23843804 Sep 10 06:40:06 AM UTC 24 Sep 10 06:49:19 AM UTC 24 14582604661 ps
T2084 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.2323120063 Sep 10 06:49:13 AM UTC 24 Sep 10 06:49:23 AM UTC 24 117392155 ps
T2085 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.1564166527 Sep 10 06:31:35 AM UTC 24 Sep 10 06:49:28 AM UTC 24 70660302240 ps
T2086 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.64473396 Sep 10 06:47:43 AM UTC 24 Sep 10 06:49:32 AM UTC 24 10282559296 ps
T2087 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.3655502413 Sep 10 06:48:31 AM UTC 24 Sep 10 06:49:36 AM UTC 24 1946506494 ps
T2088 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.572492733 Sep 10 06:47:58 AM UTC 24 Sep 10 06:49:37 AM UTC 24 5994390467 ps
T2089 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.1770663080 Sep 10 06:44:04 AM UTC 24 Sep 10 06:49:40 AM UTC 24 10818439600 ps
T2090 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.136156227 Sep 10 06:49:35 AM UTC 24 Sep 10 06:50:03 AM UTC 24 264571564 ps
T2091 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.3869420589 Sep 10 05:02:51 AM UTC 24 Sep 10 06:50:04 AM UTC 24 35457188070 ps
T2092 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.1266883430 Sep 10 06:49:56 AM UTC 24 Sep 10 06:50:04 AM UTC 24 46016247 ps
T2093 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.2245575287 Sep 10 06:48:40 AM UTC 24 Sep 10 06:50:05 AM UTC 24 2232535372 ps
T2094 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.270495421 Sep 10 06:49:58 AM UTC 24 Sep 10 06:50:06 AM UTC 24 47045462 ps
T2095 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.659135158 Sep 10 06:49:14 AM UTC 24 Sep 10 06:50:09 AM UTC 24 4085047476 ps
T2096 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.1255113473 Sep 10 06:49:29 AM UTC 24 Sep 10 06:50:13 AM UTC 24 458636121 ps
T2097 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.3424255205 Sep 10 06:49:15 AM UTC 24 Sep 10 06:50:14 AM UTC 24 529350770 ps
T2098 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.780777110 Sep 10 06:49:25 AM UTC 24 Sep 10 06:50:15 AM UTC 24 494478472 ps
T2099 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.4063004414 Sep 10 06:49:41 AM UTC 24 Sep 10 06:50:16 AM UTC 24 946267809 ps
T2100 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.736496209 Sep 10 06:49:14 AM UTC 24 Sep 10 06:50:20 AM UTC 24 6941139024 ps
T2101 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.718910513 Sep 10 06:50:02 AM UTC 24 Sep 10 06:50:21 AM UTC 24 124829738 ps
T2102 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.3308076808 Sep 10 06:43:24 AM UTC 24 Sep 10 06:50:26 AM UTC 24 23663121179 ps
T2103 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.58445392 Sep 10 06:47:31 AM UTC 24 Sep 10 06:50:41 AM UTC 24 4766534274 ps
T2104 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.3026787106 Sep 10 06:48:52 AM UTC 24 Sep 10 06:50:42 AM UTC 24 3023334087 ps
T2105 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.1807642464 Sep 10 06:38:43 AM UTC 24 Sep 10 06:50:43 AM UTC 24 47546472604 ps
T2106 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.1310432320 Sep 10 06:32:37 AM UTC 24 Sep 10 06:50:48 AM UTC 24 114621981117 ps
T2107 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.2958307841 Sep 10 06:50:24 AM UTC 24 Sep 10 06:50:48 AM UTC 24 246637276 ps
T2108 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.2364922873 Sep 10 06:50:40 AM UTC 24 Sep 10 06:50:54 AM UTC 24 126030815 ps
T2109 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.3343454224 Sep 10 06:49:46 AM UTC 24 Sep 10 06:51:03 AM UTC 24 298911704 ps
T2110 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.1181797726 Sep 10 06:40:40 AM UTC 24 Sep 10 06:51:04 AM UTC 24 39366892115 ps
T2111 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.2786362894 Sep 10 06:49:20 AM UTC 24 Sep 10 06:51:04 AM UTC 24 3107844045 ps
T2112 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.2406603036 Sep 10 06:49:40 AM UTC 24 Sep 10 06:51:13 AM UTC 24 1269215498 ps
T2113 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.1475525946 Sep 10 06:50:38 AM UTC 24 Sep 10 06:51:17 AM UTC 24 1089233143 ps
T2114 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.1098766374 Sep 10 06:51:10 AM UTC 24 Sep 10 06:51:19 AM UTC 24 38336736 ps
T2115 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.2451797609 Sep 10 06:51:08 AM UTC 24 Sep 10 06:51:21 AM UTC 24 165716576 ps
T2116 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.4282932788 Sep 10 06:50:00 AM UTC 24 Sep 10 06:51:36 AM UTC 24 5299118698 ps
T2117 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.242210630 Sep 10 06:50:33 AM UTC 24 Sep 10 06:51:36 AM UTC 24 2273283314 ps
T2118 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.1187682383 Sep 10 06:50:42 AM UTC 24 Sep 10 06:51:39 AM UTC 24 1226228492 ps
T2119 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.2436669915 Sep 10 05:50:26 AM UTC 24 Sep 10 06:51:41 AM UTC 24 30275462682 ps
T2120 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.1304729436 Sep 10 06:44:00 AM UTC 24 Sep 10 06:51:42 AM UTC 24 13616031981 ps
T2121 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.86350678 Sep 10 06:51:22 AM UTC 24 Sep 10 06:51:43 AM UTC 24 162451530 ps
T2122 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.2473499432 Sep 10 06:34:06 AM UTC 24 Sep 10 06:51:46 AM UTC 24 99506365381 ps
T2123 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.203624430 Sep 10 06:50:02 AM UTC 24 Sep 10 06:51:52 AM UTC 24 9181966535 ps
T2124 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.3367011834 Sep 10 06:51:46 AM UTC 24 Sep 10 06:51:56 AM UTC 24 188488018 ps
T2125 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.2654955674 Sep 10 06:46:14 AM UTC 24 Sep 10 06:51:58 AM UTC 24 8556615357 ps
T2126 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.713575800 Sep 10 06:51:48 AM UTC 24 Sep 10 06:52:03 AM UTC 24 127705407 ps
T2127 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.2566831347 Sep 10 06:51:08 AM UTC 24 Sep 10 06:52:10 AM UTC 24 5913846208 ps
T2128 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.2505876086 Sep 10 06:51:33 AM UTC 24 Sep 10 06:52:10 AM UTC 24 496516974 ps
T2129 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.1643593153 Sep 10 06:52:13 AM UTC 24 Sep 10 06:52:20 AM UTC 24 46780579 ps
T2130 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.3404210440 Sep 10 06:51:15 AM UTC 24 Sep 10 06:52:23 AM UTC 24 1384132920 ps
T2131 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.1868081907 Sep 10 06:52:10 AM UTC 24 Sep 10 06:52:24 AM UTC 24 207857220 ps
T2132 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.3661799598 Sep 10 06:51:48 AM UTC 24 Sep 10 06:52:32 AM UTC 24 1104344289 ps
T2133 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.3781602214 Sep 10 06:52:03 AM UTC 24 Sep 10 06:52:34 AM UTC 24 265292849 ps
T2134 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.4222809793 Sep 10 06:52:21 AM UTC 24 Sep 10 06:52:38 AM UTC 24 134625293 ps
T2135 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.1094768741 Sep 10 06:51:17 AM UTC 24 Sep 10 06:52:40 AM UTC 24 5939412301 ps
T2136 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.2193375381 Sep 10 06:50:32 AM UTC 24 Sep 10 06:52:42 AM UTC 24 2799827612 ps
T2137 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.3937828838 Sep 10 06:48:54 AM UTC 24 Sep 10 06:52:45 AM UTC 24 1755844349 ps
T2138 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.604285894 Sep 10 06:50:42 AM UTC 24 Sep 10 06:52:55 AM UTC 24 1801297796 ps
T2139 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.250624042 Sep 10 06:52:48 AM UTC 24 Sep 10 06:53:05 AM UTC 24 137657607 ps
T2140 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.2672547425 Sep 10 06:49:16 AM UTC 24 Sep 10 06:53:11 AM UTC 24 22808741781 ps
T2141 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.3681625624 Sep 10 06:53:00 AM UTC 24 Sep 10 06:53:33 AM UTC 24 669805266 ps
T2142 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.351392 Sep 10 06:41:58 AM UTC 24 Sep 10 06:53:34 AM UTC 24 78186075907 ps
T2143 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.26914950 Sep 10 06:52:51 AM UTC 24 Sep 10 06:53:38 AM UTC 24 1632099594 ps
T2144 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.1376180220 Sep 10 06:53:31 AM UTC 24 Sep 10 06:53:40 AM UTC 24 177174058 ps
T2145 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.4009366080 Sep 10 06:52:30 AM UTC 24 Sep 10 06:53:42 AM UTC 24 604881663 ps
T2146 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.574770479 Sep 10 06:52:05 AM UTC 24 Sep 10 06:53:44 AM UTC 24 289606177 ps
T2147 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3294195920 Sep 10 06:53:04 AM UTC 24 Sep 10 06:53:44 AM UTC 24 692443492 ps
T2148 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.1375139891 Sep 10 06:53:38 AM UTC 24 Sep 10 06:53:47 AM UTC 24 40382000 ps
T2149 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.2374079042 Sep 10 06:53:02 AM UTC 24 Sep 10 06:53:47 AM UTC 24 926943692 ps
T2150 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.2319461296 Sep 10 06:50:30 AM UTC 24 Sep 10 06:53:49 AM UTC 24 10767884047 ps
T2151 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.2329939280 Sep 10 06:52:17 AM UTC 24 Sep 10 06:53:53 AM UTC 24 7835873114 ps
T2152 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.1138111734 Sep 10 06:52:23 AM UTC 24 Sep 10 06:53:54 AM UTC 24 4488581713 ps
T2153 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.2805075643 Sep 10 06:50:46 AM UTC 24 Sep 10 06:53:55 AM UTC 24 651260239 ps
T2154 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.2844631222 Sep 10 06:52:00 AM UTC 24 Sep 10 06:53:56 AM UTC 24 1380741258 ps
T2155 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.1654574030 Sep 10 06:30:24 AM UTC 24 Sep 10 06:54:08 AM UTC 24 91832995525 ps
T2156 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.2299177915 Sep 10 06:53:11 AM UTC 24 Sep 10 06:54:13 AM UTC 24 930366366 ps
T2157 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.3552548379 Sep 10 06:49:40 AM UTC 24 Sep 10 06:54:14 AM UTC 24 7694990519 ps
T2158 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.3485534009 Sep 10 06:44:54 AM UTC 24 Sep 10 06:54:22 AM UTC 24 55730477347 ps
T2159 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.1015265825 Sep 10 06:52:10 AM UTC 24 Sep 10 06:54:28 AM UTC 24 2063893092 ps
T2160 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.87131980 Sep 10 06:54:15 AM UTC 24 Sep 10 06:54:30 AM UTC 24 264463076 ps
T2161 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.140730681 Sep 10 06:54:04 AM UTC 24 Sep 10 06:54:33 AM UTC 24 778409081 ps
T2162 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.260131575 Sep 10 06:45:20 AM UTC 24 Sep 10 06:54:33 AM UTC 24 14523567173 ps
T2163 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.1764722248 Sep 10 06:52:09 AM UTC 24 Sep 10 06:54:34 AM UTC 24 4126063126 ps
T2164 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.3740444816 Sep 10 06:54:15 AM UTC 24 Sep 10 06:54:36 AM UTC 24 401926855 ps
T2165 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.3157664781 Sep 10 06:54:08 AM UTC 24 Sep 10 06:54:46 AM UTC 24 492252390 ps
T2166 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.1511995125 Sep 10 06:54:42 AM UTC 24 Sep 10 06:54:55 AM UTC 24 249854608 ps
T2167 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.453449695 Sep 10 06:54:49 AM UTC 24 Sep 10 06:54:58 AM UTC 24 44437973 ps
T2168 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.2914308821 Sep 10 06:54:01 AM UTC 24 Sep 10 06:55:04 AM UTC 24 4051828542 ps
T2169 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.3287013989 Sep 10 06:54:20 AM UTC 24 Sep 10 06:55:11 AM UTC 24 1235894669 ps
T2170 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.1740980916 Sep 10 06:54:59 AM UTC 24 Sep 10 06:55:13 AM UTC 24 66260855 ps
T2171 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.1353399064 Sep 10 06:48:19 AM UTC 24 Sep 10 06:55:14 AM UTC 24 28071706786 ps
T2172 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.1654926550 Sep 10 06:54:22 AM UTC 24 Sep 10 06:55:21 AM UTC 24 1204107994 ps
T2173 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.589551285 Sep 10 06:54:35 AM UTC 24 Sep 10 06:55:21 AM UTC 24 631678858 ps
T2174 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.1572752007 Sep 10 06:46:58 AM UTC 24 Sep 10 06:55:22 AM UTC 24 49332189181 ps
T2175 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.274998805 Sep 10 06:53:52 AM UTC 24 Sep 10 06:55:23 AM UTC 24 8325616739 ps
T2176 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.140897699 Sep 10 06:55:02 AM UTC 24 Sep 10 06:55:24 AM UTC 24 224600679 ps
T833 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2154335330 Sep 10 06:27:53 AM UTC 24 Sep 10 06:55:34 AM UTC 24 118095596885 ps
T2177 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.1191042200 Sep 10 06:38:32 AM UTC 24 Sep 10 06:55:42 AM UTC 24 99741179213 ps
T2178 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.19846375 Sep 10 06:53:10 AM UTC 24 Sep 10 06:55:45 AM UTC 24 577986003 ps
T2179 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.2231895665 Sep 10 06:46:05 AM UTC 24 Sep 10 06:55:46 AM UTC 24 33882925607 ps
T2180 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.2633591179 Sep 10 06:46:14 AM UTC 24 Sep 10 06:55:49 AM UTC 24 17356967972 ps
T2181 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.3739099279 Sep 10 06:50:55 AM UTC 24 Sep 10 06:55:49 AM UTC 24 4979072519 ps
T2182 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.1099330591 Sep 10 06:52:37 AM UTC 24 Sep 10 06:55:52 AM UTC 24 12373600812 ps
T2183 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.4256599594 Sep 10 06:54:55 AM UTC 24 Sep 10 06:55:52 AM UTC 24 5697838833 ps
T2184 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.1870649246 Sep 10 06:39:40 AM UTC 24 Sep 10 06:55:53 AM UTC 24 59170552031 ps
T2185 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.2159760185 Sep 10 06:55:39 AM UTC 24 Sep 10 06:55:56 AM UTC 24 124250018 ps
T2186 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.1981931203 Sep 10 06:55:49 AM UTC 24 Sep 10 06:55:56 AM UTC 24 44446876 ps
T2187 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.214653232 Sep 10 06:44:55 AM UTC 24 Sep 10 06:55:59 AM UTC 24 40110769774 ps
T2188 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.265170226 Sep 10 06:53:07 AM UTC 24 Sep 10 06:56:00 AM UTC 24 1957070223 ps
T2189 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.1207628217 Sep 10 06:54:09 AM UTC 24 Sep 10 06:56:00 AM UTC 24 2619165862 ps
T2190 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.2903647728 Sep 10 06:55:13 AM UTC 24 Sep 10 06:56:02 AM UTC 24 556348089 ps
T2191 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.2975798400 Sep 10 06:55:52 AM UTC 24 Sep 10 06:56:03 AM UTC 24 57676311 ps
T2192 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.2870525464 Sep 10 06:54:14 AM UTC 24 Sep 10 06:56:04 AM UTC 24 5845706876 ps
T2193 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.1749293362 Sep 10 06:55:36 AM UTC 24 Sep 10 06:56:18 AM UTC 24 1043325716 ps
T789 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.633701848 Sep 10 06:24:39 AM UTC 24 Sep 10 06:56:29 AM UTC 24 100757570061 ps
T2194 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.2555364303 Sep 10 06:48:48 AM UTC 24 Sep 10 06:56:30 AM UTC 24 7080599829 ps
T2195 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.2921406675 Sep 10 06:55:24 AM UTC 24 Sep 10 06:56:33 AM UTC 24 2411330836 ps
T2196 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.1046249320 Sep 10 06:56:13 AM UTC 24 Sep 10 06:56:34 AM UTC 24 190444200 ps
T2197 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.2418387489 Sep 10 06:56:18 AM UTC 24 Sep 10 06:56:36 AM UTC 24 178582057 ps
T2198 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.1723336635 Sep 10 06:54:59 AM UTC 24 Sep 10 06:56:36 AM UTC 24 6297639918 ps
T2199 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.705387695 Sep 10 06:56:28 AM UTC 24 Sep 10 06:56:37 AM UTC 24 37182342 ps
T2200 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.178367097 Sep 10 06:55:32 AM UTC 24 Sep 10 06:56:39 AM UTC 24 2024469504 ps
T2201 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.1063086872 Sep 10 06:56:24 AM UTC 24 Sep 10 06:56:41 AM UTC 24 304812220 ps
T2202 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.2304890594 Sep 10 06:56:22 AM UTC 24 Sep 10 06:56:42 AM UTC 24 154297932 ps
T2203 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.2910684235 Sep 10 06:56:45 AM UTC 24 Sep 10 06:56:54 AM UTC 24 45294976 ps
T2204 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.2553137982 Sep 10 06:56:09 AM UTC 24 Sep 10 06:57:06 AM UTC 24 620589133 ps
T2205 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.1562481392 Sep 10 06:43:19 AM UTC 24 Sep 10 06:57:10 AM UTC 24 85093151461 ps
T2206 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.2550271490 Sep 10 06:56:01 AM UTC 24 Sep 10 06:57:22 AM UTC 24 8191084332 ps
T2207 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.1338630353 Sep 10 06:56:21 AM UTC 24 Sep 10 06:57:24 AM UTC 24 1305498838 ps
T2208 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.4005112573 Sep 10 06:56:58 AM UTC 24 Sep 10 06:57:24 AM UTC 24 685655198 ps
T2209 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.576362426 Sep 10 06:57:01 AM UTC 24 Sep 10 06:57:32 AM UTC 24 349504361 ps
T2210 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.1011730622 Sep 10 06:56:22 AM UTC 24 Sep 10 06:57:32 AM UTC 24 1143468227 ps
T2211 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.1959293826 Sep 10 06:56:10 AM UTC 24 Sep 10 06:57:37 AM UTC 24 4979722810 ps
T2212 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.3406135090 Sep 10 06:57:08 AM UTC 24 Sep 10 06:57:44 AM UTC 24 1353558478 ps
T2213 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.336931101 Sep 10 06:50:42 AM UTC 24 Sep 10 06:57:48 AM UTC 24 13561939883 ps
T2214 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.375651026 Sep 10 06:29:12 AM UTC 24 Sep 10 06:57:53 AM UTC 24 105935779576 ps
T2215 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.2623147113 Sep 10 06:57:22 AM UTC 24 Sep 10 06:58:06 AM UTC 24 328660732 ps
T2216 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.1824563244 Sep 10 06:57:58 AM UTC 24 Sep 10 06:58:07 AM UTC 24 52670157 ps
T2217 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.2505354615 Sep 10 06:39:36 AM UTC 24 Sep 10 06:58:08 AM UTC 24 95123440393 ps
T2218 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.2240654046 Sep 10 06:57:56 AM UTC 24 Sep 10 06:58:08 AM UTC 24 174168683 ps
T2219 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.1923967134 Sep 10 06:57:09 AM UTC 24 Sep 10 06:58:08 AM UTC 24 592614726 ps
T2220 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.2990599101 Sep 10 06:56:19 AM UTC 24 Sep 10 06:58:11 AM UTC 24 3012138923 ps
T2221 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.3328097000 Sep 10 06:56:57 AM UTC 24 Sep 10 06:58:12 AM UTC 24 8049001054 ps
T2222 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.3392570348 Sep 10 06:56:56 AM UTC 24 Sep 10 06:58:21 AM UTC 24 5010237558 ps
T2223 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.43118301 Sep 10 06:55:02 AM UTC 24 Sep 10 06:58:24 AM UTC 24 14214088501 ps
T2224 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.931064412 Sep 10 06:57:34 AM UTC 24 Sep 10 06:58:29 AM UTC 24 1378599637 ps
T2225 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.2795224744 Sep 10 06:45:55 AM UTC 24 Sep 10 06:58:32 AM UTC 24 82790050124 ps
T2226 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.3694575346 Sep 10 06:56:29 AM UTC 24 Sep 10 06:58:34 AM UTC 24 1587304412 ps
T2227 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.889406860 Sep 10 06:58:17 AM UTC 24 Sep 10 06:58:35 AM UTC 24 124974600 ps
T2228 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.3722850188 Sep 10 06:54:23 AM UTC 24 Sep 10 06:58:36 AM UTC 24 3020774199 ps
T2229 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.1369420939 Sep 10 06:58:19 AM UTC 24 Sep 10 06:58:37 AM UTC 24 138208786 ps
T2230 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.672412042 Sep 10 06:51:30 AM UTC 24 Sep 10 06:58:41 AM UTC 24 26464677447 ps
T2231 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.1394487881 Sep 10 06:53:23 AM UTC 24 Sep 10 06:58:45 AM UTC 24 1771862970 ps
T2232 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.1827767249 Sep 10 06:58:10 AM UTC 24 Sep 10 06:58:55 AM UTC 24 2791067824 ps
T2233 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.2348997101 Sep 10 06:58:39 AM UTC 24 Sep 10 06:59:01 AM UTC 24 167163388 ps
T2234 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.2704662238 Sep 10 06:57:04 AM UTC 24 Sep 10 06:59:09 AM UTC 24 2496537590 ps
T2235 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.75328805 Sep 10 06:58:49 AM UTC 24 Sep 10 06:59:10 AM UTC 24 419455268 ps
T2236 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.744781510 Sep 10 06:59:00 AM UTC 24 Sep 10 06:59:10 AM UTC 24 41849328 ps
T2237 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.3220971276 Sep 10 06:58:37 AM UTC 24 Sep 10 06:59:11 AM UTC 24 319738970 ps
T2238 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.3983573346 Sep 10 06:57:51 AM UTC 24 Sep 10 06:59:12 AM UTC 24 243069343 ps
T2239 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.1667461728 Sep 10 06:58:05 AM UTC 24 Sep 10 06:59:15 AM UTC 24 6773673005 ps
T2240 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.139435939 Sep 10 06:59:04 AM UTC 24 Sep 10 06:59:19 AM UTC 24 255088948 ps
T2241 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.3709680807 Sep 10 06:58:41 AM UTC 24 Sep 10 06:59:19 AM UTC 24 705872889 ps
T2242 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.127073022 Sep 10 06:57:38 AM UTC 24 Sep 10 06:59:35 AM UTC 24 1299414870 ps
T2243 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1644305418 Sep 10 06:54:40 AM UTC 24 Sep 10 06:59:40 AM UTC 24 1639297315 ps
T2244 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.2911813210 Sep 10 06:58:33 AM UTC 24 Sep 10 06:59:47 AM UTC 24 1891573539 ps
T2245 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.2470819915 Sep 10 06:59:21 AM UTC 24 Sep 10 06:59:49 AM UTC 24 320130273 ps
T2246 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.2616098667 Sep 10 06:49:19 AM UTC 24 Sep 10 06:59:50 AM UTC 24 42579277819 ps
T2247 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.226134664 Sep 10 06:59:13 AM UTC 24 Sep 10 07:00:01 AM UTC 24 1455034966 ps
T2248 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.3099343842 Sep 10 06:59:37 AM UTC 24 Sep 10 07:00:09 AM UTC 24 817652522 ps
T2249 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.3839992144 Sep 10 06:58:57 AM UTC 24 Sep 10 07:00:16 AM UTC 24 2149067327 ps
T2250 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.446110227 Sep 10 06:59:47 AM UTC 24 Sep 10 07:00:21 AM UTC 24 247627577 ps
T2251 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.733119228 Sep 10 06:59:36 AM UTC 24 Sep 10 07:00:22 AM UTC 24 1390102126 ps
T2252 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.1864272937 Sep 10 07:00:17 AM UTC 24 Sep 10 07:00:25 AM UTC 24 41856141 ps
T2253 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.2812874284 Sep 10 07:00:16 AM UTC 24 Sep 10 07:00:25 AM UTC 24 41621937 ps
T2254 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.4114506257 Sep 10 06:56:21 AM UTC 24 Sep 10 07:00:28 AM UTC 24 2871848628 ps
T2255 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.543395215 Sep 10 06:59:42 AM UTC 24 Sep 10 07:00:28 AM UTC 24 325194516 ps
T512 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.2462147044 Sep 10 06:37:22 AM UTC 24 Sep 10 07:00:33 AM UTC 24 94928079938 ps
T2256 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.2168613727 Sep 10 06:58:50 AM UTC 24 Sep 10 07:00:38 AM UTC 24 1095339207 ps
T2257 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.1182417884 Sep 10 06:59:02 AM UTC 24 Sep 10 07:00:44 AM UTC 24 8054482358 ps
T2258 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.2982830655 Sep 10 06:58:53 AM UTC 24 Sep 10 07:00:45 AM UTC 24 294839765 ps
T2259 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.1961126115 Sep 10 06:59:36 AM UTC 24 Sep 10 07:00:46 AM UTC 24 2066775710 ps
T2260 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.2416023926 Sep 10 06:59:09 AM UTC 24 Sep 10 07:00:50 AM UTC 24 6863219002 ps
T2261 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.2894349102 Sep 10 07:00:44 AM UTC 24 Sep 10 07:00:53 AM UTC 24 167902379 ps
T2262 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.3905026503 Sep 10 06:56:13 AM UTC 24 Sep 10 07:01:10 AM UTC 24 33914679179 ps
T2263 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.688744120 Sep 10 06:40:57 AM UTC 24 Sep 10 07:01:10 AM UTC 24 81377593350 ps
T2264 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.1109655251 Sep 10 07:01:11 AM UTC 24 Sep 10 07:01:18 AM UTC 24 94757537 ps
T2265 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.904737384 Sep 10 07:01:05 AM UTC 24 Sep 10 07:01:19 AM UTC 24 259475455 ps
T2266 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.4104102434 Sep 10 07:01:00 AM UTC 24 Sep 10 07:01:22 AM UTC 24 194819672 ps
T2267 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.2884642474 Sep 10 06:54:19 AM UTC 24 Sep 10 07:01:24 AM UTC 24 3688300591 ps
T2268 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.1326347091 Sep 10 06:57:52 AM UTC 24 Sep 10 07:01:25 AM UTC 24 3029772652 ps
T2269 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.1512765788 Sep 10 06:55:23 AM UTC 24 Sep 10 07:01:28 AM UTC 24 26262000521 ps
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