| T460 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1949166182 |
|
|
Sep 10 05:03:46 AM UTC 24 |
Sep 10 05:34:53 AM UTC 24 |
115314305837 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.2434649574 |
|
|
Sep 10 05:25:25 AM UTC 24 |
Sep 10 05:34:55 AM UTC 24 |
31020941378 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.714999228 |
|
|
Sep 10 05:26:56 AM UTC 24 |
Sep 10 05:34:56 AM UTC 24 |
9363480153 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.2984691966 |
|
|
Sep 10 05:32:36 AM UTC 24 |
Sep 10 05:35:20 AM UTC 24 |
1741914222 ps |
| T1403 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.3226710793 |
|
|
Sep 10 05:35:10 AM UTC 24 |
Sep 10 05:35:27 AM UTC 24 |
62557378 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1137002189 |
|
|
Sep 10 05:31:41 AM UTC 24 |
Sep 10 05:35:33 AM UTC 24 |
16384156890 ps |
| T1404 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.2422787344 |
|
|
Sep 10 05:33:49 AM UTC 24 |
Sep 10 05:35:40 AM UTC 24 |
9563773172 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.667036917 |
|
|
Sep 10 05:22:24 AM UTC 24 |
Sep 10 05:35:43 AM UTC 24 |
66054996482 ps |
| T1405 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.3512702604 |
|
|
Sep 10 05:33:59 AM UTC 24 |
Sep 10 05:35:44 AM UTC 24 |
2209662106 ps |
| T1406 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.824656568 |
|
|
Sep 10 05:35:18 AM UTC 24 |
Sep 10 05:35:51 AM UTC 24 |
555222523 ps |
| T1407 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.547508464 |
|
|
Sep 10 05:34:13 AM UTC 24 |
Sep 10 05:36:02 AM UTC 24 |
10720805828 ps |
| T1408 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3509749809 |
|
|
Sep 10 05:33:54 AM UTC 24 |
Sep 10 05:36:04 AM UTC 24 |
5371259046 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.1214433581 |
|
|
Sep 10 05:27:31 AM UTC 24 |
Sep 10 05:36:06 AM UTC 24 |
4768706567 ps |
| T1409 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.414528820 |
|
|
Sep 10 05:28:41 AM UTC 24 |
Sep 10 05:36:17 AM UTC 24 |
28549936182 ps |
| T1410 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.3775844034 |
|
|
Sep 10 05:30:13 AM UTC 24 |
Sep 10 05:36:18 AM UTC 24 |
4612043604 ps |
| T1411 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.3580504956 |
|
|
Sep 10 05:36:11 AM UTC 24 |
Sep 10 05:36:22 AM UTC 24 |
197929738 ps |
| T1412 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2970279226 |
|
|
Sep 10 05:36:18 AM UTC 24 |
Sep 10 05:36:29 AM UTC 24 |
48917876 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2307744818 |
|
|
Sep 10 05:32:37 AM UTC 24 |
Sep 10 05:36:31 AM UTC 24 |
535706753 ps |
| T1413 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.1185449286 |
|
|
Sep 10 05:35:06 AM UTC 24 |
Sep 10 05:36:33 AM UTC 24 |
1948737621 ps |
| T1414 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.3287211578 |
|
|
Sep 10 05:34:53 AM UTC 24 |
Sep 10 05:36:33 AM UTC 24 |
2574806799 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.2148618068 |
|
|
Sep 10 05:30:20 AM UTC 24 |
Sep 10 05:36:49 AM UTC 24 |
4507280701 ps |
| T1415 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.2604728157 |
|
|
Sep 10 05:36:44 AM UTC 24 |
Sep 10 05:37:15 AM UTC 24 |
212174401 ps |
| T1416 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.652058898 |
|
|
Sep 10 05:36:34 AM UTC 24 |
Sep 10 05:37:22 AM UTC 24 |
490848304 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.903118191 |
|
|
Sep 10 05:37:00 AM UTC 24 |
Sep 10 05:37:27 AM UTC 24 |
274515933 ps |
| T1417 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.141509931 |
|
|
Sep 10 05:37:14 AM UTC 24 |
Sep 10 05:37:29 AM UTC 24 |
167347571 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.2335750981 |
|
|
Sep 10 05:33:27 AM UTC 24 |
Sep 10 05:37:38 AM UTC 24 |
3395629316 ps |
| T1418 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.803818399 |
|
|
Sep 10 05:27:43 AM UTC 24 |
Sep 10 05:37:42 AM UTC 24 |
6190600846 ps |
| T1419 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3433679963 |
|
|
Sep 10 05:36:29 AM UTC 24 |
Sep 10 05:37:54 AM UTC 24 |
5937613548 ps |
| T1420 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3198830543 |
|
|
Sep 10 05:37:41 AM UTC 24 |
Sep 10 05:37:59 AM UTC 24 |
235853100 ps |
| T1421 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3810295388 |
|
|
Sep 10 05:30:12 AM UTC 24 |
Sep 10 05:38:13 AM UTC 24 |
5813502000 ps |
| T1422 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.3696875884 |
|
|
Sep 10 05:36:45 AM UTC 24 |
Sep 10 05:38:14 AM UTC 24 |
8662494245 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.1051641692 |
|
|
Sep 10 05:29:59 AM UTC 24 |
Sep 10 05:38:20 AM UTC 24 |
13462792854 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.4056085128 |
|
|
Sep 10 05:36:56 AM UTC 24 |
Sep 10 05:38:31 AM UTC 24 |
1024571248 ps |
| T1423 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.2785036051 |
|
|
Sep 10 05:36:30 AM UTC 24 |
Sep 10 05:38:33 AM UTC 24 |
7783197343 ps |
| T1424 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.835839733 |
|
|
Sep 10 05:37:02 AM UTC 24 |
Sep 10 05:38:36 AM UTC 24 |
1944970699 ps |
| T1425 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.3379732079 |
|
|
Sep 10 05:24:34 AM UTC 24 |
Sep 10 05:38:37 AM UTC 24 |
9966792216 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.1322288628 |
|
|
Sep 10 05:32:41 AM UTC 24 |
Sep 10 05:38:42 AM UTC 24 |
7843653893 ps |
| T1426 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.210925007 |
|
|
Sep 10 05:38:40 AM UTC 24 |
Sep 10 05:38:49 AM UTC 24 |
42651814 ps |
| T1427 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.360408259 |
|
|
Sep 10 05:38:47 AM UTC 24 |
Sep 10 05:38:58 AM UTC 24 |
50415762 ps |
| T1428 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.955825944 |
|
|
Sep 10 05:33:01 AM UTC 24 |
Sep 10 05:38:59 AM UTC 24 |
4370722122 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2374532154 |
|
|
Sep 10 05:35:48 AM UTC 24 |
Sep 10 05:39:11 AM UTC 24 |
1131072672 ps |
| T1429 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.489709298 |
|
|
Sep 10 05:27:38 AM UTC 24 |
Sep 10 05:39:20 AM UTC 24 |
6346092618 ps |
| T1430 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.3324782517 |
|
|
Sep 10 05:39:03 AM UTC 24 |
Sep 10 05:39:30 AM UTC 24 |
271271648 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3814217090 |
|
|
Sep 10 05:35:22 AM UTC 24 |
Sep 10 05:39:40 AM UTC 24 |
1152898859 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.635642975 |
|
|
Sep 10 05:39:03 AM UTC 24 |
Sep 10 05:39:51 AM UTC 24 |
558082426 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.4028833396 |
|
|
Sep 10 05:39:24 AM UTC 24 |
Sep 10 05:39:54 AM UTC 24 |
186731158 ps |
| T1431 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.301715719 |
|
|
Sep 10 05:39:37 AM UTC 24 |
Sep 10 05:39:58 AM UTC 24 |
138419599 ps |
| T1432 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.57295215 |
|
|
Sep 10 05:39:45 AM UTC 24 |
Sep 10 05:39:59 AM UTC 24 |
163991517 ps |
| T1433 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.3828773200 |
|
|
Sep 10 05:39:01 AM UTC 24 |
Sep 10 05:40:01 AM UTC 24 |
4520168802 ps |
| T1434 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.489608505 |
|
|
Sep 10 05:34:18 AM UTC 24 |
Sep 10 05:40:03 AM UTC 24 |
17456974472 ps |
| T1435 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.2158008594 |
|
|
Sep 10 05:35:24 AM UTC 24 |
Sep 10 05:40:08 AM UTC 24 |
3472830266 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.4118532508 |
|
|
Sep 10 05:15:06 AM UTC 24 |
Sep 10 05:40:27 AM UTC 24 |
101975155205 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.3591630764 |
|
|
Sep 10 05:36:10 AM UTC 24 |
Sep 10 05:40:33 AM UTC 24 |
3831583838 ps |
| T1436 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.1866630998 |
|
|
Sep 10 05:40:07 AM UTC 24 |
Sep 10 05:40:33 AM UTC 24 |
437352301 ps |
| T1437 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.234603068 |
|
|
Sep 10 05:38:59 AM UTC 24 |
Sep 10 05:40:57 AM UTC 24 |
7103068337 ps |
| T1438 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.1326531664 |
|
|
Sep 10 05:39:58 AM UTC 24 |
Sep 10 05:41:03 AM UTC 24 |
1374729699 ps |
| T1439 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.3058918094 |
|
|
Sep 10 05:41:00 AM UTC 24 |
Sep 10 05:41:10 AM UTC 24 |
45477159 ps |
| T1440 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.3202102528 |
|
|
Sep 10 05:41:00 AM UTC 24 |
Sep 10 05:41:13 AM UTC 24 |
198166234 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.262918741 |
|
|
Sep 10 05:38:41 AM UTC 24 |
Sep 10 05:41:28 AM UTC 24 |
3238194329 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.845897790 |
|
|
Sep 10 05:29:58 AM UTC 24 |
Sep 10 05:41:33 AM UTC 24 |
13101104342 ps |
| T1441 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.2574126655 |
|
|
Sep 10 05:31:24 AM UTC 24 |
Sep 10 05:41:46 AM UTC 24 |
66967734523 ps |
| T1442 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.2866316574 |
|
|
Sep 10 05:41:38 AM UTC 24 |
Sep 10 05:41:58 AM UTC 24 |
130916190 ps |
| T1443 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.3632853618 |
|
|
Sep 10 05:41:40 AM UTC 24 |
Sep 10 05:42:35 AM UTC 24 |
456644074 ps |
| T1444 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3802352045 |
|
|
Sep 10 05:41:30 AM UTC 24 |
Sep 10 05:42:40 AM UTC 24 |
4798306984 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.1877813588 |
|
|
Sep 10 05:42:13 AM UTC 24 |
Sep 10 05:42:46 AM UTC 24 |
397612220 ps |
| T1445 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.1723152487 |
|
|
Sep 10 05:41:19 AM UTC 24 |
Sep 10 05:42:53 AM UTC 24 |
8053519526 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.4043726798 |
|
|
Sep 10 05:08:09 AM UTC 24 |
Sep 10 05:42:54 AM UTC 24 |
13818391587 ps |
| T1446 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.3880365843 |
|
|
Sep 10 05:31:27 AM UTC 24 |
Sep 10 05:42:54 AM UTC 24 |
37080823733 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1088981568 |
|
|
Sep 10 05:23:49 AM UTC 24 |
Sep 10 05:42:56 AM UTC 24 |
11205305128 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.2033137363 |
|
|
Sep 10 05:35:20 AM UTC 24 |
Sep 10 05:43:00 AM UTC 24 |
12035431141 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2640973180 |
|
|
Sep 10 05:25:33 AM UTC 24 |
Sep 10 05:43:05 AM UTC 24 |
72363185743 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.3108381236 |
|
|
Sep 10 05:22:26 AM UTC 24 |
Sep 10 05:43:20 AM UTC 24 |
81288112702 ps |
| T1447 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.27775993 |
|
|
Sep 10 05:39:09 AM UTC 24 |
Sep 10 05:43:22 AM UTC 24 |
25875317298 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.3644086355 |
|
|
Sep 10 05:37:56 AM UTC 24 |
Sep 10 05:43:34 AM UTC 24 |
8535654647 ps |
| T1448 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.1102751038 |
|
|
Sep 10 05:43:20 AM UTC 24 |
Sep 10 05:43:40 AM UTC 24 |
133758032 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.405657945 |
|
|
Sep 10 05:43:12 AM UTC 24 |
Sep 10 05:43:50 AM UTC 24 |
206981336 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1977840661 |
|
|
Sep 10 05:36:59 AM UTC 24 |
Sep 10 05:43:52 AM UTC 24 |
24708071475 ps |
| T1449 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.1356328436 |
|
|
Sep 10 05:43:03 AM UTC 24 |
Sep 10 05:44:03 AM UTC 24 |
1611168567 ps |
| T1450 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.2646572424 |
|
|
Sep 10 05:43:06 AM UTC 24 |
Sep 10 05:44:18 AM UTC 24 |
1667403781 ps |
| T1451 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.3914179927 |
|
|
Sep 10 05:44:07 AM UTC 24 |
Sep 10 05:44:23 AM UTC 24 |
239877044 ps |
| T1452 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.1969703270 |
|
|
Sep 10 05:44:17 AM UTC 24 |
Sep 10 05:44:25 AM UTC 24 |
55997945 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.2028002585 |
|
|
Sep 10 05:37:50 AM UTC 24 |
Sep 10 05:44:36 AM UTC 24 |
3724072486 ps |
| T1453 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.1346671773 |
|
|
Sep 10 05:44:19 AM UTC 24 |
Sep 10 05:45:17 AM UTC 24 |
6325383282 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.2904386379 |
|
|
Sep 10 05:44:49 AM UTC 24 |
Sep 10 05:45:25 AM UTC 24 |
364949044 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.1866662257 |
|
|
Sep 10 05:40:55 AM UTC 24 |
Sep 10 05:45:35 AM UTC 24 |
3599583892 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.140801205 |
|
|
Sep 10 05:44:45 AM UTC 24 |
Sep 10 05:46:00 AM UTC 24 |
1502637630 ps |
| T1454 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.2008675223 |
|
|
Sep 10 05:45:53 AM UTC 24 |
Sep 10 05:46:04 AM UTC 24 |
60151902 ps |
| T1455 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.632080099 |
|
|
Sep 10 05:45:44 AM UTC 24 |
Sep 10 05:46:23 AM UTC 24 |
315574104 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.2710328052 |
|
|
Sep 10 05:40:24 AM UTC 24 |
Sep 10 05:46:26 AM UTC 24 |
6796271624 ps |
| T1456 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.3498153640 |
|
|
Sep 10 05:46:02 AM UTC 24 |
Sep 10 05:46:31 AM UTC 24 |
425552573 ps |
| T1457 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.3326555842 |
|
|
Sep 10 05:46:25 AM UTC 24 |
Sep 10 05:46:38 AM UTC 24 |
121387472 ps |
| T1458 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1763252544 |
|
|
Sep 10 05:44:30 AM UTC 24 |
Sep 10 05:46:41 AM UTC 24 |
5348639620 ps |
| T1459 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.2855904225 |
|
|
Sep 10 05:40:26 AM UTC 24 |
Sep 10 05:46:49 AM UTC 24 |
12258714722 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.3785781523 |
|
|
Sep 10 05:45:27 AM UTC 24 |
Sep 10 05:47:02 AM UTC 24 |
2702946148 ps |
| T1460 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.1565919834 |
|
|
Sep 10 05:40:28 AM UTC 24 |
Sep 10 05:47:12 AM UTC 24 |
4062138096 ps |
| T1461 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.3629271952 |
|
|
Sep 10 05:47:30 AM UTC 24 |
Sep 10 05:47:39 AM UTC 24 |
38037677 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.3974231811 |
|
|
Sep 10 05:40:15 AM UTC 24 |
Sep 10 05:47:41 AM UTC 24 |
10033906785 ps |
| T1462 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.390043452 |
|
|
Sep 10 05:47:40 AM UTC 24 |
Sep 10 05:47:52 AM UTC 24 |
55817505 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1936108150 |
|
|
Sep 10 05:43:24 AM UTC 24 |
Sep 10 05:47:56 AM UTC 24 |
808648035 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.2983593774 |
|
|
Sep 10 05:46:31 AM UTC 24 |
Sep 10 05:48:12 AM UTC 24 |
243773783 ps |
| T1463 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.2124465112 |
|
|
Sep 10 05:35:54 AM UTC 24 |
Sep 10 05:48:18 AM UTC 24 |
5572076288 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3817727570 |
|
|
Sep 10 05:38:04 AM UTC 24 |
Sep 10 05:48:25 AM UTC 24 |
4636323508 ps |
| T1464 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.3844810393 |
|
|
Sep 10 05:46:27 AM UTC 24 |
Sep 10 05:48:36 AM UTC 24 |
1388739544 ps |
| T1465 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.1155796993 |
|
|
Sep 10 05:48:23 AM UTC 24 |
Sep 10 05:48:49 AM UTC 24 |
208094176 ps |
| T1466 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.2873348313 |
|
|
Sep 10 05:48:08 AM UTC 24 |
Sep 10 05:49:08 AM UTC 24 |
5329284327 ps |
| T1467 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.420283822 |
|
|
Sep 10 05:33:01 AM UTC 24 |
Sep 10 05:49:12 AM UTC 24 |
10803075584 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.4254451003 |
|
|
Sep 10 05:43:58 AM UTC 24 |
Sep 10 05:49:25 AM UTC 24 |
4160169112 ps |
| T1468 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.1033150289 |
|
|
Sep 10 05:48:19 AM UTC 24 |
Sep 10 05:49:31 AM UTC 24 |
1794526069 ps |
| T1469 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.1032180445 |
|
|
Sep 10 05:46:48 AM UTC 24 |
Sep 10 05:49:32 AM UTC 24 |
2027719209 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.112096402 |
|
|
Sep 10 05:48:52 AM UTC 24 |
Sep 10 05:49:35 AM UTC 24 |
524138019 ps |
| T1470 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.2134662320 |
|
|
Sep 10 05:49:17 AM UTC 24 |
Sep 10 05:49:38 AM UTC 24 |
551958205 ps |
| T1471 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.1665387999 |
|
|
Sep 10 05:48:09 AM UTC 24 |
Sep 10 05:49:40 AM UTC 24 |
6070964494 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.2063583840 |
|
|
Sep 10 05:36:48 AM UTC 24 |
Sep 10 05:49:45 AM UTC 24 |
54647041015 ps |
| T1472 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.2205982783 |
|
|
Sep 10 05:49:52 AM UTC 24 |
Sep 10 05:50:03 AM UTC 24 |
57705711 ps |
| T1473 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.1166715598 |
|
|
Sep 10 05:43:33 AM UTC 24 |
Sep 10 05:50:04 AM UTC 24 |
4699364312 ps |
| T1474 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.644650015 |
|
|
Sep 10 05:35:59 AM UTC 24 |
Sep 10 05:50:09 AM UTC 24 |
11968488718 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.3526985177 |
|
|
Sep 10 05:43:19 AM UTC 24 |
Sep 10 05:50:15 AM UTC 24 |
12145313200 ps |
| T1475 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.2574858411 |
|
|
Sep 10 05:45:35 AM UTC 24 |
Sep 10 05:50:15 AM UTC 24 |
19972624587 ps |
| T1476 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.3674886741 |
|
|
Sep 10 05:49:37 AM UTC 24 |
Sep 10 05:50:16 AM UTC 24 |
695251402 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.3844409117 |
|
|
Sep 10 05:47:16 AM UTC 24 |
Sep 10 05:50:19 AM UTC 24 |
3245880864 ps |
| T1477 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.164421722 |
|
|
Sep 10 05:45:03 AM UTC 24 |
Sep 10 05:50:38 AM UTC 24 |
16227080004 ps |
| T1478 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.1944320563 |
|
|
Sep 10 05:50:36 AM UTC 24 |
Sep 10 05:50:45 AM UTC 24 |
45705153 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.4211617059 |
|
|
Sep 10 05:37:54 AM UTC 24 |
Sep 10 05:50:49 AM UTC 24 |
11462705105 ps |
| T1479 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1067866347 |
|
|
Sep 10 05:50:38 AM UTC 24 |
Sep 10 05:50:49 AM UTC 24 |
46879418 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.90903704 |
|
|
Sep 10 05:40:21 AM UTC 24 |
Sep 10 05:50:57 AM UTC 24 |
8340025855 ps |
| T1480 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.4108398093 |
|
|
Sep 10 05:49:34 AM UTC 24 |
Sep 10 05:50:59 AM UTC 24 |
1720819269 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.2870271734 |
|
|
Sep 10 05:38:09 AM UTC 24 |
Sep 10 05:50:59 AM UTC 24 |
5756278706 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.1811456407 |
|
|
Sep 10 05:49:59 AM UTC 24 |
Sep 10 05:51:00 AM UTC 24 |
69075709 ps |
| T1481 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.6712951 |
|
|
Sep 10 05:50:02 AM UTC 24 |
Sep 10 05:51:01 AM UTC 24 |
663268334 ps |
| T1482 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.1426949870 |
|
|
Sep 10 05:42:01 AM UTC 24 |
Sep 10 05:51:05 AM UTC 24 |
31712219784 ps |
| T1483 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1886720172 |
|
|
Sep 10 05:46:54 AM UTC 24 |
Sep 10 05:51:14 AM UTC 24 |
566614950 ps |
| T1484 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.1914379286 |
|
|
Sep 10 05:43:47 AM UTC 24 |
Sep 10 05:51:32 AM UTC 24 |
7493063776 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.1718058354 |
|
|
Sep 10 05:43:20 AM UTC 24 |
Sep 10 05:51:36 AM UTC 24 |
3178810737 ps |
| T1485 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.1458297142 |
|
|
Sep 10 05:50:46 AM UTC 24 |
Sep 10 05:51:43 AM UTC 24 |
1409895170 ps |
| T1486 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.1716420027 |
|
|
Sep 10 05:51:05 AM UTC 24 |
Sep 10 05:51:44 AM UTC 24 |
276649745 ps |
| T1487 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.1685455015 |
|
|
Sep 10 05:51:26 AM UTC 24 |
Sep 10 05:51:44 AM UTC 24 |
312534498 ps |
| T1488 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.2552473094 |
|
|
Sep 10 05:44:52 AM UTC 24 |
Sep 10 05:51:45 AM UTC 24 |
32387924461 ps |
| T1489 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.1409085691 |
|
|
Sep 10 05:50:43 AM UTC 24 |
Sep 10 05:51:48 AM UTC 24 |
4272592392 ps |
| T1490 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.2783860594 |
|
|
Sep 10 05:51:17 AM UTC 24 |
Sep 10 05:51:51 AM UTC 24 |
298279724 ps |
| T1491 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.3835101631 |
|
|
Sep 10 05:51:26 AM UTC 24 |
Sep 10 05:52:00 AM UTC 24 |
398255962 ps |
| T1492 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2731197709 |
|
|
Sep 10 05:51:29 AM UTC 24 |
Sep 10 05:52:07 AM UTC 24 |
848196036 ps |
| T1493 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.1924631770 |
|
|
Sep 10 05:51:26 AM UTC 24 |
Sep 10 05:52:20 AM UTC 24 |
1096821894 ps |
| T1494 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.251160008 |
|
|
Sep 10 05:51:12 AM UTC 24 |
Sep 10 05:52:26 AM UTC 24 |
7041691158 ps |
| T1495 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.415230600 |
|
|
Sep 10 05:52:17 AM UTC 24 |
Sep 10 05:52:28 AM UTC 24 |
52090373 ps |
| T1496 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.1834656282 |
|
|
Sep 10 05:50:42 AM UTC 24 |
Sep 10 05:52:29 AM UTC 24 |
8484379888 ps |
| T1497 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.819149307 |
|
|
Sep 10 05:52:16 AM UTC 24 |
Sep 10 05:52:31 AM UTC 24 |
207705888 ps |
| T1498 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.4137249830 |
|
|
Sep 10 05:48:37 AM UTC 24 |
Sep 10 05:52:37 AM UTC 24 |
19967972573 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.232817810 |
|
|
Sep 10 05:39:26 AM UTC 24 |
Sep 10 05:52:51 AM UTC 24 |
46506097782 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.2362185526 |
|
|
Sep 10 05:51:41 AM UTC 24 |
Sep 10 05:52:54 AM UTC 24 |
249690857 ps |
| T1499 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.3372407829 |
|
|
Sep 10 05:52:52 AM UTC 24 |
Sep 10 05:53:18 AM UTC 24 |
167796396 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2099173813 |
|
|
Sep 10 05:34:42 AM UTC 24 |
Sep 10 05:53:33 AM UTC 24 |
75781407351 ps |
| T1500 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.2029003908 |
|
|
Sep 10 05:53:21 AM UTC 24 |
Sep 10 05:54:01 AM UTC 24 |
447315739 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.799350251 |
|
|
Sep 10 05:27:44 AM UTC 24 |
Sep 10 05:54:08 AM UTC 24 |
15042449215 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.4121419839 |
|
|
Sep 10 05:53:18 AM UTC 24 |
Sep 10 05:54:11 AM UTC 24 |
514689208 ps |
| T1501 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.1638692275 |
|
|
Sep 10 05:54:00 AM UTC 24 |
Sep 10 05:54:11 AM UTC 24 |
97930356 ps |
| T1502 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.4140079092 |
|
|
Sep 10 05:52:25 AM UTC 24 |
Sep 10 05:54:17 AM UTC 24 |
6976344195 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.2022696206 |
|
|
Sep 10 05:53:44 AM UTC 24 |
Sep 10 05:54:21 AM UTC 24 |
244592069 ps |
| T1503 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.1452372988 |
|
|
Sep 10 05:52:46 AM UTC 24 |
Sep 10 05:54:59 AM UTC 24 |
2468226301 ps |
| T1504 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.1008667009 |
|
|
Sep 10 05:52:56 AM UTC 24 |
Sep 10 05:54:23 AM UTC 24 |
820320541 ps |
| T1505 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2798783909 |
|
|
Sep 10 05:52:33 AM UTC 24 |
Sep 10 05:54:32 AM UTC 24 |
5862077024 ps |
| T1506 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.3521431204 |
|
|
Sep 10 05:50:01 AM UTC 24 |
Sep 10 05:54:33 AM UTC 24 |
2335896945 ps |
| T1507 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.3988410275 |
|
|
Sep 10 05:52:53 AM UTC 24 |
Sep 10 05:54:40 AM UTC 24 |
11677193275 ps |
| T1508 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.4223027593 |
|
|
Sep 10 05:39:17 AM UTC 24 |
Sep 10 05:54:41 AM UTC 24 |
55112061680 ps |
| T1509 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.2197053115 |
|
|
Sep 10 05:50:04 AM UTC 24 |
Sep 10 05:55:08 AM UTC 24 |
4004199640 ps |
| T1510 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.1812268212 |
|
|
Sep 10 05:54:59 AM UTC 24 |
Sep 10 05:55:08 AM UTC 24 |
46639059 ps |
| T1511 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.1640812925 |
|
|
Sep 10 05:54:59 AM UTC 24 |
Sep 10 05:55:10 AM UTC 24 |
53193295 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.1273964659 |
|
|
Sep 10 05:43:20 AM UTC 24 |
Sep 10 05:55:10 AM UTC 24 |
16907915688 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.3691571708 |
|
|
Sep 10 05:51:30 AM UTC 24 |
Sep 10 05:55:40 AM UTC 24 |
2901699616 ps |
| T1512 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.3639428666 |
|
|
Sep 10 05:40:26 AM UTC 24 |
Sep 10 05:55:45 AM UTC 24 |
11396917471 ps |
| T1513 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.3939056823 |
|
|
Sep 10 05:55:34 AM UTC 24 |
Sep 10 05:56:13 AM UTC 24 |
312348661 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.3129194756 |
|
|
Sep 10 05:50:30 AM UTC 24 |
Sep 10 05:56:19 AM UTC 24 |
3715388648 ps |
| T1514 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.1046962050 |
|
|
Sep 10 05:55:26 AM UTC 24 |
Sep 10 05:56:25 AM UTC 24 |
1255111204 ps |
| T1515 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.1769995457 |
|
|
Sep 10 05:55:09 AM UTC 24 |
Sep 10 05:56:35 AM UTC 24 |
6193419214 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.2066080208 |
|
|
Sep 10 05:38:18 AM UTC 24 |
Sep 10 05:56:56 AM UTC 24 |
12565869636 ps |
| T1516 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.4294539688 |
|
|
Sep 10 05:56:13 AM UTC 24 |
Sep 10 05:56:59 AM UTC 24 |
488661368 ps |
| T1517 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.963119072 |
|
|
Sep 10 05:52:55 AM UTC 24 |
Sep 10 05:57:00 AM UTC 24 |
15629689824 ps |
| T1518 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.3056845947 |
|
|
Sep 10 05:56:46 AM UTC 24 |
Sep 10 05:57:14 AM UTC 24 |
409746449 ps |
| T1519 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.4140292528 |
|
|
Sep 10 05:55:06 AM UTC 24 |
Sep 10 05:57:21 AM UTC 24 |
8384971668 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.44643446 |
|
|
Sep 10 05:54:39 AM UTC 24 |
Sep 10 05:57:23 AM UTC 24 |
2098257442 ps |
| T1520 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.2645339276 |
|
|
Sep 10 05:56:39 AM UTC 24 |
Sep 10 05:57:31 AM UTC 24 |
1271342620 ps |
| T1521 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.229568606 |
|
|
Sep 10 05:41:56 AM UTC 24 |
Sep 10 05:57:39 AM UTC 24 |
94454435452 ps |
| T1522 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.3872948047 |
|
|
Sep 10 05:56:51 AM UTC 24 |
Sep 10 05:57:39 AM UTC 24 |
1267604193 ps |
| T1523 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.3417222233 |
|
|
Sep 10 05:54:28 AM UTC 24 |
Sep 10 05:57:47 AM UTC 24 |
2430101382 ps |
| T1524 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.2991215683 |
|
|
Sep 10 05:57:47 AM UTC 24 |
Sep 10 05:57:59 AM UTC 24 |
124921227 ps |
| T1525 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.3356485940 |
|
|
Sep 10 05:57:51 AM UTC 24 |
Sep 10 05:58:01 AM UTC 24 |
45019093 ps |
| T1526 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.2191443377 |
|
|
Sep 10 05:46:58 AM UTC 24 |
Sep 10 05:58:04 AM UTC 24 |
5489422832 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.3700662025 |
|
|
Sep 10 05:55:35 AM UTC 24 |
Sep 10 05:58:11 AM UTC 24 |
3447741623 ps |
| T1527 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.784950453 |
|
|
Sep 10 05:52:11 AM UTC 24 |
Sep 10 05:58:21 AM UTC 24 |
3895920211 ps |
| T1528 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.1828602184 |
|
|
Sep 10 05:58:14 AM UTC 24 |
Sep 10 05:58:48 AM UTC 24 |
214276085 ps |
| T1529 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.364547467 |
|
|
Sep 10 05:58:06 AM UTC 24 |
Sep 10 05:58:50 AM UTC 24 |
851414719 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.3465322432 |
|
|
Sep 10 05:52:03 AM UTC 24 |
Sep 10 05:59:11 AM UTC 24 |
5338884574 ps |
| T1530 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.3527829968 |
|
|
Sep 10 05:55:37 AM UTC 24 |
Sep 10 05:59:21 AM UTC 24 |
12161091154 ps |
| T1531 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.2875173769 |
|
|
Sep 10 05:58:07 AM UTC 24 |
Sep 10 05:59:30 AM UTC 24 |
5531788689 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.3431665362 |
|
|
Sep 10 05:51:59 AM UTC 24 |
Sep 10 05:59:41 AM UTC 24 |
14860305707 ps |
| T1532 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.880235384 |
|
|
Sep 10 05:59:14 AM UTC 24 |
Sep 10 05:59:43 AM UTC 24 |
677035157 ps |
| T1533 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.2070523552 |
|
|
Sep 10 05:58:48 AM UTC 24 |
Sep 10 05:59:46 AM UTC 24 |
1325886277 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.1096631650 |
|
|
Sep 10 05:52:12 AM UTC 24 |
Sep 10 05:59:51 AM UTC 24 |
4698940531 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.321479439 |
|
|
Sep 10 05:54:47 AM UTC 24 |
Sep 10 05:59:53 AM UTC 24 |
3931330995 ps |
| T1534 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.1000518144 |
|
|
Sep 10 05:59:39 AM UTC 24 |
Sep 10 05:59:55 AM UTC 24 |
209599700 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.3815056115 |
|
|
Sep 10 05:57:26 AM UTC 24 |
Sep 10 05:59:55 AM UTC 24 |
459051147 ps |
| T1535 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.1383086833 |
|
|
Sep 10 05:57:26 AM UTC 24 |
Sep 10 06:00:02 AM UTC 24 |
5513358630 ps |
| T1536 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.2743643186 |
|
|
Sep 10 05:57:58 AM UTC 24 |
Sep 10 06:00:03 AM UTC 24 |
9779781846 ps |
| T1537 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.2073590519 |
|
|
Sep 10 05:59:17 AM UTC 24 |
Sep 10 06:00:06 AM UTC 24 |
860569248 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.2399892748 |
|
|
Sep 10 04:58:45 AM UTC 24 |
Sep 10 06:00:09 AM UTC 24 |
31476360121 ps |
| T1538 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.2094255600 |
|
|
Sep 10 05:54:43 AM UTC 24 |
Sep 10 06:00:23 AM UTC 24 |
3926380586 ps |
| T1539 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.671522992 |
|
|
Sep 10 05:59:48 AM UTC 24 |
Sep 10 06:00:25 AM UTC 24 |
620405163 ps |
| T1540 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.1617516129 |
|
|
Sep 10 06:00:17 AM UTC 24 |
Sep 10 06:00:25 AM UTC 24 |
38531115 ps |
| T1541 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.3145949459 |
|
|
Sep 10 05:54:38 AM UTC 24 |
Sep 10 06:00:27 AM UTC 24 |
8802191315 ps |
| T1542 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.2689364253 |
|
|
Sep 10 06:00:19 AM UTC 24 |
Sep 10 06:00:28 AM UTC 24 |
45992404 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.2154414279 |
|
|
Sep 10 05:57:02 AM UTC 24 |
Sep 10 06:00:43 AM UTC 24 |
2581969479 ps |
| T1543 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.466138523 |
|
|
Sep 10 05:49:53 AM UTC 24 |
Sep 10 06:00:49 AM UTC 24 |
17123387059 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.3533020524 |
|
|
Sep 10 05:58:31 AM UTC 24 |
Sep 10 06:00:50 AM UTC 24 |
2766245831 ps |
| T1544 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.2228658865 |
|
|
Sep 10 05:59:57 AM UTC 24 |
Sep 10 06:01:03 AM UTC 24 |
207769236 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.1478699454 |
|
|
Sep 10 06:00:31 AM UTC 24 |
Sep 10 06:01:04 AM UTC 24 |
226839090 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.102058437 |
|
|
Sep 10 05:57:24 AM UTC 24 |
Sep 10 06:01:24 AM UTC 24 |
738746279 ps |
| T1545 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.3735672386 |
|
|
Sep 10 06:00:52 AM UTC 24 |
Sep 10 06:01:30 AM UTC 24 |
1124468961 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.729215872 |
|
|
Sep 10 05:54:34 AM UTC 24 |
Sep 10 06:01:36 AM UTC 24 |
1850099205 ps |
| T1546 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.2315160890 |
|
|
Sep 10 06:00:20 AM UTC 24 |
Sep 10 06:01:36 AM UTC 24 |
5467627929 ps |
| T1547 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.4053544782 |
|
|
Sep 10 06:00:23 AM UTC 24 |
Sep 10 06:01:39 AM UTC 24 |
1589485192 ps |
| T1548 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.3152616158 |
|
|
Sep 10 06:00:19 AM UTC 24 |
Sep 10 06:01:46 AM UTC 24 |
7592745086 ps |
| T1549 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1197729518 |
|
|
Sep 10 06:00:53 AM UTC 24 |
Sep 10 06:01:49 AM UTC 24 |
962347595 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.3627748843 |
|
|
Sep 10 06:00:36 AM UTC 24 |
Sep 10 06:01:58 AM UTC 24 |
1241138919 ps |
| T1550 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.3503604129 |
|
|
Sep 10 06:00:54 AM UTC 24 |
Sep 10 06:02:00 AM UTC 24 |
1474464015 ps |
| T1551 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.2813975047 |
|
|
Sep 10 06:01:49 AM UTC 24 |
Sep 10 06:02:03 AM UTC 24 |
192307621 ps |
| T1552 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.3913556281 |
|
|
Sep 10 06:01:56 AM UTC 24 |
Sep 10 06:02:04 AM UTC 24 |
52778523 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.872490017 |
|
|
Sep 10 06:00:52 AM UTC 24 |
Sep 10 06:02:13 AM UTC 24 |
2498771933 ps |
| T1553 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.596230231 |
|
|
Sep 10 06:02:06 AM UTC 24 |
Sep 10 06:02:15 AM UTC 24 |
137605292 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1169005043 |
|
|
Sep 10 05:28:44 AM UTC 24 |
Sep 10 06:02:40 AM UTC 24 |
132030685155 ps |
| T1554 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.970798073 |
|
|
Sep 10 06:02:15 AM UTC 24 |
Sep 10 06:02:47 AM UTC 24 |
246205194 ps |
| T1555 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.2764877443 |
|
|
Sep 10 06:02:03 AM UTC 24 |
Sep 10 06:03:06 AM UTC 24 |
7043622436 ps |
| T1556 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.4058658895 |
|
|
Sep 10 06:02:31 AM UTC 24 |
Sep 10 06:03:13 AM UTC 24 |
864903932 ps |
| T1557 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.3757398670 |
|
|
Sep 10 06:02:41 AM UTC 24 |
Sep 10 06:03:14 AM UTC 24 |
577657129 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.4160589737 |
|
|
Sep 10 05:57:41 AM UTC 24 |
Sep 10 06:03:16 AM UTC 24 |
4265625044 ps |
| T1558 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.1251030624 |
|
|
Sep 10 06:02:04 AM UTC 24 |
Sep 10 06:03:32 AM UTC 24 |
5964035865 ps |
| T1559 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.3073600524 |
|
|
Sep 10 06:02:40 AM UTC 24 |
Sep 10 06:03:36 AM UTC 24 |
527342331 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.2770450462 |
|
|
Sep 10 06:01:10 AM UTC 24 |
Sep 10 06:03:39 AM UTC 24 |
1580092611 ps |
| T1560 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.56642069 |
|
|
Sep 10 06:03:08 AM UTC 24 |
Sep 10 06:03:47 AM UTC 24 |
695297255 ps |
| T1561 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.1367483078 |
|
|
Sep 10 06:00:07 AM UTC 24 |
Sep 10 06:03:49 AM UTC 24 |
3150191839 ps |
| T1562 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.1443057006 |
|
|
Sep 10 06:02:26 AM UTC 24 |
Sep 10 06:03:51 AM UTC 24 |
856218603 ps |
| T1563 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.665674197 |
|
|
Sep 10 06:01:18 AM UTC 24 |
Sep 10 06:03:57 AM UTC 24 |
5449364245 ps |
| T1564 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.3034357953 |
|
|
Sep 10 05:47:05 AM UTC 24 |
Sep 10 06:04:05 AM UTC 24 |
9306311876 ps |
| T1565 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.437165475 |
|
|
Sep 10 06:03:15 AM UTC 24 |
Sep 10 06:04:11 AM UTC 24 |
672700525 ps |
| T1566 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.4000086901 |
|
|
Sep 10 06:03:59 AM UTC 24 |
Sep 10 06:04:13 AM UTC 24 |
230466727 ps |
| T1567 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.3885471532 |
|
|
Sep 10 06:04:03 AM UTC 24 |
Sep 10 06:04:14 AM UTC 24 |
45026876 ps |
| T1568 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.2391666841 |
|
|
Sep 10 05:48:42 AM UTC 24 |
Sep 10 06:05:04 AM UTC 24 |
61148634710 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.1866859722 |
|
|
Sep 10 06:04:15 AM UTC 24 |
Sep 10 06:05:06 AM UTC 24 |
426393054 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.4010916624 |
|
|
Sep 10 06:04:07 AM UTC 24 |
Sep 10 06:05:21 AM UTC 24 |
7899014410 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.3103339664 |
|
|
Sep 10 06:04:14 AM UTC 24 |
Sep 10 06:05:22 AM UTC 24 |
4716822895 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.491397505 |
|
|
Sep 10 06:03:34 AM UTC 24 |
Sep 10 06:05:27 AM UTC 24 |
180962804 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.1569418156 |
|
|
Sep 10 05:55:35 AM UTC 24 |
Sep 10 06:05:37 AM UTC 24 |
55980779263 ps |