| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.17 | 95.52 | 94.02 | 95.39 | 94.99 | 97.53 | 99.59 |
| T2763 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_same_source.3056612194 | Sep 10 07:35:07 AM UTC 24 | Sep 10 07:35:24 AM UTC 24 | 349141221 ps | ||
| T2764 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_error.3152923085 | Sep 10 07:30:21 AM UTC 24 | Sep 10 07:35:30 AM UTC 24 | 3863243752 ps | ||
| T2765 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.3617138281 | Sep 10 07:35:11 AM UTC 24 | Sep 10 07:35:31 AM UTC 24 | 302059112 ps | ||
| T2766 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_unmapped_addr.3548635631 | Sep 10 07:35:13 AM UTC 24 | Sep 10 07:35:32 AM UTC 24 | 431738466 ps | ||
| T2767 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_zero_delays.2242892901 | Sep 10 07:35:34 AM UTC 24 | Sep 10 07:35:44 AM UTC 24 | 45158815 ps | ||
| T2768 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random.1015364934 | Sep 10 07:34:44 AM UTC 24 | Sep 10 07:35:48 AM UTC 24 | 1552361457 ps | ||
| T2769 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke.1339902400 | Sep 10 07:35:38 AM UTC 24 | Sep 10 07:35:48 AM UTC 24 | 155789653 ps | ||
| T2770 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.3946750093 | Sep 10 07:34:11 AM UTC 24 | Sep 10 07:35:50 AM UTC 24 | 1236987408 ps | ||
| T2771 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_random.3193008632 | Sep 10 07:35:15 AM UTC 24 | Sep 10 07:35:53 AM UTC 24 | 448329692 ps | ||
| T2772 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random.412030370 | Sep 10 07:35:46 AM UTC 24 | Sep 10 07:36:03 AM UTC 24 | 160507625 ps | ||
| T2773 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device.2122862594 | Sep 10 07:35:56 AM UTC 24 | Sep 10 07:36:07 AM UTC 24 | 26660825 ps | ||
| T2774 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.708432614 | Sep 10 07:05:53 AM UTC 24 | Sep 10 07:36:12 AM UTC 24 | 111951533205 ps | ||
| T2775 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_error.630819076 | Sep 10 07:33:15 AM UTC 24 | Sep 10 07:36:16 AM UTC 24 | 2799762002 ps | ||
| T2776 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.2990573211 | Sep 10 07:34:40 AM UTC 24 | Sep 10 07:36:17 AM UTC 24 | 5393510066 ps | ||
| T2777 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_large_delays.1775242817 | Sep 10 07:34:35 AM UTC 24 | Sep 10 07:36:23 AM UTC 24 | 9545056911 ps | ||
| T2778 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all.2117743326 | Sep 10 07:31:13 AM UTC 24 | Sep 10 07:36:31 AM UTC 24 | 3699803020 ps | ||
| T2779 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.2113315770 | Sep 10 07:22:14 AM UTC 24 | Sep 10 07:36:46 AM UTC 24 | 16828266925 ps | ||
| T2780 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device.1562953002 | Sep 10 07:34:59 AM UTC 24 | Sep 10 07:36:46 AM UTC 24 | 1261896854 ps | ||
| T2781 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.1190527371 | Sep 10 07:32:19 AM UTC 24 | Sep 10 07:36:47 AM UTC 24 | 2262458208 ps | ||
| T2782 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_same_source.3710488745 | Sep 10 07:36:12 AM UTC 24 | Sep 10 07:36:49 AM UTC 24 | 1400607587 ps | ||
| T2783 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_zero_delays.4038293651 | Sep 10 07:35:50 AM UTC 24 | Sep 10 07:36:50 AM UTC 24 | 553971401 ps | ||
| T2784 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_zero_delays.1362991461 | Sep 10 07:36:42 AM UTC 24 | Sep 10 07:36:52 AM UTC 24 | 46696766 ps | ||
| T2785 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke.3273341574 | Sep 10 07:36:43 AM UTC 24 | Sep 10 07:36:56 AM UTC 24 | 189035433 ps | ||
| T2786 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.846930675 | Sep 10 07:32:49 AM UTC 24 | Sep 10 07:36:58 AM UTC 24 | 16203263801 ps | ||
| T2787 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.2367077074 | Sep 10 07:35:20 AM UTC 24 | Sep 10 07:37:00 AM UTC 24 | 405469386 ps | ||
| T2788 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.1087912607 | Sep 10 07:36:17 AM UTC 24 | Sep 10 07:37:05 AM UTC 24 | 315390276 ps | ||
| T2789 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_unmapped_addr.1729994048 | Sep 10 07:36:16 AM UTC 24 | Sep 10 07:37:08 AM UTC 24 | 1041794330 ps | ||
| T2790 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.664828816 | Sep 10 07:36:40 AM UTC 24 | Sep 10 07:37:10 AM UTC 24 | 67398967 ps | ||
| T2791 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.250310904 | Sep 10 07:28:46 AM UTC 24 | Sep 10 07:37:10 AM UTC 24 | 12604907719 ps | ||
| T2792 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_zero_delays.2511721396 | Sep 10 07:37:15 AM UTC 24 | Sep 10 07:37:28 AM UTC 24 | 82341334 ps | ||
| T2793 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_large_delays.1461445676 | Sep 10 07:35:42 AM UTC 24 | Sep 10 07:37:29 AM UTC 24 | 8321308387 ps | ||
| T2794 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.695487470 | Sep 10 07:36:31 AM UTC 24 | Sep 10 07:37:35 AM UTC 24 | 118798032 ps | ||
| T2795 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_random.3170950454 | Sep 10 07:36:11 AM UTC 24 | Sep 10 07:37:39 AM UTC 24 | 2352728503 ps | ||
| T2796 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.3877410055 | Sep 10 07:35:43 AM UTC 24 | Sep 10 07:37:41 AM UTC 24 | 4855972869 ps | ||
| T2797 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.3648424253 | Sep 10 07:09:41 AM UTC 24 | Sep 10 07:37:44 AM UTC 24 | 104241847417 ps | ||
| T2798 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.1426464825 | Sep 10 07:37:27 AM UTC 24 | Sep 10 07:37:45 AM UTC 24 | 353499437 ps | ||
| T2799 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_random.1929920691 | Sep 10 07:37:24 AM UTC 24 | Sep 10 07:37:50 AM UTC 24 | 293924099 ps | ||
| T2800 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_unmapped_addr.4111213163 | Sep 10 07:37:23 AM UTC 24 | Sep 10 07:37:50 AM UTC 24 | 629513216 ps | ||
| T2801 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device.3100566410 | Sep 10 07:37:18 AM UTC 24 | Sep 10 07:37:59 AM UTC 24 | 851831447 ps | ||
| T2802 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.2118029677 | Sep 10 07:34:13 AM UTC 24 | Sep 10 07:38:05 AM UTC 24 | 3763667408 ps | ||
| T2803 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke.3308928394 | Sep 10 07:37:55 AM UTC 24 | Sep 10 07:38:07 AM UTC 24 | 214582484 ps | ||
| T2804 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_zero_delays.328798520 | Sep 10 07:38:03 AM UTC 24 | Sep 10 07:38:13 AM UTC 24 | 51562529 ps | ||
| T2805 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_error.364743585 | Sep 10 07:31:17 AM UTC 24 | Sep 10 07:38:19 AM UTC 24 | 14049151196 ps | ||
| T2806 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random.2305178459 | Sep 10 07:37:13 AM UTC 24 | Sep 10 07:38:20 AM UTC 24 | 1963668230 ps | ||
| T2807 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.531577225 | Sep 10 07:28:56 AM UTC 24 | Sep 10 07:38:28 AM UTC 24 | 13593686792 ps | ||
| T2808 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_same_source.3340748850 | Sep 10 07:37:20 AM UTC 24 | Sep 10 07:38:33 AM UTC 24 | 2331325731 ps | ||
| T2809 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_large_delays.2540054898 | Sep 10 07:36:50 AM UTC 24 | Sep 10 07:38:34 AM UTC 24 | 8123793476 ps | ||
| T2810 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random.601612295 | Sep 10 07:38:10 AM UTC 24 | Sep 10 07:38:34 AM UTC 24 | 236153073 ps | ||
| T2811 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.1869359023 | Sep 10 07:07:09 AM UTC 24 | Sep 10 07:38:39 AM UTC 24 | 127435650487 ps | ||
| T2812 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_random.2171435269 | Sep 10 07:38:39 AM UTC 24 | Sep 10 07:38:47 AM UTC 24 | 35002275 ps | ||
| T2813 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.1471618524 | Sep 10 07:36:57 AM UTC 24 | Sep 10 07:38:48 AM UTC 24 | 5128869633 ps | ||
| T2814 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_same_source.3367393683 | Sep 10 07:38:34 AM UTC 24 | Sep 10 07:38:50 AM UTC 24 | 116261723 ps | ||
| T2815 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_zero_delays.3118141356 | Sep 10 07:38:12 AM UTC 24 | Sep 10 07:38:53 AM UTC 24 | 385689628 ps | ||
| T2816 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all.1204747797 | Sep 10 07:32:12 AM UTC 24 | Sep 10 07:38:55 AM UTC 24 | 4553014936 ps | ||
| T2817 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_error.3297695272 | Sep 10 07:36:32 AM UTC 24 | Sep 10 07:38:57 AM UTC 24 | 4140044804 ps | ||
| T2818 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_slow_rsp.630330308 | Sep 10 07:31:39 AM UTC 24 | Sep 10 07:39:10 AM UTC 24 | 32729216514 ps | ||
| T2819 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_unmapped_addr.2233108888 | Sep 10 07:38:45 AM UTC 24 | Sep 10 07:39:11 AM UTC 24 | 602700488 ps | ||
| T2820 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_large_delays.397002606 | Sep 10 07:38:06 AM UTC 24 | Sep 10 07:39:13 AM UTC 24 | 7499614087 ps | ||
| T2821 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke.4281191229 | Sep 10 07:39:07 AM UTC 24 | Sep 10 07:39:16 AM UTC 24 | 170053914 ps | ||
| T2822 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_zero_delays.1644316011 | Sep 10 07:39:14 AM UTC 24 | Sep 10 07:39:25 AM UTC 24 | 44351831 ps | ||
| T2823 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device.2301779317 | Sep 10 07:38:28 AM UTC 24 | Sep 10 07:39:35 AM UTC 24 | 872554861 ps | ||
| T2824 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_zero_delays.1030777058 | Sep 10 07:39:23 AM UTC 24 | Sep 10 07:39:46 AM UTC 24 | 172275353 ps | ||
| T2825 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.285778799 | Sep 10 07:38:47 AM UTC 24 | Sep 10 07:39:57 AM UTC 24 | 1350608818 ps | ||
| T2826 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.3331359203 | Sep 10 07:38:10 AM UTC 24 | Sep 10 07:40:12 AM UTC 24 | 6336368157 ps | ||
| T2827 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_same_source.1307069105 | Sep 10 07:39:45 AM UTC 24 | Sep 10 07:40:20 AM UTC 24 | 702210578 ps | ||
| T2828 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random.3417604749 | Sep 10 07:39:22 AM UTC 24 | Sep 10 07:40:21 AM UTC 24 | 1215404897 ps | ||
| T2829 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.2998267290 | Sep 10 07:27:02 AM UTC 24 | Sep 10 07:40:23 AM UTC 24 | 56456559421 ps | ||
| T2830 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_slow_rsp.4277908757 | Sep 10 07:39:38 AM UTC 24 | Sep 10 07:40:27 AM UTC 24 | 3693079464 ps | ||
| T2831 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device.886920478 | Sep 10 07:39:40 AM UTC 24 | Sep 10 07:40:27 AM UTC 24 | 451823686 ps | ||
| T2832 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all.3885144677 | Sep 10 07:35:16 AM UTC 24 | Sep 10 07:40:35 AM UTC 24 | 7959705390 ps | ||
| T2833 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_slow_rsp.2985616783 | Sep 10 07:38:16 AM UTC 24 | Sep 10 07:40:43 AM UTC 24 | 7055889025 ps | ||
| T2834 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_unmapped_addr.2192009219 | Sep 10 07:40:04 AM UTC 24 | Sep 10 07:40:46 AM UTC 24 | 865807541 ps | ||
| T2835 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_large_delays.2632201965 | Sep 10 07:39:14 AM UTC 24 | Sep 10 07:40:58 AM UTC 24 | 9976366610 ps | ||
| T2836 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.3190474365 | Sep 10 07:39:19 AM UTC 24 | Sep 10 07:41:01 AM UTC 24 | 4416725724 ps | ||
| T2837 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.125981347 | Sep 10 07:40:14 AM UTC 24 | Sep 10 07:41:03 AM UTC 24 | 870272395 ps | ||
| T2838 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all.2541590913 | Sep 10 07:40:26 AM UTC 24 | Sep 10 07:41:04 AM UTC 24 | 232287619 ps | ||
| T2839 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke.4109148389 | Sep 10 07:40:50 AM UTC 24 | Sep 10 07:41:05 AM UTC 24 | 232284538 ps | ||
| T2840 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_zero_delays.2016361940 | Sep 10 07:40:55 AM UTC 24 | Sep 10 07:41:05 AM UTC 24 | 44901416 ps | ||
| T2841 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.2809656386 | Sep 10 07:10:42 AM UTC 24 | Sep 10 07:41:11 AM UTC 24 | 117805018332 ps | ||
| T2842 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_random.3035408900 | Sep 10 07:39:54 AM UTC 24 | Sep 10 07:41:15 AM UTC 24 | 2166920625 ps | ||
| T2843 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all.371006171 | Sep 10 07:29:56 AM UTC 24 | Sep 10 07:41:18 AM UTC 24 | 18822786005 ps | ||
| T2844 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_slow_rsp.2124674865 | Sep 10 07:33:56 AM UTC 24 | Sep 10 07:41:20 AM UTC 24 | 31727700708 ps | ||
| T2845 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_zero_delays.572295687 | Sep 10 07:41:08 AM UTC 24 | Sep 10 07:41:31 AM UTC 24 | 244644751 ps | ||
| T2846 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_large_delays.3774098563 | Sep 10 07:39:24 AM UTC 24 | Sep 10 07:41:36 AM UTC 24 | 13246088987 ps | ||
| T2847 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_same_source.3981984471 | Sep 10 07:41:28 AM UTC 24 | Sep 10 07:41:44 AM UTC 24 | 368713331 ps | ||
| T2848 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_error.4021249753 | Sep 10 07:35:28 AM UTC 24 | Sep 10 07:41:44 AM UTC 24 | 13173657047 ps | ||
| T2849 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.2661274631 | Sep 10 07:35:33 AM UTC 24 | Sep 10 07:41:53 AM UTC 24 | 8530317701 ps | ||
| T2850 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device.749393423 | Sep 10 07:41:26 AM UTC 24 | Sep 10 07:41:54 AM UTC 24 | 444083261 ps | ||
| T2851 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_large_delays.149753128 | Sep 10 07:33:58 AM UTC 24 | Sep 10 07:41:56 AM UTC 24 | 48220420682 ps | ||
| T2852 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random.1939275991 | Sep 10 07:41:11 AM UTC 24 | Sep 10 07:41:57 AM UTC 24 | 581754390 ps | ||
| T2853 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_unmapped_addr.3188722901 | Sep 10 07:41:36 AM UTC 24 | Sep 10 07:42:06 AM UTC 24 | 741881491 ps | ||
| T2854 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.2701060426 | Sep 10 07:41:42 AM UTC 24 | Sep 10 07:42:08 AM UTC 24 | 256836806 ps | ||
| T2855 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_zero_delays.1006695795 | Sep 10 07:42:10 AM UTC 24 | Sep 10 07:42:18 AM UTC 24 | 58792916 ps | ||
| T2856 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke.3272775462 | Sep 10 07:42:08 AM UTC 24 | Sep 10 07:42:22 AM UTC 24 | 238730525 ps | ||
| T2857 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_large_delays.19298686 | Sep 10 07:37:15 AM UTC 24 | Sep 10 07:42:27 AM UTC 24 | 25079206648 ps | ||
| T2858 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.3774280481 | Sep 10 07:39:00 AM UTC 24 | Sep 10 07:42:30 AM UTC 24 | 703091578 ps | ||
| T2859 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_large_delays.2613925904 | Sep 10 07:40:53 AM UTC 24 | Sep 10 07:42:35 AM UTC 24 | 6688936931 ps | ||
| T2860 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.393056882 | Sep 10 07:13:30 AM UTC 24 | Sep 10 07:42:39 AM UTC 24 | 130779289993 ps | ||
| T2861 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_random.1821184550 | Sep 10 07:41:28 AM UTC 24 | Sep 10 07:42:42 AM UTC 24 | 2421892410 ps | ||
| T2862 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.827520275 | Sep 10 07:39:41 AM UTC 24 | Sep 10 07:42:55 AM UTC 24 | 12250866930 ps | ||
| T2863 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random.2871661793 | Sep 10 07:42:21 AM UTC 24 | Sep 10 07:42:59 AM UTC 24 | 313793432 ps | ||
| T2864 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all.3944038229 | Sep 10 07:37:35 AM UTC 24 | Sep 10 07:43:00 AM UTC 24 | 9149634786 ps | ||
| T2865 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_zero_delays.2210121323 | Sep 10 07:42:25 AM UTC 24 | Sep 10 07:43:05 AM UTC 24 | 386841292 ps | ||
| T2866 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_unmapped_addr.1240046142 | Sep 10 07:43:04 AM UTC 24 | Sep 10 07:43:18 AM UTC 24 | 246589831 ps | ||
| T2867 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.3124480048 | Sep 10 07:41:04 AM UTC 24 | Sep 10 07:43:18 AM UTC 24 | 6111142021 ps | ||
| T2868 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_slow_rsp.3241726378 | Sep 10 07:34:57 AM UTC 24 | Sep 10 07:43:21 AM UTC 24 | 28664096354 ps | ||
| T2869 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.882429855 | Sep 10 07:43:06 AM UTC 24 | Sep 10 07:43:27 AM UTC 24 | 501345721 ps | ||
| T2870 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_large_delays.389780834 | Sep 10 07:28:10 AM UTC 24 | Sep 10 07:43:30 AM UTC 24 | 88032272750 ps | ||
| T2871 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all.3596329799 | Sep 10 07:38:54 AM UTC 24 | Sep 10 07:43:32 AM UTC 24 | 8370940816 ps | ||
| T2872 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.2192550224 | Sep 10 07:25:03 AM UTC 24 | Sep 10 07:43:34 AM UTC 24 | 13491306848 ps | ||
| T636 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_random.4075207767 | Sep 10 07:42:59 AM UTC 24 | Sep 10 07:43:34 AM UTC 24 | 772869135 ps | ||
| T2873 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_large_delays.3364309195 | Sep 10 07:30:53 AM UTC 24 | Sep 10 07:43:41 AM UTC 24 | 83540480126 ps | ||
| T2874 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device.2902149336 | Sep 10 07:42:46 AM UTC 24 | Sep 10 07:43:41 AM UTC 24 | 748364009 ps | ||
| T2875 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.3255572642 | Sep 10 07:40:48 AM UTC 24 | Sep 10 07:43:45 AM UTC 24 | 4238083317 ps | ||
| T2876 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.2328945596 | Sep 10 07:27:38 AM UTC 24 | Sep 10 07:43:50 AM UTC 24 | 8163620282 ps | ||
| T2877 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_large_delays.1859916458 | Sep 10 07:42:17 AM UTC 24 | Sep 10 07:43:57 AM UTC 24 | 10203751438 ps | ||
| T2878 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.2894973285 | Sep 10 07:42:19 AM UTC 24 | Sep 10 07:44:00 AM UTC 24 | 5217512629 ps | ||
| T2879 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all.2119711405 | Sep 10 07:41:43 AM UTC 24 | Sep 10 07:44:01 AM UTC 24 | 3480422814 ps | ||
| T2880 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_error.2868353712 | Sep 10 07:37:32 AM UTC 24 | Sep 10 07:44:01 AM UTC 24 | 13307549680 ps | ||
| T2881 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.3775997939 | Sep 10 07:41:59 AM UTC 24 | Sep 10 07:44:08 AM UTC 24 | 2057541193 ps | ||
| T2882 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.2646966210 | Sep 10 07:35:58 AM UTC 24 | Sep 10 07:44:14 AM UTC 24 | 32169597255 ps | ||
| T2883 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_same_source.2112541826 | Sep 10 07:42:54 AM UTC 24 | Sep 10 07:44:24 AM UTC 24 | 2699457960 ps | ||
| T2884 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_slow_rsp.3631168987 | Sep 10 07:28:18 AM UTC 24 | Sep 10 07:44:29 AM UTC 24 | 66939983280 ps | ||
| T2885 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_slow_rsp.2698443382 | Sep 10 07:30:52 AM UTC 24 | Sep 10 07:44:35 AM UTC 24 | 56624247335 ps | ||
| T2886 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.3638051068 | Sep 10 07:23:11 AM UTC 24 | Sep 10 07:44:35 AM UTC 24 | 89118725711 ps | ||
| T2887 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.1253072600 | Sep 10 07:41:46 AM UTC 24 | Sep 10 07:44:43 AM UTC 24 | 3547885756 ps | ||
| T2888 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all.951660807 | Sep 10 07:36:20 AM UTC 24 | Sep 10 07:44:47 AM UTC 24 | 15369431842 ps | ||
| T593 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_error.3670227127 | Sep 10 07:40:48 AM UTC 24 | Sep 10 07:44:55 AM UTC 24 | 8722463698 ps | ||
| T2889 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.990567574 | Sep 10 07:25:52 AM UTC 24 | Sep 10 07:44:56 AM UTC 24 | 71565366568 ps | ||
| T2890 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_error.289811377 | Sep 10 07:39:01 AM UTC 24 | Sep 10 07:44:59 AM UTC 24 | 12060700795 ps | ||
| T2891 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.531355254 | Sep 10 07:37:15 AM UTC 24 | Sep 10 07:45:00 AM UTC 24 | 33194916068 ps | ||
| T2892 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.1022545240 | Sep 10 07:24:25 AM UTC 24 | Sep 10 07:45:02 AM UTC 24 | 87839303445 ps | ||
| T2893 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.1306387824 | Sep 10 07:31:00 AM UTC 24 | Sep 10 07:45:05 AM UTC 24 | 59894148177 ps | ||
| T2894 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.1297603123 | Sep 10 07:33:05 AM UTC 24 | Sep 10 07:45:21 AM UTC 24 | 6378981945 ps | ||
| T2895 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.883619386 | Sep 10 07:40:41 AM UTC 24 | Sep 10 07:45:21 AM UTC 24 | 2845848574 ps | ||
| T2896 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.2875877915 | Sep 10 07:43:27 AM UTC 24 | Sep 10 07:45:26 AM UTC 24 | 1866452682 ps | ||
| T2897 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.2144047222 | Sep 10 07:37:57 AM UTC 24 | Sep 10 07:45:59 AM UTC 24 | 7583754782 ps | ||
| T2898 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.618533467 | Sep 10 07:29:42 AM UTC 24 | Sep 10 07:46:15 AM UTC 24 | 67777665638 ps | ||
| T2899 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.856766289 | Sep 10 07:38:59 AM UTC 24 | Sep 10 07:46:18 AM UTC 24 | 10176136480 ps | ||
| T2900 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all.221502925 | Sep 10 07:43:10 AM UTC 24 | Sep 10 07:46:21 AM UTC 24 | 6237703007 ps | ||
| T2901 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.421435368 | Sep 10 07:41:29 AM UTC 24 | Sep 10 07:46:30 AM UTC 24 | 24628574948 ps | ||
| T2902 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_slow_rsp.3459709301 | Sep 10 07:42:34 AM UTC 24 | Sep 10 07:46:34 AM UTC 24 | 17620248597 ps | ||
| T2903 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.433197829 | Sep 10 07:37:32 AM UTC 24 | Sep 10 07:46:39 AM UTC 24 | 9497705086 ps | ||
| T2904 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.2781282452 | Sep 10 07:08:36 AM UTC 24 | Sep 10 07:46:41 AM UTC 24 | 132881972289 ps | ||
| T2905 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_error.3648947295 | Sep 10 07:43:27 AM UTC 24 | Sep 10 07:46:47 AM UTC 24 | 7179127546 ps | ||
| T2906 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_error.2113454104 | Sep 10 07:41:58 AM UTC 24 | Sep 10 07:46:49 AM UTC 24 | 10123441291 ps | ||
| T2907 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.1284510474 | Sep 10 07:43:21 AM UTC 24 | Sep 10 07:46:58 AM UTC 24 | 3464348577 ps | ||
| T2908 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_large_delays.1890972976 | Sep 10 07:34:55 AM UTC 24 | Sep 10 07:48:04 AM UTC 24 | 91063614980 ps | ||
| T2909 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_large_delays.1625005493 | Sep 10 07:31:37 AM UTC 24 | Sep 10 07:48:09 AM UTC 24 | 100731336831 ps | ||
| T2910 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_large_delays.518006148 | Sep 10 07:38:17 AM UTC 24 | Sep 10 07:48:52 AM UTC 24 | 70076186138 ps | ||
| T2911 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_slow_rsp.263025824 | Sep 10 07:37:13 AM UTC 24 | Sep 10 07:49:14 AM UTC 24 | 47556830532 ps | ||
| T2912 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_large_delays.1717289738 | Sep 10 07:42:34 AM UTC 24 | Sep 10 07:49:17 AM UTC 24 | 46911493209 ps | ||
| T2913 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.2997137789 | Sep 10 04:58:42 AM UTC 24 | Sep 10 07:49:29 AM UTC 24 | 51429169528 ps | ||
| T2914 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.1596339514 | Sep 10 07:14:35 AM UTC 24 | Sep 10 07:49:40 AM UTC 24 | 132284821134 ps | ||
| T2915 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.3983830789 | Sep 10 07:28:24 AM UTC 24 | Sep 10 07:49:54 AM UTC 24 | 91869240225 ps | ||
| T2916 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.3886271436 | Sep 10 07:35:03 AM UTC 24 | Sep 10 07:50:02 AM UTC 24 | 58404318658 ps | ||
| T2917 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_slow_rsp.4036224089 | Sep 10 07:35:55 AM UTC 24 | Sep 10 07:50:19 AM UTC 24 | 64735645449 ps | ||
| T2918 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_large_delays.1067048476 | Sep 10 07:35:52 AM UTC 24 | Sep 10 07:51:14 AM UTC 24 | 102409084399 ps | ||
| T2919 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_slow_rsp.4117079213 | Sep 10 07:41:25 AM UTC 24 | Sep 10 07:52:07 AM UTC 24 | 51518316824 ps | ||
| T2920 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.4024143987 | Sep 10 07:33:58 AM UTC 24 | Sep 10 07:52:17 AM UTC 24 | 82653907286 ps | ||
| T2921 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.2546206577 | Sep 10 07:31:54 AM UTC 24 | Sep 10 07:52:35 AM UTC 24 | 90470056981 ps | ||
| T2922 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_large_delays.2527091319 | Sep 10 07:41:24 AM UTC 24 | Sep 10 07:53:12 AM UTC 24 | 87168369017 ps | ||
| T2923 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.538124787 | Sep 10 07:20:19 AM UTC 24 | Sep 10 08:00:09 AM UTC 24 | 188708576641 ps | ||
| T2924 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2219320153 | Sep 10 07:38:32 AM UTC 24 | Sep 10 08:00:35 AM UTC 24 | 107082214918 ps | ||
| T2925 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.3360899037 | Sep 10 07:42:49 AM UTC 24 | Sep 10 08:02:09 AM UTC 24 | 103885284180 ps | ||
| T2926 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_aliasing.2899643940 | Sep 10 05:10:25 AM UTC 24 | Sep 10 08:04:02 AM UTC 24 | 64076904286 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1778511807 | Sep 10 04:57:31 AM UTC 24 | Sep 10 05:01:16 AM UTC 24 | 5270324488 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.296976557 | Sep 10 04:57:13 AM UTC 24 | Sep 10 05:01:31 AM UTC 24 | 4324896968 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1261812808 | Sep 10 04:57:23 AM UTC 24 | Sep 10 05:02:29 AM UTC 24 | 5436225298 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1154731506 | Sep 10 04:57:46 AM UTC 24 | Sep 10 05:02:31 AM UTC 24 | 3965641920 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.4144977578 | Sep 10 04:57:38 AM UTC 24 | Sep 10 05:02:31 AM UTC 24 | 5822172632 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3761447309 | Sep 10 04:57:31 AM UTC 24 | Sep 10 05:02:32 AM UTC 24 | 4150944288 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.222195295 | Sep 10 04:57:57 AM UTC 24 | Sep 10 05:03:22 AM UTC 24 | 3717351035 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.30774363 | Sep 10 04:57:50 AM UTC 24 | Sep 10 05:03:32 AM UTC 24 | 5560367908 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3144087861 | Sep 10 04:57:36 AM UTC 24 | Sep 10 05:03:39 AM UTC 24 | 6286045685 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1405085081 | Sep 10 04:58:23 AM UTC 24 | Sep 10 05:04:15 AM UTC 24 | 5447514506 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1043640595 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3384035914 ps |
| CPU time | 257.77 seconds |
| Started | Sep 09 10:41:53 PM UTC 24 |
| Finished | Sep 09 10:46:14 PM UTC 24 |
| Peak memory | 623868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043640595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_ mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.1043640595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.3671950904 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 19218847556 ps |
| CPU time | 1931.85 seconds |
| Started | Sep 10 03:13:52 AM UTC 24 |
| Finished | Sep 10 03:46:28 AM UTC 24 |
| Peak memory | 623264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367195 0904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_csr_rw.3671950904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.3844850526 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 6041004944 ps |
| CPU time | 1034.35 seconds |
| Started | Sep 09 11:12:20 PM UTC 24 |
| Finished | Sep 09 11:29:48 PM UTC 24 |
| Peak memory | 625736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844850526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch ip_plic_all_irqs_0.3844850526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_plic_all_irqs_0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.4045203578 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 10205944921 ps |
| CPU time | 392.66 seconds |
| Started | Sep 10 05:12:37 AM UTC 24 |
| Finished | Sep 10 05:19:16 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045203578 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.4045203578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.932471286 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 4428577938 ps |
| CPU time | 490.12 seconds |
| Started | Sep 09 10:39:27 PM UTC 24 |
| Finished | Sep 09 10:47:44 PM UTC 24 |
| Peak memory | 674224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932471286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.932471286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.3269762800 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 2142252039 ps |
| CPU time | 115.31 seconds |
| Started | Sep 10 05:00:44 AM UTC 24 |
| Finished | Sep 10 05:02:42 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269762800 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.3269762800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1778511807 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 5270324488 ps |
| CPU time | 221.96 seconds |
| Started | Sep 10 04:57:31 AM UTC 24 |
| Finished | Sep 10 05:01:16 AM UTC 24 |
| Peak memory | 656300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778511 807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 3.chip_ padctrl_attributes.1778511807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.4118532508 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 101975155205 ps |
| CPU time | 1504.14 seconds |
| Started | Sep 10 05:15:06 AM UTC 24 |
| Finished | Sep 10 05:40:27 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118532508 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.4118532508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.1681880981 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 9439810704 ps |
| CPU time | 1802.7 seconds |
| Started | Sep 09 11:07:32 PM UTC 24 |
| Finished | Sep 09 11:37:58 PM UTC 24 |
| Peak memory | 625676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681880981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sidel oad_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.1681880981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.2633852953 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 3033911020 ps |
| CPU time | 294.27 seconds |
| Started | Sep 09 10:59:04 PM UTC 24 |
| Finished | Sep 09 11:04:03 PM UTC 24 |
| Peak memory | 623808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand om_seed=2633852953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aler t_test.2633852953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1169005043 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 132030685155 ps |
| CPU time | 2012.7 seconds |
| Started | Sep 10 05:28:44 AM UTC 24 |
| Finished | Sep 10 06:02:40 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169005043 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.1169005043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.1766652694 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 7334467440 ps |
| CPU time | 686.69 seconds |
| Started | Sep 09 10:48:59 PM UTC 24 |
| Finished | Sep 09 11:00:36 PM UTC 24 |
| Peak memory | 640156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766652694 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.1766652694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.48236390 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 4486069116 ps |
| CPU time | 764.29 seconds |
| Started | Sep 09 11:13:03 PM UTC 24 |
| Finished | Sep 09 11:25:58 PM UTC 24 |
| Peak memory | 625576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=48236390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_plic_all_irqs_20.48236390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_plic_all_irqs_20/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1487252626 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 7774060204 ps |
| CPU time | 459.4 seconds |
| Started | Sep 09 11:23:37 PM UTC 24 |
| Finished | Sep 09 11:31:23 PM UTC 24 |
| Peak memory | 625880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_w ake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1487252626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1487252626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.1663190629 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 9024961576 ps |
| CPU time | 360.92 seconds |
| Started | Sep 10 05:02:12 AM UTC 24 |
| Finished | Sep 10 05:08:19 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663190629 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1663190629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.3694627042 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 5821615240 ps |
| CPU time | 1340.41 seconds |
| Started | Sep 09 11:35:01 PM UTC 24 |
| Finished | Sep 09 11:57:38 PM UTC 24 |
| Peak memory | 640604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_tim eout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv + sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694627042 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_virus.3694627042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3106533782 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 82048162417 ps |
| CPU time | 1342.03 seconds |
| Started | Sep 10 05:01:46 AM UTC 24 |
| Finished | Sep 10 05:24:24 AM UTC 24 |
| Peak memory | 599104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106533782 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.3106533782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.3278824742 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 3357683738 ps |
| CPU time | 259.59 seconds |
| Started | Sep 10 04:59:49 AM UTC 24 |
| Finished | Sep 10 05:04:13 AM UTC 24 |
| Peak memory | 620960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278824742 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.3278824742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2016372361 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 2674958654 ps |
| CPU time | 252.15 seconds |
| Started | Sep 09 11:26:50 PM UTC 24 |
| Finished | Sep 09 11:31:06 PM UTC 24 |
| Peak memory | 623540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_im ages=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016372361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.2016372361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2099173813 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 75781407351 ps |
| CPU time | 1117.22 seconds |
| Started | Sep 10 05:34:42 AM UTC 24 |
| Finished | Sep 10 05:53:33 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099173813 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.2099173813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2640973180 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 72363185743 ps |
| CPU time | 1040.07 seconds |
| Started | Sep 10 05:25:33 AM UTC 24 |
| Finished | Sep 10 05:43:05 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640973180 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.2640973180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.1154172586 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 18657493718 ps |
| CPU time | 1892.46 seconds |
| Started | Sep 09 11:21:28 PM UTC 24 |
| Finished | Sep 09 11:53:25 PM UTC 24 |
| Peak memory | 623008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115417 2586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_csr_rw.1154172586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.650258269 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 2433277650 ps |
| CPU time | 272.12 seconds |
| Started | Sep 09 10:41:28 PM UTC 24 |
| Finished | Sep 09 10:46:04 PM UTC 24 |
| Peak memory | 623600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650258269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_spi_host_tx_rx.650258269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.90903704 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 8340025855 ps |
| CPU time | 627.14 seconds |
| Started | Sep 10 05:40:21 AM UTC 24 |
| Finished | Sep 10 05:50:57 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90903704 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.90903704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.169985749 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3731178392 ps |
| CPU time | 439.44 seconds |
| Started | Sep 09 10:43:25 PM UTC 24 |
| Finished | Sep 09 10:50:51 PM UTC 24 |
| Peak memory | 623524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=169985749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_gpio.169985749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_gpio/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.551354972 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 6377884191 ps |
| CPU time | 880.3 seconds |
| Started | Sep 09 11:05:54 PM UTC 24 |
| Finished | Sep 09 11:20:47 PM UTC 24 |
| Peak memory | 626008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551354972 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.551354972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.748829420 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 7210556606 ps |
| CPU time | 461.67 seconds |
| Started | Sep 10 05:07:49 AM UTC 24 |
| Finished | Sep 10 05:15:37 AM UTC 24 |
| Peak memory | 680236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748829420 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_reset.748829420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3456740196 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 41252232 ps |
| CPU time | 8.82 seconds |
| Started | Sep 10 05:00:04 AM UTC 24 |
| Finished | Sep 10 05:00:14 AM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456740196 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3456740196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.3938796771 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 5720594437 ps |
| CPU time | 595.61 seconds |
| Started | Sep 10 05:21:10 AM UTC 24 |
| Finished | Sep 10 05:31:14 AM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938796771 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.3938796771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3227125488 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4054332043 ps |
| CPU time | 421.2 seconds |
| Started | Sep 09 10:43:18 PM UTC 24 |
| Finished | Sep 09 10:50:26 PM UTC 24 |
| Peak memory | 625524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227125488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ct rl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.3227125488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.3831009326 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 4232048280 ps |
| CPU time | 665.7 seconds |
| Started | Sep 09 11:12:37 PM UTC 24 |
| Finished | Sep 09 11:23:52 PM UTC 24 |
| Peak memory | 623792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3831009326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_plic_all_irqs_10.3831009326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_plic_all_irqs_10/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.633701848 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 100757570061 ps |
| CPU time | 1887.54 seconds |
| Started | Sep 10 06:24:39 AM UTC 24 |
| Finished | Sep 10 06:56:29 AM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633701848 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.633701848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.967885738 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 30262630228 ps |
| CPU time | 314.22 seconds |
| Started | Sep 10 05:00:59 AM UTC 24 |
| Finished | Sep 10 05:06:18 AM UTC 24 |
| Peak memory | 596028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967885738 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.967885738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.2211569267 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 43648154125 ps |
| CPU time | 5311.1 seconds |
| Started | Sep 09 10:41:39 PM UTC 24 |
| Finished | Sep 10 12:11:15 AM UTC 24 |
| Peak memory | 639376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw _build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211569267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip _earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.2211569267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.147796572 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 15454690925 ps |
| CPU time | 3696.54 seconds |
| Started | Sep 09 11:42:08 PM UTC 24 |
| Finished | Sep 10 12:44:31 AM UTC 24 |
| Peak memory | 623872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=147796572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.147796572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.3783395322 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 5975504663 ps |
| CPU time | 589.42 seconds |
| Started | Sep 10 05:04:41 AM UTC 24 |
| Finished | Sep 10 05:14:39 AM UTC 24 |
| Peak memory | 619044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783395322 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.3783395322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.1790770761 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 4708075696 ps |
| CPU time | 526 seconds |
| Started | Sep 10 05:18:29 AM UTC 24 |
| Finished | Sep 10 05:27:22 AM UTC 24 |
| Peak memory | 620960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790770761 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.1790770761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3939480237 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 10779649430 ps |
| CPU time | 1191.64 seconds |
| Started | Sep 09 11:02:27 PM UTC 24 |
| Finished | Sep 09 11:22:35 PM UTC 24 |
| Peak memory | 625824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939480237 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_hand ler_lpg_sleep_mode_pings.3939480237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.4167627519 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3587456756 ps |
| CPU time | 275.69 seconds |
| Started | Sep 10 12:42:35 AM UTC 24 |
| Finished | Sep 10 12:47:15 AM UTC 24 |
| Peak memory | 625852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167627519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_ mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.4167627519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3027898118 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 3682559616 ps |
| CPU time | 249.26 seconds |
| Started | Sep 09 10:46:20 PM UTC 24 |
| Finished | Sep 09 10:50:34 PM UTC 24 |
| Peak memory | 635944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027898118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.3027898118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4260663534 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 4537796444 ps |
| CPU time | 447.52 seconds |
| Started | Sep 09 11:11:54 PM UTC 24 |
| Finished | Sep 09 11:19:28 PM UTC 24 |
| Peak memory | 626020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_im ages=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260663534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4260663534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1208950703 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 5172795834 ps |
| CPU time | 600.67 seconds |
| Started | Sep 09 10:54:09 PM UTC 24 |
| Finished | Sep 09 11:04:20 PM UTC 24 |
| Peak memory | 627896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1208950703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_sysrst_ctrl_in_irq.1208950703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.3413841310 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 6554240200 ps |
| CPU time | 660.99 seconds |
| Started | Sep 09 10:45:09 PM UTC 24 |
| Finished | Sep 09 10:56:19 PM UTC 24 |
| Peak memory | 625812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413841310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ct rl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.3413841310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.2931946607 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 11668957232 ps |
| CPU time | 2135.63 seconds |
| Started | Sep 09 11:54:03 PM UTC 24 |
| Finished | Sep 10 12:30:08 AM UTC 24 |
| Peak memory | 640292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_devic e=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931946607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jta g_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.2931946607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.1681324670 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3893935071 ps |
| CPU time | 250.18 seconds |
| Started | Sep 09 10:42:05 PM UTC 24 |
| Finished | Sep 09 10:46:19 PM UTC 24 |
| Peak memory | 636296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1681324670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_device_pinmux_sleep_retention.1681324670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1088981568 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 11205305128 ps |
| CPU time | 1132.74 seconds |
| Started | Sep 10 05:23:49 AM UTC 24 |
| Finished | Sep 10 05:42:56 AM UTC 24 |
| Peak memory | 596032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088981568 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.1088981568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2313363782 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3276571587 ps |
| CPU time | 339.03 seconds |
| Started | Sep 10 02:04:38 AM UTC 24 |
| Finished | Sep 10 02:10:23 AM UTC 24 |
| Peak memory | 623540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313363782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_ mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.2313363782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2729676015 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 625626355 ps |
| CPU time | 200.77 seconds |
| Started | Sep 10 05:04:18 AM UTC 24 |
| Finished | Sep 10 05:07:42 AM UTC 24 |
| Peak memory | 595964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729676015 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.2729676015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2163936305 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 6395833595 ps |
| CPU time | 636.58 seconds |
| Started | Sep 09 11:03:52 PM UTC 24 |
| Finished | Sep 09 11:14:38 PM UTC 24 |
| Peak memory | 625772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_ otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163936305 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_lc_hw_debug_en_test.2163936305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.1015750608 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 5060054440 ps |
| CPU time | 524.66 seconds |
| Started | Sep 09 10:40:32 PM UTC 24 |
| Finished | Sep 09 10:49:25 PM UTC 24 |
| Peak memory | 625652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015750608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.1015750608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.3948764293 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 4255536820 ps |
| CPU time | 390.2 seconds |
| Started | Sep 10 05:28:03 AM UTC 24 |
| Finished | Sep 10 05:34:39 AM UTC 24 |
| Peak memory | 620964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948764293 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.3948764293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.4042103053 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 3884811848 ps |
| CPU time | 463.84 seconds |
| Started | Sep 09 11:09:58 PM UTC 24 |
| Finished | Sep 09 11:17:49 PM UTC 24 |
| Peak memory | 625780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042103053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_ access.4042103053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.2328136154 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 2476866499 ps |
| CPU time | 135.77 seconds |
| Started | Sep 10 05:25:28 AM UTC 24 |
| Finished | Sep 10 05:27:47 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328136154 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.2328136154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.3284576817 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 4067317466 ps |
| CPU time | 455.77 seconds |
| Started | Sep 09 10:52:13 PM UTC 24 |
| Finished | Sep 09 10:59:55 PM UTC 24 |
| Peak memory | 625780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284576817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch ip_sw_rstmgr_cpu_info.3284576817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.3333742713 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 5342339944 ps |
| CPU time | 824.89 seconds |
| Started | Sep 10 04:25:13 AM UTC 24 |
| Finished | Sep 10 04:39:10 AM UTC 24 |
| Peak memory | 674224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333742713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.3333742713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.3798577423 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 5036112320 ps |
| CPU time | 601.19 seconds |
| Started | Sep 10 04:57:35 AM UTC 24 |
| Finished | Sep 10 05:07:44 AM UTC 24 |
| Peak memory | 675052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798577423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.3798577423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.1018525497 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 5442737000 ps |
| CPU time | 578.88 seconds |
| Started | Sep 10 04:19:09 AM UTC 24 |
| Finished | Sep 10 04:28:56 AM UTC 24 |
| Peak memory | 674420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018525497 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.1018525497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.1658694610 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 7647335768 ps |
| CPU time | 1767.12 seconds |
| Started | Sep 09 11:04:50 PM UTC 24 |
| Finished | Sep 09 11:34:40 PM UTC 24 |
| Peak memory | 623908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_ srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658694610 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.1658694610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.3606696191 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 3363241203 ps |
| CPU time | 299.9 seconds |
| Started | Sep 10 05:02:53 AM UTC 24 |
| Finished | Sep 10 05:07:58 AM UTC 24 |
| Peak memory | 620956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606696191 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.3606696191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.3483417585 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 3209837876 ps |
| CPU time | 218.72 seconds |
| Started | Sep 09 11:25:52 PM UTC 24 |
| Finished | Sep 09 11:29:34 PM UTC 24 |
| Peak memory | 652668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483417585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_tap_straps_rma.3483417585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.3043781655 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 685661399 ps |
| CPU time | 78.15 seconds |
| Started | Sep 10 05:03:43 AM UTC 24 |
| Finished | Sep 10 05:05:03 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043781655 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.3043781655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.2819388232 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 6080181180 ps |
| CPU time | 772.1 seconds |
| Started | Sep 09 11:12:08 PM UTC 24 |
| Finished | Sep 09 11:25:11 PM UTC 24 |
| Peak memory | 623540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819388232 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.2819388232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3746803092 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 15596810590 ps |
| CPU time | 1230.84 seconds |
| Started | Sep 09 10:54:52 PM UTC 24 |
| Finished | Sep 09 11:15:38 PM UTC 24 |
| Peak memory | 625856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746803092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3746803092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.845897790 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 13101104342 ps |
| CPU time | 685.76 seconds |
| Started | Sep 10 05:29:58 AM UTC 24 |
| Finished | Sep 10 05:41:33 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845897790 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.845897790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.2346328414 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 48504859705 ps |
| CPU time | 6253.99 seconds |
| Started | Sep 09 10:48:31 PM UTC 24 |
| Finished | Sep 10 12:34:02 AM UTC 24 |
| Peak memory | 643256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346328414 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_dev.2346328414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.3610647228 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 6217147680 ps |
| CPU time | 1088.22 seconds |
| Started | Sep 10 01:33:07 AM UTC 24 |
| Finished | Sep 10 01:51:31 AM UTC 24 |
| Peak memory | 623544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610647228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_plic_all_irqs_0.3610647228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_plic_all_irqs_0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.576864232 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4932560110 ps |
| CPU time | 835.5 seconds |
| Started | Sep 10 01:33:49 AM UTC 24 |
| Finished | Sep 10 01:47:56 AM UTC 24 |
| Peak memory | 623536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=576864232 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_plic_all_irqs_20.576864232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_plic_all_irqs_20/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.939980815 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 5214583590 ps |
| CPU time | 313.05 seconds |
| Started | Sep 10 05:04:38 AM UTC 24 |
| Finished | Sep 10 05:09:56 AM UTC 24 |
| Peak memory | 680444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939980815 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_reset.939980815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.1184165405 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 2946515732 ps |
| CPU time | 240.14 seconds |
| Started | Sep 09 10:54:53 PM UTC 24 |
| Finished | Sep 09 10:58:57 PM UTC 24 |
| Peak memory | 623696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1184165405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_rstmgr_sw_rst.1184165405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1678958313 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 8351883944 ps |
| CPU time | 1349.67 seconds |
| Started | Sep 09 10:41:52 PM UTC 24 |
| Finished | Sep 09 11:04:40 PM UTC 24 |
| Peak memory | 636104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678958313 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_alt_clk_freq.1678958313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.525104867 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3006263720 ps |
| CPU time | 295.84 seconds |
| Started | Sep 09 10:43:24 PM UTC 24 |
| Finished | Sep 09 10:48:25 PM UTC 24 |
| Peak memory | 623596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=525104867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_sleep_pin_retention.525104867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.687131276 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 44015571200 ps |
| CPU time | 5950.09 seconds |
| Started | Sep 10 12:53:20 AM UTC 24 |
| Finished | Sep 10 02:33:45 AM UTC 24 |
| Peak memory | 640936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw _build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687131276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_ earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.687131276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.4110653915 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 95125043827 ps |
| CPU time | 1376.56 seconds |
| Started | Sep 10 05:49:03 AM UTC 24 |
| Finished | Sep 10 06:12:16 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110653915 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.4110653915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.2425477131 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 4449575990 ps |
| CPU time | 531.87 seconds |
| Started | Sep 10 05:21:41 AM UTC 24 |
| Finished | Sep 10 05:30:40 AM UTC 24 |
| Peak memory | 617244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425477131 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.2425477131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.604975400 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 15147545456 ps |
| CPU time | 1348.84 seconds |
| Started | Sep 10 05:10:24 AM UTC 24 |
| Finished | Sep 10 05:33:09 AM UTC 24 |
| Peak memory | 608816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=604975400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.chip_same_csr_outstanding.604975400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.296976557 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4324896968 ps |
| CPU time | 254.04 seconds |
| Started | Sep 10 04:57:13 AM UTC 24 |
| Finished | Sep 10 05:01:31 AM UTC 24 |
| Peak memory | 656116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969765 57 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 0.chip_p adctrl_attributes.296976557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.1383920079 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 6322913656 ps |
| CPU time | 1072.17 seconds |
| Started | Sep 10 03:06:49 AM UTC 24 |
| Finished | Sep 10 03:24:56 AM UTC 24 |
| Peak memory | 625772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383920079 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_plic_all_irqs_0.1383920079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_plic_all_irqs_0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.3917597515 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3329470712 ps |
| CPU time | 450.31 seconds |
| Started | Sep 09 10:43:31 PM UTC 24 |
| Finished | Sep 09 10:51:08 PM UTC 24 |
| Peak memory | 625688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917597515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.3917597515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.3919340924 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 4963101100 ps |
| CPU time | 305.38 seconds |
| Started | Sep 10 02:04:39 AM UTC 24 |
| Finished | Sep 10 02:09:49 AM UTC 24 |
| Peak memory | 625648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919340924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.3919340924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.605773567 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 2818965034 ps |
| CPU time | 386.44 seconds |
| Started | Sep 10 07:00:02 AM UTC 24 |
| Finished | Sep 10 07:06:36 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605773567 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_rand_reset.605773567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2037462880 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 507950678 ps |
| CPU time | 164.21 seconds |
| Started | Sep 10 05:02:09 AM UTC 24 |
| Finished | Sep 10 05:04:56 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037462880 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.2037462880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_rand_baudrate.313203349 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 7444434560 ps |
| CPU time | 1259.58 seconds |
| Started | Sep 09 10:41:46 PM UTC 24 |
| Finished | Sep 09 11:03:02 PM UTC 24 |
| Peak memory | 635896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313203349 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.313203349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.654980021 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 6528014940 ps |
| CPU time | 655.16 seconds |
| Started | Sep 10 01:30:59 AM UTC 24 |
| Finished | Sep 10 01:42:03 AM UTC 24 |
| Peak memory | 623848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654980021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.654980021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.321479439 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 3931330995 ps |
| CPU time | 301.22 seconds |
| Started | Sep 10 05:54:47 AM UTC 24 |
| Finished | Sep 10 05:59:53 AM UTC 24 |
| Peak memory | 621104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321479439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.321479439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/20.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.3971187156 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 4877999730 ps |
| CPU time | 588.47 seconds |
| Started | Sep 10 03:41:20 AM UTC 24 |
| Finished | Sep 10 03:51:16 AM UTC 24 |
| Peak memory | 623532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971187156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.3971187156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.741852192 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 4557403924 ps |
| CPU time | 513.18 seconds |
| Started | Sep 10 03:50:51 AM UTC 24 |
| Finished | Sep 10 03:59:31 AM UTC 24 |
| Peak memory | 623792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741852192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.741852192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.4106145576 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 4378639806 ps |
| CPU time | 581.92 seconds |
| Started | Sep 10 06:00:08 AM UTC 24 |
| Finished | Sep 10 06:09:58 AM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106145576 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.4106145576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.453578539 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 18120120638 ps |
| CPU time | 537.9 seconds |
| Started | Sep 09 10:54:54 PM UTC 24 |
| Finished | Sep 09 11:04:00 PM UTC 24 |
| Peak memory | 636044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453578539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.453578539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.2215137000 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 49054967496 ps |
| CPU time | 6829.01 seconds |
| Started | Sep 09 10:49:05 PM UTC 24 |
| Finished | Sep 10 12:44:17 AM UTC 24 |
| Peak memory | 643428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215137000 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prod.2215137000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.4214807360 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 2093324473 ps |
| CPU time | 206.84 seconds |
| Started | Sep 10 02:20:22 AM UTC 24 |
| Finished | Sep 10 02:23:53 AM UTC 24 |
| Peak memory | 637888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_ access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=4214807360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.4214807360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.714999228 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 9363480153 ps |
| CPU time | 473.49 seconds |
| Started | Sep 10 05:26:56 AM UTC 24 |
| Finished | Sep 10 05:34:56 AM UTC 24 |
| Peak memory | 596108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714999228 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.714999228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.2148836679 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 5207286828 ps |
| CPU time | 669.8 seconds |
| Started | Sep 10 03:06:56 AM UTC 24 |
| Finished | Sep 10 03:18:15 AM UTC 24 |
| Peak memory | 623536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2148836679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_plic_all_irqs_20.2148836679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_plic_all_irqs_20/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3702656479 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 711682910 ps |
| CPU time | 341.91 seconds |
| Started | Sep 10 06:21:55 AM UTC 24 |
| Finished | Sep 10 06:27:42 AM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702656479 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.3702656479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.1342920385 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 5674259240 ps |
| CPU time | 327.69 seconds |
| Started | Sep 09 10:43:39 PM UTC 24 |
| Finished | Sep 09 10:49:12 PM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342920385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.1342920385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.2654918008 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 10566498728 ps |
| CPU time | 815.18 seconds |
| Started | Sep 10 05:08:07 AM UTC 24 |
| Finished | Sep 10 05:21:54 AM UTC 24 |
| Peak memory | 670116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2654918008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.chip_csr_mem_rw_with_rand_reset.2654918008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.986530424 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 25227229000 ps |
| CPU time | 1778.14 seconds |
| Started | Sep 09 10:54:12 PM UTC 24 |
| Finished | Sep 09 11:24:12 PM UTC 24 |
| Peak memory | 630140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_i mages=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986530424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.986530424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2726936299 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 4425206902 ps |
| CPU time | 530.75 seconds |
| Started | Sep 09 11:28:30 PM UTC 24 |
| Finished | Sep 09 11:37:28 PM UTC 24 |
| Peak memory | 623668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726936299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2726936299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.3110283239 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 4421307603 ps |
| CPU time | 153.01 seconds |
| Started | Sep 10 05:04:28 AM UTC 24 |
| Finished | Sep 10 05:07:04 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110283239 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.3110283239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.3080163929 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 1494004258 ps |
| CPU time | 70.94 seconds |
| Started | Sep 10 06:40:56 AM UTC 24 |
| Finished | Sep 10 06:42:09 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080163929 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3080163929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/48.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.2608256693 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 4127992482 ps |
| CPU time | 480 seconds |
| Started | Sep 10 03:06:44 AM UTC 24 |
| Finished | Sep 10 03:14:51 AM UTC 24 |
| Peak memory | 623600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2608256693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_plic_all_irqs_10.2608256693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_plic_all_irqs_10/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.1211759066 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 4224202600 ps |
| CPU time | 439.41 seconds |
| Started | Sep 09 10:40:07 PM UTC 24 |
| Finished | Sep 09 10:47:33 PM UTC 24 |
| Peak memory | 640012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211759066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.1211759066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.2176425665 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 3625299940 ps |
| CPU time | 523.1 seconds |
| Started | Sep 09 10:41:29 PM UTC 24 |
| Finished | Sep 09 10:50:20 PM UTC 24 |
| Peak memory | 639980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176425665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.2176425665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3373462243 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 3870924980 ps |
| CPU time | 598.36 seconds |
| Started | Sep 09 11:17:32 PM UTC 24 |
| Finished | Sep 09 11:27:39 PM UTC 24 |
| Peak memory | 625784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373462243 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_dev.3373462243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.2687218197 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 778648992 ps |
| CPU time | 71.72 seconds |
| Started | Sep 10 05:11:59 AM UTC 24 |
| Finished | Sep 10 05:13:12 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687218197 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.2687218197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.610072115 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 21808859480 ps |
| CPU time | 1937.15 seconds |
| Started | Sep 09 10:42:03 PM UTC 24 |
| Finished | Sep 09 11:14:45 PM UTC 24 |
| Peak memory | 630880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610072115 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.610072115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_init/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.3419423013 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 5306191593 ps |
| CPU time | 563.49 seconds |
| Started | Sep 10 06:07:49 AM UTC 24 |
| Finished | Sep 10 06:17:20 AM UTC 24 |
| Peak memory | 595920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419423013 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3419423013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/25.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.4211617059 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 11462705105 ps |
| CPU time | 764.31 seconds |
| Started | Sep 10 05:37:54 AM UTC 24 |
| Finished | Sep 10 05:50:49 AM UTC 24 |
| Peak memory | 596004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211617059 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.4211617059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.569170805 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 663939191 ps |
| CPU time | 375.29 seconds |
| Started | Sep 10 06:42:35 AM UTC 24 |
| Finished | Sep 10 06:48:55 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569170805 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.569170805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.2650194336 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 7658564072 ps |
| CPU time | 1476.54 seconds |
| Started | Sep 09 10:42:59 PM UTC 24 |
| Finished | Sep 09 11:07:55 PM UTC 24 |
| Peak memory | 623800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650194336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.2650194336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.6490260 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 33328239397 ps |
| CPU time | 6616.95 seconds |
| Started | Sep 10 01:50:46 AM UTC 24 |
| Finished | Sep 10 03:42:25 AM UTC 24 |
| Peak memory | 628916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim _dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6490260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.6490260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.2399892748 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 31476360121 ps |
| CPU time | 3640.78 seconds |
| Started | Sep 10 04:58:45 AM UTC 24 |
| Finished | Sep 10 06:00:09 AM UTC 24 |
| Peak memory | 613820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2399892748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.chip_same_csr_outstanding.2399892748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.2148618068 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 4507280701 ps |
| CPU time | 383.33 seconds |
| Started | Sep 10 05:30:20 AM UTC 24 |
| Finished | Sep 10 05:36:49 AM UTC 24 |
| Peak memory | 620960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148618068 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.2148618068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.2749928064 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 44826503592 ps |
| CPU time | 6326.43 seconds |
| Started | Sep 10 02:17:25 AM UTC 24 |
| Finished | Sep 10 04:04:15 AM UTC 24 |
| Peak memory | 638892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw _build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749928064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip _earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.2749928064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1904710470 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 9051528666 ps |
| CPU time | 419.16 seconds |
| Started | Sep 09 10:53:15 PM UTC 24 |
| Finished | Sep 09 11:00:20 PM UTC 24 |
| Peak memory | 625896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1904710470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.chip_sw_pwrmgr_full_aon_reset.1904710470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.3718994208 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 11946460300 ps |
| CPU time | 1448.84 seconds |
| Started | Sep 10 01:02:45 AM UTC 24 |
| Finished | Sep 10 01:27:14 AM UTC 24 |
| Peak memory | 625640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_buil d_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718994208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.3718994208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.3622011924 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 2863276986 ps |
| CPU time | 301.12 seconds |
| Started | Sep 09 11:13:04 PM UTC 24 |
| Finished | Sep 09 11:18:10 PM UTC 24 |
| Peak memory | 625516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3622011924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_plic_sw_irq.3622011924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.748479086 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 2093500142 ps |
| CPU time | 194.33 seconds |
| Started | Sep 10 06:33:07 AM UTC 24 |
| Finished | Sep 10 06:36:24 AM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748479086 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.748479086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/42.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.8919743 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 3474420424 ps |
| CPU time | 402.14 seconds |
| Started | Sep 09 11:03:21 PM UTC 24 |
| Finished | Sep 09 11:10:09 PM UTC 24 |
| Peak memory | 672424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8919743 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_slee p_mode_alerts.8919743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2642917927 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 16615449028 ps |
| CPU time | 4274.39 seconds |
| Started | Sep 09 10:55:32 PM UTC 24 |
| Finished | Sep 10 12:07:41 AM UTC 24 |
| Peak memory | 628772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642917927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.2642917927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2532049534 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2891384696 ps |
| CPU time | 271.12 seconds |
| Started | Sep 09 10:44:32 PM UTC 24 |
| Finished | Sep 09 10:49:08 PM UTC 24 |
| Peak memory | 639856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_ access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2532049534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.2532049534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.3953448694 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 5956890920 ps |
| CPU time | 361.46 seconds |
| Started | Sep 10 05:10:15 AM UTC 24 |
| Finished | Sep 10 05:16:22 AM UTC 24 |
| Peak memory | 680224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953448694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_reset.3953448694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.1811456407 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 69075709 ps |
| CPU time | 59.28 seconds |
| Started | Sep 10 05:49:59 AM UTC 24 |
| Finished | Sep 10 05:51:00 AM UTC 24 |
| Peak memory | 595940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811456407 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.1811456407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.873632589 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 3511565776 ps |
| CPU time | 201.58 seconds |
| Started | Sep 10 05:24:35 AM UTC 24 |
| Finished | Sep 10 05:28:00 AM UTC 24 |
| Peak memory | 621192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873632589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.873632589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1182212848 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 3638399460 ps |
| CPU time | 425.74 seconds |
| Started | Sep 10 01:17:28 AM UTC 24 |
| Finished | Sep 10 01:24:40 AM UTC 24 |
| Peak memory | 672464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182212848 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_s leep_mode_alerts.1182212848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.1800739254 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 3914159090 ps |
| CPU time | 568.13 seconds |
| Started | Sep 10 12:41:11 AM UTC 24 |
| Finished | Sep 10 12:50:48 AM UTC 24 |
| Peak memory | 674296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800739254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.1800739254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3935514511 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 4000909888 ps |
| CPU time | 294.54 seconds |
| Started | Sep 10 04:07:25 AM UTC 24 |
| Finished | Sep 10 04:12:24 AM UTC 24 |
| Peak memory | 672356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935514511 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3935514511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.3143254397 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 5089344840 ps |
| CPU time | 670.58 seconds |
| Started | Sep 10 04:05:31 AM UTC 24 |
| Finished | Sep 10 04:16:51 AM UTC 24 |
| Peak memory | 674220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143254397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.3143254397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1044829733 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 4060740310 ps |
| CPU time | 404.59 seconds |
| Started | Sep 10 04:08:25 AM UTC 24 |
| Finished | Sep 10 04:15:16 AM UTC 24 |
| Peak memory | 672272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044829733 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1044829733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.907939691 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 5315949660 ps |
| CPU time | 756.13 seconds |
| Started | Sep 10 04:08:30 AM UTC 24 |
| Finished | Sep 10 04:21:16 AM UTC 24 |
| Peak memory | 674224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907939691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.907939691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.403860914 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 3831577304 ps |
| CPU time | 523.62 seconds |
| Started | Sep 10 04:08:47 AM UTC 24 |
| Finished | Sep 10 04:17:38 AM UTC 24 |
| Peak memory | 672188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403860914 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_alert_handler_lpg_s leep_mode_alerts.403860914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.3976156510 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 5088864824 ps |
| CPU time | 629.98 seconds |
| Started | Sep 10 04:08:31 AM UTC 24 |
| Finished | Sep 10 04:19:09 AM UTC 24 |
| Peak memory | 674424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976156510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.3976156510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2903638017 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 3942543420 ps |
| CPU time | 465.68 seconds |
| Started | Sep 10 04:12:20 AM UTC 24 |
| Finished | Sep 10 04:20:14 AM UTC 24 |
| Peak memory | 672412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903638017 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2903638017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.2404091280 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 5072924856 ps |
| CPU time | 661.89 seconds |
| Started | Sep 10 04:12:23 AM UTC 24 |
| Finished | Sep 10 04:23:34 AM UTC 24 |
| Peak memory | 674436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404091280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.2404091280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.632821026 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 3480093770 ps |
| CPU time | 439.62 seconds |
| Started | Sep 10 04:13:07 AM UTC 24 |
| Finished | Sep 10 04:20:33 AM UTC 24 |
| Peak memory | 672184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632821026 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_alert_handler_lpg_s leep_mode_alerts.632821026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.4220081 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 4237022120 ps |
| CPU time | 430.07 seconds |
| Started | Sep 10 04:16:22 AM UTC 24 |
| Finished | Sep 10 04:23:38 AM UTC 24 |
| Peak memory | 672184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220081 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_alert_handler_lpg_sle ep_mode_alerts.4220081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2503343901 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 3780885248 ps |
| CPU time | 349.95 seconds |
| Started | Sep 10 04:19:06 AM UTC 24 |
| Finished | Sep 10 04:25:01 AM UTC 24 |
| Peak memory | 672184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503343901 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2503343901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.126937621 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 3481036776 ps |
| CPU time | 377.23 seconds |
| Started | Sep 10 04:19:17 AM UTC 24 |
| Finished | Sep 10 04:25:40 AM UTC 24 |
| Peak memory | 672256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126937621 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_alert_handler_lpg_s leep_mode_alerts.126937621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.2748619479 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 5556016916 ps |
| CPU time | 579.54 seconds |
| Started | Sep 10 04:19:15 AM UTC 24 |
| Finished | Sep 10 04:29:03 AM UTC 24 |
| Peak memory | 674456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748619479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.2748619479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.985580311 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 3406541224 ps |
| CPU time | 315.6 seconds |
| Started | Sep 10 04:20:08 AM UTC 24 |
| Finished | Sep 10 04:25:29 AM UTC 24 |
| Peak memory | 672256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985580311 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_alert_handler_lpg_s leep_mode_alerts.985580311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.4037875429 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 5985927734 ps |
| CPU time | 776.65 seconds |
| Started | Sep 10 04:19:48 AM UTC 24 |
| Finished | Sep 10 04:32:57 AM UTC 24 |
| Peak memory | 674524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037875429 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.4037875429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1406256318 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 3873364968 ps |
| CPU time | 396.65 seconds |
| Started | Sep 10 02:49:39 AM UTC 24 |
| Finished | Sep 10 02:56:21 AM UTC 24 |
| Peak memory | 672176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406256318 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_s leep_mode_alerts.1406256318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.3601949317 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 5668829208 ps |
| CPU time | 629.34 seconds |
| Started | Sep 10 02:03:57 AM UTC 24 |
| Finished | Sep 10 02:14:34 AM UTC 24 |
| Peak memory | 674320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601949317 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.3601949317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1816528513 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 4340647864 ps |
| CPU time | 416.82 seconds |
| Started | Sep 10 04:22:14 AM UTC 24 |
| Finished | Sep 10 04:29:17 AM UTC 24 |
| Peak memory | 670436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816528513 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1816528513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2727716995 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 3364323686 ps |
| CPU time | 395.96 seconds |
| Started | Sep 10 04:22:16 AM UTC 24 |
| Finished | Sep 10 04:28:58 AM UTC 24 |
| Peak memory | 672368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727716995 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2727716995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.3101090451 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 5678514660 ps |
| CPU time | 450.31 seconds |
| Started | Sep 10 04:22:20 AM UTC 24 |
| Finished | Sep 10 04:29:57 AM UTC 24 |
| Peak memory | 674456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101090451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.3101090451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3657254600 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 3831032500 ps |
| CPU time | 406.5 seconds |
| Started | Sep 10 04:22:50 AM UTC 24 |
| Finished | Sep 10 04:29:42 AM UTC 24 |
| Peak memory | 672184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657254600 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3657254600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.4157183344 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 6264497524 ps |
| CPU time | 758.33 seconds |
| Started | Sep 10 04:22:21 AM UTC 24 |
| Finished | Sep 10 04:35:09 AM UTC 24 |
| Peak memory | 674472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157183344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.4157183344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2594981274 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 3991730590 ps |
| CPU time | 433.97 seconds |
| Started | Sep 10 04:23:21 AM UTC 24 |
| Finished | Sep 10 04:30:41 AM UTC 24 |
| Peak memory | 672412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594981274 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2594981274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2435680088 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 3623142750 ps |
| CPU time | 421.5 seconds |
| Started | Sep 10 04:25:12 AM UTC 24 |
| Finished | Sep 10 04:32:20 AM UTC 24 |
| Peak memory | 672180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435680088 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2435680088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.916507953 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 3912230760 ps |
| CPU time | 469 seconds |
| Started | Sep 10 04:25:08 AM UTC 24 |
| Finished | Sep 10 04:33:04 AM UTC 24 |
| Peak memory | 672440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916507953 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_alert_handler_lpg_s leep_mode_alerts.916507953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.3244748458 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 5435873300 ps |
| CPU time | 657.59 seconds |
| Started | Sep 10 04:25:08 AM UTC 24 |
| Finished | Sep 10 04:36:15 AM UTC 24 |
| Peak memory | 674220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244748458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.3244748458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3267874768 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 3818366200 ps |
| CPU time | 344.93 seconds |
| Started | Sep 10 04:26:48 AM UTC 24 |
| Finished | Sep 10 04:32:38 AM UTC 24 |
| Peak memory | 672252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267874768 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3267874768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.254199871 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 4758075800 ps |
| CPU time | 694.3 seconds |
| Started | Sep 10 04:26:26 AM UTC 24 |
| Finished | Sep 10 04:38:10 AM UTC 24 |
| Peak memory | 674212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254199871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.254199871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2360949420 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 3823951338 ps |
| CPU time | 375.5 seconds |
| Started | Sep 10 04:26:44 AM UTC 24 |
| Finished | Sep 10 04:33:05 AM UTC 24 |
| Peak memory | 672420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360949420 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2360949420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.1426745661 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 5562451720 ps |
| CPU time | 587.63 seconds |
| Started | Sep 10 04:26:51 AM UTC 24 |
| Finished | Sep 10 04:36:47 AM UTC 24 |
| Peak memory | 674224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426745661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.1426745661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.1008251226 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 5285495040 ps |
| CPU time | 687.47 seconds |
| Started | Sep 10 04:27:37 AM UTC 24 |
| Finished | Sep 10 04:39:14 AM UTC 24 |
| Peak memory | 674228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008251226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.1008251226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.4245631940 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 4488873280 ps |
| CPU time | 505.39 seconds |
| Started | Sep 10 04:30:49 AM UTC 24 |
| Finished | Sep 10 04:39:22 AM UTC 24 |
| Peak memory | 674448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245631940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.4245631940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.981096868 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 4657331158 ps |
| CPU time | 451.72 seconds |
| Started | Sep 10 04:31:01 AM UTC 24 |
| Finished | Sep 10 04:38:40 AM UTC 24 |
| Peak memory | 672392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981096868 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_alert_handler_lpg_s leep_mode_alerts.981096868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.3899585923 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 6307129080 ps |
| CPU time | 743.25 seconds |
| Started | Sep 10 04:30:59 AM UTC 24 |
| Finished | Sep 10 04:43:33 AM UTC 24 |
| Peak memory | 674288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899585923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.3899585923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.607021279 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 3668190490 ps |
| CPU time | 374.92 seconds |
| Started | Sep 10 04:31:37 AM UTC 24 |
| Finished | Sep 10 04:37:58 AM UTC 24 |
| Peak memory | 672388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607021279 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_alert_handler_lpg_s leep_mode_alerts.607021279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.4285871986 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 5263935300 ps |
| CPU time | 537.22 seconds |
| Started | Sep 10 04:30:58 AM UTC 24 |
| Finished | Sep 10 04:40:03 AM UTC 24 |
| Peak memory | 674216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285871986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.4285871986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.190155959 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 3834251524 ps |
| CPU time | 316.99 seconds |
| Started | Sep 10 04:32:42 AM UTC 24 |
| Finished | Sep 10 04:38:04 AM UTC 24 |
| Peak memory | 672188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190155959 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_alert_handler_lpg_s leep_mode_alerts.190155959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.558007827 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 6034978770 ps |
| CPU time | 706.19 seconds |
| Started | Sep 10 04:32:40 AM UTC 24 |
| Finished | Sep 10 04:44:36 AM UTC 24 |
| Peak memory | 674292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558007827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.558007827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.4128619287 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 4517355524 ps |
| CPU time | 601 seconds |
| Started | Sep 10 04:32:45 AM UTC 24 |
| Finished | Sep 10 04:42:55 AM UTC 24 |
| Peak memory | 674460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128619287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.4128619287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.2545138668 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 5667949572 ps |
| CPU time | 549.92 seconds |
| Started | Sep 10 04:34:38 AM UTC 24 |
| Finished | Sep 10 04:43:56 AM UTC 24 |
| Peak memory | 674528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545138668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.2545138668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2904642637 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 3658767704 ps |
| CPU time | 397.56 seconds |
| Started | Sep 10 04:37:44 AM UTC 24 |
| Finished | Sep 10 04:44:27 AM UTC 24 |
| Peak memory | 672248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904642637 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2904642637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.3588069719 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 6060272856 ps |
| CPU time | 447.51 seconds |
| Started | Sep 10 04:37:48 AM UTC 24 |
| Finished | Sep 10 04:45:22 AM UTC 24 |
| Peak memory | 674460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588069719 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.3588069719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2405677579 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 3866172648 ps |
| CPU time | 353.91 seconds |
| Started | Sep 10 04:37:45 AM UTC 24 |
| Finished | Sep 10 04:43:44 AM UTC 24 |
| Peak memory | 672200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405677579 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2405677579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.3970594243 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 4942809240 ps |
| CPU time | 524.8 seconds |
| Started | Sep 10 04:37:49 AM UTC 24 |
| Finished | Sep 10 04:46:41 AM UTC 24 |
| Peak memory | 674448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970594243 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.3970594243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.408757408 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 5181438296 ps |
| CPU time | 587.39 seconds |
| Started | Sep 10 04:37:48 AM UTC 24 |
| Finished | Sep 10 04:47:43 AM UTC 24 |
| Peak memory | 674468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408757408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.408757408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.819886416 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 3635509190 ps |
| CPU time | 352.29 seconds |
| Started | Sep 10 04:40:45 AM UTC 24 |
| Finished | Sep 10 04:46:42 AM UTC 24 |
| Peak memory | 672188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819886416 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_alert_handler_lpg_s leep_mode_alerts.819886416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.251618381 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 5059074464 ps |
| CPU time | 426.48 seconds |
| Started | Sep 10 04:41:21 AM UTC 24 |
| Finished | Sep 10 04:48:33 AM UTC 24 |
| Peak memory | 674476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251618381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.251618381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.735859552 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 4351975892 ps |
| CPU time | 439.66 seconds |
| Started | Sep 10 03:52:55 AM UTC 24 |
| Finished | Sep 10 04:00:21 AM UTC 24 |
| Peak memory | 674344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735859552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.735859552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.955686418 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 4129326520 ps |
| CPU time | 355.27 seconds |
| Started | Sep 10 04:41:19 AM UTC 24 |
| Finished | Sep 10 04:47:19 AM UTC 24 |
| Peak memory | 672308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955686418 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_alert_handler_lpg_s leep_mode_alerts.955686418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_all_escalation_resets.590663527 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 4867734616 ps |
| CPU time | 532.76 seconds |
| Started | Sep 10 04:41:14 AM UTC 24 |
| Finished | Sep 10 04:50:15 AM UTC 24 |
| Peak memory | 674472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590663527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.590663527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.4178860605 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 4509186168 ps |
| CPU time | 504.67 seconds |
| Started | Sep 10 04:41:18 AM UTC 24 |
| Finished | Sep 10 04:49:50 AM UTC 24 |
| Peak memory | 674220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178860605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.4178860605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.1462215139 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 4603474716 ps |
| CPU time | 438.83 seconds |
| Started | Sep 10 04:42:02 AM UTC 24 |
| Finished | Sep 10 04:49:27 AM UTC 24 |
| Peak memory | 674396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462215139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.1462215139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3453868102 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 3071791950 ps |
| CPU time | 290.85 seconds |
| Started | Sep 10 04:45:26 AM UTC 24 |
| Finished | Sep 10 04:50:21 AM UTC 24 |
| Peak memory | 672444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453868102 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3453868102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.2917096947 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 5014953128 ps |
| CPU time | 570.18 seconds |
| Started | Sep 10 04:44:55 AM UTC 24 |
| Finished | Sep 10 04:54:33 AM UTC 24 |
| Peak memory | 674308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917096947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.2917096947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1649543906 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 4356603570 ps |
| CPU time | 509.11 seconds |
| Started | Sep 10 03:57:33 AM UTC 24 |
| Finished | Sep 10 04:06:10 AM UTC 24 |
| Peak memory | 672256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649543906 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_alert_handler_lpg_s leep_mode_alerts.1649543906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.4004725850 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 5297588324 ps |
| CPU time | 606.37 seconds |
| Started | Sep 10 03:55:41 AM UTC 24 |
| Finished | Sep 10 04:05:56 AM UTC 24 |
| Peak memory | 674220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004725850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.4004725850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.4165228874 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 4244172112 ps |
| CPU time | 315.88 seconds |
| Started | Sep 10 04:45:46 AM UTC 24 |
| Finished | Sep 10 04:51:06 AM UTC 24 |
| Peak memory | 672184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165228874 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_alert_handler_lpg_ sleep_mode_alerts.4165228874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.954536935 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 5121669960 ps |
| CPU time | 550.65 seconds |
| Started | Sep 10 04:47:02 AM UTC 24 |
| Finished | Sep 10 04:56:20 AM UTC 24 |
| Peak memory | 674556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954536935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.954536935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.1224789577 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 5369205768 ps |
| CPU time | 519.04 seconds |
| Started | Sep 10 04:46:25 AM UTC 24 |
| Finished | Sep 10 04:55:11 AM UTC 24 |
| Peak memory | 674440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224789577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.1224789577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2745667594 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 3463868064 ps |
| CPU time | 374.52 seconds |
| Started | Sep 10 04:50:04 AM UTC 24 |
| Finished | Sep 10 04:56:24 AM UTC 24 |
| Peak memory | 672180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745667594 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2745667594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.431422993 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 5851141908 ps |
| CPU time | 591.36 seconds |
| Started | Sep 10 04:47:23 AM UTC 24 |
| Finished | Sep 10 04:57:22 AM UTC 24 |
| Peak memory | 674464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431422993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.431422993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.3747825582 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 6709450704 ps |
| CPU time | 621.16 seconds |
| Started | Sep 10 04:48:53 AM UTC 24 |
| Finished | Sep 10 04:59:23 AM UTC 24 |
| Peak memory | 674220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747825582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.3747825582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3196313821 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 2785754772 ps |
| CPU time | 300.35 seconds |
| Started | Sep 10 04:50:09 AM UTC 24 |
| Finished | Sep 10 04:55:14 AM UTC 24 |
| Peak memory | 672340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196313821 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3196313821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.1764163697 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 5056914432 ps |
| CPU time | 627.03 seconds |
| Started | Sep 10 04:51:06 AM UTC 24 |
| Finished | Sep 10 05:01:42 AM UTC 24 |
| Peak memory | 674940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764163697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.1764163697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.4274551641 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 3931191864 ps |
| CPU time | 372.97 seconds |
| Started | Sep 10 04:50:54 AM UTC 24 |
| Finished | Sep 10 04:57:13 AM UTC 24 |
| Peak memory | 672376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274551641 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_alert_handler_lpg_ sleep_mode_alerts.4274551641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.4167325342 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 5165358882 ps |
| CPU time | 519.17 seconds |
| Started | Sep 10 04:52:56 AM UTC 24 |
| Finished | Sep 10 05:01:42 AM UTC 24 |
| Peak memory | 674220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167325342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.4167325342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.1252286239 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 6139864278 ps |
| CPU time | 670.05 seconds |
| Started | Sep 10 04:53:08 AM UTC 24 |
| Finished | Sep 10 05:04:27 AM UTC 24 |
| Peak memory | 674868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252286239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.1252286239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.2056391401 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 223797278 ps |
| CPU time | 32.61 seconds |
| Started | Sep 10 05:00:46 AM UTC 24 |
| Finished | Sep 10 05:01:20 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056391401 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.2056391401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.1866662257 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 3599583892 ps |
| CPU time | 275.79 seconds |
| Started | Sep 10 05:40:55 AM UTC 24 |
| Finished | Sep 10 05:45:35 AM UTC 24 |
| Peak memory | 620964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866662257 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.1866662257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2887267213 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 25211968950 ps |
| CPU time | 2039.16 seconds |
| Started | Sep 09 11:12:23 PM UTC 24 |
| Finished | Sep 09 11:46:47 PM UTC 24 |
| Peak memory | 625712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887267213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_re set_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.2887267213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3522928696 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 3821148012 ps |
| CPU time | 406.28 seconds |
| Started | Sep 09 11:25:06 PM UTC 24 |
| Finished | Sep 09 11:31:58 PM UTC 24 |
| Peak memory | 625808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=3522928696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_pwrmgr_lowpower_cancel.3522928696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.298636626 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 5320370880 ps |
| CPU time | 338.44 seconds |
| Started | Sep 09 11:25:05 PM UTC 24 |
| Finished | Sep 09 11:30:49 PM UTC 24 |
| Peak memory | 625868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298636626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.298636626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.234587404 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4248710822 ps |
| CPU time | 485.87 seconds |
| Started | Sep 10 12:52:17 AM UTC 24 |
| Finished | Sep 10 01:00:29 AM UTC 24 |
| Peak memory | 623700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=234587404 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_gpio.234587404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_gpio/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pattgen_ios.1879917886 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 2477449180 ps |
| CPU time | 247.58 seconds |
| Started | Sep 10 12:46:04 AM UTC 24 |
| Finished | Sep 10 12:50:16 AM UTC 24 |
| Peak memory | 623720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_im ages=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879917886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.1879917886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pattgen_ios/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2371774520 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 5643551833 ps |
| CPU time | 520.6 seconds |
| Started | Sep 09 11:25:07 PM UTC 24 |
| Finished | Sep 09 11:33:55 PM UTC 24 |
| Peak memory | 640164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_han dler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371774520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_esc alation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.2371774520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.1883473787 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 3953757464 ps |
| CPU time | 411.86 seconds |
| Started | Sep 09 11:24:40 PM UTC 24 |
| Finished | Sep 09 11:31:38 PM UTC 24 |
| Peak memory | 636024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883473787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_ reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.1883473787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1406445299 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 5109570814 ps |
| CPU time | 661.16 seconds |
| Started | Sep 09 10:42:20 PM UTC 24 |
| Finished | Sep 09 10:53:30 PM UTC 24 |
| Peak memory | 623600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1406445299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.1406445299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.1492904939 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 3772667604 ps |
| CPU time | 489.47 seconds |
| Started | Sep 10 01:33:26 AM UTC 24 |
| Finished | Sep 10 01:41:43 AM UTC 24 |
| Peak memory | 623728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1492904939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_plic_all_irqs_10.1492904939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_plic_all_irqs_10/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1363461173 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 3922642118 ps |
| CPU time | 565.44 seconds |
| Started | Sep 10 02:15:49 AM UTC 24 |
| Finished | Sep 10 02:25:22 AM UTC 24 |
| Peak memory | 623464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363461173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.1363461173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_masking_off.3523570733 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 3055786664 ps |
| CPU time | 262.08 seconds |
| Started | Sep 09 10:59:02 PM UTC 24 |
| Finished | Sep 09 11:03:28 PM UTC 24 |
| Peak memory | 623764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523570733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_aes_masking_off.3523570733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_masking_off/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1722204626 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 7671158672 ps |
| CPU time | 528.8 seconds |
| Started | Sep 09 10:55:03 PM UTC 24 |
| Finished | Sep 09 11:03:59 PM UTC 24 |
| Peak memory | 632056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722204626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1722204626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.3172710396 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 15941086003 ps |
| CPU time | 1573.2 seconds |
| Started | Sep 09 11:24:59 PM UTC 24 |
| Finished | Sep 09 11:51:32 PM UTC 24 |
| Peak memory | 640464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172710396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.3172710396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_rst_inputs.57785765 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 19767238657 ps |
| CPU time | 2899.03 seconds |
| Started | Sep 10 01:50:02 AM UTC 24 |
| Finished | Sep 10 02:39:00 AM UTC 24 |
| Peak memory | 628716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_ images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57785765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.57785765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2677744647 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 3157807738 ps |
| CPU time | 187.08 seconds |
| Started | Sep 10 12:56:40 AM UTC 24 |
| Finished | Sep 10 12:59:51 AM UTC 24 |
| Peak memory | 637968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_ access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2677744647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.2677744647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.1282288816 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 2291471487 ps |
| CPU time | 234.66 seconds |
| Started | Sep 09 11:06:04 PM UTC 24 |
| Finished | Sep 09 11:10:03 PM UTC 24 |
| Peak memory | 625736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1282288816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.chip_sw_hmac_enc_jitter_en.1282288816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.2691181718 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 2197568320 ps |
| CPU time | 273.02 seconds |
| Started | Sep 10 12:51:00 AM UTC 24 |
| Finished | Sep 10 12:55:37 AM UTC 24 |
| Peak memory | 625896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691181718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 1.chip_sw_spi_host_tx_rx.2691181718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.4150627855 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 15322105178 ps |
| CPU time | 817.44 seconds |
| Started | Sep 10 05:00:00 AM UTC 24 |
| Finished | Sep 10 05:13:52 AM UTC 24 |
| Peak memory | 606536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_c pu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4150627855 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. chip_rv_dm_lc_disabled.4150627855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.3462052398 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 8351151350 ps |
| CPU time | 1301.91 seconds |
| Started | Sep 09 11:00:37 PM UTC 24 |
| Finished | Sep 09 11:22:35 PM UTC 24 |
| Peak memory | 625800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462052398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.3462052398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.2743140116 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 14285281520 ps |
| CPU time | 3829.13 seconds |
| Started | Sep 09 11:08:34 PM UTC 24 |
| Finished | Sep 10 12:13:10 AM UTC 24 |
| Peak memory | 628928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743140116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.2743140116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.2016988991 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 4848319040 ps |
| CPU time | 390.06 seconds |
| Started | Sep 09 11:23:22 PM UTC 24 |
| Finished | Sep 09 11:29:57 PM UTC 24 |
| Peak memory | 625844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016988991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_l c_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.2016988991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.2825515544 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 4674984012 ps |
| CPU time | 240.29 seconds |
| Started | Sep 10 05:02:29 AM UTC 24 |
| Finished | Sep 10 05:06:33 AM UTC 24 |
| Peak memory | 680224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825515544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_reset.2825515544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.2491811356 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1319748491 ps |
| CPU time | 49.14 seconds |
| Started | Sep 10 05:01:58 AM UTC 24 |
| Finished | Sep 10 05:02:48 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491811356 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2491811356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.1245896434 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 280285284 ps |
| CPU time | 33.62 seconds |
| Started | Sep 10 05:03:59 AM UTC 24 |
| Finished | Sep 10 05:04:34 AM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245896434 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1245896434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.3431665362 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 14860305707 ps |
| CPU time | 455.8 seconds |
| Started | Sep 10 05:51:59 AM UTC 24 |
| Finished | Sep 10 05:59:41 AM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431665362 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3431665362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.3027881553 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 4137348178 ps |
| CPU time | 326.52 seconds |
| Started | Sep 10 06:23:58 AM UTC 24 |
| Finished | Sep 10 06:29:29 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027881553 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3027881553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/35.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3517943960 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 1756841362 ps |
| CPU time | 202.79 seconds |
| Started | Sep 10 06:23:59 AM UTC 24 |
| Finished | Sep 10 06:27:25 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517943960 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.3517943960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.1535558579 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 17243577819 ps |
| CPU time | 606.82 seconds |
| Started | Sep 10 07:04:50 AM UTC 24 |
| Finished | Sep 10 07:15:05 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535558579 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.1535558579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/68.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.1359398772 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 2873408963 ps |
| CPU time | 294.23 seconds |
| Started | Sep 10 07:09:11 AM UTC 24 |
| Finished | Sep 10 07:14:09 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359398772 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_reset_error.1359398772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.3835893109 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 1731732288 ps |
| CPU time | 72.32 seconds |
| Started | Sep 10 07:34:04 AM UTC 24 |
| Finished | Sep 10 07:35:18 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835893109 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.3835893109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/92.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_error.3670227127 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 8722463698 ps |
| CPU time | 243.17 seconds |
| Started | Sep 10 07:40:48 AM UTC 24 |
| Finished | Sep 10 07:44:55 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670227127 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.3670227127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/97.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_random.4075207767 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 772869135 ps |
| CPU time | 33.82 seconds |
| Started | Sep 10 07:42:59 AM UTC 24 |
| Finished | Sep 10 07:43:34 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075207767 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.4075207767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/99.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.57894832 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 5955050072 ps |
| CPU time | 638.8 seconds |
| Started | Sep 09 10:40:07 PM UTC 24 |
| Finished | Sep 09 10:50:54 PM UTC 24 |
| Peak memory | 623736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=57894832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.57894832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.3336919641 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 13123767920 ps |
| CPU time | 1806.41 seconds |
| Started | Sep 09 10:52:42 PM UTC 24 |
| Finished | Sep 09 11:23:12 PM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_buil d_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336919641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.3336919641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1234914487 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 4363600076 ps |
| CPU time | 635.27 seconds |
| Started | Sep 09 10:56:05 PM UTC 24 |
| Finished | Sep 09 11:06:48 PM UTC 24 |
| Peak memory | 623528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234914487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.1234914487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.361509189 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 4050906202 ps |
| CPU time | 437 seconds |
| Started | Sep 10 01:41:08 AM UTC 24 |
| Finished | Sep 10 01:48:32 AM UTC 24 |
| Peak memory | 625568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=361509189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_pwrmgr_lowpower_cancel.361509189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.1149998089 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 3478400229 ps |
| CPU time | 280.53 seconds |
| Started | Sep 10 12:51:00 AM UTC 24 |
| Finished | Sep 10 12:55:45 AM UTC 24 |
| Peak memory | 636356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1149998089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_device_pinmux_sleep_retention.1149998089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.3839569514 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 3013847080 ps |
| CPU time | 420.07 seconds |
| Started | Sep 09 11:02:49 PM UTC 24 |
| Finished | Sep 09 11:09:55 PM UTC 24 |
| Peak memory | 623664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerat e_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839569514 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_boot_mode.3839569514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_inject_scramble_seed.4190887929 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 66557508491 ps |
| CPU time | 16381.3 seconds |
| Started | Sep 09 10:43:52 PM UTC 24 |
| Finished | Sep 10 03:20:14 AM UTC 24 |
| Peak memory | 643284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=1 50_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190887929 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.4190887929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.4137523344 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 2872239460 ps |
| CPU time | 389.4 seconds |
| Started | Sep 09 10:55:37 PM UTC 24 |
| Finished | Sep 09 11:02:12 PM UTC 24 |
| Peak memory | 625520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137523344 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.4137523344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.545958564 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 2120687400 ps |
| CPU time | 128.02 seconds |
| Started | Sep 09 11:26:51 PM UTC 24 |
| Finished | Sep 09 11:29:01 PM UTC 24 |
| Peak memory | 673680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_ima ges=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=545958564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.545958564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3570509049 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 24214432886 ps |
| CPU time | 7358.45 seconds |
| Started | Sep 09 11:40:02 PM UTC 24 |
| Finished | Sep 10 01:44:16 AM UTC 24 |
| Peak memory | 626716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570509049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3570509049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.2997137789 |
| Short name | T2913 |
| Test name | |
| Test status | |
| Simulation time | 51429169528 ps |
| CPU time | 10131.9 seconds |
| Started | Sep 10 04:58:42 AM UTC 24 |
| Finished | Sep 10 07:49:29 AM UTC 24 |
| Peak memory | 654916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2997137789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_ csr_aliasing.2997137789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.1888526938 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 49440837251 ps |
| CPU time | 5032.98 seconds |
| Started | Sep 10 04:58:32 AM UTC 24 |
| Finished | Sep 10 06:23:24 AM UTC 24 |
| Peak memory | 620152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1888526938 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.chip_csr_bit_bash.1888526938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3718553733 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 7337748100 ps |
| CPU time | 600.33 seconds |
| Started | Sep 10 05:02:46 AM UTC 24 |
| Finished | Sep 10 05:12:55 AM UTC 24 |
| Peak memory | 660000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3718553733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.chip_csr_mem_rw_with_rand_reset.3718553733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.638018789 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 4621312552 ps |
| CPU time | 344.41 seconds |
| Started | Sep 10 05:02:45 AM UTC 24 |
| Finished | Sep 10 05:08:35 AM UTC 24 |
| Peak memory | 616880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638018789 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.638018789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.1636446404 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 6451609870 ps |
| CPU time | 255.51 seconds |
| Started | Sep 10 04:59:57 AM UTC 24 |
| Finished | Sep 10 05:04:16 AM UTC 24 |
| Peak memory | 606428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636446404 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.1636446404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.2806156432 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 1070127837 ps |
| CPU time | 59.15 seconds |
| Started | Sep 10 05:01:43 AM UTC 24 |
| Finished | Sep 10 05:02:44 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806156432 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.2806156432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3098324512 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 342018982 ps |
| CPU time | 21.15 seconds |
| Started | Sep 10 05:02:09 AM UTC 24 |
| Finished | Sep 10 05:02:31 AM UTC 24 |
| Peak memory | 596092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098324512 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.3098324512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.824555148 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 137393010 ps |
| CPU time | 20.54 seconds |
| Started | Sep 10 05:01:59 AM UTC 24 |
| Finished | Sep 10 05:02:21 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824555148 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.824555148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.2753112951 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 6701259403 ps |
| CPU time | 153.09 seconds |
| Started | Sep 10 05:01:03 AM UTC 24 |
| Finished | Sep 10 05:03:39 AM UTC 24 |
| Peak memory | 596028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753112951 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2753112951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.2036147031 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 166370978 ps |
| CPU time | 12.65 seconds |
| Started | Sep 10 05:00:02 AM UTC 24 |
| Finished | Sep 10 05:00:18 AM UTC 24 |
| Peak memory | 593880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036147031 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2036147031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.649745155 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 7156251699 ps |
| CPU time | 101.9 seconds |
| Started | Sep 10 05:00:17 AM UTC 24 |
| Finished | Sep 10 05:02:01 AM UTC 24 |
| Peak memory | 594072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649745155 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.649745155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1722290606 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 4348883316 ps |
| CPU time | 100.73 seconds |
| Started | Sep 10 05:00:41 AM UTC 24 |
| Finished | Sep 10 05:02:24 AM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722290606 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1722290606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.1953743654 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 474329824 ps |
| CPU time | 63.75 seconds |
| Started | Sep 10 05:02:09 AM UTC 24 |
| Finished | Sep 10 05:03:15 AM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953743654 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1953743654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2337573265 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 464674948 ps |
| CPU time | 161.89 seconds |
| Started | Sep 10 05:02:26 AM UTC 24 |
| Finished | Sep 10 05:05:11 AM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337573265 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.2337573265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.3407733184 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 259097093 ps |
| CPU time | 16.15 seconds |
| Started | Sep 10 05:02:01 AM UTC 24 |
| Finished | Sep 10 05:02:18 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407733184 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3407733184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.3869420589 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 35457188070 ps |
| CPU time | 6351.34 seconds |
| Started | Sep 10 05:02:51 AM UTC 24 |
| Finished | Sep 10 06:50:04 AM UTC 24 |
| Peak memory | 613760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3869420589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_ csr_aliasing.3869420589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.2180071133 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 7459385556 ps |
| CPU time | 684.06 seconds |
| Started | Sep 10 05:02:49 AM UTC 24 |
| Finished | Sep 10 05:14:22 AM UTC 24 |
| Peak memory | 616928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2180071133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.chip_csr_bit_bash.2180071133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.2265559278 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 11735879726 ps |
| CPU time | 700.25 seconds |
| Started | Sep 10 05:04:41 AM UTC 24 |
| Finished | Sep 10 05:16:30 AM UTC 24 |
| Peak memory | 668272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2265559278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.chip_csr_mem_rw_with_rand_reset.2265559278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.413497816 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 3211265600 ps |
| CPU time | 164.63 seconds |
| Started | Sep 10 05:02:56 AM UTC 24 |
| Finished | Sep 10 05:05:44 AM UTC 24 |
| Peak memory | 606728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413497816 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.413497816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_prim_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1464731590 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 24299173497 ps |
| CPU time | 1312.74 seconds |
| Started | Sep 10 05:02:56 AM UTC 24 |
| Finished | Sep 10 05:25:05 AM UTC 24 |
| Peak memory | 606292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_c pu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1464731590 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. chip_rv_dm_lc_disabled.1464731590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.318653278 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 29603919834 ps |
| CPU time | 4037.66 seconds |
| Started | Sep 10 05:02:52 AM UTC 24 |
| Finished | Sep 10 06:10:58 AM UTC 24 |
| Peak memory | 614012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=318653278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.chip_same_csr_outstanding.318653278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1949166182 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 115314305837 ps |
| CPU time | 1843.19 seconds |
| Started | Sep 10 05:03:46 AM UTC 24 |
| Finished | Sep 10 05:34:53 AM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949166182 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.1949166182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.823766534 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 152480384 ps |
| CPU time | 22.93 seconds |
| Started | Sep 10 05:04:06 AM UTC 24 |
| Finished | Sep 10 05:04:30 AM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823766534 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.823766534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.3289715597 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 2192476354 ps |
| CPU time | 91.79 seconds |
| Started | Sep 10 05:03:15 AM UTC 24 |
| Finished | Sep 10 05:04:49 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289715597 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.3289715597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.1272968819 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 65752523881 ps |
| CPU time | 744.81 seconds |
| Started | Sep 10 05:03:36 AM UTC 24 |
| Finished | Sep 10 05:16:10 AM UTC 24 |
| Peak memory | 596028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272968819 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.1272968819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.299207502 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 44755976683 ps |
| CPU time | 591.86 seconds |
| Started | Sep 10 05:03:40 AM UTC 24 |
| Finished | Sep 10 05:13:40 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299207502 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.299207502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.1774352295 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 526152171 ps |
| CPU time | 48.47 seconds |
| Started | Sep 10 05:03:14 AM UTC 24 |
| Finished | Sep 10 05:04:04 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774352295 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.1774352295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.485781667 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 455674536 ps |
| CPU time | 24.41 seconds |
| Started | Sep 10 05:03:47 AM UTC 24 |
| Finished | Sep 10 05:04:12 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485781667 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.485781667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.3131549714 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 202425290 ps |
| CPU time | 8.76 seconds |
| Started | Sep 10 05:02:59 AM UTC 24 |
| Finished | Sep 10 05:03:09 AM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131549714 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3131549714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.178278279 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 9554046143 ps |
| CPU time | 133.11 seconds |
| Started | Sep 10 05:03:09 AM UTC 24 |
| Finished | Sep 10 05:05:25 AM UTC 24 |
| Peak memory | 593844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178278279 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.178278279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1633038520 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 5109898473 ps |
| CPU time | 91.11 seconds |
| Started | Sep 10 05:03:11 AM UTC 24 |
| Finished | Sep 10 05:04:44 AM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633038520 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1633038520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1868156948 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 55160032 ps |
| CPU time | 10.54 seconds |
| Started | Sep 10 05:03:08 AM UTC 24 |
| Finished | Sep 10 05:03:19 AM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868156948 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1868156948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.389599822 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 10800172134 ps |
| CPU time | 440.95 seconds |
| Started | Sep 10 05:04:09 AM UTC 24 |
| Finished | Sep 10 05:11:37 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389599822 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.389599822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1477931222 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 729331449 ps |
| CPU time | 180.22 seconds |
| Started | Sep 10 05:04:38 AM UTC 24 |
| Finished | Sep 10 05:07:41 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477931222 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.1477931222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.1582361342 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 154715841 ps |
| CPU time | 10.27 seconds |
| Started | Sep 10 05:04:05 AM UTC 24 |
| Finished | Sep 10 05:04:16 AM UTC 24 |
| Peak memory | 594028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582361342 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1582361342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3810295388 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 5813502000 ps |
| CPU time | 474.83 seconds |
| Started | Sep 10 05:30:12 AM UTC 24 |
| Finished | Sep 10 05:38:13 AM UTC 24 |
| Peak memory | 662120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3810295388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 10.chip_csr_mem_rw_with_rand_reset.3810295388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.3775844034 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 4612043604 ps |
| CPU time | 360.47 seconds |
| Started | Sep 10 05:30:13 AM UTC 24 |
| Finished | Sep 10 05:36:18 AM UTC 24 |
| Peak memory | 616944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775844034 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.3775844034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.799350251 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 15042449215 ps |
| CPU time | 1565.53 seconds |
| Started | Sep 10 05:27:44 AM UTC 24 |
| Finished | Sep 10 05:54:08 AM UTC 24 |
| Peak memory | 610876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=799350251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 10.chip_same_csr_outstanding.799350251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.22541620 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 532476401 ps |
| CPU time | 63.95 seconds |
| Started | Sep 10 05:28:41 AM UTC 24 |
| Finished | Sep 10 05:29:47 AM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22541620 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.22541620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2307897109 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 1376657549 ps |
| CPU time | 67.57 seconds |
| Started | Sep 10 05:29:42 AM UTC 24 |
| Finished | Sep 10 05:30:52 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307897109 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2307897109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.1955004826 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 280212575 ps |
| CPU time | 33.74 seconds |
| Started | Sep 10 05:28:55 AM UTC 24 |
| Finished | Sep 10 05:29:30 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955004826 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1955004826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.2760819651 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 991128376 ps |
| CPU time | 50.54 seconds |
| Started | Sep 10 05:28:26 AM UTC 24 |
| Finished | Sep 10 05:29:18 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760819651 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.2760819651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.254371845 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 23059505345 ps |
| CPU time | 233 seconds |
| Started | Sep 10 05:28:34 AM UTC 24 |
| Finished | Sep 10 05:32:30 AM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254371845 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.254371845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.414528820 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 28549936182 ps |
| CPU time | 450.69 seconds |
| Started | Sep 10 05:28:41 AM UTC 24 |
| Finished | Sep 10 05:36:17 AM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414528820 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.414528820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.716673406 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 346614071 ps |
| CPU time | 43.12 seconds |
| Started | Sep 10 05:28:30 AM UTC 24 |
| Finished | Sep 10 05:29:15 AM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716673406 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.716673406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.132953970 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 2224817084 ps |
| CPU time | 92.42 seconds |
| Started | Sep 10 05:28:51 AM UTC 24 |
| Finished | Sep 10 05:30:25 AM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132953970 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.132953970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.2287699662 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 222790749 ps |
| CPU time | 9.1 seconds |
| Started | Sep 10 05:28:03 AM UTC 24 |
| Finished | Sep 10 05:28:13 AM UTC 24 |
| Peak memory | 593888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287699662 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2287699662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.1455090938 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 7220170849 ps |
| CPU time | 98.98 seconds |
| Started | Sep 10 05:28:12 AM UTC 24 |
| Finished | Sep 10 05:29:53 AM UTC 24 |
| Peak memory | 593720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455090938 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1455090938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.378626494 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 3786933382 ps |
| CPU time | 88.52 seconds |
| Started | Sep 10 05:28:17 AM UTC 24 |
| Finished | Sep 10 05:29:48 AM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378626494 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.378626494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.295979043 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 37693462 ps |
| CPU time | 8.82 seconds |
| Started | Sep 10 05:28:13 AM UTC 24 |
| Finished | Sep 10 05:28:23 AM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295979043 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.295979043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.555785308 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 2088075288 ps |
| CPU time | 224.4 seconds |
| Started | Sep 10 05:29:45 AM UTC 24 |
| Finished | Sep 10 05:33:33 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555785308 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.555785308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.1051641692 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 13462792854 ps |
| CPU time | 494.47 seconds |
| Started | Sep 10 05:29:59 AM UTC 24 |
| Finished | Sep 10 05:38:20 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051641692 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1051641692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.575279436 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 2166346621 ps |
| CPU time | 121.77 seconds |
| Started | Sep 10 05:30:05 AM UTC 24 |
| Finished | Sep 10 05:32:09 AM UTC 24 |
| Peak memory | 596072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575279436 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.575279436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.2001855780 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 559134505 ps |
| CPU time | 36.62 seconds |
| Started | Sep 10 05:29:00 AM UTC 24 |
| Finished | Sep 10 05:29:38 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001855780 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2001855780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.420283822 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 10803075584 ps |
| CPU time | 957.84 seconds |
| Started | Sep 10 05:33:01 AM UTC 24 |
| Finished | Sep 10 05:49:12 AM UTC 24 |
| Peak memory | 670116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=420283822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.420283822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.955825944 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 4370722122 ps |
| CPU time | 352.92 seconds |
| Started | Sep 10 05:33:01 AM UTC 24 |
| Finished | Sep 10 05:38:59 AM UTC 24 |
| Peak memory | 616732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955825944 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.955825944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.2953778882 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 17906947124 ps |
| CPU time | 2611.1 seconds |
| Started | Sep 10 05:30:13 AM UTC 24 |
| Finished | Sep 10 06:14:16 AM UTC 24 |
| Peak memory | 613824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2953778882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.chip_same_csr_outstanding.2953778882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.396529989 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 349565743 ps |
| CPU time | 26.89 seconds |
| Started | Sep 10 05:31:29 AM UTC 24 |
| Finished | Sep 10 05:31:57 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396529989 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.396529989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1137002189 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 16384156890 ps |
| CPU time | 227.81 seconds |
| Started | Sep 10 05:31:41 AM UTC 24 |
| Finished | Sep 10 05:35:33 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137002189 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.1137002189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.4084785939 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 126276737 ps |
| CPU time | 20.39 seconds |
| Started | Sep 10 05:32:27 AM UTC 24 |
| Finished | Sep 10 05:32:49 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084785939 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.4084785939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.3170678082 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 2488823334 ps |
| CPU time | 100.42 seconds |
| Started | Sep 10 05:32:18 AM UTC 24 |
| Finished | Sep 10 05:34:01 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170678082 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3170678082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.1330662900 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 1660166576 ps |
| CPU time | 80.12 seconds |
| Started | Sep 10 05:31:12 AM UTC 24 |
| Finished | Sep 10 05:32:34 AM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330662900 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.1330662900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.2574126655 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 66967734523 ps |
| CPU time | 614.2 seconds |
| Started | Sep 10 05:31:24 AM UTC 24 |
| Finished | Sep 10 05:41:46 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574126655 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2574126655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.3880365843 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 37080823733 ps |
| CPU time | 678.16 seconds |
| Started | Sep 10 05:31:27 AM UTC 24 |
| Finished | Sep 10 05:42:54 AM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880365843 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3880365843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.938941653 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 437579585 ps |
| CPU time | 47.4 seconds |
| Started | Sep 10 05:31:18 AM UTC 24 |
| Finished | Sep 10 05:32:07 AM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938941653 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.938941653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.2202070248 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 2694113234 ps |
| CPU time | 114.09 seconds |
| Started | Sep 10 05:32:17 AM UTC 24 |
| Finished | Sep 10 05:34:14 AM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202070248 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2202070248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.4052162334 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 230304560 ps |
| CPU time | 14.56 seconds |
| Started | Sep 10 05:30:20 AM UTC 24 |
| Finished | Sep 10 05:30:36 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052162334 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.4052162334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.3364472047 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 5336774565 ps |
| CPU time | 56.92 seconds |
| Started | Sep 10 05:31:02 AM UTC 24 |
| Finished | Sep 10 05:32:01 AM UTC 24 |
| Peak memory | 593724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364472047 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3364472047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.511219462 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 5620828284 ps |
| CPU time | 123.83 seconds |
| Started | Sep 10 05:31:07 AM UTC 24 |
| Finished | Sep 10 05:33:14 AM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511219462 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.511219462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.4075844731 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 45416974 ps |
| CPU time | 9.24 seconds |
| Started | Sep 10 05:30:50 AM UTC 24 |
| Finished | Sep 10 05:31:00 AM UTC 24 |
| Peak memory | 593808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075844731 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.4075844731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.2984691966 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1741914222 ps |
| CPU time | 161.13 seconds |
| Started | Sep 10 05:32:36 AM UTC 24 |
| Finished | Sep 10 05:35:20 AM UTC 24 |
| Peak memory | 596100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984691966 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2984691966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.1322288628 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 7843653893 ps |
| CPU time | 356.07 seconds |
| Started | Sep 10 05:32:41 AM UTC 24 |
| Finished | Sep 10 05:38:42 AM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322288628 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1322288628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2307744818 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 535706753 ps |
| CPU time | 230.73 seconds |
| Started | Sep 10 05:32:37 AM UTC 24 |
| Finished | Sep 10 05:36:31 AM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307744818 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.2307744818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1842759948 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 161359848 ps |
| CPU time | 33.61 seconds |
| Started | Sep 10 05:32:58 AM UTC 24 |
| Finished | Sep 10 05:33:33 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842759948 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.1842759948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.563509791 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 1282590245 ps |
| CPU time | 56.98 seconds |
| Started | Sep 10 05:32:23 AM UTC 24 |
| Finished | Sep 10 05:33:21 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563509791 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.563509791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.644650015 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 11968488718 ps |
| CPU time | 837.87 seconds |
| Started | Sep 10 05:35:59 AM UTC 24 |
| Finished | Sep 10 05:50:09 AM UTC 24 |
| Peak memory | 670120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=644650015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.644650015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.2124465112 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 5572076288 ps |
| CPU time | 733.81 seconds |
| Started | Sep 10 05:35:54 AM UTC 24 |
| Finished | Sep 10 05:48:18 AM UTC 24 |
| Peak memory | 614904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124465112 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.2124465112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.1939855644 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 26697940569 ps |
| CPU time | 3207.75 seconds |
| Started | Sep 10 05:33:16 AM UTC 24 |
| Finished | Sep 10 06:27:24 AM UTC 24 |
| Peak memory | 613816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1939855644 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.chip_same_csr_outstanding.1939855644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.2335750981 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 3395629316 ps |
| CPU time | 246.84 seconds |
| Started | Sep 10 05:33:27 AM UTC 24 |
| Finished | Sep 10 05:37:38 AM UTC 24 |
| Peak memory | 621104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335750981 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.2335750981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.1991640637 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 196233408 ps |
| CPU time | 14.25 seconds |
| Started | Sep 10 05:34:28 AM UTC 24 |
| Finished | Sep 10 05:34:43 AM UTC 24 |
| Peak memory | 594028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991640637 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1991640637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.824656568 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 555222523 ps |
| CPU time | 31.71 seconds |
| Started | Sep 10 05:35:18 AM UTC 24 |
| Finished | Sep 10 05:35:51 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824656568 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.824656568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.1185449286 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 1948737621 ps |
| CPU time | 85.1 seconds |
| Started | Sep 10 05:35:06 AM UTC 24 |
| Finished | Sep 10 05:36:33 AM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185449286 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1185449286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.3512702604 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 2209662106 ps |
| CPU time | 103.19 seconds |
| Started | Sep 10 05:33:59 AM UTC 24 |
| Finished | Sep 10 05:35:44 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512702604 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.3512702604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.547508464 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 10720805828 ps |
| CPU time | 106.75 seconds |
| Started | Sep 10 05:34:13 AM UTC 24 |
| Finished | Sep 10 05:36:02 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547508464 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.547508464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.489608505 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 17456974472 ps |
| CPU time | 340.44 seconds |
| Started | Sep 10 05:34:18 AM UTC 24 |
| Finished | Sep 10 05:40:03 AM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489608505 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.489608505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.1756136400 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 357192271 ps |
| CPU time | 46.65 seconds |
| Started | Sep 10 05:34:01 AM UTC 24 |
| Finished | Sep 10 05:34:49 AM UTC 24 |
| Peak memory | 595880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756136400 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.1756136400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.3287211578 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 2574806799 ps |
| CPU time | 97.99 seconds |
| Started | Sep 10 05:34:53 AM UTC 24 |
| Finished | Sep 10 05:36:33 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287211578 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3287211578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.4142161698 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 50735778 ps |
| CPU time | 8.67 seconds |
| Started | Sep 10 05:33:37 AM UTC 24 |
| Finished | Sep 10 05:33:46 AM UTC 24 |
| Peak memory | 593916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142161698 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.4142161698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.2422787344 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 9563773172 ps |
| CPU time | 108.43 seconds |
| Started | Sep 10 05:33:49 AM UTC 24 |
| Finished | Sep 10 05:35:40 AM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422787344 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2422787344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3509749809 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 5371259046 ps |
| CPU time | 126.79 seconds |
| Started | Sep 10 05:33:54 AM UTC 24 |
| Finished | Sep 10 05:36:04 AM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509749809 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3509749809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2465327829 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 49034439 ps |
| CPU time | 7.53 seconds |
| Started | Sep 10 05:33:41 AM UTC 24 |
| Finished | Sep 10 05:33:50 AM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465327829 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2465327829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.2033137363 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 12035431141 ps |
| CPU time | 453.79 seconds |
| Started | Sep 10 05:35:20 AM UTC 24 |
| Finished | Sep 10 05:43:00 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033137363 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2033137363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.2158008594 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 3472830266 ps |
| CPU time | 280.03 seconds |
| Started | Sep 10 05:35:24 AM UTC 24 |
| Finished | Sep 10 05:40:08 AM UTC 24 |
| Peak memory | 596032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158008594 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2158008594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3814217090 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 1152898859 ps |
| CPU time | 253.93 seconds |
| Started | Sep 10 05:35:22 AM UTC 24 |
| Finished | Sep 10 05:39:40 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814217090 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.3814217090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2374532154 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 1131072672 ps |
| CPU time | 199.21 seconds |
| Started | Sep 10 05:35:48 AM UTC 24 |
| Finished | Sep 10 05:39:11 AM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374532154 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.2374532154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.3226710793 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 62557378 ps |
| CPU time | 15.42 seconds |
| Started | Sep 10 05:35:10 AM UTC 24 |
| Finished | Sep 10 05:35:27 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226710793 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3226710793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.2066080208 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 12565869636 ps |
| CPU time | 1104.82 seconds |
| Started | Sep 10 05:38:18 AM UTC 24 |
| Finished | Sep 10 05:56:56 AM UTC 24 |
| Peak memory | 657832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2066080208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 13.chip_csr_mem_rw_with_rand_reset.2066080208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.2870271734 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 5756278706 ps |
| CPU time | 760.45 seconds |
| Started | Sep 10 05:38:09 AM UTC 24 |
| Finished | Sep 10 05:50:59 AM UTC 24 |
| Peak memory | 614900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870271734 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.2870271734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.776193051 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 31414224564 ps |
| CPU time | 3799.67 seconds |
| Started | Sep 10 05:36:06 AM UTC 24 |
| Finished | Sep 10 06:40:11 AM UTC 24 |
| Peak memory | 613816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=776193051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 13.chip_same_csr_outstanding.776193051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.3591630764 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 3831583838 ps |
| CPU time | 258.31 seconds |
| Started | Sep 10 05:36:10 AM UTC 24 |
| Finished | Sep 10 05:40:33 AM UTC 24 |
| Peak memory | 620964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591630764 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.3591630764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.4056085128 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 1024571248 ps |
| CPU time | 93.55 seconds |
| Started | Sep 10 05:36:56 AM UTC 24 |
| Finished | Sep 10 05:38:31 AM UTC 24 |
| Peak memory | 595940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056085128 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.4056085128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1977840661 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 24708071475 ps |
| CPU time | 407.05 seconds |
| Started | Sep 10 05:36:59 AM UTC 24 |
| Finished | Sep 10 05:43:52 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977840661 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.1977840661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3198830543 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 235853100 ps |
| CPU time | 17.5 seconds |
| Started | Sep 10 05:37:41 AM UTC 24 |
| Finished | Sep 10 05:37:59 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198830543 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.3198830543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.835839733 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 1944970699 ps |
| CPU time | 91.66 seconds |
| Started | Sep 10 05:37:02 AM UTC 24 |
| Finished | Sep 10 05:38:36 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835839733 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.835839733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.652058898 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 490848304 ps |
| CPU time | 46.73 seconds |
| Started | Sep 10 05:36:34 AM UTC 24 |
| Finished | Sep 10 05:37:22 AM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652058898 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.652058898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.3696875884 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 8662494245 ps |
| CPU time | 86.89 seconds |
| Started | Sep 10 05:36:45 AM UTC 24 |
| Finished | Sep 10 05:38:14 AM UTC 24 |
| Peak memory | 593724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696875884 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3696875884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.2063583840 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 54647041015 ps |
| CPU time | 767.77 seconds |
| Started | Sep 10 05:36:48 AM UTC 24 |
| Finished | Sep 10 05:49:45 AM UTC 24 |
| Peak memory | 595788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063583840 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2063583840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.2604728157 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 212174401 ps |
| CPU time | 29.59 seconds |
| Started | Sep 10 05:36:44 AM UTC 24 |
| Finished | Sep 10 05:37:15 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604728157 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.2604728157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.903118191 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 274515933 ps |
| CPU time | 25.26 seconds |
| Started | Sep 10 05:37:00 AM UTC 24 |
| Finished | Sep 10 05:37:27 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903118191 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.903118191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.3580504956 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 197929738 ps |
| CPU time | 9.72 seconds |
| Started | Sep 10 05:36:11 AM UTC 24 |
| Finished | Sep 10 05:36:22 AM UTC 24 |
| Peak memory | 593788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580504956 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.3580504956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.2785036051 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 7783197343 ps |
| CPU time | 120.99 seconds |
| Started | Sep 10 05:36:30 AM UTC 24 |
| Finished | Sep 10 05:38:33 AM UTC 24 |
| Peak memory | 593720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785036051 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2785036051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3433679963 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 5937613548 ps |
| CPU time | 82.59 seconds |
| Started | Sep 10 05:36:29 AM UTC 24 |
| Finished | Sep 10 05:37:54 AM UTC 24 |
| Peak memory | 593908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433679963 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.3433679963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2970279226 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 48917876 ps |
| CPU time | 9.83 seconds |
| Started | Sep 10 05:36:18 AM UTC 24 |
| Finished | Sep 10 05:36:29 AM UTC 24 |
| Peak memory | 593780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970279226 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.2970279226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.2028002585 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 3724072486 ps |
| CPU time | 400.24 seconds |
| Started | Sep 10 05:37:50 AM UTC 24 |
| Finished | Sep 10 05:44:36 AM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028002585 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2028002585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.3644086355 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 8535654647 ps |
| CPU time | 333.63 seconds |
| Started | Sep 10 05:37:56 AM UTC 24 |
| Finished | Sep 10 05:43:34 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644086355 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3644086355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3817727570 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 4636323508 ps |
| CPU time | 611.76 seconds |
| Started | Sep 10 05:38:04 AM UTC 24 |
| Finished | Sep 10 05:48:25 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817727570 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.3817727570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.141509931 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 167347571 ps |
| CPU time | 13.94 seconds |
| Started | Sep 10 05:37:14 AM UTC 24 |
| Finished | Sep 10 05:37:29 AM UTC 24 |
| Peak memory | 593660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141509931 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.141509931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.3639428666 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 11396917471 ps |
| CPU time | 906.6 seconds |
| Started | Sep 10 05:40:26 AM UTC 24 |
| Finished | Sep 10 05:55:45 AM UTC 24 |
| Peak memory | 670312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3639428666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 14.chip_csr_mem_rw_with_rand_reset.3639428666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.1565919834 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 4062138096 ps |
| CPU time | 396.99 seconds |
| Started | Sep 10 05:40:28 AM UTC 24 |
| Finished | Sep 10 05:47:12 AM UTC 24 |
| Peak memory | 619188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565919834 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.1565919834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.2261530977 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 16019490735 ps |
| CPU time | 1925.18 seconds |
| Started | Sep 10 05:38:27 AM UTC 24 |
| Finished | Sep 10 06:10:56 AM UTC 24 |
| Peak memory | 610660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2261530977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.chip_same_csr_outstanding.2261530977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.262918741 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 3238194329 ps |
| CPU time | 164.43 seconds |
| Started | Sep 10 05:38:41 AM UTC 24 |
| Finished | Sep 10 05:41:28 AM UTC 24 |
| Peak memory | 621100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262918741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.262918741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.4028833396 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 186731158 ps |
| CPU time | 28.5 seconds |
| Started | Sep 10 05:39:24 AM UTC 24 |
| Finished | Sep 10 05:39:54 AM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028833396 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.4028833396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.232817810 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 46506097782 ps |
| CPU time | 795.18 seconds |
| Started | Sep 10 05:39:26 AM UTC 24 |
| Finished | Sep 10 05:52:51 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232817810 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.232817810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.1866630998 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 437352301 ps |
| CPU time | 24.83 seconds |
| Started | Sep 10 05:40:07 AM UTC 24 |
| Finished | Sep 10 05:40:33 AM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866630998 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.1866630998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.57295215 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 163991517 ps |
| CPU time | 12.53 seconds |
| Started | Sep 10 05:39:45 AM UTC 24 |
| Finished | Sep 10 05:39:59 AM UTC 24 |
| Peak memory | 593656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57295215 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.57295215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.3324782517 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 271271648 ps |
| CPU time | 26.02 seconds |
| Started | Sep 10 05:39:03 AM UTC 24 |
| Finished | Sep 10 05:39:30 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324782517 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.3324782517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.27775993 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 25875317298 ps |
| CPU time | 248.99 seconds |
| Started | Sep 10 05:39:09 AM UTC 24 |
| Finished | Sep 10 05:43:22 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27775993 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.27775993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.4223027593 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 55112061680 ps |
| CPU time | 911.88 seconds |
| Started | Sep 10 05:39:17 AM UTC 24 |
| Finished | Sep 10 05:54:41 AM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223027593 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.4223027593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.635642975 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 558082426 ps |
| CPU time | 46.01 seconds |
| Started | Sep 10 05:39:03 AM UTC 24 |
| Finished | Sep 10 05:39:51 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635642975 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.635642975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.301715719 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 138419599 ps |
| CPU time | 19.45 seconds |
| Started | Sep 10 05:39:37 AM UTC 24 |
| Finished | Sep 10 05:39:58 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301715719 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.301715719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.210925007 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 42651814 ps |
| CPU time | 8.42 seconds |
| Started | Sep 10 05:38:40 AM UTC 24 |
| Finished | Sep 10 05:38:49 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210925007 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.210925007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.234603068 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 7103068337 ps |
| CPU time | 115.89 seconds |
| Started | Sep 10 05:38:59 AM UTC 24 |
| Finished | Sep 10 05:40:57 AM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234603068 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.234603068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.3828773200 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 4520168802 ps |
| CPU time | 58.32 seconds |
| Started | Sep 10 05:39:01 AM UTC 24 |
| Finished | Sep 10 05:40:01 AM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828773200 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.3828773200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.360408259 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 50415762 ps |
| CPU time | 9.51 seconds |
| Started | Sep 10 05:38:47 AM UTC 24 |
| Finished | Sep 10 05:38:58 AM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360408259 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.360408259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.3974231811 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 10033906785 ps |
| CPU time | 440.18 seconds |
| Started | Sep 10 05:40:15 AM UTC 24 |
| Finished | Sep 10 05:47:41 AM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974231811 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3974231811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.2855904225 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 12258714722 ps |
| CPU time | 377.22 seconds |
| Started | Sep 10 05:40:26 AM UTC 24 |
| Finished | Sep 10 05:46:49 AM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855904225 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2855904225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.2710328052 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 6796271624 ps |
| CPU time | 357.16 seconds |
| Started | Sep 10 05:40:24 AM UTC 24 |
| Finished | Sep 10 05:46:26 AM UTC 24 |
| Peak memory | 596012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710328052 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.2710328052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.1326531664 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 1374729699 ps |
| CPU time | 63.19 seconds |
| Started | Sep 10 05:39:58 AM UTC 24 |
| Finished | Sep 10 05:41:03 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326531664 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1326531664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.1914379286 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 7493063776 ps |
| CPU time | 458.8 seconds |
| Started | Sep 10 05:43:47 AM UTC 24 |
| Finished | Sep 10 05:51:32 AM UTC 24 |
| Peak memory | 660072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1914379286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 15.chip_csr_mem_rw_with_rand_reset.1914379286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.1166715598 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 4699364312 ps |
| CPU time | 385.92 seconds |
| Started | Sep 10 05:43:33 AM UTC 24 |
| Finished | Sep 10 05:50:04 AM UTC 24 |
| Peak memory | 614680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166715598 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.1166715598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.499166448 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 29240341234 ps |
| CPU time | 2926.51 seconds |
| Started | Sep 10 05:40:37 AM UTC 24 |
| Finished | Sep 10 06:29:59 AM UTC 24 |
| Peak memory | 614068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=499166448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 15.chip_same_csr_outstanding.499166448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.1877813588 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 397612220 ps |
| CPU time | 31 seconds |
| Started | Sep 10 05:42:13 AM UTC 24 |
| Finished | Sep 10 05:42:46 AM UTC 24 |
| Peak memory | 595720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877813588 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.1877813588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.997335240 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 123216214946 ps |
| CPU time | 1810.17 seconds |
| Started | Sep 10 05:42:25 AM UTC 24 |
| Finished | Sep 10 06:12:56 AM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997335240 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.997335240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.1102751038 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 133758032 ps |
| CPU time | 18.94 seconds |
| Started | Sep 10 05:43:20 AM UTC 24 |
| Finished | Sep 10 05:43:40 AM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102751038 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.1102751038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.2646572424 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 1667403781 ps |
| CPU time | 70.12 seconds |
| Started | Sep 10 05:43:06 AM UTC 24 |
| Finished | Sep 10 05:44:18 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646572424 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2646572424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.2866316574 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 130916190 ps |
| CPU time | 19.15 seconds |
| Started | Sep 10 05:41:38 AM UTC 24 |
| Finished | Sep 10 05:41:58 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866316574 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.2866316574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.229568606 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 94454435452 ps |
| CPU time | 931.17 seconds |
| Started | Sep 10 05:41:56 AM UTC 24 |
| Finished | Sep 10 05:57:39 AM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229568606 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.229568606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.1426949870 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 31712219784 ps |
| CPU time | 536.15 seconds |
| Started | Sep 10 05:42:01 AM UTC 24 |
| Finished | Sep 10 05:51:05 AM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426949870 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1426949870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.3632853618 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 456644074 ps |
| CPU time | 53.95 seconds |
| Started | Sep 10 05:41:40 AM UTC 24 |
| Finished | Sep 10 05:42:35 AM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632853618 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3632853618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.1356328436 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 1611168567 ps |
| CPU time | 57.97 seconds |
| Started | Sep 10 05:43:03 AM UTC 24 |
| Finished | Sep 10 05:44:03 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356328436 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1356328436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.3202102528 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 198166234 ps |
| CPU time | 12.01 seconds |
| Started | Sep 10 05:41:00 AM UTC 24 |
| Finished | Sep 10 05:41:13 AM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202102528 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3202102528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.1723152487 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 8053519526 ps |
| CPU time | 92.1 seconds |
| Started | Sep 10 05:41:19 AM UTC 24 |
| Finished | Sep 10 05:42:53 AM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723152487 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1723152487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3802352045 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 4798306984 ps |
| CPU time | 68.44 seconds |
| Started | Sep 10 05:41:30 AM UTC 24 |
| Finished | Sep 10 05:42:40 AM UTC 24 |
| Peak memory | 593984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802352045 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3802352045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.3058918094 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 45477159 ps |
| CPU time | 9.73 seconds |
| Started | Sep 10 05:41:00 AM UTC 24 |
| Finished | Sep 10 05:41:10 AM UTC 24 |
| Peak memory | 593888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058918094 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.3058918094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.3526985177 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 12145313200 ps |
| CPU time | 410.36 seconds |
| Started | Sep 10 05:43:19 AM UTC 24 |
| Finished | Sep 10 05:50:15 AM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526985177 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3526985177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.1273964659 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 16907915688 ps |
| CPU time | 699.71 seconds |
| Started | Sep 10 05:43:20 AM UTC 24 |
| Finished | Sep 10 05:55:10 AM UTC 24 |
| Peak memory | 596000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273964659 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.1273964659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.1718058354 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 3178810737 ps |
| CPU time | 489.14 seconds |
| Started | Sep 10 05:43:20 AM UTC 24 |
| Finished | Sep 10 05:51:36 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718058354 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.1718058354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1936108150 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 808648035 ps |
| CPU time | 267.5 seconds |
| Started | Sep 10 05:43:24 AM UTC 24 |
| Finished | Sep 10 05:47:56 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936108150 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.1936108150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.405657945 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 206981336 ps |
| CPU time | 35.52 seconds |
| Started | Sep 10 05:43:12 AM UTC 24 |
| Finished | Sep 10 05:43:50 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405657945 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.405657945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.3034357953 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 9306311876 ps |
| CPU time | 1006.94 seconds |
| Started | Sep 10 05:47:05 AM UTC 24 |
| Finished | Sep 10 06:04:05 AM UTC 24 |
| Peak memory | 670116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3034357953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 16.chip_csr_mem_rw_with_rand_reset.3034357953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.2191443377 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 5489422832 ps |
| CPU time | 656.75 seconds |
| Started | Sep 10 05:46:58 AM UTC 24 |
| Finished | Sep 10 05:58:04 AM UTC 24 |
| Peak memory | 616744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191443377 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.2191443377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.508241819 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 15402101816 ps |
| CPU time | 1837.85 seconds |
| Started | Sep 10 05:43:47 AM UTC 24 |
| Finished | Sep 10 06:14:47 AM UTC 24 |
| Peak memory | 610720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=508241819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 16.chip_same_csr_outstanding.508241819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.4254451003 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 4160169112 ps |
| CPU time | 322.28 seconds |
| Started | Sep 10 05:43:58 AM UTC 24 |
| Finished | Sep 10 05:49:25 AM UTC 24 |
| Peak memory | 621096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254451003 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.4254451003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.3785781523 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 2702946148 ps |
| CPU time | 93.37 seconds |
| Started | Sep 10 05:45:27 AM UTC 24 |
| Finished | Sep 10 05:47:02 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785781523 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.3785781523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.2574858411 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 19972624587 ps |
| CPU time | 276.44 seconds |
| Started | Sep 10 05:45:35 AM UTC 24 |
| Finished | Sep 10 05:50:15 AM UTC 24 |
| Peak memory | 596124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574858411 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.2574858411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.3326555842 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 121387472 ps |
| CPU time | 11.97 seconds |
| Started | Sep 10 05:46:25 AM UTC 24 |
| Finished | Sep 10 05:46:38 AM UTC 24 |
| Peak memory | 593864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326555842 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.3326555842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.2008675223 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 60151902 ps |
| CPU time | 10.37 seconds |
| Started | Sep 10 05:45:53 AM UTC 24 |
| Finished | Sep 10 05:46:04 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008675223 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.2008675223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.140801205 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 1502637630 ps |
| CPU time | 72.94 seconds |
| Started | Sep 10 05:44:45 AM UTC 24 |
| Finished | Sep 10 05:46:00 AM UTC 24 |
| Peak memory | 596088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140801205 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.140801205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.2552473094 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 32387924461 ps |
| CPU time | 406.65 seconds |
| Started | Sep 10 05:44:52 AM UTC 24 |
| Finished | Sep 10 05:51:45 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552473094 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2552473094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.164421722 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 16227080004 ps |
| CPU time | 329.58 seconds |
| Started | Sep 10 05:45:03 AM UTC 24 |
| Finished | Sep 10 05:50:38 AM UTC 24 |
| Peak memory | 596116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164421722 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.164421722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.2904386379 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 364949044 ps |
| CPU time | 34.15 seconds |
| Started | Sep 10 05:44:49 AM UTC 24 |
| Finished | Sep 10 05:45:25 AM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904386379 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.2904386379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.632080099 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 315574104 ps |
| CPU time | 37.31 seconds |
| Started | Sep 10 05:45:44 AM UTC 24 |
| Finished | Sep 10 05:46:23 AM UTC 24 |
| Peak memory | 595980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632080099 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.632080099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.3914179927 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 239877044 ps |
| CPU time | 14.31 seconds |
| Started | Sep 10 05:44:07 AM UTC 24 |
| Finished | Sep 10 05:44:23 AM UTC 24 |
| Peak memory | 593780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914179927 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3914179927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.1346671773 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 6325383282 ps |
| CPU time | 56.95 seconds |
| Started | Sep 10 05:44:19 AM UTC 24 |
| Finished | Sep 10 05:45:17 AM UTC 24 |
| Peak memory | 594096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346671773 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1346671773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1763252544 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 5348639620 ps |
| CPU time | 127.95 seconds |
| Started | Sep 10 05:44:30 AM UTC 24 |
| Finished | Sep 10 05:46:41 AM UTC 24 |
| Peak memory | 593860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763252544 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1763252544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.1969703270 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 55997945 ps |
| CPU time | 7.55 seconds |
| Started | Sep 10 05:44:17 AM UTC 24 |
| Finished | Sep 10 05:44:25 AM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969703270 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.1969703270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.3844810393 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 1388739544 ps |
| CPU time | 126.59 seconds |
| Started | Sep 10 05:46:27 AM UTC 24 |
| Finished | Sep 10 05:48:36 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844810393 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3844810393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.1032180445 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 2027719209 ps |
| CPU time | 161.85 seconds |
| Started | Sep 10 05:46:48 AM UTC 24 |
| Finished | Sep 10 05:49:32 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032180445 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1032180445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.2983593774 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 243773783 ps |
| CPU time | 98.14 seconds |
| Started | Sep 10 05:46:31 AM UTC 24 |
| Finished | Sep 10 05:48:12 AM UTC 24 |
| Peak memory | 595720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983593774 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.2983593774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1886720172 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 566614950 ps |
| CPU time | 255.31 seconds |
| Started | Sep 10 05:46:54 AM UTC 24 |
| Finished | Sep 10 05:51:14 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886720172 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.1886720172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.3498153640 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 425552573 ps |
| CPU time | 26.72 seconds |
| Started | Sep 10 05:46:02 AM UTC 24 |
| Finished | Sep 10 05:46:31 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498153640 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3498153640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.3085741327 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 9499074992 ps |
| CPU time | 1086.83 seconds |
| Started | Sep 10 05:50:11 AM UTC 24 |
| Finished | Sep 10 06:08:32 AM UTC 24 |
| Peak memory | 670340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3085741327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 17.chip_csr_mem_rw_with_rand_reset.3085741327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.2197053115 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 4004199640 ps |
| CPU time | 299.72 seconds |
| Started | Sep 10 05:50:04 AM UTC 24 |
| Finished | Sep 10 05:55:08 AM UTC 24 |
| Peak memory | 616732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197053115 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.2197053115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.2205581389 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 16746326794 ps |
| CPU time | 1465.24 seconds |
| Started | Sep 10 05:47:08 AM UTC 24 |
| Finished | Sep 10 06:11:52 AM UTC 24 |
| Peak memory | 610876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2205581389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 17.chip_same_csr_outstanding.2205581389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.3844409117 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 3245880864 ps |
| CPU time | 180.06 seconds |
| Started | Sep 10 05:47:16 AM UTC 24 |
| Finished | Sep 10 05:50:19 AM UTC 24 |
| Peak memory | 621044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844409117 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.3844409117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.112096402 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 524138019 ps |
| CPU time | 41.13 seconds |
| Started | Sep 10 05:48:52 AM UTC 24 |
| Finished | Sep 10 05:49:35 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112096402 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.112096402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.2205982783 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 57705711 ps |
| CPU time | 9.56 seconds |
| Started | Sep 10 05:49:52 AM UTC 24 |
| Finished | Sep 10 05:50:03 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205982783 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.2205982783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.4108398093 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 1720819269 ps |
| CPU time | 83.32 seconds |
| Started | Sep 10 05:49:34 AM UTC 24 |
| Finished | Sep 10 05:50:59 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108398093 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.4108398093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.1033150289 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 1794526069 ps |
| CPU time | 69.76 seconds |
| Started | Sep 10 05:48:19 AM UTC 24 |
| Finished | Sep 10 05:49:31 AM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033150289 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.1033150289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.4137249830 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 19967972573 ps |
| CPU time | 236.76 seconds |
| Started | Sep 10 05:48:37 AM UTC 24 |
| Finished | Sep 10 05:52:37 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137249830 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.4137249830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.2391666841 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 61148634710 ps |
| CPU time | 969.53 seconds |
| Started | Sep 10 05:48:42 AM UTC 24 |
| Finished | Sep 10 06:05:04 AM UTC 24 |
| Peak memory | 595788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391666841 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2391666841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.1155796993 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 208094176 ps |
| CPU time | 24.05 seconds |
| Started | Sep 10 05:48:23 AM UTC 24 |
| Finished | Sep 10 05:48:49 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155796993 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.1155796993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.2134662320 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 551958205 ps |
| CPU time | 20.26 seconds |
| Started | Sep 10 05:49:17 AM UTC 24 |
| Finished | Sep 10 05:49:38 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134662320 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2134662320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.3629271952 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 38037677 ps |
| CPU time | 8.12 seconds |
| Started | Sep 10 05:47:30 AM UTC 24 |
| Finished | Sep 10 05:47:39 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629271952 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3629271952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.2873348313 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 5329284327 ps |
| CPU time | 57.95 seconds |
| Started | Sep 10 05:48:08 AM UTC 24 |
| Finished | Sep 10 05:49:08 AM UTC 24 |
| Peak memory | 593908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873348313 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2873348313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.1665387999 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 6070964494 ps |
| CPU time | 89.21 seconds |
| Started | Sep 10 05:48:09 AM UTC 24 |
| Finished | Sep 10 05:49:40 AM UTC 24 |
| Peak memory | 593724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665387999 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1665387999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.390043452 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 55817505 ps |
| CPU time | 10.25 seconds |
| Started | Sep 10 05:47:40 AM UTC 24 |
| Finished | Sep 10 05:47:52 AM UTC 24 |
| Peak memory | 594036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390043452 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.390043452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.466138523 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 17123387059 ps |
| CPU time | 646.86 seconds |
| Started | Sep 10 05:49:53 AM UTC 24 |
| Finished | Sep 10 06:00:49 AM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466138523 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.466138523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.6712951 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 663268334 ps |
| CPU time | 57.43 seconds |
| Started | Sep 10 05:50:02 AM UTC 24 |
| Finished | Sep 10 05:51:01 AM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6712951 -assert nopostproc +UVM_TESTNAME=x bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.6712951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.3521431204 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 2335896945 ps |
| CPU time | 267.38 seconds |
| Started | Sep 10 05:50:01 AM UTC 24 |
| Finished | Sep 10 05:54:33 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521431204 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.3521431204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.3674886741 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 695251402 ps |
| CPU time | 37.45 seconds |
| Started | Sep 10 05:49:37 AM UTC 24 |
| Finished | Sep 10 05:50:16 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674886741 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3674886741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.2204413834 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 10695399484 ps |
| CPU time | 929.48 seconds |
| Started | Sep 10 05:52:11 AM UTC 24 |
| Finished | Sep 10 06:07:53 AM UTC 24 |
| Peak memory | 664032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2204413834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 18.chip_csr_mem_rw_with_rand_reset.2204413834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.784950453 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 3895920211 ps |
| CPU time | 365.37 seconds |
| Started | Sep 10 05:52:11 AM UTC 24 |
| Finished | Sep 10 05:58:21 AM UTC 24 |
| Peak memory | 614688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784950453 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.784950453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.2436669915 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 30275462682 ps |
| CPU time | 3632.36 seconds |
| Started | Sep 10 05:50:26 AM UTC 24 |
| Finished | Sep 10 06:51:41 AM UTC 24 |
| Peak memory | 614044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2436669915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.chip_same_csr_outstanding.2436669915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.3129194756 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 3715388648 ps |
| CPU time | 343.92 seconds |
| Started | Sep 10 05:50:30 AM UTC 24 |
| Finished | Sep 10 05:56:19 AM UTC 24 |
| Peak memory | 621100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129194756 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.3129194756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.2783860594 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 298279724 ps |
| CPU time | 32.31 seconds |
| Started | Sep 10 05:51:17 AM UTC 24 |
| Finished | Sep 10 05:51:51 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783860594 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.2783860594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.388807214 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 126343751974 ps |
| CPU time | 1841.9 seconds |
| Started | Sep 10 05:51:23 AM UTC 24 |
| Finished | Sep 10 06:22:27 AM UTC 24 |
| Peak memory | 596420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388807214 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.388807214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2731197709 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 848196036 ps |
| CPU time | 36.63 seconds |
| Started | Sep 10 05:51:29 AM UTC 24 |
| Finished | Sep 10 05:52:07 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731197709 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.2731197709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.3835101631 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 398255962 ps |
| CPU time | 32.3 seconds |
| Started | Sep 10 05:51:26 AM UTC 24 |
| Finished | Sep 10 05:52:00 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835101631 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3835101631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.1458297142 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 1409895170 ps |
| CPU time | 55.63 seconds |
| Started | Sep 10 05:50:46 AM UTC 24 |
| Finished | Sep 10 05:51:43 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458297142 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.1458297142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.251160008 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 7041691158 ps |
| CPU time | 73.02 seconds |
| Started | Sep 10 05:51:12 AM UTC 24 |
| Finished | Sep 10 05:52:26 AM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251160008 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.251160008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.4294258027 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 50485509974 ps |
| CPU time | 924.31 seconds |
| Started | Sep 10 05:51:16 AM UTC 24 |
| Finished | Sep 10 06:06:53 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294258027 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.4294258027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.1716420027 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 276649745 ps |
| CPU time | 37.57 seconds |
| Started | Sep 10 05:51:05 AM UTC 24 |
| Finished | Sep 10 05:51:44 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716420027 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.1716420027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.1685455015 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 312534498 ps |
| CPU time | 16.42 seconds |
| Started | Sep 10 05:51:26 AM UTC 24 |
| Finished | Sep 10 05:51:44 AM UTC 24 |
| Peak memory | 595720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685455015 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1685455015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.1944320563 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 45705153 ps |
| CPU time | 8.03 seconds |
| Started | Sep 10 05:50:36 AM UTC 24 |
| Finished | Sep 10 05:50:45 AM UTC 24 |
| Peak memory | 593732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944320563 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1944320563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.1834656282 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 8484379888 ps |
| CPU time | 103.97 seconds |
| Started | Sep 10 05:50:42 AM UTC 24 |
| Finished | Sep 10 05:52:29 AM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834656282 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1834656282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.1409085691 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 4272592392 ps |
| CPU time | 63.42 seconds |
| Started | Sep 10 05:50:43 AM UTC 24 |
| Finished | Sep 10 05:51:48 AM UTC 24 |
| Peak memory | 593724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409085691 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1409085691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1067866347 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 46879418 ps |
| CPU time | 9.93 seconds |
| Started | Sep 10 05:50:38 AM UTC 24 |
| Finished | Sep 10 05:50:49 AM UTC 24 |
| Peak memory | 593772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067866347 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1067866347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.3691571708 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2901699616 ps |
| CPU time | 245.9 seconds |
| Started | Sep 10 05:51:30 AM UTC 24 |
| Finished | Sep 10 05:55:40 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691571708 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.3691571708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.2362185526 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 249690857 ps |
| CPU time | 71.23 seconds |
| Started | Sep 10 05:51:41 AM UTC 24 |
| Finished | Sep 10 05:52:54 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362185526 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.2362185526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.3465322432 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 5338884574 ps |
| CPU time | 422.14 seconds |
| Started | Sep 10 05:52:03 AM UTC 24 |
| Finished | Sep 10 05:59:11 AM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465322432 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.3465322432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.1924631770 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 1096821894 ps |
| CPU time | 52.59 seconds |
| Started | Sep 10 05:51:26 AM UTC 24 |
| Finished | Sep 10 05:52:20 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924631770 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1924631770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.3849991536 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 11294316882 ps |
| CPU time | 887.54 seconds |
| Started | Sep 10 05:54:49 AM UTC 24 |
| Finished | Sep 10 06:09:47 AM UTC 24 |
| Peak memory | 670112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3849991536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 19.chip_csr_mem_rw_with_rand_reset.3849991536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.2094255600 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 3926380586 ps |
| CPU time | 335.15 seconds |
| Started | Sep 10 05:54:43 AM UTC 24 |
| Finished | Sep 10 06:00:23 AM UTC 24 |
| Peak memory | 614732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094255600 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.2094255600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.735512804 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 29012120758 ps |
| CPU time | 3174.61 seconds |
| Started | Sep 10 05:52:11 AM UTC 24 |
| Finished | Sep 10 06:45:44 AM UTC 24 |
| Peak memory | 613824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=735512804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 19.chip_same_csr_outstanding.735512804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.1096631650 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 4698940531 ps |
| CPU time | 452.2 seconds |
| Started | Sep 10 05:52:12 AM UTC 24 |
| Finished | Sep 10 05:59:51 AM UTC 24 |
| Peak memory | 621204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096631650 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.1096631650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.1008667009 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 820320541 ps |
| CPU time | 85.12 seconds |
| Started | Sep 10 05:52:56 AM UTC 24 |
| Finished | Sep 10 05:54:23 AM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008667009 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1008667009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.2647210804 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 119915190015 ps |
| CPU time | 1653.03 seconds |
| Started | Sep 10 05:53:02 AM UTC 24 |
| Finished | Sep 10 06:20:55 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647210804 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.2647210804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.1638692275 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 97930356 ps |
| CPU time | 10.4 seconds |
| Started | Sep 10 05:54:00 AM UTC 24 |
| Finished | Sep 10 05:54:11 AM UTC 24 |
| Peak memory | 593732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638692275 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.1638692275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.2029003908 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 447315739 ps |
| CPU time | 38.66 seconds |
| Started | Sep 10 05:53:21 AM UTC 24 |
| Finished | Sep 10 05:54:01 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029003908 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2029003908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.1452372988 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 2468226301 ps |
| CPU time | 130.75 seconds |
| Started | Sep 10 05:52:46 AM UTC 24 |
| Finished | Sep 10 05:54:59 AM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452372988 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.1452372988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.3988410275 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 11677193275 ps |
| CPU time | 104.84 seconds |
| Started | Sep 10 05:52:53 AM UTC 24 |
| Finished | Sep 10 05:54:40 AM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988410275 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3988410275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.963119072 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 15629689824 ps |
| CPU time | 240.9 seconds |
| Started | Sep 10 05:52:55 AM UTC 24 |
| Finished | Sep 10 05:57:00 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963119072 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.963119072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.3372407829 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 167796396 ps |
| CPU time | 24.44 seconds |
| Started | Sep 10 05:52:52 AM UTC 24 |
| Finished | Sep 10 05:53:18 AM UTC 24 |
| Peak memory | 595980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372407829 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.3372407829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.4121419839 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 514689208 ps |
| CPU time | 50.95 seconds |
| Started | Sep 10 05:53:18 AM UTC 24 |
| Finished | Sep 10 05:54:11 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121419839 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.4121419839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.819149307 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 207705888 ps |
| CPU time | 13.75 seconds |
| Started | Sep 10 05:52:16 AM UTC 24 |
| Finished | Sep 10 05:52:31 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819149307 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.819149307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.4140079092 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 6976344195 ps |
| CPU time | 109.61 seconds |
| Started | Sep 10 05:52:25 AM UTC 24 |
| Finished | Sep 10 05:54:17 AM UTC 24 |
| Peak memory | 593952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140079092 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.4140079092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2798783909 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 5862077024 ps |
| CPU time | 115.97 seconds |
| Started | Sep 10 05:52:33 AM UTC 24 |
| Finished | Sep 10 05:54:32 AM UTC 24 |
| Peak memory | 593720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798783909 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2798783909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.415230600 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 52090373 ps |
| CPU time | 9.34 seconds |
| Started | Sep 10 05:52:17 AM UTC 24 |
| Finished | Sep 10 05:52:28 AM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415230600 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.415230600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.3417222233 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 2430101382 ps |
| CPU time | 195.49 seconds |
| Started | Sep 10 05:54:28 AM UTC 24 |
| Finished | Sep 10 05:57:47 AM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417222233 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3417222233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.3145949459 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 8802191315 ps |
| CPU time | 343.22 seconds |
| Started | Sep 10 05:54:38 AM UTC 24 |
| Finished | Sep 10 06:00:27 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145949459 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3145949459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.729215872 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 1850099205 ps |
| CPU time | 415.78 seconds |
| Started | Sep 10 05:54:34 AM UTC 24 |
| Finished | Sep 10 06:01:36 AM UTC 24 |
| Peak memory | 596144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729215872 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.729215872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.44643446 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 2098257442 ps |
| CPU time | 161.69 seconds |
| Started | Sep 10 05:54:39 AM UTC 24 |
| Finished | Sep 10 05:57:23 AM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44643446 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.44643446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.2022696206 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 244592069 ps |
| CPU time | 35.54 seconds |
| Started | Sep 10 05:53:44 AM UTC 24 |
| Finished | Sep 10 05:54:21 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022696206 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2022696206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_aliasing.2021833898 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 36343249568 ps |
| CPU time | 4827.92 seconds |
| Started | Sep 10 05:04:53 AM UTC 24 |
| Finished | Sep 10 06:26:15 AM UTC 24 |
| Peak memory | 615808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2021833898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_ csr_aliasing.2021833898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_bit_bash.1145992074 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 3758102898 ps |
| CPU time | 265.21 seconds |
| Started | Sep 10 05:04:39 AM UTC 24 |
| Finished | Sep 10 05:09:09 AM UTC 24 |
| Peak memory | 616676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1145992074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.chip_csr_bit_bash.1145992074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.3179898309 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 5633223800 ps |
| CPU time | 754.42 seconds |
| Started | Sep 10 05:07:57 AM UTC 24 |
| Finished | Sep 10 05:20:42 AM UTC 24 |
| Peak memory | 616968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179898309 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.3179898309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.3161100271 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 10731091860 ps |
| CPU time | 604.08 seconds |
| Started | Sep 10 05:05:02 AM UTC 24 |
| Finished | Sep 10 05:15:15 AM UTC 24 |
| Peak memory | 608720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161100271 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.3161100271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_prim_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.3276616728 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 13875390228 ps |
| CPU time | 664.74 seconds |
| Started | Sep 10 05:05:11 AM UTC 24 |
| Finished | Sep 10 05:16:25 AM UTC 24 |
| Peak memory | 606544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_c pu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3276616728 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. chip_rv_dm_lc_disabled.3276616728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.353583932 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 28500330478 ps |
| CPU time | 4213.71 seconds |
| Started | Sep 10 05:04:57 AM UTC 24 |
| Finished | Sep 10 06:16:02 AM UTC 24 |
| Peak memory | 614024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=353583932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.chip_same_csr_outstanding.353583932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.278182943 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 3089856886 ps |
| CPU time | 206 seconds |
| Started | Sep 10 05:05:01 AM UTC 24 |
| Finished | Sep 10 05:08:31 AM UTC 24 |
| Peak memory | 621152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278182943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.278182943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.3336438992 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 580274692 ps |
| CPU time | 34.17 seconds |
| Started | Sep 10 05:06:10 AM UTC 24 |
| Finished | Sep 10 05:06:46 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336438992 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.3336438992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.4088167142 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 26028538265 ps |
| CPU time | 391.02 seconds |
| Started | Sep 10 05:06:22 AM UTC 24 |
| Finished | Sep 10 05:12:58 AM UTC 24 |
| Peak memory | 596004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088167142 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.4088167142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.3148520128 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 1076547056 ps |
| CPU time | 44.98 seconds |
| Started | Sep 10 05:06:59 AM UTC 24 |
| Finished | Sep 10 05:07:46 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148520128 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3148520128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.3218687798 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 1974975032 ps |
| CPU time | 96.63 seconds |
| Started | Sep 10 05:06:52 AM UTC 24 |
| Finished | Sep 10 05:08:30 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218687798 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3218687798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.2353115825 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 393703091 ps |
| CPU time | 49.73 seconds |
| Started | Sep 10 05:05:38 AM UTC 24 |
| Finished | Sep 10 05:06:29 AM UTC 24 |
| Peak memory | 595980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353115825 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.2353115825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.441260223 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 98209038399 ps |
| CPU time | 952.38 seconds |
| Started | Sep 10 05:05:55 AM UTC 24 |
| Finished | Sep 10 05:21:58 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441260223 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.441260223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.432042422 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 10654454814 ps |
| CPU time | 154 seconds |
| Started | Sep 10 05:06:01 AM UTC 24 |
| Finished | Sep 10 05:08:38 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432042422 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.432042422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.617587625 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 221069797 ps |
| CPU time | 30.71 seconds |
| Started | Sep 10 05:05:52 AM UTC 24 |
| Finished | Sep 10 05:06:24 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617587625 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.617587625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.4174305928 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 1258365992 ps |
| CPU time | 56.06 seconds |
| Started | Sep 10 05:06:46 AM UTC 24 |
| Finished | Sep 10 05:07:44 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174305928 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.4174305928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.2413272866 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 210166722 ps |
| CPU time | 11.09 seconds |
| Started | Sep 10 05:05:16 AM UTC 24 |
| Finished | Sep 10 05:05:28 AM UTC 24 |
| Peak memory | 593844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413272866 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2413272866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.967332301 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 9211833447 ps |
| CPU time | 84.31 seconds |
| Started | Sep 10 05:05:28 AM UTC 24 |
| Finished | Sep 10 05:06:55 AM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967332301 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.967332301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.3384929752 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 6115111190 ps |
| CPU time | 118.37 seconds |
| Started | Sep 10 05:05:30 AM UTC 24 |
| Finished | Sep 10 05:07:31 AM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384929752 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3384929752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.114585093 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 54494831 ps |
| CPU time | 10.05 seconds |
| Started | Sep 10 05:05:23 AM UTC 24 |
| Finished | Sep 10 05:05:34 AM UTC 24 |
| Peak memory | 593776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114585093 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.114585093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.751262326 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 2091934113 ps |
| CPU time | 224.16 seconds |
| Started | Sep 10 05:07:12 AM UTC 24 |
| Finished | Sep 10 05:11:00 AM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751262326 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.751262326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.3433397584 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 1158552519 ps |
| CPU time | 38.61 seconds |
| Started | Sep 10 05:07:22 AM UTC 24 |
| Finished | Sep 10 05:08:02 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433397584 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3433397584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.3876450136 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 542383992 ps |
| CPU time | 170.76 seconds |
| Started | Sep 10 05:07:17 AM UTC 24 |
| Finished | Sep 10 05:10:11 AM UTC 24 |
| Peak memory | 596092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876450136 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.3876450136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.2378451370 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 6768479 ps |
| CPU time | 7.41 seconds |
| Started | Sep 10 05:07:32 AM UTC 24 |
| Finished | Sep 10 05:07:40 AM UTC 24 |
| Peak memory | 593656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378451370 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.2378451370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.340115843 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 326097057 ps |
| CPU time | 24.12 seconds |
| Started | Sep 10 05:06:57 AM UTC 24 |
| Finished | Sep 10 05:07:22 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340115843 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.340115843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.3700662025 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 3447741623 ps |
| CPU time | 152.44 seconds |
| Started | Sep 10 05:55:35 AM UTC 24 |
| Finished | Sep 10 05:58:11 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700662025 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.3700662025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/20.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.3606615475 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 85881350954 ps |
| CPU time | 1406.61 seconds |
| Started | Sep 10 05:56:07 AM UTC 24 |
| Finished | Sep 10 06:19:50 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606615475 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.3606615475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.3872948047 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 1267604193 ps |
| CPU time | 47.32 seconds |
| Started | Sep 10 05:56:51 AM UTC 24 |
| Finished | Sep 10 05:57:39 AM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872948047 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.3872948047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.2645339276 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 1271342620 ps |
| CPU time | 50.5 seconds |
| Started | Sep 10 05:56:39 AM UTC 24 |
| Finished | Sep 10 05:57:31 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645339276 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.2645339276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/20.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.1046962050 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 1255111204 ps |
| CPU time | 57.89 seconds |
| Started | Sep 10 05:55:26 AM UTC 24 |
| Finished | Sep 10 05:56:25 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046962050 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.1046962050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/20.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.1569418156 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 55980779263 ps |
| CPU time | 594.31 seconds |
| Started | Sep 10 05:55:35 AM UTC 24 |
| Finished | Sep 10 06:05:37 AM UTC 24 |
| Peak memory | 596004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569418156 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1569418156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/20.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.3527829968 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 12161091154 ps |
| CPU time | 219.56 seconds |
| Started | Sep 10 05:55:37 AM UTC 24 |
| Finished | Sep 10 05:59:21 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527829968 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3527829968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/20.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.3939056823 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 312348661 ps |
| CPU time | 37.65 seconds |
| Started | Sep 10 05:55:34 AM UTC 24 |
| Finished | Sep 10 05:56:13 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939056823 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.3939056823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/20.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.4294539688 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 488661368 ps |
| CPU time | 45.07 seconds |
| Started | Sep 10 05:56:13 AM UTC 24 |
| Finished | Sep 10 05:56:59 AM UTC 24 |
| Peak memory | 595720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294539688 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.4294539688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/20.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.1640812925 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 53193295 ps |
| CPU time | 9.66 seconds |
| Started | Sep 10 05:54:59 AM UTC 24 |
| Finished | Sep 10 05:55:10 AM UTC 24 |
| Peak memory | 593992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640812925 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1640812925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/20.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.4140292528 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 8384971668 ps |
| CPU time | 132.95 seconds |
| Started | Sep 10 05:55:06 AM UTC 24 |
| Finished | Sep 10 05:57:21 AM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140292528 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.4140292528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/20.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.1769995457 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 6193419214 ps |
| CPU time | 84.38 seconds |
| Started | Sep 10 05:55:09 AM UTC 24 |
| Finished | Sep 10 05:56:35 AM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769995457 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1769995457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.1812268212 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 46639059 ps |
| CPU time | 8.02 seconds |
| Started | Sep 10 05:54:59 AM UTC 24 |
| Finished | Sep 10 05:55:08 AM UTC 24 |
| Peak memory | 593880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812268212 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.1812268212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/20.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.2154414279 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 2581969479 ps |
| CPU time | 216.78 seconds |
| Started | Sep 10 05:57:02 AM UTC 24 |
| Finished | Sep 10 06:00:43 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154414279 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2154414279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/20.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.1383086833 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 5513358630 ps |
| CPU time | 153.06 seconds |
| Started | Sep 10 05:57:26 AM UTC 24 |
| Finished | Sep 10 06:00:02 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383086833 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1383086833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/20.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.102058437 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 738746279 ps |
| CPU time | 236.66 seconds |
| Started | Sep 10 05:57:24 AM UTC 24 |
| Finished | Sep 10 06:01:24 AM UTC 24 |
| Peak memory | 596080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102058437 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.102058437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.3815056115 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 459051147 ps |
| CPU time | 145.84 seconds |
| Started | Sep 10 05:57:26 AM UTC 24 |
| Finished | Sep 10 05:59:55 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815056115 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.3815056115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.3056845947 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 409746449 ps |
| CPU time | 26.43 seconds |
| Started | Sep 10 05:56:46 AM UTC 24 |
| Finished | Sep 10 05:57:14 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056845947 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3056845947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/20.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.4160589737 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 4265625044 ps |
| CPU time | 329.73 seconds |
| Started | Sep 10 05:57:41 AM UTC 24 |
| Finished | Sep 10 06:03:16 AM UTC 24 |
| Peak memory | 620964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160589737 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.4160589737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/21.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.3533020524 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 2766245831 ps |
| CPU time | 136.85 seconds |
| Started | Sep 10 05:58:31 AM UTC 24 |
| Finished | Sep 10 06:00:50 AM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533020524 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.3533020524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/21.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.3569298792 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 94560235601 ps |
| CPU time | 1432.96 seconds |
| Started | Sep 10 05:58:39 AM UTC 24 |
| Finished | Sep 10 06:22:49 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569298792 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.3569298792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.1000518144 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 209599700 ps |
| CPU time | 15.04 seconds |
| Started | Sep 10 05:59:39 AM UTC 24 |
| Finished | Sep 10 05:59:55 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000518144 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.1000518144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.880235384 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 677035157 ps |
| CPU time | 28 seconds |
| Started | Sep 10 05:59:14 AM UTC 24 |
| Finished | Sep 10 05:59:43 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880235384 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.880235384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/21.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.364547467 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 851414719 ps |
| CPU time | 41.83 seconds |
| Started | Sep 10 05:58:06 AM UTC 24 |
| Finished | Sep 10 05:58:50 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364547467 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.364547467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/21.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.863870718 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 81003939844 ps |
| CPU time | 736.24 seconds |
| Started | Sep 10 05:58:26 AM UTC 24 |
| Finished | Sep 10 06:10:51 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863870718 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.863870718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/21.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.3534911777 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 53202623889 ps |
| CPU time | 799.73 seconds |
| Started | Sep 10 05:58:28 AM UTC 24 |
| Finished | Sep 10 06:11:58 AM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534911777 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3534911777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/21.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.1828602184 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 214276085 ps |
| CPU time | 32.27 seconds |
| Started | Sep 10 05:58:14 AM UTC 24 |
| Finished | Sep 10 05:58:48 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828602184 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.1828602184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/21.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.2070523552 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 1325886277 ps |
| CPU time | 56.16 seconds |
| Started | Sep 10 05:58:48 AM UTC 24 |
| Finished | Sep 10 05:59:46 AM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070523552 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2070523552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/21.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.2991215683 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 124921227 ps |
| CPU time | 10.77 seconds |
| Started | Sep 10 05:57:47 AM UTC 24 |
| Finished | Sep 10 05:57:59 AM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991215683 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2991215683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/21.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.2743643186 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 9779781846 ps |
| CPU time | 122.68 seconds |
| Started | Sep 10 05:57:58 AM UTC 24 |
| Finished | Sep 10 06:00:03 AM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743643186 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2743643186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/21.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.2875173769 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 5531788689 ps |
| CPU time | 81.12 seconds |
| Started | Sep 10 05:58:07 AM UTC 24 |
| Finished | Sep 10 05:59:30 AM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875173769 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2875173769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.3356485940 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 45019093 ps |
| CPU time | 8.9 seconds |
| Started | Sep 10 05:57:51 AM UTC 24 |
| Finished | Sep 10 05:58:01 AM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356485940 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3356485940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/21.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.671522992 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 620405163 ps |
| CPU time | 35.73 seconds |
| Started | Sep 10 05:59:48 AM UTC 24 |
| Finished | Sep 10 06:00:25 AM UTC 24 |
| Peak memory | 595816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671522992 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.671522992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/21.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.1367483078 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 3150191839 ps |
| CPU time | 218.79 seconds |
| Started | Sep 10 06:00:07 AM UTC 24 |
| Finished | Sep 10 06:03:49 AM UTC 24 |
| Peak memory | 596044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367483078 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1367483078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/21.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.2228658865 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 207769236 ps |
| CPU time | 64.21 seconds |
| Started | Sep 10 05:59:57 AM UTC 24 |
| Finished | Sep 10 06:01:03 AM UTC 24 |
| Peak memory | 595940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228658865 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.2228658865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.2073590519 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 860569248 ps |
| CPU time | 47.59 seconds |
| Started | Sep 10 05:59:17 AM UTC 24 |
| Finished | Sep 10 06:00:06 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073590519 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2073590519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/21.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.2936504411 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 4449206296 ps |
| CPU time | 480.34 seconds |
| Started | Sep 10 06:00:11 AM UTC 24 |
| Finished | Sep 10 06:08:19 AM UTC 24 |
| Peak memory | 621204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936504411 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.2936504411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/22.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.3627748843 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 1241138919 ps |
| CPU time | 80.63 seconds |
| Started | Sep 10 06:00:36 AM UTC 24 |
| Finished | Sep 10 06:01:58 AM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627748843 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3627748843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/22.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.2674514766 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 51774901942 ps |
| CPU time | 815.87 seconds |
| Started | Sep 10 06:00:49 AM UTC 24 |
| Finished | Sep 10 06:14:35 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674514766 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.2674514766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1197729518 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 962347595 ps |
| CPU time | 55.29 seconds |
| Started | Sep 10 06:00:53 AM UTC 24 |
| Finished | Sep 10 06:01:49 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197729518 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.1197729518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.3735672386 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 1124468961 ps |
| CPU time | 37.01 seconds |
| Started | Sep 10 06:00:52 AM UTC 24 |
| Finished | Sep 10 06:01:30 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735672386 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3735672386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/22.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.4053544782 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 1589485192 ps |
| CPU time | 73.96 seconds |
| Started | Sep 10 06:00:23 AM UTC 24 |
| Finished | Sep 10 06:01:39 AM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053544782 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.4053544782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/22.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.817970645 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 27258252798 ps |
| CPU time | 403.9 seconds |
| Started | Sep 10 06:00:31 AM UTC 24 |
| Finished | Sep 10 06:07:21 AM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817970645 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.817970645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/22.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.1807956548 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 42404045583 ps |
| CPU time | 655.93 seconds |
| Started | Sep 10 06:00:30 AM UTC 24 |
| Finished | Sep 10 06:11:35 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807956548 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1807956548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/22.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.1478699454 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 226839090 ps |
| CPU time | 31.44 seconds |
| Started | Sep 10 06:00:31 AM UTC 24 |
| Finished | Sep 10 06:01:04 AM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478699454 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.1478699454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/22.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.872490017 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 2498771933 ps |
| CPU time | 78.38 seconds |
| Started | Sep 10 06:00:52 AM UTC 24 |
| Finished | Sep 10 06:02:13 AM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872490017 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.872490017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/22.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.1617516129 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 38531115 ps |
| CPU time | 7.52 seconds |
| Started | Sep 10 06:00:17 AM UTC 24 |
| Finished | Sep 10 06:00:25 AM UTC 24 |
| Peak memory | 593776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617516129 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1617516129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/22.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.3152616158 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 7592745086 ps |
| CPU time | 85.28 seconds |
| Started | Sep 10 06:00:19 AM UTC 24 |
| Finished | Sep 10 06:01:46 AM UTC 24 |
| Peak memory | 593532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152616158 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.3152616158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/22.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.2315160890 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 5467627929 ps |
| CPU time | 74.44 seconds |
| Started | Sep 10 06:00:20 AM UTC 24 |
| Finished | Sep 10 06:01:36 AM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315160890 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2315160890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.2689364253 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 45992404 ps |
| CPU time | 7.55 seconds |
| Started | Sep 10 06:00:19 AM UTC 24 |
| Finished | Sep 10 06:00:28 AM UTC 24 |
| Peak memory | 593424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689364253 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.2689364253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/22.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.2770450462 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 1580092611 ps |
| CPU time | 146.52 seconds |
| Started | Sep 10 06:01:10 AM UTC 24 |
| Finished | Sep 10 06:03:39 AM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770450462 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2770450462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/22.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.665674197 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 5449364245 ps |
| CPU time | 155.96 seconds |
| Started | Sep 10 06:01:18 AM UTC 24 |
| Finished | Sep 10 06:03:57 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665674197 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.665674197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/22.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.863080533 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 727340410 ps |
| CPU time | 268.42 seconds |
| Started | Sep 10 06:01:16 AM UTC 24 |
| Finished | Sep 10 06:05:49 AM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863080533 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.863080533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.105581539 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 3567042035 ps |
| CPU time | 301.83 seconds |
| Started | Sep 10 06:01:31 AM UTC 24 |
| Finished | Sep 10 06:06:37 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105581539 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.105581539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.3503604129 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 1474464015 ps |
| CPU time | 64.71 seconds |
| Started | Sep 10 06:00:54 AM UTC 24 |
| Finished | Sep 10 06:02:00 AM UTC 24 |
| Peak memory | 596036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503604129 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3503604129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/22.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.1434871601 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 4358259992 ps |
| CPU time | 336.75 seconds |
| Started | Sep 10 06:01:31 AM UTC 24 |
| Finished | Sep 10 06:07:13 AM UTC 24 |
| Peak memory | 621036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434871601 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.1434871601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/23.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.1443057006 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 856218603 ps |
| CPU time | 82.82 seconds |
| Started | Sep 10 06:02:26 AM UTC 24 |
| Finished | Sep 10 06:03:51 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443057006 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1443057006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/23.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.2615527201 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 116588780698 ps |
| CPU time | 1793.76 seconds |
| Started | Sep 10 06:02:30 AM UTC 24 |
| Finished | Sep 10 06:32:46 AM UTC 24 |
| Peak memory | 599168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615527201 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.2615527201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.56642069 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 695297255 ps |
| CPU time | 38.08 seconds |
| Started | Sep 10 06:03:08 AM UTC 24 |
| Finished | Sep 10 06:03:47 AM UTC 24 |
| Peak memory | 595964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56642069 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.56642069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.3073600524 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 527342331 ps |
| CPU time | 54.48 seconds |
| Started | Sep 10 06:02:40 AM UTC 24 |
| Finished | Sep 10 06:03:36 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073600524 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3073600524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/23.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.596230231 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 137605292 ps |
| CPU time | 7.69 seconds |
| Started | Sep 10 06:02:06 AM UTC 24 |
| Finished | Sep 10 06:02:15 AM UTC 24 |
| Peak memory | 593660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596230231 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.596230231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/23.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.3493806719 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 30173287122 ps |
| CPU time | 368.28 seconds |
| Started | Sep 10 06:02:15 AM UTC 24 |
| Finished | Sep 10 06:08:29 AM UTC 24 |
| Peak memory | 596040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493806719 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3493806719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/23.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.3159322757 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 42345217828 ps |
| CPU time | 598.17 seconds |
| Started | Sep 10 06:02:26 AM UTC 24 |
| Finished | Sep 10 06:12:31 AM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159322757 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3159322757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/23.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.970798073 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 246205194 ps |
| CPU time | 31.17 seconds |
| Started | Sep 10 06:02:15 AM UTC 24 |
| Finished | Sep 10 06:02:47 AM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970798073 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.970798073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/23.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.4058658895 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 864903932 ps |
| CPU time | 40.24 seconds |
| Started | Sep 10 06:02:31 AM UTC 24 |
| Finished | Sep 10 06:03:13 AM UTC 24 |
| Peak memory | 596096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058658895 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.4058658895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/23.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.2813975047 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 192307621 ps |
| CPU time | 12.4 seconds |
| Started | Sep 10 06:01:49 AM UTC 24 |
| Finished | Sep 10 06:02:03 AM UTC 24 |
| Peak memory | 593844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813975047 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.2813975047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/23.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.2764877443 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 7043622436 ps |
| CPU time | 62.06 seconds |
| Started | Sep 10 06:02:03 AM UTC 24 |
| Finished | Sep 10 06:03:06 AM UTC 24 |
| Peak memory | 593956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764877443 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2764877443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/23.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.1251030624 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 5964035865 ps |
| CPU time | 86.73 seconds |
| Started | Sep 10 06:02:04 AM UTC 24 |
| Finished | Sep 10 06:03:32 AM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251030624 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1251030624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.3913556281 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 52778523 ps |
| CPU time | 6.93 seconds |
| Started | Sep 10 06:01:56 AM UTC 24 |
| Finished | Sep 10 06:02:04 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913556281 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3913556281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/23.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.437165475 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 672700525 ps |
| CPU time | 54.93 seconds |
| Started | Sep 10 06:03:15 AM UTC 24 |
| Finished | Sep 10 06:04:11 AM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437165475 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.437165475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/23.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.1934077711 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 10745004608 ps |
| CPU time | 385.92 seconds |
| Started | Sep 10 06:03:32 AM UTC 24 |
| Finished | Sep 10 06:10:04 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934077711 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1934077711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/23.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.491397505 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 180962804 ps |
| CPU time | 110.41 seconds |
| Started | Sep 10 06:03:34 AM UTC 24 |
| Finished | Sep 10 06:05:27 AM UTC 24 |
| Peak memory | 596044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491397505 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.491397505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.778035822 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 974371620 ps |
| CPU time | 291.59 seconds |
| Started | Sep 10 06:03:41 AM UTC 24 |
| Finished | Sep 10 06:08:37 AM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778035822 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.778035822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.3757398670 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 577657129 ps |
| CPU time | 31.06 seconds |
| Started | Sep 10 06:02:41 AM UTC 24 |
| Finished | Sep 10 06:03:14 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757398670 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3757398670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/23.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.1226903737 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 3863110650 ps |
| CPU time | 267.86 seconds |
| Started | Sep 10 06:03:38 AM UTC 24 |
| Finished | Sep 10 06:08:10 AM UTC 24 |
| Peak memory | 621224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226903737 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.1226903737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/24.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.1400599646 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 1552855981 ps |
| CPU time | 86.63 seconds |
| Started | Sep 10 06:04:39 AM UTC 24 |
| Finished | Sep 10 06:06:08 AM UTC 24 |
| Peak memory | 595720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400599646 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1400599646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/24.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1402698492 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 23619330153 ps |
| CPU time | 401.31 seconds |
| Started | Sep 10 06:04:40 AM UTC 24 |
| Finished | Sep 10 06:11:27 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402698492 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.1402698492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.3033447184 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 376030588 ps |
| CPU time | 22.94 seconds |
| Started | Sep 10 06:05:49 AM UTC 24 |
| Finished | Sep 10 06:06:13 AM UTC 24 |
| Peak memory | 595920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033447184 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.3033447184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.3446969558 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 397666245 ps |
| CPU time | 37.98 seconds |
| Started | Sep 10 06:05:31 AM UTC 24 |
| Finished | Sep 10 06:06:10 AM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446969558 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3446969558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/24.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.4026187915 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 2168460917 ps |
| CPU time | 100.82 seconds |
| Started | Sep 10 06:04:17 AM UTC 24 |
| Finished | Sep 10 06:06:00 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026187915 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.4026187915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/24.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.2936948154 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 65086436684 ps |
| CPU time | 644.47 seconds |
| Started | Sep 10 06:04:24 AM UTC 24 |
| Finished | Sep 10 06:15:17 AM UTC 24 |
| Peak memory | 595980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936948154 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2936948154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/24.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.3154210677 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 51990098031 ps |
| CPU time | 782.98 seconds |
| Started | Sep 10 06:04:33 AM UTC 24 |
| Finished | Sep 10 06:17:46 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154210677 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3154210677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/24.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.1866859722 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 426393054 ps |
| CPU time | 49.59 seconds |
| Started | Sep 10 06:04:15 AM UTC 24 |
| Finished | Sep 10 06:05:06 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866859722 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1866859722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/24.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.1458632158 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 2409538847 ps |
| CPU time | 81.93 seconds |
| Started | Sep 10 06:04:41 AM UTC 24 |
| Finished | Sep 10 06:06:05 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458632158 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1458632158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/24.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.4000086901 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 230466727 ps |
| CPU time | 12.83 seconds |
| Started | Sep 10 06:03:59 AM UTC 24 |
| Finished | Sep 10 06:04:13 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000086901 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.4000086901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/24.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.4010916624 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 7899014410 ps |
| CPU time | 72.73 seconds |
| Started | Sep 10 06:04:07 AM UTC 24 |
| Finished | Sep 10 06:05:21 AM UTC 24 |
| Peak memory | 593724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010916624 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.4010916624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/24.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.3103339664 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 4716822895 ps |
| CPU time | 66.48 seconds |
| Started | Sep 10 06:04:14 AM UTC 24 |
| Finished | Sep 10 06:05:22 AM UTC 24 |
| Peak memory | 593980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103339664 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3103339664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.3885471532 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 45026876 ps |
| CPU time | 9.5 seconds |
| Started | Sep 10 06:04:03 AM UTC 24 |
| Finished | Sep 10 06:04:14 AM UTC 24 |
| Peak memory | 593724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885471532 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.3885471532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/24.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.2530489074 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 252053953 ps |
| CPU time | 16.48 seconds |
| Started | Sep 10 06:05:50 AM UTC 24 |
| Finished | Sep 10 06:06:07 AM UTC 24 |
| Peak memory | 593884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530489074 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2530489074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/24.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.2041824366 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 3380862127 ps |
| CPU time | 110.86 seconds |
| Started | Sep 10 06:06:04 AM UTC 24 |
| Finished | Sep 10 06:07:57 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041824366 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2041824366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/24.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.893056337 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 544180592 ps |
| CPU time | 338.53 seconds |
| Started | Sep 10 06:05:54 AM UTC 24 |
| Finished | Sep 10 06:11:37 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893056337 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.893056337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.4111870102 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 106100138 ps |
| CPU time | 48.11 seconds |
| Started | Sep 10 06:06:08 AM UTC 24 |
| Finished | Sep 10 06:06:57 AM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111870102 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.4111870102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.838977324 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 498186374 ps |
| CPU time | 27.27 seconds |
| Started | Sep 10 06:05:34 AM UTC 24 |
| Finished | Sep 10 06:06:02 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838977324 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.838977324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/24.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.2137578717 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 3851390127 ps |
| CPU time | 327.42 seconds |
| Started | Sep 10 06:06:15 AM UTC 24 |
| Finished | Sep 10 06:11:48 AM UTC 24 |
| Peak memory | 616992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137578717 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.2137578717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/25.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.3531499405 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 691873054 ps |
| CPU time | 28.44 seconds |
| Started | Sep 10 06:07:05 AM UTC 24 |
| Finished | Sep 10 06:07:35 AM UTC 24 |
| Peak memory | 595940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531499405 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3531499405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/25.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.2361178235 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 98544819969 ps |
| CPU time | 1480.16 seconds |
| Started | Sep 10 06:07:07 AM UTC 24 |
| Finished | Sep 10 06:32:04 AM UTC 24 |
| Peak memory | 598944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361178235 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.2361178235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.3750971265 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 659416745 ps |
| CPU time | 27.43 seconds |
| Started | Sep 10 06:07:41 AM UTC 24 |
| Finished | Sep 10 06:08:09 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750971265 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3750971265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.2955056581 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 413429820 ps |
| CPU time | 38.24 seconds |
| Started | Sep 10 06:07:24 AM UTC 24 |
| Finished | Sep 10 06:08:04 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955056581 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2955056581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/25.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.3128569068 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 331587185 ps |
| CPU time | 31.37 seconds |
| Started | Sep 10 06:06:36 AM UTC 24 |
| Finished | Sep 10 06:07:09 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128569068 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.3128569068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/25.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.912379756 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 38362326864 ps |
| CPU time | 519.49 seconds |
| Started | Sep 10 06:06:38 AM UTC 24 |
| Finished | Sep 10 06:15:24 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912379756 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.912379756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/25.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.1146966298 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 27651148249 ps |
| CPU time | 450.41 seconds |
| Started | Sep 10 06:07:06 AM UTC 24 |
| Finished | Sep 10 06:14:42 AM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146966298 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1146966298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/25.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.179376292 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 325487967 ps |
| CPU time | 42.45 seconds |
| Started | Sep 10 06:06:37 AM UTC 24 |
| Finished | Sep 10 06:07:22 AM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179376292 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.179376292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/25.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.4004245983 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 165567827 ps |
| CPU time | 18.68 seconds |
| Started | Sep 10 06:07:17 AM UTC 24 |
| Finished | Sep 10 06:07:37 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004245983 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.4004245983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/25.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.4094971182 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 47964536 ps |
| CPU time | 8.98 seconds |
| Started | Sep 10 06:06:27 AM UTC 24 |
| Finished | Sep 10 06:06:37 AM UTC 24 |
| Peak memory | 593788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094971182 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.4094971182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/25.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.2043150181 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 8567419089 ps |
| CPU time | 121.52 seconds |
| Started | Sep 10 06:06:31 AM UTC 24 |
| Finished | Sep 10 06:08:35 AM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043150181 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2043150181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/25.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.1535876149 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 4301548441 ps |
| CPU time | 72.44 seconds |
| Started | Sep 10 06:06:34 AM UTC 24 |
| Finished | Sep 10 06:07:49 AM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535876149 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1535876149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.1111459041 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 38479413 ps |
| CPU time | 9.16 seconds |
| Started | Sep 10 06:06:29 AM UTC 24 |
| Finished | Sep 10 06:06:39 AM UTC 24 |
| Peak memory | 593816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111459041 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.1111459041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/25.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.967858529 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 2707253651 ps |
| CPU time | 274.22 seconds |
| Started | Sep 10 06:08:02 AM UTC 24 |
| Finished | Sep 10 06:12:41 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967858529 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.967858529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/25.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.3208902027 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 236210635 ps |
| CPU time | 126.94 seconds |
| Started | Sep 10 06:07:49 AM UTC 24 |
| Finished | Sep 10 06:09:58 AM UTC 24 |
| Peak memory | 596064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208902027 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.3208902027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.1569877007 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 16876429647 ps |
| CPU time | 825.63 seconds |
| Started | Sep 10 06:08:03 AM UTC 24 |
| Finished | Sep 10 06:22:00 AM UTC 24 |
| Peak memory | 596200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569877007 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.1569877007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.400287279 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 233874375 ps |
| CPU time | 40.4 seconds |
| Started | Sep 10 06:07:35 AM UTC 24 |
| Finished | Sep 10 06:08:17 AM UTC 24 |
| Peak memory | 596144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400287279 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.400287279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/25.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.2638439648 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 4345766367 ps |
| CPU time | 348.24 seconds |
| Started | Sep 10 06:08:16 AM UTC 24 |
| Finished | Sep 10 06:14:09 AM UTC 24 |
| Peak memory | 621104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638439648 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.2638439648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/26.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.899949387 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 408752163 ps |
| CPU time | 48.05 seconds |
| Started | Sep 10 06:09:00 AM UTC 24 |
| Finished | Sep 10 06:09:49 AM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899949387 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.899949387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/26.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.1218878685 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 125227979878 ps |
| CPU time | 2011.86 seconds |
| Started | Sep 10 06:09:01 AM UTC 24 |
| Finished | Sep 10 06:42:56 AM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218878685 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.1218878685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.1439456388 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 256850988 ps |
| CPU time | 13.06 seconds |
| Started | Sep 10 06:09:41 AM UTC 24 |
| Finished | Sep 10 06:09:56 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439456388 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1439456388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.1522274871 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 2417204653 ps |
| CPU time | 104.19 seconds |
| Started | Sep 10 06:09:03 AM UTC 24 |
| Finished | Sep 10 06:10:49 AM UTC 24 |
| Peak memory | 596148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522274871 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1522274871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/26.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.918166379 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 1305690132 ps |
| CPU time | 61.38 seconds |
| Started | Sep 10 06:08:38 AM UTC 24 |
| Finished | Sep 10 06:09:41 AM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918166379 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.918166379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/26.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.1791803158 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 76739304822 ps |
| CPU time | 861.74 seconds |
| Started | Sep 10 06:08:47 AM UTC 24 |
| Finished | Sep 10 06:23:19 AM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791803158 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1791803158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/26.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.1450786504 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 45386697867 ps |
| CPU time | 751.83 seconds |
| Started | Sep 10 06:08:54 AM UTC 24 |
| Finished | Sep 10 06:21:36 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450786504 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1450786504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/26.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.1006952134 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 368560929 ps |
| CPU time | 45.93 seconds |
| Started | Sep 10 06:08:42 AM UTC 24 |
| Finished | Sep 10 06:09:29 AM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006952134 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.1006952134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/26.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.340762480 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 250294171 ps |
| CPU time | 11.7 seconds |
| Started | Sep 10 06:09:00 AM UTC 24 |
| Finished | Sep 10 06:09:13 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340762480 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.340762480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/26.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.860728289 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 47782412 ps |
| CPU time | 9.25 seconds |
| Started | Sep 10 06:08:21 AM UTC 24 |
| Finished | Sep 10 06:08:31 AM UTC 24 |
| Peak memory | 593860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860728289 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.860728289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/26.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.3552204403 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 9799596423 ps |
| CPU time | 107.99 seconds |
| Started | Sep 10 06:08:32 AM UTC 24 |
| Finished | Sep 10 06:10:22 AM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552204403 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3552204403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/26.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.1342032475 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 4987660472 ps |
| CPU time | 84.48 seconds |
| Started | Sep 10 06:08:36 AM UTC 24 |
| Finished | Sep 10 06:10:02 AM UTC 24 |
| Peak memory | 593860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342032475 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1342032475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.2827915447 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 46525855 ps |
| CPU time | 9 seconds |
| Started | Sep 10 06:08:24 AM UTC 24 |
| Finished | Sep 10 06:08:34 AM UTC 24 |
| Peak memory | 593900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827915447 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.2827915447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/26.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.2861726274 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 2089502282 ps |
| CPU time | 210.78 seconds |
| Started | Sep 10 06:09:51 AM UTC 24 |
| Finished | Sep 10 06:13:25 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861726274 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2861726274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/26.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.56609879 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 3156154906 ps |
| CPU time | 132.7 seconds |
| Started | Sep 10 06:10:09 AM UTC 24 |
| Finished | Sep 10 06:12:24 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56609879 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.56609879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/26.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.2172571649 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 379345170 ps |
| CPU time | 175.95 seconds |
| Started | Sep 10 06:09:56 AM UTC 24 |
| Finished | Sep 10 06:12:55 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172571649 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.2172571649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.2057730416 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 265586260 ps |
| CPU time | 35.06 seconds |
| Started | Sep 10 06:10:16 AM UTC 24 |
| Finished | Sep 10 06:10:52 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057730416 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.2057730416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.2419896805 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 283608142 ps |
| CPU time | 17.07 seconds |
| Started | Sep 10 06:09:04 AM UTC 24 |
| Finished | Sep 10 06:09:22 AM UTC 24 |
| Peak memory | 595796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419896805 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2419896805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/26.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.2991005215 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 4030998300 ps |
| CPU time | 386.91 seconds |
| Started | Sep 10 06:10:17 AM UTC 24 |
| Finished | Sep 10 06:16:50 AM UTC 24 |
| Peak memory | 621100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991005215 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.2991005215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/27.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.650011772 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1292641816 ps |
| CPU time | 74.68 seconds |
| Started | Sep 10 06:11:17 AM UTC 24 |
| Finished | Sep 10 06:12:34 AM UTC 24 |
| Peak memory | 595720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650011772 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.650011772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/27.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.678723036 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 98402429404 ps |
| CPU time | 1455.44 seconds |
| Started | Sep 10 06:11:18 AM UTC 24 |
| Finished | Sep 10 06:35:50 AM UTC 24 |
| Peak memory | 596668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678723036 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.678723036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.3635468076 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 224498502 ps |
| CPU time | 16.73 seconds |
| Started | Sep 10 06:11:34 AM UTC 24 |
| Finished | Sep 10 06:11:51 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635468076 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3635468076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.2053764435 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 38861715 ps |
| CPU time | 9.21 seconds |
| Started | Sep 10 06:11:23 AM UTC 24 |
| Finished | Sep 10 06:11:33 AM UTC 24 |
| Peak memory | 593804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053764435 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2053764435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/27.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.1711102520 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 1517215881 ps |
| CPU time | 73.41 seconds |
| Started | Sep 10 06:10:31 AM UTC 24 |
| Finished | Sep 10 06:11:46 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711102520 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.1711102520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/27.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.2546475315 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 61984444282 ps |
| CPU time | 609.47 seconds |
| Started | Sep 10 06:11:00 AM UTC 24 |
| Finished | Sep 10 06:21:17 AM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546475315 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2546475315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/27.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.3156849687 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 44630936982 ps |
| CPU time | 610.53 seconds |
| Started | Sep 10 06:11:02 AM UTC 24 |
| Finished | Sep 10 06:21:20 AM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156849687 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3156849687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/27.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.2491987077 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 146738307 ps |
| CPU time | 14.96 seconds |
| Started | Sep 10 06:10:49 AM UTC 24 |
| Finished | Sep 10 06:11:05 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491987077 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2491987077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/27.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.2115387751 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 286116137 ps |
| CPU time | 15.36 seconds |
| Started | Sep 10 06:11:20 AM UTC 24 |
| Finished | Sep 10 06:11:37 AM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115387751 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2115387751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/27.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.487804244 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 200462247 ps |
| CPU time | 11.19 seconds |
| Started | Sep 10 06:10:22 AM UTC 24 |
| Finished | Sep 10 06:10:34 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487804244 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.487804244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/27.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.1034256845 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 10616430757 ps |
| CPU time | 113.53 seconds |
| Started | Sep 10 06:10:26 AM UTC 24 |
| Finished | Sep 10 06:12:22 AM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034256845 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1034256845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/27.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.1984663031 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 5095482189 ps |
| CPU time | 71.87 seconds |
| Started | Sep 10 06:10:30 AM UTC 24 |
| Finished | Sep 10 06:11:44 AM UTC 24 |
| Peak memory | 593984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984663031 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.1984663031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.2766569011 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 57563521 ps |
| CPU time | 8.65 seconds |
| Started | Sep 10 06:10:26 AM UTC 24 |
| Finished | Sep 10 06:10:36 AM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766569011 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.2766569011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/27.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.1302136183 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 4956310171 ps |
| CPU time | 169.31 seconds |
| Started | Sep 10 06:11:54 AM UTC 24 |
| Finished | Sep 10 06:14:46 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302136183 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1302136183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/27.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.164236073 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 176738633 ps |
| CPU time | 25.56 seconds |
| Started | Sep 10 06:12:02 AM UTC 24 |
| Finished | Sep 10 06:12:28 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164236073 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.164236073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/27.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.4117871318 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 10977855359 ps |
| CPU time | 555.9 seconds |
| Started | Sep 10 06:12:01 AM UTC 24 |
| Finished | Sep 10 06:21:23 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117871318 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.4117871318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.3444433363 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 14025045773 ps |
| CPU time | 629.15 seconds |
| Started | Sep 10 06:12:05 AM UTC 24 |
| Finished | Sep 10 06:22:42 AM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444433363 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.3444433363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.2422937596 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 74891570 ps |
| CPU time | 14.26 seconds |
| Started | Sep 10 06:11:25 AM UTC 24 |
| Finished | Sep 10 06:11:41 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422937596 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2422937596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/27.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.2595002374 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 3522498216 ps |
| CPU time | 210.47 seconds |
| Started | Sep 10 06:12:05 AM UTC 24 |
| Finished | Sep 10 06:15:38 AM UTC 24 |
| Peak memory | 620960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595002374 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.2595002374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/28.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.3093367546 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 973873369 ps |
| CPU time | 56.03 seconds |
| Started | Sep 10 06:12:45 AM UTC 24 |
| Finished | Sep 10 06:13:43 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093367546 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.3093367546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/28.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.3449090777 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 53196162440 ps |
| CPU time | 911.51 seconds |
| Started | Sep 10 06:12:46 AM UTC 24 |
| Finished | Sep 10 06:28:09 AM UTC 24 |
| Peak memory | 596164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449090777 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.3449090777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.1249054482 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 178124198 ps |
| CPU time | 28.88 seconds |
| Started | Sep 10 06:12:56 AM UTC 24 |
| Finished | Sep 10 06:13:26 AM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249054482 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.1249054482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.3461312276 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 141834811 ps |
| CPU time | 11.42 seconds |
| Started | Sep 10 06:12:50 AM UTC 24 |
| Finished | Sep 10 06:13:03 AM UTC 24 |
| Peak memory | 593804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461312276 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3461312276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/28.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.3822656241 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 585384755 ps |
| CPU time | 66.94 seconds |
| Started | Sep 10 06:12:19 AM UTC 24 |
| Finished | Sep 10 06:13:28 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822656241 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.3822656241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/28.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.1775685666 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 108542116635 ps |
| CPU time | 1049.12 seconds |
| Started | Sep 10 06:12:24 AM UTC 24 |
| Finished | Sep 10 06:30:05 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775685666 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1775685666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/28.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.2312239332 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 29854691775 ps |
| CPU time | 521.02 seconds |
| Started | Sep 10 06:12:41 AM UTC 24 |
| Finished | Sep 10 06:21:29 AM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312239332 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2312239332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/28.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.689129236 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 255906087 ps |
| CPU time | 27.85 seconds |
| Started | Sep 10 06:12:16 AM UTC 24 |
| Finished | Sep 10 06:12:45 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689129236 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.689129236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/28.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.944801791 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 978553648 ps |
| CPU time | 32.03 seconds |
| Started | Sep 10 06:12:48 AM UTC 24 |
| Finished | Sep 10 06:13:22 AM UTC 24 |
| Peak memory | 596056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944801791 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.944801791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/28.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.482582074 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 190790270 ps |
| CPU time | 12.38 seconds |
| Started | Sep 10 06:12:06 AM UTC 24 |
| Finished | Sep 10 06:12:19 AM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482582074 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.482582074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/28.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.3665636862 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 8513689649 ps |
| CPU time | 93.15 seconds |
| Started | Sep 10 06:12:14 AM UTC 24 |
| Finished | Sep 10 06:13:49 AM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665636862 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3665636862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/28.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.2935371001 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 3476679338 ps |
| CPU time | 75.01 seconds |
| Started | Sep 10 06:12:14 AM UTC 24 |
| Finished | Sep 10 06:13:30 AM UTC 24 |
| Peak memory | 593720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935371001 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2935371001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.3361037426 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 53659907 ps |
| CPU time | 9.55 seconds |
| Started | Sep 10 06:12:11 AM UTC 24 |
| Finished | Sep 10 06:12:22 AM UTC 24 |
| Peak memory | 593956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361037426 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.3361037426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/28.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.2636840291 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1455801454 ps |
| CPU time | 121.23 seconds |
| Started | Sep 10 06:12:58 AM UTC 24 |
| Finished | Sep 10 06:15:02 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636840291 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2636840291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/28.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.3847372997 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 4390633069 ps |
| CPU time | 201.59 seconds |
| Started | Sep 10 06:13:11 AM UTC 24 |
| Finished | Sep 10 06:16:36 AM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847372997 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3847372997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/28.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.1656720884 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 4940223085 ps |
| CPU time | 503.82 seconds |
| Started | Sep 10 06:13:06 AM UTC 24 |
| Finished | Sep 10 06:21:36 AM UTC 24 |
| Peak memory | 596220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656720884 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.1656720884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.1911526587 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 7639563575 ps |
| CPU time | 321.15 seconds |
| Started | Sep 10 06:13:22 AM UTC 24 |
| Finished | Sep 10 06:18:48 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911526587 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.1911526587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.3668020641 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 915898975 ps |
| CPU time | 35.92 seconds |
| Started | Sep 10 06:12:56 AM UTC 24 |
| Finished | Sep 10 06:13:34 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668020641 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3668020641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/28.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.1664439270 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 3442345565 ps |
| CPU time | 285.62 seconds |
| Started | Sep 10 06:13:23 AM UTC 24 |
| Finished | Sep 10 06:18:13 AM UTC 24 |
| Peak memory | 620964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664439270 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.1664439270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/29.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.2525218587 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 2794217358 ps |
| CPU time | 114.35 seconds |
| Started | Sep 10 06:14:10 AM UTC 24 |
| Finished | Sep 10 06:16:06 AM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525218587 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.2525218587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/29.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.1086798087 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 32131231348 ps |
| CPU time | 460.61 seconds |
| Started | Sep 10 06:14:15 AM UTC 24 |
| Finished | Sep 10 06:22:01 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086798087 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.1086798087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.3704947875 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 71962989 ps |
| CPU time | 13.87 seconds |
| Started | Sep 10 06:14:59 AM UTC 24 |
| Finished | Sep 10 06:15:14 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704947875 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.3704947875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.848126263 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 106689574 ps |
| CPU time | 13.19 seconds |
| Started | Sep 10 06:14:36 AM UTC 24 |
| Finished | Sep 10 06:14:51 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848126263 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.848126263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/29.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.2276941655 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 443002776 ps |
| CPU time | 40.14 seconds |
| Started | Sep 10 06:13:53 AM UTC 24 |
| Finished | Sep 10 06:14:35 AM UTC 24 |
| Peak memory | 595720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276941655 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.2276941655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/29.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.2645616018 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 102848654187 ps |
| CPU time | 918.22 seconds |
| Started | Sep 10 06:14:00 AM UTC 24 |
| Finished | Sep 10 06:29:29 AM UTC 24 |
| Peak memory | 596108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645616018 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2645616018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/29.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.939049550 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 34982826433 ps |
| CPU time | 480.13 seconds |
| Started | Sep 10 06:14:08 AM UTC 24 |
| Finished | Sep 10 06:22:14 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939049550 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.939049550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/29.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.2210309700 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 259258497 ps |
| CPU time | 34.37 seconds |
| Started | Sep 10 06:13:56 AM UTC 24 |
| Finished | Sep 10 06:14:32 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210309700 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.2210309700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/29.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.2588927935 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 206687512 ps |
| CPU time | 13.2 seconds |
| Started | Sep 10 06:14:26 AM UTC 24 |
| Finished | Sep 10 06:14:41 AM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588927935 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2588927935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/29.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.160780443 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 43972726 ps |
| CPU time | 8.93 seconds |
| Started | Sep 10 06:13:30 AM UTC 24 |
| Finished | Sep 10 06:13:40 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160780443 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.160780443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/29.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.1280298442 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 5881686415 ps |
| CPU time | 93.4 seconds |
| Started | Sep 10 06:13:51 AM UTC 24 |
| Finished | Sep 10 06:15:26 AM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280298442 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1280298442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/29.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.1242575411 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 5848882542 ps |
| CPU time | 101.66 seconds |
| Started | Sep 10 06:13:51 AM UTC 24 |
| Finished | Sep 10 06:15:34 AM UTC 24 |
| Peak memory | 593720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242575411 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1242575411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.2600612280 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 57321939 ps |
| CPU time | 10.68 seconds |
| Started | Sep 10 06:13:48 AM UTC 24 |
| Finished | Sep 10 06:13:59 AM UTC 24 |
| Peak memory | 593816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600612280 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.2600612280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/29.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.2152085794 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 1920071976 ps |
| CPU time | 228.84 seconds |
| Started | Sep 10 06:14:59 AM UTC 24 |
| Finished | Sep 10 06:18:52 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152085794 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2152085794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/29.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.202611184 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 1341978493 ps |
| CPU time | 115.52 seconds |
| Started | Sep 10 06:15:06 AM UTC 24 |
| Finished | Sep 10 06:17:04 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202611184 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.202611184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/29.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.2454549605 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 3628667508 ps |
| CPU time | 459.94 seconds |
| Started | Sep 10 06:15:03 AM UTC 24 |
| Finished | Sep 10 06:22:49 AM UTC 24 |
| Peak memory | 596012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454549605 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.2454549605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.793109286 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 3745632823 ps |
| CPU time | 454.44 seconds |
| Started | Sep 10 06:15:08 AM UTC 24 |
| Finished | Sep 10 06:22:49 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793109286 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.793109286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.3997003457 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 39567528 ps |
| CPU time | 9.58 seconds |
| Started | Sep 10 06:14:44 AM UTC 24 |
| Finished | Sep 10 06:14:54 AM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997003457 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3997003457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/29.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_aliasing.3908719892 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 31100701660 ps |
| CPU time | 5973.35 seconds |
| Started | Sep 10 05:08:10 AM UTC 24 |
| Finished | Sep 10 06:48:54 AM UTC 24 |
| Peak memory | 619900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3908719892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_ csr_aliasing.3908719892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.593550968 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 5818415711 ps |
| CPU time | 670.21 seconds |
| Started | Sep 10 05:08:09 AM UTC 24 |
| Finished | Sep 10 05:19:28 AM UTC 24 |
| Peak memory | 616672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=593550968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.chip_csr_bit_bash.593550968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.2488601761 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 10399164824 ps |
| CPU time | 1153.87 seconds |
| Started | Sep 10 05:10:23 AM UTC 24 |
| Finished | Sep 10 05:29:52 AM UTC 24 |
| Peak memory | 670360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2488601761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.chip_csr_mem_rw_with_rand_reset.2488601761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.2794241061 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 4197862130 ps |
| CPU time | 352.72 seconds |
| Started | Sep 10 05:10:20 AM UTC 24 |
| Finished | Sep 10 05:16:18 AM UTC 24 |
| Peak memory | 614688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794241061 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.2794241061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.4043726798 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 13818391587 ps |
| CPU time | 2058.71 seconds |
| Started | Sep 10 05:08:09 AM UTC 24 |
| Finished | Sep 10 05:42:54 AM UTC 24 |
| Peak memory | 613840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=4043726798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.chip_same_csr_outstanding.4043726798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.2944051545 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 4040159016 ps |
| CPU time | 233.21 seconds |
| Started | Sep 10 05:08:11 AM UTC 24 |
| Finished | Sep 10 05:12:08 AM UTC 24 |
| Peak memory | 621088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944051545 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.2944051545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.3749139180 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 2940495571 ps |
| CPU time | 151.77 seconds |
| Started | Sep 10 05:08:57 AM UTC 24 |
| Finished | Sep 10 05:11:32 AM UTC 24 |
| Peak memory | 596128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749139180 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.3749139180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.1718222830 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 46903779251 ps |
| CPU time | 705.54 seconds |
| Started | Sep 10 05:08:56 AM UTC 24 |
| Finished | Sep 10 05:20:51 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718222830 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.1718222830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.1983495996 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 925770997 ps |
| CPU time | 52.77 seconds |
| Started | Sep 10 05:09:28 AM UTC 24 |
| Finished | Sep 10 05:10:22 AM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983495996 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.1983495996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.9397698 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 2456140481 ps |
| CPU time | 90.83 seconds |
| Started | Sep 10 05:09:06 AM UTC 24 |
| Finished | Sep 10 05:10:39 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9397698 -assert nopostproc +UVM_TESTNAME=x bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.9397698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.1593098641 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 473625060 ps |
| CPU time | 49.52 seconds |
| Started | Sep 10 05:08:49 AM UTC 24 |
| Finished | Sep 10 05:09:40 AM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593098641 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.1593098641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.1430652079 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 53716742535 ps |
| CPU time | 621.4 seconds |
| Started | Sep 10 05:08:57 AM UTC 24 |
| Finished | Sep 10 05:19:26 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430652079 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1430652079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.892558769 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 13593640356 ps |
| CPU time | 194.29 seconds |
| Started | Sep 10 05:08:57 AM UTC 24 |
| Finished | Sep 10 05:12:15 AM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892558769 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.892558769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.1275867462 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 111816357 ps |
| CPU time | 18.89 seconds |
| Started | Sep 10 05:08:51 AM UTC 24 |
| Finished | Sep 10 05:09:11 AM UTC 24 |
| Peak memory | 595880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275867462 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.1275867462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.2306812594 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 830523381 ps |
| CPU time | 26.46 seconds |
| Started | Sep 10 05:09:01 AM UTC 24 |
| Finished | Sep 10 05:09:28 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306812594 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2306812594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.1171889782 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 221268145 ps |
| CPU time | 14.14 seconds |
| Started | Sep 10 05:08:13 AM UTC 24 |
| Finished | Sep 10 05:08:29 AM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171889782 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.1171889782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.1875457613 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 8447007723 ps |
| CPU time | 82.84 seconds |
| Started | Sep 10 05:08:29 AM UTC 24 |
| Finished | Sep 10 05:09:53 AM UTC 24 |
| Peak memory | 593952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875457613 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1875457613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.2430722639 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 4412832660 ps |
| CPU time | 101.98 seconds |
| Started | Sep 10 05:08:46 AM UTC 24 |
| Finished | Sep 10 05:10:30 AM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430722639 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2430722639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.2190546327 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 51430031 ps |
| CPU time | 9.87 seconds |
| Started | Sep 10 05:08:24 AM UTC 24 |
| Finished | Sep 10 05:08:35 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190546327 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.2190546327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.1892019963 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 1141076088 ps |
| CPU time | 113.73 seconds |
| Started | Sep 10 05:09:36 AM UTC 24 |
| Finished | Sep 10 05:11:32 AM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892019963 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1892019963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.29919626 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 3922639992 ps |
| CPU time | 322.26 seconds |
| Started | Sep 10 05:09:56 AM UTC 24 |
| Finished | Sep 10 05:15:23 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29919626 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.29919626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.931000804 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 234367297 ps |
| CPU time | 201.68 seconds |
| Started | Sep 10 05:09:39 AM UTC 24 |
| Finished | Sep 10 05:13:05 AM UTC 24 |
| Peak memory | 595720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931000804 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.931000804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.2820480633 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 4979750219 ps |
| CPU time | 307.72 seconds |
| Started | Sep 10 05:10:06 AM UTC 24 |
| Finished | Sep 10 05:15:18 AM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820480633 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.2820480633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.2131412055 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 527553780 ps |
| CPU time | 35.71 seconds |
| Started | Sep 10 05:09:15 AM UTC 24 |
| Finished | Sep 10 05:09:52 AM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131412055 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2131412055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.1691386730 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 520661121 ps |
| CPU time | 61.01 seconds |
| Started | Sep 10 06:15:49 AM UTC 24 |
| Finished | Sep 10 06:16:52 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691386730 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.1691386730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/30.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.2241727486 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 42054913782 ps |
| CPU time | 738.65 seconds |
| Started | Sep 10 06:15:52 AM UTC 24 |
| Finished | Sep 10 06:28:20 AM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241727486 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.2241727486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.3189687225 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 1094765461 ps |
| CPU time | 42.03 seconds |
| Started | Sep 10 06:16:29 AM UTC 24 |
| Finished | Sep 10 06:17:13 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189687225 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3189687225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.2252058160 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 1817533776 ps |
| CPU time | 68.72 seconds |
| Started | Sep 10 06:15:58 AM UTC 24 |
| Finished | Sep 10 06:17:09 AM UTC 24 |
| Peak memory | 596012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252058160 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2252058160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/30.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.1439141367 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 2373478267 ps |
| CPU time | 110.64 seconds |
| Started | Sep 10 06:15:28 AM UTC 24 |
| Finished | Sep 10 06:17:21 AM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439141367 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.1439141367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/30.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.2082445515 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 26872602782 ps |
| CPU time | 265.81 seconds |
| Started | Sep 10 06:15:41 AM UTC 24 |
| Finished | Sep 10 06:20:11 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082445515 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2082445515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/30.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.313991671 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 47126326314 ps |
| CPU time | 759.93 seconds |
| Started | Sep 10 06:15:48 AM UTC 24 |
| Finished | Sep 10 06:28:38 AM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313991671 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.313991671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/30.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.3898454292 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 650247538 ps |
| CPU time | 58.65 seconds |
| Started | Sep 10 06:15:42 AM UTC 24 |
| Finished | Sep 10 06:16:42 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898454292 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.3898454292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/30.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.2816102124 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 2542567693 ps |
| CPU time | 74.11 seconds |
| Started | Sep 10 06:15:54 AM UTC 24 |
| Finished | Sep 10 06:17:10 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816102124 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2816102124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/30.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.2027079818 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 45383821 ps |
| CPU time | 7.2 seconds |
| Started | Sep 10 06:15:13 AM UTC 24 |
| Finished | Sep 10 06:15:21 AM UTC 24 |
| Peak memory | 593788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027079818 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2027079818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/30.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.3753224725 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 8745717075 ps |
| CPU time | 121.69 seconds |
| Started | Sep 10 06:15:18 AM UTC 24 |
| Finished | Sep 10 06:17:23 AM UTC 24 |
| Peak memory | 593908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753224725 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3753224725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/30.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.1370648513 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 5566454632 ps |
| CPU time | 69.56 seconds |
| Started | Sep 10 06:15:21 AM UTC 24 |
| Finished | Sep 10 06:16:32 AM UTC 24 |
| Peak memory | 593912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370648513 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1370648513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2184738733 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 38010583 ps |
| CPU time | 8.54 seconds |
| Started | Sep 10 06:15:13 AM UTC 24 |
| Finished | Sep 10 06:15:23 AM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184738733 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2184738733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/30.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.1193598307 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 362314374 ps |
| CPU time | 37.35 seconds |
| Started | Sep 10 06:16:33 AM UTC 24 |
| Finished | Sep 10 06:17:12 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193598307 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1193598307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/30.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.3670124737 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 5517515245 ps |
| CPU time | 205.3 seconds |
| Started | Sep 10 06:17:00 AM UTC 24 |
| Finished | Sep 10 06:20:29 AM UTC 24 |
| Peak memory | 596204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670124737 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3670124737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/30.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.1390441811 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 3383030591 ps |
| CPU time | 324.49 seconds |
| Started | Sep 10 06:16:46 AM UTC 24 |
| Finished | Sep 10 06:22:16 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390441811 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.1390441811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.3648772524 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 876064233 ps |
| CPU time | 123.23 seconds |
| Started | Sep 10 06:17:02 AM UTC 24 |
| Finished | Sep 10 06:19:07 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648772524 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.3648772524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.2578186349 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 137385481 ps |
| CPU time | 12.42 seconds |
| Started | Sep 10 06:16:06 AM UTC 24 |
| Finished | Sep 10 06:16:19 AM UTC 24 |
| Peak memory | 593656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578186349 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2578186349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/30.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.2344014056 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 652398531 ps |
| CPU time | 36.5 seconds |
| Started | Sep 10 06:17:45 AM UTC 24 |
| Finished | Sep 10 06:18:23 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344014056 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.2344014056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/31.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.295953132 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 77588406669 ps |
| CPU time | 1214.77 seconds |
| Started | Sep 10 06:17:45 AM UTC 24 |
| Finished | Sep 10 06:38:15 AM UTC 24 |
| Peak memory | 599092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295953132 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.295953132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.3397835755 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 94792043 ps |
| CPU time | 16.48 seconds |
| Started | Sep 10 06:18:07 AM UTC 24 |
| Finished | Sep 10 06:18:25 AM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397835755 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.3397835755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.4075947869 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 613330680 ps |
| CPU time | 31.34 seconds |
| Started | Sep 10 06:17:49 AM UTC 24 |
| Finished | Sep 10 06:18:22 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075947869 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.4075947869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/31.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.1243025229 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 2193950164 ps |
| CPU time | 107.98 seconds |
| Started | Sep 10 06:17:36 AM UTC 24 |
| Finished | Sep 10 06:19:26 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243025229 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.1243025229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/31.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.2282528732 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 44640361291 ps |
| CPU time | 402.28 seconds |
| Started | Sep 10 06:17:37 AM UTC 24 |
| Finished | Sep 10 06:24:25 AM UTC 24 |
| Peak memory | 595980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282528732 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2282528732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/31.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.527886035 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 23692954874 ps |
| CPU time | 395.2 seconds |
| Started | Sep 10 06:17:41 AM UTC 24 |
| Finished | Sep 10 06:24:21 AM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527886035 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.527886035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/31.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.196611501 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 514397423 ps |
| CPU time | 55.74 seconds |
| Started | Sep 10 06:17:37 AM UTC 24 |
| Finished | Sep 10 06:18:34 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196611501 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.196611501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/31.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.1282074975 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 874565922 ps |
| CPU time | 36.57 seconds |
| Started | Sep 10 06:17:48 AM UTC 24 |
| Finished | Sep 10 06:18:26 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282074975 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1282074975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/31.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.1510852942 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 201259284 ps |
| CPU time | 9.06 seconds |
| Started | Sep 10 06:17:09 AM UTC 24 |
| Finished | Sep 10 06:17:19 AM UTC 24 |
| Peak memory | 593916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510852942 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.1510852942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/31.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.423291156 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 8027453893 ps |
| CPU time | 131.46 seconds |
| Started | Sep 10 06:17:19 AM UTC 24 |
| Finished | Sep 10 06:19:33 AM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423291156 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.423291156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/31.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.2441595848 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 5323886785 ps |
| CPU time | 76.24 seconds |
| Started | Sep 10 06:17:31 AM UTC 24 |
| Finished | Sep 10 06:18:49 AM UTC 24 |
| Peak memory | 593724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441595848 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2441595848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.290245721 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 52312036 ps |
| CPU time | 9.41 seconds |
| Started | Sep 10 06:17:17 AM UTC 24 |
| Finished | Sep 10 06:17:28 AM UTC 24 |
| Peak memory | 593656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290245721 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.290245721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/31.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.1909272159 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 4093663246 ps |
| CPU time | 353.85 seconds |
| Started | Sep 10 06:18:14 AM UTC 24 |
| Finished | Sep 10 06:24:13 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909272159 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1909272159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/31.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.805529386 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 4142938126 ps |
| CPU time | 285.86 seconds |
| Started | Sep 10 06:18:48 AM UTC 24 |
| Finished | Sep 10 06:23:38 AM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805529386 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.805529386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/31.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.1078343842 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 445174547 ps |
| CPU time | 253.32 seconds |
| Started | Sep 10 06:18:36 AM UTC 24 |
| Finished | Sep 10 06:22:53 AM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078343842 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.1078343842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.3750230361 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 225355888 ps |
| CPU time | 65.76 seconds |
| Started | Sep 10 06:18:44 AM UTC 24 |
| Finished | Sep 10 06:19:52 AM UTC 24 |
| Peak memory | 595884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750230361 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.3750230361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.1873733141 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 450149761 ps |
| CPU time | 25.16 seconds |
| Started | Sep 10 06:17:55 AM UTC 24 |
| Finished | Sep 10 06:18:22 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873733141 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1873733141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/31.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.3418568905 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 2792839924 ps |
| CPU time | 137.96 seconds |
| Started | Sep 10 06:19:25 AM UTC 24 |
| Finished | Sep 10 06:21:46 AM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418568905 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.3418568905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/32.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.3158157546 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 14074069276 ps |
| CPU time | 197.76 seconds |
| Started | Sep 10 06:19:36 AM UTC 24 |
| Finished | Sep 10 06:22:56 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158157546 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.3158157546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.1173213479 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 169858091 ps |
| CPU time | 26.4 seconds |
| Started | Sep 10 06:20:06 AM UTC 24 |
| Finished | Sep 10 06:20:34 AM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173213479 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.1173213479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.1177404672 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 540516627 ps |
| CPU time | 46.08 seconds |
| Started | Sep 10 06:20:00 AM UTC 24 |
| Finished | Sep 10 06:20:47 AM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177404672 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1177404672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/32.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.154443801 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 482769882 ps |
| CPU time | 27.93 seconds |
| Started | Sep 10 06:19:11 AM UTC 24 |
| Finished | Sep 10 06:19:40 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154443801 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.154443801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/32.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.1952441681 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 107392904963 ps |
| CPU time | 981.4 seconds |
| Started | Sep 10 06:19:18 AM UTC 24 |
| Finished | Sep 10 06:35:50 AM UTC 24 |
| Peak memory | 596120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952441681 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1952441681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/32.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.2775161013 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 43355068712 ps |
| CPU time | 630.22 seconds |
| Started | Sep 10 06:19:22 AM UTC 24 |
| Finished | Sep 10 06:30:00 AM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775161013 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2775161013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/32.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.1020227381 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 221890245 ps |
| CPU time | 25.29 seconds |
| Started | Sep 10 06:19:15 AM UTC 24 |
| Finished | Sep 10 06:19:42 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020227381 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1020227381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/32.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.2638546432 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 337217207 ps |
| CPU time | 26.21 seconds |
| Started | Sep 10 06:19:54 AM UTC 24 |
| Finished | Sep 10 06:20:21 AM UTC 24 |
| Peak memory | 595792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638546432 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2638546432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/32.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.518977520 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 42361940 ps |
| CPU time | 5.9 seconds |
| Started | Sep 10 06:18:47 AM UTC 24 |
| Finished | Sep 10 06:18:54 AM UTC 24 |
| Peak memory | 592920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518977520 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.518977520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/32.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.3810192534 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 9337428769 ps |
| CPU time | 141.63 seconds |
| Started | Sep 10 06:18:50 AM UTC 24 |
| Finished | Sep 10 06:21:14 AM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810192534 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.3810192534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/32.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.2420939998 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 4765911380 ps |
| CPU time | 66.92 seconds |
| Started | Sep 10 06:19:01 AM UTC 24 |
| Finished | Sep 10 06:20:10 AM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420939998 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2420939998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.26166120 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 39114118 ps |
| CPU time | 9 seconds |
| Started | Sep 10 06:18:49 AM UTC 24 |
| Finished | Sep 10 06:18:59 AM UTC 24 |
| Peak memory | 593748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26166120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.26166120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/32.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.184619465 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 8141826665 ps |
| CPU time | 321.87 seconds |
| Started | Sep 10 06:20:08 AM UTC 24 |
| Finished | Sep 10 06:25:35 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184619465 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.184619465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/32.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.4140450833 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 1533968931 ps |
| CPU time | 63.67 seconds |
| Started | Sep 10 06:20:17 AM UTC 24 |
| Finished | Sep 10 06:21:23 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140450833 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.4140450833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/32.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.2299723777 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 503782989 ps |
| CPU time | 132.47 seconds |
| Started | Sep 10 06:20:17 AM UTC 24 |
| Finished | Sep 10 06:22:32 AM UTC 24 |
| Peak memory | 595964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299723777 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.2299723777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.541312365 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 15736851571 ps |
| CPU time | 666.05 seconds |
| Started | Sep 10 06:20:36 AM UTC 24 |
| Finished | Sep 10 06:31:51 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541312365 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.541312365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.2769426867 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 142014248 ps |
| CPU time | 17.51 seconds |
| Started | Sep 10 06:20:08 AM UTC 24 |
| Finished | Sep 10 06:20:27 AM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769426867 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2769426867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/32.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.3557065214 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 79908379 ps |
| CPU time | 11.45 seconds |
| Started | Sep 10 06:21:27 AM UTC 24 |
| Finished | Sep 10 06:21:39 AM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557065214 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3557065214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/33.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.3889588988 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 58098358230 ps |
| CPU time | 975.45 seconds |
| Started | Sep 10 06:21:38 AM UTC 24 |
| Finished | Sep 10 06:38:06 AM UTC 24 |
| Peak memory | 596004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889588988 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.3889588988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.3145900767 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 58017682 ps |
| CPU time | 12.17 seconds |
| Started | Sep 10 06:21:52 AM UTC 24 |
| Finished | Sep 10 06:22:05 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145900767 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3145900767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.2661494237 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 543162962 ps |
| CPU time | 48.97 seconds |
| Started | Sep 10 06:21:44 AM UTC 24 |
| Finished | Sep 10 06:22:34 AM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661494237 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.2661494237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/33.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.2942405354 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 79597009 ps |
| CPU time | 8.31 seconds |
| Started | Sep 10 06:21:01 AM UTC 24 |
| Finished | Sep 10 06:21:10 AM UTC 24 |
| Peak memory | 595788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942405354 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.2942405354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/33.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.171150478 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 29743212342 ps |
| CPU time | 311.1 seconds |
| Started | Sep 10 06:21:18 AM UTC 24 |
| Finished | Sep 10 06:26:34 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171150478 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.171150478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/33.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.941632655 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 2551610526 ps |
| CPU time | 44.42 seconds |
| Started | Sep 10 06:21:22 AM UTC 24 |
| Finished | Sep 10 06:22:08 AM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941632655 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.941632655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/33.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.686828055 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 283797505 ps |
| CPU time | 37.59 seconds |
| Started | Sep 10 06:21:16 AM UTC 24 |
| Finished | Sep 10 06:21:55 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686828055 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.686828055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/33.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.906524877 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 370759109 ps |
| CPU time | 40.04 seconds |
| Started | Sep 10 06:21:41 AM UTC 24 |
| Finished | Sep 10 06:22:22 AM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906524877 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.906524877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/33.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.3012021746 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 58992463 ps |
| CPU time | 9.69 seconds |
| Started | Sep 10 06:20:39 AM UTC 24 |
| Finished | Sep 10 06:20:50 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012021746 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.3012021746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/33.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.2771387933 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 5044405705 ps |
| CPU time | 86.46 seconds |
| Started | Sep 10 06:20:54 AM UTC 24 |
| Finished | Sep 10 06:22:23 AM UTC 24 |
| Peak memory | 593844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771387933 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2771387933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/33.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.2704992297 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 3156046493 ps |
| CPU time | 74.55 seconds |
| Started | Sep 10 06:20:56 AM UTC 24 |
| Finished | Sep 10 06:22:13 AM UTC 24 |
| Peak memory | 593844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704992297 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.2704992297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.2840162807 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 58151746 ps |
| CPU time | 9.87 seconds |
| Started | Sep 10 06:20:50 AM UTC 24 |
| Finished | Sep 10 06:21:01 AM UTC 24 |
| Peak memory | 593772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840162807 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.2840162807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/33.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.688241370 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 14800958961 ps |
| CPU time | 499.71 seconds |
| Started | Sep 10 06:21:48 AM UTC 24 |
| Finished | Sep 10 06:30:14 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688241370 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.688241370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/33.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.392737896 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 11165307157 ps |
| CPU time | 358.82 seconds |
| Started | Sep 10 06:22:03 AM UTC 24 |
| Finished | Sep 10 06:28:07 AM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392737896 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.392737896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/33.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.758160927 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 6499115744 ps |
| CPU time | 394.03 seconds |
| Started | Sep 10 06:22:05 AM UTC 24 |
| Finished | Sep 10 06:28:45 AM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758160927 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.758160927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.3014995800 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 1337098371 ps |
| CPU time | 78.01 seconds |
| Started | Sep 10 06:21:45 AM UTC 24 |
| Finished | Sep 10 06:23:05 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014995800 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3014995800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/33.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.585302631 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 2344731838 ps |
| CPU time | 85.86 seconds |
| Started | Sep 10 06:22:41 AM UTC 24 |
| Finished | Sep 10 06:24:09 AM UTC 24 |
| Peak memory | 596004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585302631 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.585302631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/34.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.3813343705 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 59782416008 ps |
| CPU time | 953.92 seconds |
| Started | Sep 10 06:22:40 AM UTC 24 |
| Finished | Sep 10 06:38:45 AM UTC 24 |
| Peak memory | 596160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813343705 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.3813343705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.3871772910 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 1450343416 ps |
| CPU time | 53.36 seconds |
| Started | Sep 10 06:22:47 AM UTC 24 |
| Finished | Sep 10 06:23:42 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871772910 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.3871772910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.3423035364 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 512045320 ps |
| CPU time | 48.76 seconds |
| Started | Sep 10 06:22:43 AM UTC 24 |
| Finished | Sep 10 06:23:33 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423035364 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3423035364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/34.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.3542850893 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 767030612 ps |
| CPU time | 35.73 seconds |
| Started | Sep 10 06:22:27 AM UTC 24 |
| Finished | Sep 10 06:23:04 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542850893 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.3542850893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/34.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.3423777085 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 102728391803 ps |
| CPU time | 1043.14 seconds |
| Started | Sep 10 06:22:35 AM UTC 24 |
| Finished | Sep 10 06:40:11 AM UTC 24 |
| Peak memory | 599024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423777085 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.3423777085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/34.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.2612429925 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 65590418546 ps |
| CPU time | 1028.48 seconds |
| Started | Sep 10 06:22:41 AM UTC 24 |
| Finished | Sep 10 06:40:01 AM UTC 24 |
| Peak memory | 596012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612429925 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2612429925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/34.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.3151281287 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 295695824 ps |
| CPU time | 26.8 seconds |
| Started | Sep 10 06:22:32 AM UTC 24 |
| Finished | Sep 10 06:23:00 AM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151281287 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3151281287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/34.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.4063920953 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 588040952 ps |
| CPU time | 21.99 seconds |
| Started | Sep 10 06:22:42 AM UTC 24 |
| Finished | Sep 10 06:23:05 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063920953 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.4063920953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/34.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.1225574521 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 237577024 ps |
| CPU time | 9.13 seconds |
| Started | Sep 10 06:22:04 AM UTC 24 |
| Finished | Sep 10 06:22:14 AM UTC 24 |
| Peak memory | 593780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225574521 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1225574521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/34.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.1422762398 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 8797830805 ps |
| CPU time | 120.07 seconds |
| Started | Sep 10 06:22:20 AM UTC 24 |
| Finished | Sep 10 06:24:22 AM UTC 24 |
| Peak memory | 593956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422762398 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1422762398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/34.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.3241852395 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 5244858344 ps |
| CPU time | 72.68 seconds |
| Started | Sep 10 06:22:27 AM UTC 24 |
| Finished | Sep 10 06:23:42 AM UTC 24 |
| Peak memory | 593844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241852395 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3241852395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.403588080 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 42901384 ps |
| CPU time | 6.37 seconds |
| Started | Sep 10 06:22:10 AM UTC 24 |
| Finished | Sep 10 06:22:18 AM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403588080 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.403588080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/34.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.2467725571 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 11849630701 ps |
| CPU time | 381.27 seconds |
| Started | Sep 10 06:22:54 AM UTC 24 |
| Finished | Sep 10 06:29:20 AM UTC 24 |
| Peak memory | 595940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467725571 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2467725571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/34.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.3940069605 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 6154966801 ps |
| CPU time | 260.16 seconds |
| Started | Sep 10 06:23:02 AM UTC 24 |
| Finished | Sep 10 06:27:26 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940069605 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3940069605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/34.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.3738765638 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 89407319 ps |
| CPU time | 30.81 seconds |
| Started | Sep 10 06:22:58 AM UTC 24 |
| Finished | Sep 10 06:23:30 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738765638 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.3738765638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.1663109456 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 3092532073 ps |
| CPU time | 411.46 seconds |
| Started | Sep 10 06:23:02 AM UTC 24 |
| Finished | Sep 10 06:29:59 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663109456 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.1663109456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.68243530 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 105931417 ps |
| CPU time | 19.39 seconds |
| Started | Sep 10 06:22:46 AM UTC 24 |
| Finished | Sep 10 06:23:07 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68243530 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.68243530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/34.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.199263277 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 2275357408 ps |
| CPU time | 94.15 seconds |
| Started | Sep 10 06:23:31 AM UTC 24 |
| Finished | Sep 10 06:25:07 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199263277 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.199263277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/35.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.3528366354 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 52786382419 ps |
| CPU time | 793.69 seconds |
| Started | Sep 10 06:23:31 AM UTC 24 |
| Finished | Sep 10 06:36:55 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528366354 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.3528366354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.521233483 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 131685662 ps |
| CPU time | 20.75 seconds |
| Started | Sep 10 06:23:44 AM UTC 24 |
| Finished | Sep 10 06:24:07 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521233483 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.521233483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.486683803 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 133589110 ps |
| CPU time | 10.48 seconds |
| Started | Sep 10 06:23:30 AM UTC 24 |
| Finished | Sep 10 06:23:43 AM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486683803 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.486683803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/35.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.3874779039 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 156412018 ps |
| CPU time | 20.31 seconds |
| Started | Sep 10 06:23:19 AM UTC 24 |
| Finished | Sep 10 06:23:40 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874779039 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.3874779039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/35.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.2947746424 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 44620657121 ps |
| CPU time | 475.58 seconds |
| Started | Sep 10 06:23:22 AM UTC 24 |
| Finished | Sep 10 06:31:24 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947746424 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2947746424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/35.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.3343405130 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 20965337614 ps |
| CPU time | 361.28 seconds |
| Started | Sep 10 06:23:27 AM UTC 24 |
| Finished | Sep 10 06:29:33 AM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343405130 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3343405130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/35.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.1693434223 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 352672357 ps |
| CPU time | 33.79 seconds |
| Started | Sep 10 06:23:22 AM UTC 24 |
| Finished | Sep 10 06:23:58 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693434223 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1693434223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/35.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.3685818373 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 498244998 ps |
| CPU time | 37.42 seconds |
| Started | Sep 10 06:23:32 AM UTC 24 |
| Finished | Sep 10 06:24:12 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685818373 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3685818373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/35.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.1849193614 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 206807269 ps |
| CPU time | 8.68 seconds |
| Started | Sep 10 06:23:06 AM UTC 24 |
| Finished | Sep 10 06:23:16 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849193614 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1849193614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/35.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.1538111262 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 9115945659 ps |
| CPU time | 100.96 seconds |
| Started | Sep 10 06:23:16 AM UTC 24 |
| Finished | Sep 10 06:24:59 AM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538111262 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1538111262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/35.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.167666658 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 5193560250 ps |
| CPU time | 92.71 seconds |
| Started | Sep 10 06:23:16 AM UTC 24 |
| Finished | Sep 10 06:24:50 AM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167666658 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.167666658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.2864966427 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 45334463 ps |
| CPU time | 8.78 seconds |
| Started | Sep 10 06:23:17 AM UTC 24 |
| Finished | Sep 10 06:23:27 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864966427 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.2864966427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/35.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.2447986245 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 4040711876 ps |
| CPU time | 138.76 seconds |
| Started | Sep 10 06:23:46 AM UTC 24 |
| Finished | Sep 10 06:26:08 AM UTC 24 |
| Peak memory | 596000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447986245 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2447986245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/35.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.3162328672 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 6305740562 ps |
| CPU time | 272.21 seconds |
| Started | Sep 10 06:23:54 AM UTC 24 |
| Finished | Sep 10 06:28:31 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162328672 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.3162328672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.2833359315 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 85906248 ps |
| CPU time | 15.6 seconds |
| Started | Sep 10 06:23:43 AM UTC 24 |
| Finished | Sep 10 06:24:00 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833359315 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2833359315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/35.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.2535997165 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 400631952 ps |
| CPU time | 23.09 seconds |
| Started | Sep 10 06:24:36 AM UTC 24 |
| Finished | Sep 10 06:25:00 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535997165 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.2535997165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/36.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.1708115302 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 256105005 ps |
| CPU time | 31.19 seconds |
| Started | Sep 10 06:24:49 AM UTC 24 |
| Finished | Sep 10 06:25:22 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708115302 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.1708115302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.1193391017 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 100881806 ps |
| CPU time | 15.34 seconds |
| Started | Sep 10 06:24:43 AM UTC 24 |
| Finished | Sep 10 06:24:59 AM UTC 24 |
| Peak memory | 595996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193391017 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1193391017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/36.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.504548142 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 561278869 ps |
| CPU time | 29.85 seconds |
| Started | Sep 10 06:24:10 AM UTC 24 |
| Finished | Sep 10 06:24:41 AM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504548142 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.504548142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/36.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.4249370911 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 53388018350 ps |
| CPU time | 492.92 seconds |
| Started | Sep 10 06:24:26 AM UTC 24 |
| Finished | Sep 10 06:32:45 AM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249370911 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.4249370911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/36.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.2562431557 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 39191138601 ps |
| CPU time | 638.78 seconds |
| Started | Sep 10 06:24:33 AM UTC 24 |
| Finished | Sep 10 06:35:20 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562431557 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2562431557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/36.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.2385698812 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 80454586 ps |
| CPU time | 13.54 seconds |
| Started | Sep 10 06:24:21 AM UTC 24 |
| Finished | Sep 10 06:24:35 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385698812 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2385698812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/36.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.1950407503 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 1847585274 ps |
| CPU time | 58.72 seconds |
| Started | Sep 10 06:24:37 AM UTC 24 |
| Finished | Sep 10 06:25:38 AM UTC 24 |
| Peak memory | 595820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950407503 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.1950407503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/36.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.2112880589 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 44906005 ps |
| CPU time | 9.4 seconds |
| Started | Sep 10 06:24:04 AM UTC 24 |
| Finished | Sep 10 06:24:14 AM UTC 24 |
| Peak memory | 593900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112880589 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2112880589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/36.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.2576128330 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 9311370552 ps |
| CPU time | 84.23 seconds |
| Started | Sep 10 06:24:08 AM UTC 24 |
| Finished | Sep 10 06:25:34 AM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576128330 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2576128330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/36.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.2646389581 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 5490829419 ps |
| CPU time | 68.2 seconds |
| Started | Sep 10 06:24:08 AM UTC 24 |
| Finished | Sep 10 06:25:18 AM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646389581 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2646389581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.1789217530 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 55497292 ps |
| CPU time | 6.96 seconds |
| Started | Sep 10 06:24:08 AM UTC 24 |
| Finished | Sep 10 06:24:16 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789217530 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1789217530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/36.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.1342230453 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 7178993346 ps |
| CPU time | 247.72 seconds |
| Started | Sep 10 06:24:50 AM UTC 24 |
| Finished | Sep 10 06:29:02 AM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342230453 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1342230453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/36.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.2251629737 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 8017940321 ps |
| CPU time | 287.8 seconds |
| Started | Sep 10 06:25:04 AM UTC 24 |
| Finished | Sep 10 06:29:56 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251629737 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2251629737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/36.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.1300615580 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 8433264838 ps |
| CPU time | 470.61 seconds |
| Started | Sep 10 06:24:52 AM UTC 24 |
| Finished | Sep 10 06:32:49 AM UTC 24 |
| Peak memory | 596004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300615580 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.1300615580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1540050482 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 290535361 ps |
| CPU time | 109.38 seconds |
| Started | Sep 10 06:25:09 AM UTC 24 |
| Finished | Sep 10 06:27:01 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540050482 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.1540050482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.3820649206 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 1088637045 ps |
| CPU time | 49.19 seconds |
| Started | Sep 10 06:24:43 AM UTC 24 |
| Finished | Sep 10 06:25:34 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820649206 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.3820649206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/36.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.2141289815 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 739450864 ps |
| CPU time | 63.16 seconds |
| Started | Sep 10 06:26:02 AM UTC 24 |
| Finished | Sep 10 06:27:06 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141289815 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.2141289815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/37.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.864279965 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 11060323006 ps |
| CPU time | 166.92 seconds |
| Started | Sep 10 06:25:55 AM UTC 24 |
| Finished | Sep 10 06:28:45 AM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864279965 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.864279965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.4193282254 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 79704638 ps |
| CPU time | 9.45 seconds |
| Started | Sep 10 06:26:34 AM UTC 24 |
| Finished | Sep 10 06:26:44 AM UTC 24 |
| Peak memory | 593784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193282254 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.4193282254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.2019499744 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 199326186 ps |
| CPU time | 23.34 seconds |
| Started | Sep 10 06:26:04 AM UTC 24 |
| Finished | Sep 10 06:26:29 AM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019499744 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2019499744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/37.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.2972418038 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 300662124 ps |
| CPU time | 31.25 seconds |
| Started | Sep 10 06:25:34 AM UTC 24 |
| Finished | Sep 10 06:26:06 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972418038 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.2972418038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/37.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.2877609778 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 49663459981 ps |
| CPU time | 615.83 seconds |
| Started | Sep 10 06:25:47 AM UTC 24 |
| Finished | Sep 10 06:36:11 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877609778 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2877609778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/37.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.1395579531 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 53213581549 ps |
| CPU time | 893.72 seconds |
| Started | Sep 10 06:25:57 AM UTC 24 |
| Finished | Sep 10 06:41:02 AM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395579531 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1395579531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/37.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.3774613443 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 553629959 ps |
| CPU time | 50.64 seconds |
| Started | Sep 10 06:25:45 AM UTC 24 |
| Finished | Sep 10 06:26:37 AM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774613443 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.3774613443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/37.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.3763948171 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 158711207 ps |
| CPU time | 8.65 seconds |
| Started | Sep 10 06:26:03 AM UTC 24 |
| Finished | Sep 10 06:26:13 AM UTC 24 |
| Peak memory | 593780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763948171 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3763948171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/37.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.782571652 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 50638758 ps |
| CPU time | 9.62 seconds |
| Started | Sep 10 06:25:18 AM UTC 24 |
| Finished | Sep 10 06:25:28 AM UTC 24 |
| Peak memory | 593784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782571652 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.782571652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/37.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.268117454 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 8554927927 ps |
| CPU time | 125.77 seconds |
| Started | Sep 10 06:25:27 AM UTC 24 |
| Finished | Sep 10 06:27:36 AM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268117454 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.268117454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/37.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.3052214484 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 5555120642 ps |
| CPU time | 127.62 seconds |
| Started | Sep 10 06:25:26 AM UTC 24 |
| Finished | Sep 10 06:27:36 AM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052214484 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3052214484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.1082916102 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 56456095 ps |
| CPU time | 9.98 seconds |
| Started | Sep 10 06:25:27 AM UTC 24 |
| Finished | Sep 10 06:25:38 AM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082916102 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.1082916102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/37.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.515641585 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 2651065801 ps |
| CPU time | 250.32 seconds |
| Started | Sep 10 06:26:35 AM UTC 24 |
| Finished | Sep 10 06:30:49 AM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515641585 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.515641585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/37.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.3271408680 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 8945468263 ps |
| CPU time | 303.8 seconds |
| Started | Sep 10 06:26:44 AM UTC 24 |
| Finished | Sep 10 06:31:52 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271408680 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3271408680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/37.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.3253611933 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 621705937 ps |
| CPU time | 169.26 seconds |
| Started | Sep 10 06:26:37 AM UTC 24 |
| Finished | Sep 10 06:29:29 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253611933 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.3253611933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.1604944649 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 17169223230 ps |
| CPU time | 581.82 seconds |
| Started | Sep 10 06:26:57 AM UTC 24 |
| Finished | Sep 10 06:36:46 AM UTC 24 |
| Peak memory | 596004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604944649 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.1604944649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.4254344815 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 1408371487 ps |
| CPU time | 73.34 seconds |
| Started | Sep 10 06:26:06 AM UTC 24 |
| Finished | Sep 10 06:27:21 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254344815 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.4254344815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/37.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.3771842660 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 2516024935 ps |
| CPU time | 113.92 seconds |
| Started | Sep 10 06:27:51 AM UTC 24 |
| Finished | Sep 10 06:29:47 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771842660 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.3771842660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/38.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2154335330 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 118095596885 ps |
| CPU time | 1642.55 seconds |
| Started | Sep 10 06:27:53 AM UTC 24 |
| Finished | Sep 10 06:55:34 AM UTC 24 |
| Peak memory | 598940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154335330 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.2154335330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.1409847426 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 322908165 ps |
| CPU time | 29.68 seconds |
| Started | Sep 10 06:28:10 AM UTC 24 |
| Finished | Sep 10 06:28:41 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409847426 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.1409847426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.3159422549 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 828747029 ps |
| CPU time | 30.14 seconds |
| Started | Sep 10 06:28:03 AM UTC 24 |
| Finished | Sep 10 06:28:35 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159422549 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3159422549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/38.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.1478938996 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 452853203 ps |
| CPU time | 19.58 seconds |
| Started | Sep 10 06:27:33 AM UTC 24 |
| Finished | Sep 10 06:27:53 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478938996 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.1478938996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/38.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.3778838809 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 106867383316 ps |
| CPU time | 1085.68 seconds |
| Started | Sep 10 06:27:43 AM UTC 24 |
| Finished | Sep 10 06:46:01 AM UTC 24 |
| Peak memory | 598868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778838809 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3778838809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/38.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.2645975877 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 47138902776 ps |
| CPU time | 682.62 seconds |
| Started | Sep 10 06:27:46 AM UTC 24 |
| Finished | Sep 10 06:39:17 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645975877 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2645975877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/38.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.215916848 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 599435479 ps |
| CPU time | 48.84 seconds |
| Started | Sep 10 06:27:37 AM UTC 24 |
| Finished | Sep 10 06:28:27 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215916848 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.215916848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/38.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.990358956 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 872721429 ps |
| CPU time | 30.64 seconds |
| Started | Sep 10 06:27:54 AM UTC 24 |
| Finished | Sep 10 06:28:26 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990358956 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.990358956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/38.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.750937675 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 177858089 ps |
| CPU time | 9.67 seconds |
| Started | Sep 10 06:27:02 AM UTC 24 |
| Finished | Sep 10 06:27:13 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750937675 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.750937675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/38.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.3453381972 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 6415254420 ps |
| CPU time | 63.16 seconds |
| Started | Sep 10 06:27:11 AM UTC 24 |
| Finished | Sep 10 06:28:16 AM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453381972 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3453381972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/38.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.3541248356 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 6869212757 ps |
| CPU time | 134.42 seconds |
| Started | Sep 10 06:27:27 AM UTC 24 |
| Finished | Sep 10 06:29:44 AM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541248356 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3541248356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.500479605 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 49460079 ps |
| CPU time | 9.52 seconds |
| Started | Sep 10 06:27:05 AM UTC 24 |
| Finished | Sep 10 06:27:15 AM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500479605 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.500479605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/38.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.3755535859 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 1006857249 ps |
| CPU time | 39.42 seconds |
| Started | Sep 10 06:28:22 AM UTC 24 |
| Finished | Sep 10 06:29:03 AM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755535859 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3755535859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/38.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.3056842179 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 8637515544 ps |
| CPU time | 314.37 seconds |
| Started | Sep 10 06:28:37 AM UTC 24 |
| Finished | Sep 10 06:33:56 AM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056842179 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3056842179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/38.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.2362887892 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 6214736873 ps |
| CPU time | 519.64 seconds |
| Started | Sep 10 06:28:35 AM UTC 24 |
| Finished | Sep 10 06:37:21 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362887892 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.2362887892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.1985974829 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 138336879 ps |
| CPU time | 38.75 seconds |
| Started | Sep 10 06:28:40 AM UTC 24 |
| Finished | Sep 10 06:29:20 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985974829 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.1985974829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.2230207696 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 329165903 ps |
| CPU time | 23.06 seconds |
| Started | Sep 10 06:28:05 AM UTC 24 |
| Finished | Sep 10 06:28:29 AM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230207696 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.2230207696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/38.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.1266901713 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 2815160326 ps |
| CPU time | 114.8 seconds |
| Started | Sep 10 06:29:10 AM UTC 24 |
| Finished | Sep 10 06:31:07 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266901713 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.1266901713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/39.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.375651026 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 105935779576 ps |
| CPU time | 1701.7 seconds |
| Started | Sep 10 06:29:12 AM UTC 24 |
| Finished | Sep 10 06:57:53 AM UTC 24 |
| Peak memory | 598940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375651026 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.375651026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.4016108414 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 160516645 ps |
| CPU time | 16.76 seconds |
| Started | Sep 10 06:29:30 AM UTC 24 |
| Finished | Sep 10 06:29:48 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016108414 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.4016108414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.2828271252 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 2194066053 ps |
| CPU time | 71.63 seconds |
| Started | Sep 10 06:29:27 AM UTC 24 |
| Finished | Sep 10 06:30:41 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828271252 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2828271252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/39.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.2677525165 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 1830046844 ps |
| CPU time | 63.11 seconds |
| Started | Sep 10 06:28:55 AM UTC 24 |
| Finished | Sep 10 06:30:00 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677525165 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.2677525165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/39.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.2422377993 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 106011994853 ps |
| CPU time | 993.92 seconds |
| Started | Sep 10 06:29:06 AM UTC 24 |
| Finished | Sep 10 06:45:52 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422377993 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2422377993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/39.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.4251877245 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 9882671308 ps |
| CPU time | 143.62 seconds |
| Started | Sep 10 06:29:08 AM UTC 24 |
| Finished | Sep 10 06:31:34 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251877245 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.4251877245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/39.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.349910625 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 242617925 ps |
| CPU time | 27.16 seconds |
| Started | Sep 10 06:29:00 AM UTC 24 |
| Finished | Sep 10 06:29:28 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349910625 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.349910625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/39.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.3800657796 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 1210520451 ps |
| CPU time | 43.36 seconds |
| Started | Sep 10 06:29:26 AM UTC 24 |
| Finished | Sep 10 06:30:11 AM UTC 24 |
| Peak memory | 595720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800657796 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3800657796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/39.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.2866514436 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 177537062 ps |
| CPU time | 12.21 seconds |
| Started | Sep 10 06:28:48 AM UTC 24 |
| Finished | Sep 10 06:29:01 AM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866514436 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2866514436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/39.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.2255564070 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 6803190785 ps |
| CPU time | 84.27 seconds |
| Started | Sep 10 06:28:55 AM UTC 24 |
| Finished | Sep 10 06:30:21 AM UTC 24 |
| Peak memory | 594100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255564070 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2255564070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/39.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.1376844765 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 5347326042 ps |
| CPU time | 77.71 seconds |
| Started | Sep 10 06:28:57 AM UTC 24 |
| Finished | Sep 10 06:30:17 AM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376844765 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1376844765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.3618067062 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 46994843 ps |
| CPU time | 9.54 seconds |
| Started | Sep 10 06:28:53 AM UTC 24 |
| Finished | Sep 10 06:29:04 AM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618067062 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.3618067062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/39.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.1492444521 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 6878890747 ps |
| CPU time | 254.22 seconds |
| Started | Sep 10 06:29:47 AM UTC 24 |
| Finished | Sep 10 06:34:06 AM UTC 24 |
| Peak memory | 596036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492444521 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1492444521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/39.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.1359133566 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 389010468 ps |
| CPU time | 28.55 seconds |
| Started | Sep 10 06:29:55 AM UTC 24 |
| Finished | Sep 10 06:30:25 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359133566 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.1359133566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/39.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.4040108927 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 7326070191 ps |
| CPU time | 834.08 seconds |
| Started | Sep 10 06:29:46 AM UTC 24 |
| Finished | Sep 10 06:43:51 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040108927 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.4040108927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.882716044 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 206069170 ps |
| CPU time | 83.31 seconds |
| Started | Sep 10 06:29:53 AM UTC 24 |
| Finished | Sep 10 06:31:19 AM UTC 24 |
| Peak memory | 595940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882716044 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.882716044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.3229757906 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 263561136 ps |
| CPU time | 42.47 seconds |
| Started | Sep 10 06:29:30 AM UTC 24 |
| Finished | Sep 10 06:30:14 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229757906 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3229757906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/39.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_aliasing.2899643940 |
| Short name | T2926 |
| Test name | |
| Test status | |
| Simulation time | 64076904286 ps |
| CPU time | 10302.9 seconds |
| Started | Sep 10 05:10:25 AM UTC 24 |
| Finished | Sep 10 08:04:02 AM UTC 24 |
| Peak memory | 665352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2899643940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_ csr_aliasing.2899643940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.1921458406 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 5175531484 ps |
| CPU time | 374.8 seconds |
| Started | Sep 10 05:10:21 AM UTC 24 |
| Finished | Sep 10 05:16:41 AM UTC 24 |
| Peak memory | 617156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1921458406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.chip_csr_bit_bash.1921458406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.425085379 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 6350816410 ps |
| CPU time | 296.39 seconds |
| Started | Sep 10 05:13:18 AM UTC 24 |
| Finished | Sep 10 05:18:19 AM UTC 24 |
| Peak memory | 680444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425085379 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_reset.425085379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.470660711 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 7706400615 ps |
| CPU time | 874.21 seconds |
| Started | Sep 10 05:13:21 AM UTC 24 |
| Finished | Sep 10 05:28:08 AM UTC 24 |
| Peak memory | 670112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=470660711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.470660711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.1105397642 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 3914869048 ps |
| CPU time | 375.78 seconds |
| Started | Sep 10 05:13:19 AM UTC 24 |
| Finished | Sep 10 05:19:40 AM UTC 24 |
| Peak memory | 616736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105397642 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.1105397642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.169412470 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 3450971837 ps |
| CPU time | 254.99 seconds |
| Started | Sep 10 05:10:38 AM UTC 24 |
| Finished | Sep 10 05:14:57 AM UTC 24 |
| Peak memory | 620960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169412470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.169412470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.2513134236 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 11131884364 ps |
| CPU time | 217.57 seconds |
| Started | Sep 10 05:11:59 AM UTC 24 |
| Finished | Sep 10 05:15:40 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513134236 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.2513134236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.4053555111 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 307606610 ps |
| CPU time | 19.25 seconds |
| Started | Sep 10 05:12:34 AM UTC 24 |
| Finished | Sep 10 05:12:55 AM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053555111 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.4053555111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.1167262551 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 375128081 ps |
| CPU time | 45.38 seconds |
| Started | Sep 10 05:12:07 AM UTC 24 |
| Finished | Sep 10 05:12:54 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167262551 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1167262551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.1302401124 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 412418601 ps |
| CPU time | 41.75 seconds |
| Started | Sep 10 05:11:29 AM UTC 24 |
| Finished | Sep 10 05:12:12 AM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302401124 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.1302401124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.109178818 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 102187899666 ps |
| CPU time | 989.76 seconds |
| Started | Sep 10 05:11:36 AM UTC 24 |
| Finished | Sep 10 05:28:17 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109178818 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.109178818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.1354950756 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 33590150666 ps |
| CPU time | 638.91 seconds |
| Started | Sep 10 05:11:39 AM UTC 24 |
| Finished | Sep 10 05:22:26 AM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354950756 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1354950756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.735462810 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 223102792 ps |
| CPU time | 30.96 seconds |
| Started | Sep 10 05:11:35 AM UTC 24 |
| Finished | Sep 10 05:12:07 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735462810 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.735462810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.1407408816 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 480799918 ps |
| CPU time | 53.77 seconds |
| Started | Sep 10 05:12:03 AM UTC 24 |
| Finished | Sep 10 05:12:58 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407408816 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1407408816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.241048916 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 210634060 ps |
| CPU time | 13.55 seconds |
| Started | Sep 10 05:10:47 AM UTC 24 |
| Finished | Sep 10 05:11:01 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241048916 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.241048916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.1063619486 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 10393832948 ps |
| CPU time | 100.43 seconds |
| Started | Sep 10 05:11:05 AM UTC 24 |
| Finished | Sep 10 05:12:48 AM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063619486 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1063619486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.1100210386 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 5005741229 ps |
| CPU time | 88.2 seconds |
| Started | Sep 10 05:11:28 AM UTC 24 |
| Finished | Sep 10 05:12:58 AM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100210386 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1100210386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.2103597710 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 57206643 ps |
| CPU time | 10.55 seconds |
| Started | Sep 10 05:10:57 AM UTC 24 |
| Finished | Sep 10 05:11:09 AM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103597710 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2103597710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.2114628533 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 4828230843 ps |
| CPU time | 145.75 seconds |
| Started | Sep 10 05:13:10 AM UTC 24 |
| Finished | Sep 10 05:15:39 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114628533 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2114628533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.4222872647 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 2726499978 ps |
| CPU time | 425.82 seconds |
| Started | Sep 10 05:12:42 AM UTC 24 |
| Finished | Sep 10 05:19:54 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222872647 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.4222872647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.489100372 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 1403649347 ps |
| CPU time | 191.47 seconds |
| Started | Sep 10 05:13:20 AM UTC 24 |
| Finished | Sep 10 05:16:35 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489100372 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.489100372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.752989942 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 82092412 ps |
| CPU time | 18.16 seconds |
| Started | Sep 10 05:12:35 AM UTC 24 |
| Finished | Sep 10 05:12:54 AM UTC 24 |
| Peak memory | 596096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752989942 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.752989942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.1461383739 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 2665515965 ps |
| CPU time | 113.55 seconds |
| Started | Sep 10 06:30:24 AM UTC 24 |
| Finished | Sep 10 06:32:20 AM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461383739 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.1461383739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/40.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.1654574030 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 91832995525 ps |
| CPU time | 1408.49 seconds |
| Started | Sep 10 06:30:24 AM UTC 24 |
| Finished | Sep 10 06:54:08 AM UTC 24 |
| Peak memory | 598584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654574030 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.1654574030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.798806002 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 758170464 ps |
| CPU time | 38.27 seconds |
| Started | Sep 10 06:30:27 AM UTC 24 |
| Finished | Sep 10 06:31:07 AM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798806002 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.798806002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.552608529 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 99483655 ps |
| CPU time | 14.05 seconds |
| Started | Sep 10 06:30:26 AM UTC 24 |
| Finished | Sep 10 06:30:41 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552608529 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.552608529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/40.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.2804781338 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 582158858 ps |
| CPU time | 65.54 seconds |
| Started | Sep 10 06:30:13 AM UTC 24 |
| Finished | Sep 10 06:31:21 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804781338 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.2804781338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/40.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.3295579990 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 99221888520 ps |
| CPU time | 996.66 seconds |
| Started | Sep 10 06:30:17 AM UTC 24 |
| Finished | Sep 10 06:47:05 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295579990 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3295579990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/40.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.1411500409 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 29886562704 ps |
| CPU time | 424.16 seconds |
| Started | Sep 10 06:30:27 AM UTC 24 |
| Finished | Sep 10 06:37:37 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411500409 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1411500409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/40.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.1941567833 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 81218875 ps |
| CPU time | 10.75 seconds |
| Started | Sep 10 06:30:11 AM UTC 24 |
| Finished | Sep 10 06:30:23 AM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941567833 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1941567833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/40.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.1568365437 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 1121335998 ps |
| CPU time | 44.16 seconds |
| Started | Sep 10 06:30:26 AM UTC 24 |
| Finished | Sep 10 06:31:12 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568365437 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1568365437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/40.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.3335523868 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 192492629 ps |
| CPU time | 11.26 seconds |
| Started | Sep 10 06:29:53 AM UTC 24 |
| Finished | Sep 10 06:30:06 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335523868 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3335523868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/40.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.3432912166 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 7847600653 ps |
| CPU time | 106.15 seconds |
| Started | Sep 10 06:30:00 AM UTC 24 |
| Finished | Sep 10 06:31:48 AM UTC 24 |
| Peak memory | 593804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432912166 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.3432912166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/40.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.58609920 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 6090980823 ps |
| CPU time | 114.66 seconds |
| Started | Sep 10 06:30:10 AM UTC 24 |
| Finished | Sep 10 06:32:07 AM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58609920 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.58609920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.691177301 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 43790745 ps |
| CPU time | 9.05 seconds |
| Started | Sep 10 06:29:53 AM UTC 24 |
| Finished | Sep 10 06:30:03 AM UTC 24 |
| Peak memory | 593656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691177301 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.691177301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/40.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.2306495777 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 17353981943 ps |
| CPU time | 562.58 seconds |
| Started | Sep 10 06:30:33 AM UTC 24 |
| Finished | Sep 10 06:40:03 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306495777 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2306495777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/40.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.1953810422 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 7084435687 ps |
| CPU time | 271.68 seconds |
| Started | Sep 10 06:30:40 AM UTC 24 |
| Finished | Sep 10 06:35:16 AM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953810422 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1953810422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/40.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.2927521429 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 494418482 ps |
| CPU time | 190.32 seconds |
| Started | Sep 10 06:30:36 AM UTC 24 |
| Finished | Sep 10 06:33:49 AM UTC 24 |
| Peak memory | 596068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927521429 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.2927521429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3078094684 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 7169278306 ps |
| CPU time | 418.56 seconds |
| Started | Sep 10 06:30:39 AM UTC 24 |
| Finished | Sep 10 06:37:43 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078094684 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.3078094684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.2136241090 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 997286030 ps |
| CPU time | 46.81 seconds |
| Started | Sep 10 06:30:28 AM UTC 24 |
| Finished | Sep 10 06:31:17 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136241090 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2136241090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/40.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.3146670530 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 710895541 ps |
| CPU time | 34.48 seconds |
| Started | Sep 10 06:31:32 AM UTC 24 |
| Finished | Sep 10 06:32:08 AM UTC 24 |
| Peak memory | 596044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146670530 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.3146670530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/41.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.1564166527 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 70660302240 ps |
| CPU time | 1061.22 seconds |
| Started | Sep 10 06:31:35 AM UTC 24 |
| Finished | Sep 10 06:49:28 AM UTC 24 |
| Peak memory | 596160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564166527 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.1564166527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.815437377 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 277839993 ps |
| CPU time | 33.94 seconds |
| Started | Sep 10 06:31:46 AM UTC 24 |
| Finished | Sep 10 06:32:21 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815437377 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.815437377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.4045305600 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 400367422 ps |
| CPU time | 38.02 seconds |
| Started | Sep 10 06:31:41 AM UTC 24 |
| Finished | Sep 10 06:32:20 AM UTC 24 |
| Peak memory | 595720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045305600 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.4045305600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/41.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.2021107112 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 155195841 ps |
| CPU time | 10.09 seconds |
| Started | Sep 10 06:31:05 AM UTC 24 |
| Finished | Sep 10 06:31:16 AM UTC 24 |
| Peak memory | 593668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021107112 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.2021107112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/41.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.1538220046 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 91196359922 ps |
| CPU time | 933.75 seconds |
| Started | Sep 10 06:31:21 AM UTC 24 |
| Finished | Sep 10 06:47:06 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538220046 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1538220046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/41.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.4008272692 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 18924763050 ps |
| CPU time | 292 seconds |
| Started | Sep 10 06:31:26 AM UTC 24 |
| Finished | Sep 10 06:36:22 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008272692 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.4008272692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/41.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.1971658651 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 190858980 ps |
| CPU time | 19.91 seconds |
| Started | Sep 10 06:31:16 AM UTC 24 |
| Finished | Sep 10 06:31:37 AM UTC 24 |
| Peak memory | 595788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971658651 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1971658651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/41.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.3531705207 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 2061665337 ps |
| CPU time | 63.62 seconds |
| Started | Sep 10 06:31:34 AM UTC 24 |
| Finished | Sep 10 06:32:39 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531705207 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3531705207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/41.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.3845559053 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 209159733 ps |
| CPU time | 12.58 seconds |
| Started | Sep 10 06:30:46 AM UTC 24 |
| Finished | Sep 10 06:30:59 AM UTC 24 |
| Peak memory | 593788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845559053 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3845559053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/41.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.3260353428 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 8553499541 ps |
| CPU time | 83.72 seconds |
| Started | Sep 10 06:30:49 AM UTC 24 |
| Finished | Sep 10 06:32:14 AM UTC 24 |
| Peak memory | 593908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260353428 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3260353428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/41.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.2919186815 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 4018939288 ps |
| CPU time | 93.44 seconds |
| Started | Sep 10 06:31:04 AM UTC 24 |
| Finished | Sep 10 06:32:40 AM UTC 24 |
| Peak memory | 593988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919186815 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2919186815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.1421654815 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 49858482 ps |
| CPU time | 7.06 seconds |
| Started | Sep 10 06:30:45 AM UTC 24 |
| Finished | Sep 10 06:30:53 AM UTC 24 |
| Peak memory | 593860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421654815 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.1421654815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/41.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.907167548 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 2643753056 ps |
| CPU time | 111.45 seconds |
| Started | Sep 10 06:31:48 AM UTC 24 |
| Finished | Sep 10 06:33:41 AM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907167548 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.907167548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/41.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.2368011540 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 1797361885 ps |
| CPU time | 147.89 seconds |
| Started | Sep 10 06:32:01 AM UTC 24 |
| Finished | Sep 10 06:34:31 AM UTC 24 |
| Peak memory | 596084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368011540 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2368011540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/41.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.4156455510 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 198440077 ps |
| CPU time | 102.41 seconds |
| Started | Sep 10 06:31:50 AM UTC 24 |
| Finished | Sep 10 06:33:35 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156455510 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.4156455510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.1781645037 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 2397438351 ps |
| CPU time | 327.16 seconds |
| Started | Sep 10 06:32:02 AM UTC 24 |
| Finished | Sep 10 06:37:34 AM UTC 24 |
| Peak memory | 596004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781645037 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.1781645037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.2545115163 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 312968631 ps |
| CPU time | 19.82 seconds |
| Started | Sep 10 06:31:43 AM UTC 24 |
| Finished | Sep 10 06:32:04 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545115163 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2545115163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/41.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.2772913351 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 1044460060 ps |
| CPU time | 51.86 seconds |
| Started | Sep 10 06:32:44 AM UTC 24 |
| Finished | Sep 10 06:33:37 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772913351 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2772913351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/42.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.4244297924 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 18412419328 ps |
| CPU time | 386.84 seconds |
| Started | Sep 10 06:32:48 AM UTC 24 |
| Finished | Sep 10 06:39:20 AM UTC 24 |
| Peak memory | 596156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244297924 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.4244297924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.2670064460 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 1073335507 ps |
| CPU time | 51.64 seconds |
| Started | Sep 10 06:33:05 AM UTC 24 |
| Finished | Sep 10 06:33:58 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670064460 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2670064460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.3624035748 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 376948947 ps |
| CPU time | 42.19 seconds |
| Started | Sep 10 06:32:55 AM UTC 24 |
| Finished | Sep 10 06:33:38 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624035748 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3624035748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/42.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.897323766 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 389615897 ps |
| CPU time | 33.11 seconds |
| Started | Sep 10 06:32:32 AM UTC 24 |
| Finished | Sep 10 06:33:07 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897323766 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.897323766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/42.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.1310432320 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 114621981117 ps |
| CPU time | 1079.12 seconds |
| Started | Sep 10 06:32:37 AM UTC 24 |
| Finished | Sep 10 06:50:48 AM UTC 24 |
| Peak memory | 596164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310432320 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1310432320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/42.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.2597338494 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 52823662371 ps |
| CPU time | 774.99 seconds |
| Started | Sep 10 06:32:40 AM UTC 24 |
| Finished | Sep 10 06:45:45 AM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597338494 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2597338494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/42.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.138072727 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 570852726 ps |
| CPU time | 57.03 seconds |
| Started | Sep 10 06:32:34 AM UTC 24 |
| Finished | Sep 10 06:33:33 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138072727 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.138072727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/42.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.2965686097 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 373487020 ps |
| CPU time | 31.36 seconds |
| Started | Sep 10 06:32:48 AM UTC 24 |
| Finished | Sep 10 06:33:20 AM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965686097 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2965686097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/42.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.3601663457 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 224499934 ps |
| CPU time | 13.37 seconds |
| Started | Sep 10 06:32:13 AM UTC 24 |
| Finished | Sep 10 06:32:27 AM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601663457 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3601663457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/42.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.410552861 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 9856554065 ps |
| CPU time | 119.81 seconds |
| Started | Sep 10 06:32:19 AM UTC 24 |
| Finished | Sep 10 06:34:21 AM UTC 24 |
| Peak memory | 593908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410552861 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.410552861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/42.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.1054919622 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 5431752669 ps |
| CPU time | 122.6 seconds |
| Started | Sep 10 06:32:31 AM UTC 24 |
| Finished | Sep 10 06:34:36 AM UTC 24 |
| Peak memory | 593984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054919622 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1054919622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.1743756547 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 46458228 ps |
| CPU time | 8.96 seconds |
| Started | Sep 10 06:32:17 AM UTC 24 |
| Finished | Sep 10 06:32:28 AM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743756547 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.1743756547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/42.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.1133526439 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 38913478 ps |
| CPU time | 9.73 seconds |
| Started | Sep 10 06:33:14 AM UTC 24 |
| Finished | Sep 10 06:33:25 AM UTC 24 |
| Peak memory | 593900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133526439 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.1133526439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/42.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.4036068143 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 469119446 ps |
| CPU time | 237.47 seconds |
| Started | Sep 10 06:33:12 AM UTC 24 |
| Finished | Sep 10 06:37:13 AM UTC 24 |
| Peak memory | 595720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036068143 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.4036068143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.426715635 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 6479831343 ps |
| CPU time | 693.98 seconds |
| Started | Sep 10 06:33:16 AM UTC 24 |
| Finished | Sep 10 06:45:00 AM UTC 24 |
| Peak memory | 596204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426715635 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.426715635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.3031882256 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 1063984675 ps |
| CPU time | 52.53 seconds |
| Started | Sep 10 06:32:54 AM UTC 24 |
| Finished | Sep 10 06:33:48 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031882256 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3031882256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/42.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.2278037966 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 420407545 ps |
| CPU time | 43.22 seconds |
| Started | Sep 10 06:34:11 AM UTC 24 |
| Finished | Sep 10 06:34:55 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278037966 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.2278037966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/43.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.2169183842 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 145289376535 ps |
| CPU time | 2222.45 seconds |
| Started | Sep 10 06:34:15 AM UTC 24 |
| Finished | Sep 10 07:11:43 AM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169183842 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.2169183842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.3942042992 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 489145772 ps |
| CPU time | 23.34 seconds |
| Started | Sep 10 06:34:25 AM UTC 24 |
| Finished | Sep 10 06:34:50 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942042992 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.3942042992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.1962366832 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 2108109492 ps |
| CPU time | 81.18 seconds |
| Started | Sep 10 06:34:24 AM UTC 24 |
| Finished | Sep 10 06:35:47 AM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962366832 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1962366832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/43.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.3187272015 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 1500160004 ps |
| CPU time | 52.82 seconds |
| Started | Sep 10 06:34:01 AM UTC 24 |
| Finished | Sep 10 06:34:56 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187272015 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.3187272015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/43.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.2473499432 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 99506365381 ps |
| CPU time | 1046.79 seconds |
| Started | Sep 10 06:34:06 AM UTC 24 |
| Finished | Sep 10 06:51:46 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473499432 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2473499432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/43.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.1461597918 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 18935528302 ps |
| CPU time | 246.17 seconds |
| Started | Sep 10 06:34:06 AM UTC 24 |
| Finished | Sep 10 06:38:16 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461597918 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1461597918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/43.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.3842937726 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 306192576 ps |
| CPU time | 27.13 seconds |
| Started | Sep 10 06:34:04 AM UTC 24 |
| Finished | Sep 10 06:34:33 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842937726 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.3842937726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/43.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.2331034105 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 2518664050 ps |
| CPU time | 63.37 seconds |
| Started | Sep 10 06:34:14 AM UTC 24 |
| Finished | Sep 10 06:35:19 AM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331034105 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2331034105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/43.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.3569005757 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 46503431 ps |
| CPU time | 8.64 seconds |
| Started | Sep 10 06:33:33 AM UTC 24 |
| Finished | Sep 10 06:33:43 AM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569005757 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3569005757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/43.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.2156372115 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 9519764447 ps |
| CPU time | 104.18 seconds |
| Started | Sep 10 06:33:53 AM UTC 24 |
| Finished | Sep 10 06:35:39 AM UTC 24 |
| Peak memory | 593720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156372115 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2156372115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/43.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.524964377 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 5963424457 ps |
| CPU time | 79.82 seconds |
| Started | Sep 10 06:33:59 AM UTC 24 |
| Finished | Sep 10 06:35:20 AM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524964377 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.524964377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.815700572 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 50068036 ps |
| CPU time | 8.63 seconds |
| Started | Sep 10 06:33:47 AM UTC 24 |
| Finished | Sep 10 06:33:57 AM UTC 24 |
| Peak memory | 593656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815700572 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.815700572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/43.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.2027849224 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 10450480512 ps |
| CPU time | 375.02 seconds |
| Started | Sep 10 06:34:33 AM UTC 24 |
| Finished | Sep 10 06:40:54 AM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027849224 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2027849224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/43.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.2873943953 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 2645605050 ps |
| CPU time | 228.12 seconds |
| Started | Sep 10 06:34:59 AM UTC 24 |
| Finished | Sep 10 06:38:50 AM UTC 24 |
| Peak memory | 595984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873943953 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2873943953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/43.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.2672267022 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 190936624 ps |
| CPU time | 122.86 seconds |
| Started | Sep 10 06:34:48 AM UTC 24 |
| Finished | Sep 10 06:36:53 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672267022 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.2672267022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.1217330218 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 5827987325 ps |
| CPU time | 545.12 seconds |
| Started | Sep 10 06:34:58 AM UTC 24 |
| Finished | Sep 10 06:44:11 AM UTC 24 |
| Peak memory | 599872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217330218 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.1217330218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.3866585899 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 572500835 ps |
| CPU time | 33.94 seconds |
| Started | Sep 10 06:34:23 AM UTC 24 |
| Finished | Sep 10 06:34:58 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866585899 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3866585899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/43.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.743124010 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 3040504065 ps |
| CPU time | 129.53 seconds |
| Started | Sep 10 06:35:48 AM UTC 24 |
| Finished | Sep 10 06:38:00 AM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743124010 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.743124010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/44.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.4028396291 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 10674524411 ps |
| CPU time | 192.7 seconds |
| Started | Sep 10 06:35:47 AM UTC 24 |
| Finished | Sep 10 06:39:03 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028396291 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.4028396291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.1496519449 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 318546806 ps |
| CPU time | 21.71 seconds |
| Started | Sep 10 06:36:08 AM UTC 24 |
| Finished | Sep 10 06:36:31 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496519449 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.1496519449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.3646229007 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 784768085 ps |
| CPU time | 37.38 seconds |
| Started | Sep 10 06:35:55 AM UTC 24 |
| Finished | Sep 10 06:36:34 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646229007 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3646229007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/44.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.3195534246 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 1663598191 ps |
| CPU time | 56.34 seconds |
| Started | Sep 10 06:35:23 AM UTC 24 |
| Finished | Sep 10 06:36:21 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195534246 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.3195534246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/44.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.1310095638 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 16910024677 ps |
| CPU time | 201.01 seconds |
| Started | Sep 10 06:35:42 AM UTC 24 |
| Finished | Sep 10 06:39:06 AM UTC 24 |
| Peak memory | 596108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310095638 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1310095638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/44.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.4259877707 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 37831994002 ps |
| CPU time | 659.59 seconds |
| Started | Sep 10 06:35:43 AM UTC 24 |
| Finished | Sep 10 06:46:51 AM UTC 24 |
| Peak memory | 596136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259877707 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.4259877707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/44.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.2390692307 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 37588626 ps |
| CPU time | 9.11 seconds |
| Started | Sep 10 06:35:26 AM UTC 24 |
| Finished | Sep 10 06:35:36 AM UTC 24 |
| Peak memory | 593788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390692307 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.2390692307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/44.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.3892045298 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 1634404564 ps |
| CPU time | 64.98 seconds |
| Started | Sep 10 06:35:49 AM UTC 24 |
| Finished | Sep 10 06:36:56 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892045298 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3892045298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/44.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.2476424062 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 205295235 ps |
| CPU time | 12.56 seconds |
| Started | Sep 10 06:35:03 AM UTC 24 |
| Finished | Sep 10 06:35:17 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476424062 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2476424062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/44.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.3265147773 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 7353575289 ps |
| CPU time | 115.82 seconds |
| Started | Sep 10 06:35:18 AM UTC 24 |
| Finished | Sep 10 06:37:16 AM UTC 24 |
| Peak memory | 593760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265147773 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3265147773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/44.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.4085461036 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 5151832807 ps |
| CPU time | 105.34 seconds |
| Started | Sep 10 06:35:23 AM UTC 24 |
| Finished | Sep 10 06:37:10 AM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085461036 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.4085461036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.262012398 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 44638094 ps |
| CPU time | 8.61 seconds |
| Started | Sep 10 06:35:18 AM UTC 24 |
| Finished | Sep 10 06:35:28 AM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262012398 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.262012398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/44.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.1731112746 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 1213911998 ps |
| CPU time | 70.56 seconds |
| Started | Sep 10 06:36:15 AM UTC 24 |
| Finished | Sep 10 06:37:27 AM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731112746 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1731112746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/44.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.1633639292 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 2884553750 ps |
| CPU time | 212.62 seconds |
| Started | Sep 10 06:36:18 AM UTC 24 |
| Finished | Sep 10 06:39:54 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633639292 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1633639292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/44.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.642488512 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 5569195653 ps |
| CPU time | 481.65 seconds |
| Started | Sep 10 06:36:18 AM UTC 24 |
| Finished | Sep 10 06:44:26 AM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642488512 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.642488512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.2289126584 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 6073380882 ps |
| CPU time | 584.73 seconds |
| Started | Sep 10 06:36:39 AM UTC 24 |
| Finished | Sep 10 06:46:31 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289126584 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.2289126584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.727719553 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 333398028 ps |
| CPU time | 44.91 seconds |
| Started | Sep 10 06:36:04 AM UTC 24 |
| Finished | Sep 10 06:36:51 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727719553 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.727719553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/44.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.498926224 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 438271405 ps |
| CPU time | 40.38 seconds |
| Started | Sep 10 06:37:24 AM UTC 24 |
| Finished | Sep 10 06:38:06 AM UTC 24 |
| Peak memory | 596076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498926224 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.498926224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/45.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.2462147044 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 94928079938 ps |
| CPU time | 1375.02 seconds |
| Started | Sep 10 06:37:22 AM UTC 24 |
| Finished | Sep 10 07:00:33 AM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462147044 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.2462147044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.3232564586 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 200861638 ps |
| CPU time | 15.87 seconds |
| Started | Sep 10 06:37:38 AM UTC 24 |
| Finished | Sep 10 06:37:55 AM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232564586 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.3232564586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.1532670177 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 166633290 ps |
| CPU time | 16.84 seconds |
| Started | Sep 10 06:37:29 AM UTC 24 |
| Finished | Sep 10 06:37:48 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532670177 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1532670177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/45.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.3855989144 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 2125242232 ps |
| CPU time | 88.52 seconds |
| Started | Sep 10 06:37:00 AM UTC 24 |
| Finished | Sep 10 06:38:31 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855989144 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.3855989144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/45.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.3431263212 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 21112671243 ps |
| CPU time | 248.18 seconds |
| Started | Sep 10 06:37:17 AM UTC 24 |
| Finished | Sep 10 06:41:29 AM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431263212 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3431263212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/45.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.1284984262 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 5712810980 ps |
| CPU time | 96.81 seconds |
| Started | Sep 10 06:37:20 AM UTC 24 |
| Finished | Sep 10 06:38:59 AM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284984262 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1284984262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/45.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.2002995321 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 518544721 ps |
| CPU time | 59.55 seconds |
| Started | Sep 10 06:37:14 AM UTC 24 |
| Finished | Sep 10 06:38:15 AM UTC 24 |
| Peak memory | 596084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002995321 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2002995321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/45.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.1677292013 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 2673191041 ps |
| CPU time | 82.34 seconds |
| Started | Sep 10 06:37:27 AM UTC 24 |
| Finished | Sep 10 06:38:52 AM UTC 24 |
| Peak memory | 596032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677292013 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1677292013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/45.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.3691145928 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 42114908 ps |
| CPU time | 8.42 seconds |
| Started | Sep 10 06:36:50 AM UTC 24 |
| Finished | Sep 10 06:36:59 AM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691145928 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3691145928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/45.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.904333224 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 11312171732 ps |
| CPU time | 93.03 seconds |
| Started | Sep 10 06:36:53 AM UTC 24 |
| Finished | Sep 10 06:38:28 AM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904333224 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.904333224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/45.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.1196903097 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 4409818126 ps |
| CPU time | 81.86 seconds |
| Started | Sep 10 06:36:57 AM UTC 24 |
| Finished | Sep 10 06:38:21 AM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196903097 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1196903097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.873439134 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 51163487 ps |
| CPU time | 9.67 seconds |
| Started | Sep 10 06:36:50 AM UTC 24 |
| Finished | Sep 10 06:37:01 AM UTC 24 |
| Peak memory | 594004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873439134 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.873439134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/45.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.3236625028 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 2902860026 ps |
| CPU time | 243.38 seconds |
| Started | Sep 10 06:37:40 AM UTC 24 |
| Finished | Sep 10 06:41:47 AM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236625028 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3236625028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/45.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.4245881846 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 9532148975 ps |
| CPU time | 299.72 seconds |
| Started | Sep 10 06:37:53 AM UTC 24 |
| Finished | Sep 10 06:42:58 AM UTC 24 |
| Peak memory | 596000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245881846 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.4245881846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/45.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.604107763 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 1587694018 ps |
| CPU time | 130.98 seconds |
| Started | Sep 10 06:37:46 AM UTC 24 |
| Finished | Sep 10 06:40:00 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604107763 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.604107763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.2369106717 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 1016853162 ps |
| CPU time | 318.12 seconds |
| Started | Sep 10 06:38:02 AM UTC 24 |
| Finished | Sep 10 06:43:25 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369106717 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.2369106717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.3788276234 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 1378319543 ps |
| CPU time | 77.76 seconds |
| Started | Sep 10 06:37:36 AM UTC 24 |
| Finished | Sep 10 06:38:55 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788276234 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3788276234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/45.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.2919594288 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 257874427 ps |
| CPU time | 17.9 seconds |
| Started | Sep 10 06:38:42 AM UTC 24 |
| Finished | Sep 10 06:39:01 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919594288 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2919594288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/46.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.4002904508 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 2913359704 ps |
| CPU time | 45.69 seconds |
| Started | Sep 10 06:38:43 AM UTC 24 |
| Finished | Sep 10 06:39:30 AM UTC 24 |
| Peak memory | 593720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002904508 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.4002904508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.85017085 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 1402528354 ps |
| CPU time | 47.26 seconds |
| Started | Sep 10 06:38:55 AM UTC 24 |
| Finished | Sep 10 06:39:44 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85017085 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.85017085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.1527073142 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 2290157433 ps |
| CPU time | 62.28 seconds |
| Started | Sep 10 06:38:44 AM UTC 24 |
| Finished | Sep 10 06:39:48 AM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527073142 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1527073142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/46.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.2581289421 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 309551822 ps |
| CPU time | 38.28 seconds |
| Started | Sep 10 06:38:28 AM UTC 24 |
| Finished | Sep 10 06:39:07 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581289421 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.2581289421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/46.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.1191042200 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 99741179213 ps |
| CPU time | 1017.84 seconds |
| Started | Sep 10 06:38:32 AM UTC 24 |
| Finished | Sep 10 06:55:42 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191042200 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1191042200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/46.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.1807642464 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 47546472604 ps |
| CPU time | 710.87 seconds |
| Started | Sep 10 06:38:43 AM UTC 24 |
| Finished | Sep 10 06:50:43 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807642464 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1807642464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/46.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.584521280 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 35171199 ps |
| CPU time | 8.83 seconds |
| Started | Sep 10 06:38:32 AM UTC 24 |
| Finished | Sep 10 06:38:42 AM UTC 24 |
| Peak memory | 593660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584521280 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.584521280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/46.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.3727925568 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 364744848 ps |
| CPU time | 36.03 seconds |
| Started | Sep 10 06:38:45 AM UTC 24 |
| Finished | Sep 10 06:39:22 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727925568 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3727925568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/46.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.2032328570 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 174783713 ps |
| CPU time | 11.61 seconds |
| Started | Sep 10 06:38:03 AM UTC 24 |
| Finished | Sep 10 06:38:16 AM UTC 24 |
| Peak memory | 593636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032328570 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2032328570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/46.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.354327769 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 9317069209 ps |
| CPU time | 89.02 seconds |
| Started | Sep 10 06:38:12 AM UTC 24 |
| Finished | Sep 10 06:39:43 AM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354327769 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.354327769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/46.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.115409768 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 6002987638 ps |
| CPU time | 125.46 seconds |
| Started | Sep 10 06:38:21 AM UTC 24 |
| Finished | Sep 10 06:40:29 AM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115409768 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.115409768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.2544357074 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 47173073 ps |
| CPU time | 6.06 seconds |
| Started | Sep 10 06:38:09 AM UTC 24 |
| Finished | Sep 10 06:38:16 AM UTC 24 |
| Peak memory | 593784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544357074 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.2544357074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/46.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.4101642553 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 10958441033 ps |
| CPU time | 332.65 seconds |
| Started | Sep 10 06:38:57 AM UTC 24 |
| Finished | Sep 10 06:44:34 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101642553 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.4101642553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/46.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.2475006965 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 15718346331 ps |
| CPU time | 571.4 seconds |
| Started | Sep 10 06:39:10 AM UTC 24 |
| Finished | Sep 10 06:48:50 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475006965 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2475006965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/46.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.3418145727 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 316612056 ps |
| CPU time | 155.67 seconds |
| Started | Sep 10 06:39:09 AM UTC 24 |
| Finished | Sep 10 06:41:48 AM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418145727 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.3418145727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.3925126150 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 2043238764 ps |
| CPU time | 238.09 seconds |
| Started | Sep 10 06:39:14 AM UTC 24 |
| Finished | Sep 10 06:43:16 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925126150 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.3925126150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.580686504 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 915463765 ps |
| CPU time | 54.01 seconds |
| Started | Sep 10 06:38:50 AM UTC 24 |
| Finished | Sep 10 06:39:45 AM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580686504 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.580686504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/46.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.1141660141 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 464687685 ps |
| CPU time | 46.93 seconds |
| Started | Sep 10 06:39:45 AM UTC 24 |
| Finished | Sep 10 06:40:33 AM UTC 24 |
| Peak memory | 596124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141660141 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.1141660141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/47.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.760431069 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 114108500222 ps |
| CPU time | 1703.85 seconds |
| Started | Sep 10 06:39:48 AM UTC 24 |
| Finished | Sep 10 07:08:32 AM UTC 24 |
| Peak memory | 599180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760431069 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.760431069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.41739347 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 1309329308 ps |
| CPU time | 54.89 seconds |
| Started | Sep 10 06:39:58 AM UTC 24 |
| Finished | Sep 10 06:40:55 AM UTC 24 |
| Peak memory | 596052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41739347 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.41739347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.3286845559 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 412580726 ps |
| CPU time | 40.13 seconds |
| Started | Sep 10 06:39:51 AM UTC 24 |
| Finished | Sep 10 06:40:33 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286845559 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3286845559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/47.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.3132433482 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 593263877 ps |
| CPU time | 63.3 seconds |
| Started | Sep 10 06:39:30 AM UTC 24 |
| Finished | Sep 10 06:40:36 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132433482 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.3132433482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/47.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.2505354615 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 95123440393 ps |
| CPU time | 1099.05 seconds |
| Started | Sep 10 06:39:36 AM UTC 24 |
| Finished | Sep 10 06:58:08 AM UTC 24 |
| Peak memory | 595756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505354615 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.2505354615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/47.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.1870649246 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 59170552031 ps |
| CPU time | 961.46 seconds |
| Started | Sep 10 06:39:40 AM UTC 24 |
| Finished | Sep 10 06:55:53 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870649246 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1870649246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/47.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.4159760988 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 351912945 ps |
| CPU time | 37.73 seconds |
| Started | Sep 10 06:39:30 AM UTC 24 |
| Finished | Sep 10 06:40:10 AM UTC 24 |
| Peak memory | 595788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159760988 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.4159760988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/47.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.2831679704 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 1165170631 ps |
| CPU time | 46.8 seconds |
| Started | Sep 10 06:39:48 AM UTC 24 |
| Finished | Sep 10 06:40:36 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831679704 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2831679704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/47.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.1633876772 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 138570572 ps |
| CPU time | 9.92 seconds |
| Started | Sep 10 06:39:14 AM UTC 24 |
| Finished | Sep 10 06:39:25 AM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633876772 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1633876772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/47.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.2963520737 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 4501423374 ps |
| CPU time | 48.52 seconds |
| Started | Sep 10 06:39:24 AM UTC 24 |
| Finished | Sep 10 06:40:14 AM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963520737 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2963520737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/47.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1956057725 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 5057568092 ps |
| CPU time | 98.79 seconds |
| Started | Sep 10 06:39:28 AM UTC 24 |
| Finished | Sep 10 06:41:09 AM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956057725 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1956057725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.4114579438 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 46971250 ps |
| CPU time | 9.12 seconds |
| Started | Sep 10 06:39:22 AM UTC 24 |
| Finished | Sep 10 06:39:32 AM UTC 24 |
| Peak memory | 593724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114579438 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.4114579438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/47.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.23843804 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 14582604661 ps |
| CPU time | 545.9 seconds |
| Started | Sep 10 06:40:06 AM UTC 24 |
| Finished | Sep 10 06:49:19 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23843804 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.23843804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/47.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.1285053339 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 1598375852 ps |
| CPU time | 112.25 seconds |
| Started | Sep 10 06:40:11 AM UTC 24 |
| Finished | Sep 10 06:42:05 AM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285053339 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1285053339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/47.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.272753708 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 693133057 ps |
| CPU time | 255.56 seconds |
| Started | Sep 10 06:40:09 AM UTC 24 |
| Finished | Sep 10 06:44:28 AM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272753708 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.272753708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.2899716329 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 569797214 ps |
| CPU time | 116.01 seconds |
| Started | Sep 10 06:40:12 AM UTC 24 |
| Finished | Sep 10 06:42:10 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899716329 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.2899716329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.2998276271 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 1024698265 ps |
| CPU time | 44.86 seconds |
| Started | Sep 10 06:39:58 AM UTC 24 |
| Finished | Sep 10 06:40:44 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998276271 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2998276271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/47.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.688744120 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 81377593350 ps |
| CPU time | 1199.52 seconds |
| Started | Sep 10 06:40:57 AM UTC 24 |
| Finished | Sep 10 07:01:10 AM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688744120 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.688744120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.188203942 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 244947851 ps |
| CPU time | 30 seconds |
| Started | Sep 10 06:41:04 AM UTC 24 |
| Finished | Sep 10 06:41:35 AM UTC 24 |
| Peak memory | 595692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188203942 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.188203942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.3615252275 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 2084495523 ps |
| CPU time | 68.42 seconds |
| Started | Sep 10 06:41:00 AM UTC 24 |
| Finished | Sep 10 06:42:10 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615252275 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3615252275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/48.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.1477554853 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 457941627 ps |
| CPU time | 44.55 seconds |
| Started | Sep 10 06:40:37 AM UTC 24 |
| Finished | Sep 10 06:41:23 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477554853 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.1477554853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/48.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.38277725 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 53771452596 ps |
| CPU time | 463.26 seconds |
| Started | Sep 10 06:40:35 AM UTC 24 |
| Finished | Sep 10 06:48:24 AM UTC 24 |
| Peak memory | 596108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38277725 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.38277725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/48.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.1181797726 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 39366892115 ps |
| CPU time | 616.88 seconds |
| Started | Sep 10 06:40:40 AM UTC 24 |
| Finished | Sep 10 06:51:04 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181797726 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.1181797726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/48.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.3801308820 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 36110414 ps |
| CPU time | 8.75 seconds |
| Started | Sep 10 06:40:38 AM UTC 24 |
| Finished | Sep 10 06:40:47 AM UTC 24 |
| Peak memory | 593656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801308820 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.3801308820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/48.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.2439995057 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 506389413 ps |
| CPU time | 38.73 seconds |
| Started | Sep 10 06:40:57 AM UTC 24 |
| Finished | Sep 10 06:41:37 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439995057 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2439995057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/48.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.3040653729 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 48010526 ps |
| CPU time | 8.01 seconds |
| Started | Sep 10 06:40:19 AM UTC 24 |
| Finished | Sep 10 06:40:28 AM UTC 24 |
| Peak memory | 593636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040653729 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3040653729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/48.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.2060569528 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 9680504048 ps |
| CPU time | 101.1 seconds |
| Started | Sep 10 06:40:27 AM UTC 24 |
| Finished | Sep 10 06:42:11 AM UTC 24 |
| Peak memory | 593844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060569528 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2060569528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/48.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.1304661032 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 6044316694 ps |
| CPU time | 85.67 seconds |
| Started | Sep 10 06:40:27 AM UTC 24 |
| Finished | Sep 10 06:41:55 AM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304661032 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1304661032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.2880351958 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 48799435 ps |
| CPU time | 7.95 seconds |
| Started | Sep 10 06:40:25 AM UTC 24 |
| Finished | Sep 10 06:40:34 AM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880351958 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2880351958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/48.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.2760633259 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 5876190171 ps |
| CPU time | 203.59 seconds |
| Started | Sep 10 06:41:01 AM UTC 24 |
| Finished | Sep 10 06:44:28 AM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760633259 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2760633259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/48.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.3911464531 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 345966341 ps |
| CPU time | 23.69 seconds |
| Started | Sep 10 06:41:10 AM UTC 24 |
| Finished | Sep 10 06:41:35 AM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911464531 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3911464531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/48.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.2434283678 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 510815461 ps |
| CPU time | 233.41 seconds |
| Started | Sep 10 06:41:11 AM UTC 24 |
| Finished | Sep 10 06:45:08 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434283678 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.2434283678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.4240022537 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 1971388625 ps |
| CPU time | 243.4 seconds |
| Started | Sep 10 06:41:23 AM UTC 24 |
| Finished | Sep 10 06:45:30 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240022537 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.4240022537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.2642781941 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 1372525053 ps |
| CPU time | 63.78 seconds |
| Started | Sep 10 06:41:01 AM UTC 24 |
| Finished | Sep 10 06:42:07 AM UTC 24 |
| Peak memory | 595820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642781941 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2642781941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/48.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.3314103677 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 171398843 ps |
| CPU time | 15.89 seconds |
| Started | Sep 10 06:42:05 AM UTC 24 |
| Finished | Sep 10 06:42:22 AM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314103677 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.3314103677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/49.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.2955919509 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 141041747345 ps |
| CPU time | 2070.36 seconds |
| Started | Sep 10 06:42:02 AM UTC 24 |
| Finished | Sep 10 07:16:56 AM UTC 24 |
| Peak memory | 598932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955919509 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.2955919509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.99407830 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 1238645336 ps |
| CPU time | 57.56 seconds |
| Started | Sep 10 06:42:33 AM UTC 24 |
| Finished | Sep 10 06:43:32 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99407830 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.99407830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.2289077756 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 534759280 ps |
| CPU time | 45.57 seconds |
| Started | Sep 10 06:42:14 AM UTC 24 |
| Finished | Sep 10 06:43:02 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289077756 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2289077756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/49.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.1294585385 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 2293080578 ps |
| CPU time | 77.44 seconds |
| Started | Sep 10 06:41:52 AM UTC 24 |
| Finished | Sep 10 06:43:12 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294585385 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.1294585385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/49.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.351392 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 78186075907 ps |
| CPU time | 687.71 seconds |
| Started | Sep 10 06:41:58 AM UTC 24 |
| Finished | Sep 10 06:53:34 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351392 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.351392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/49.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.1386372791 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 12969283879 ps |
| CPU time | 211.76 seconds |
| Started | Sep 10 06:42:00 AM UTC 24 |
| Finished | Sep 10 06:45:35 AM UTC 24 |
| Peak memory | 595980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386372791 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1386372791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/49.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.657263038 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 150185411 ps |
| CPU time | 15.99 seconds |
| Started | Sep 10 06:41:57 AM UTC 24 |
| Finished | Sep 10 06:42:14 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657263038 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.657263038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/49.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.3679991560 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 125114743 ps |
| CPU time | 16.39 seconds |
| Started | Sep 10 06:42:13 AM UTC 24 |
| Finished | Sep 10 06:42:31 AM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679991560 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3679991560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/49.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.1742638682 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 44566431 ps |
| CPU time | 8.44 seconds |
| Started | Sep 10 06:41:23 AM UTC 24 |
| Finished | Sep 10 06:41:32 AM UTC 24 |
| Peak memory | 593636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742638682 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1742638682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/49.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.2834124643 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 8189547576 ps |
| CPU time | 95.96 seconds |
| Started | Sep 10 06:41:38 AM UTC 24 |
| Finished | Sep 10 06:43:16 AM UTC 24 |
| Peak memory | 594092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834124643 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2834124643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/49.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.384423639 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 4871551203 ps |
| CPU time | 107.3 seconds |
| Started | Sep 10 06:41:49 AM UTC 24 |
| Finished | Sep 10 06:43:39 AM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384423639 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.384423639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3652715297 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 48200872 ps |
| CPU time | 7.94 seconds |
| Started | Sep 10 06:41:28 AM UTC 24 |
| Finished | Sep 10 06:41:37 AM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652715297 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3652715297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/49.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.791218115 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 1922412864 ps |
| CPU time | 157.76 seconds |
| Started | Sep 10 06:42:32 AM UTC 24 |
| Finished | Sep 10 06:45:12 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791218115 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.791218115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/49.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.1094811190 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 4666554397 ps |
| CPU time | 199.05 seconds |
| Started | Sep 10 06:42:30 AM UTC 24 |
| Finished | Sep 10 06:45:52 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094811190 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1094811190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/49.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.2001117564 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 2923381017 ps |
| CPU time | 196.47 seconds |
| Started | Sep 10 06:42:36 AM UTC 24 |
| Finished | Sep 10 06:45:56 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001117564 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.2001117564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.3337475801 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 356793526 ps |
| CPU time | 24.06 seconds |
| Started | Sep 10 06:42:21 AM UTC 24 |
| Finished | Sep 10 06:42:46 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337475801 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3337475801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/49.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.2548584707 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 12141175828 ps |
| CPU time | 1085.89 seconds |
| Started | Sep 10 05:16:08 AM UTC 24 |
| Finished | Sep 10 05:34:28 AM UTC 24 |
| Peak memory | 655784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2548584707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 5.chip_csr_mem_rw_with_rand_reset.2548584707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.1519618538 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 5533818600 ps |
| CPU time | 735.95 seconds |
| Started | Sep 10 05:16:06 AM UTC 24 |
| Finished | Sep 10 05:28:32 AM UTC 24 |
| Peak memory | 616864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519618538 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.1519618538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.1483637859 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 30070191444 ps |
| CPU time | 3930.25 seconds |
| Started | Sep 10 05:13:22 AM UTC 24 |
| Finished | Sep 10 06:19:42 AM UTC 24 |
| Peak memory | 613820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1483637859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.chip_same_csr_outstanding.1483637859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.2204364427 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 4164236634 ps |
| CPU time | 384.3 seconds |
| Started | Sep 10 05:13:23 AM UTC 24 |
| Finished | Sep 10 05:19:54 AM UTC 24 |
| Peak memory | 620960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204364427 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.2204364427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.2630365380 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 1102729824 ps |
| CPU time | 42.13 seconds |
| Started | Sep 10 05:14:48 AM UTC 24 |
| Finished | Sep 10 05:15:32 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630365380 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.2630365380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.1343091511 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 336035495 ps |
| CPU time | 18.23 seconds |
| Started | Sep 10 05:15:45 AM UTC 24 |
| Finished | Sep 10 05:16:05 AM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343091511 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1343091511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.794635528 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 204658488 ps |
| CPU time | 23.58 seconds |
| Started | Sep 10 05:15:41 AM UTC 24 |
| Finished | Sep 10 05:16:05 AM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794635528 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.794635528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.3280162205 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 160239592 ps |
| CPU time | 13.78 seconds |
| Started | Sep 10 05:14:07 AM UTC 24 |
| Finished | Sep 10 05:14:22 AM UTC 24 |
| Peak memory | 593660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280162205 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.3280162205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.1128706518 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 59071615561 ps |
| CPU time | 598.3 seconds |
| Started | Sep 10 05:14:18 AM UTC 24 |
| Finished | Sep 10 05:24:23 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128706518 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1128706518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.2772825226 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 58402008249 ps |
| CPU time | 962.81 seconds |
| Started | Sep 10 05:14:49 AM UTC 24 |
| Finished | Sep 10 05:31:03 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772825226 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2772825226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.1325457769 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 533235920 ps |
| CPU time | 65.69 seconds |
| Started | Sep 10 05:14:05 AM UTC 24 |
| Finished | Sep 10 05:15:13 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325457769 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.1325457769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.1778495371 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1573910972 ps |
| CPU time | 45.5 seconds |
| Started | Sep 10 05:15:25 AM UTC 24 |
| Finished | Sep 10 05:16:12 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778495371 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.1778495371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.4273745345 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 53481159 ps |
| CPU time | 7.02 seconds |
| Started | Sep 10 05:13:19 AM UTC 24 |
| Finished | Sep 10 05:13:27 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273745345 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.4273745345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.1417513305 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 7868990700 ps |
| CPU time | 123.64 seconds |
| Started | Sep 10 05:13:37 AM UTC 24 |
| Finished | Sep 10 05:15:43 AM UTC 24 |
| Peak memory | 593844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417513305 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.1417513305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.869756535 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 6541885477 ps |
| CPU time | 141.12 seconds |
| Started | Sep 10 05:13:53 AM UTC 24 |
| Finished | Sep 10 05:16:17 AM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869756535 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.869756535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.1164316819 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 46956498 ps |
| CPU time | 9.48 seconds |
| Started | Sep 10 05:13:31 AM UTC 24 |
| Finished | Sep 10 05:13:42 AM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164316819 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.1164316819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.3114259680 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 1975469379 ps |
| CPU time | 73.01 seconds |
| Started | Sep 10 05:15:48 AM UTC 24 |
| Finished | Sep 10 05:17:03 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114259680 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3114259680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.3379190093 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 3966440627 ps |
| CPU time | 389.48 seconds |
| Started | Sep 10 05:16:00 AM UTC 24 |
| Finished | Sep 10 05:22:35 AM UTC 24 |
| Peak memory | 596036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379190093 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3379190093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.937459693 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 58429915 ps |
| CPU time | 59.06 seconds |
| Started | Sep 10 05:16:00 AM UTC 24 |
| Finished | Sep 10 05:17:00 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937459693 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.937459693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1253310952 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 2951447326 ps |
| CPU time | 333.63 seconds |
| Started | Sep 10 05:16:06 AM UTC 24 |
| Finished | Sep 10 05:21:44 AM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253310952 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.1253310952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.454145372 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 76485082 ps |
| CPU time | 17.82 seconds |
| Started | Sep 10 05:15:42 AM UTC 24 |
| Finished | Sep 10 05:16:01 AM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454145372 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.454145372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.1611099451 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 331970983 ps |
| CPU time | 38.22 seconds |
| Started | Sep 10 06:43:24 AM UTC 24 |
| Finished | Sep 10 06:44:03 AM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611099451 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device.1611099451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/50.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.2261455236 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 98206500197 ps |
| CPU time | 1497.2 seconds |
| Started | Sep 10 06:43:26 AM UTC 24 |
| Finished | Sep 10 07:08:41 AM UTC 24 |
| Peak memory | 596740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261455236 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device_slow_rsp.2261455236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.3221119078 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 74546160 ps |
| CPU time | 8.62 seconds |
| Started | Sep 10 06:43:51 AM UTC 24 |
| Finished | Sep 10 06:44:01 AM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221119078 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_addr.3221119078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.1745702931 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 2057567435 ps |
| CPU time | 79.76 seconds |
| Started | Sep 10 06:43:44 AM UTC 24 |
| Finished | Sep 10 06:45:05 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745702931 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.1745702931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/50.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.1634358260 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 2475739308 ps |
| CPU time | 86.91 seconds |
| Started | Sep 10 06:43:12 AM UTC 24 |
| Finished | Sep 10 06:44:41 AM UTC 24 |
| Peak memory | 596068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634358260 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.1634358260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/50.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.1562481392 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 85093151461 ps |
| CPU time | 822.28 seconds |
| Started | Sep 10 06:43:19 AM UTC 24 |
| Finished | Sep 10 06:57:10 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562481392 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.1562481392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/50.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.3308076808 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 23663121179 ps |
| CPU time | 416.59 seconds |
| Started | Sep 10 06:43:24 AM UTC 24 |
| Finished | Sep 10 06:50:26 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308076808 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.3308076808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/50.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.1631885740 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 135580232 ps |
| CPU time | 19.18 seconds |
| Started | Sep 10 06:43:14 AM UTC 24 |
| Finished | Sep 10 06:43:35 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631885740 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_delays.1631885740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/50.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.2968709118 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 284269594 ps |
| CPU time | 30.2 seconds |
| Started | Sep 10 06:43:38 AM UTC 24 |
| Finished | Sep 10 06:44:09 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968709118 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.2968709118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/50.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.3252024291 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 40381636 ps |
| CPU time | 6.36 seconds |
| Started | Sep 10 06:42:37 AM UTC 24 |
| Finished | Sep 10 06:42:44 AM UTC 24 |
| Peak memory | 593772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252024291 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.3252024291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/50.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.205714719 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 8953981077 ps |
| CPU time | 104.38 seconds |
| Started | Sep 10 06:42:50 AM UTC 24 |
| Finished | Sep 10 06:44:37 AM UTC 24 |
| Peak memory | 593776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205714719 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.205714719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/50.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.1798655148 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 3831941853 ps |
| CPU time | 54.54 seconds |
| Started | Sep 10 06:42:52 AM UTC 24 |
| Finished | Sep 10 06:43:48 AM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798655148 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.1798655148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.2230465900 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 50257580 ps |
| CPU time | 9.49 seconds |
| Started | Sep 10 06:42:41 AM UTC 24 |
| Finished | Sep 10 06:42:52 AM UTC 24 |
| Peak memory | 593784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230465900 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delays.2230465900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/50.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.1304729436 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 13616031981 ps |
| CPU time | 456.15 seconds |
| Started | Sep 10 06:44:00 AM UTC 24 |
| Finished | Sep 10 06:51:42 AM UTC 24 |
| Peak memory | 596128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304729436 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.1304729436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/50.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.1770663080 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 10818439600 ps |
| CPU time | 331.76 seconds |
| Started | Sep 10 06:44:04 AM UTC 24 |
| Finished | Sep 10 06:49:40 AM UTC 24 |
| Peak memory | 596192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770663080 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.1770663080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/50.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.2406801630 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 5890870758 ps |
| CPU time | 296.86 seconds |
| Started | Sep 10 06:44:01 AM UTC 24 |
| Finished | Sep 10 06:49:02 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406801630 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_rand_reset.2406801630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.2234728606 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 84316318 ps |
| CPU time | 34.34 seconds |
| Started | Sep 10 06:44:16 AM UTC 24 |
| Finished | Sep 10 06:44:51 AM UTC 24 |
| Peak memory | 595884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234728606 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_reset_error.2234728606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.3100124945 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 46550779 ps |
| CPU time | 8 seconds |
| Started | Sep 10 06:43:42 AM UTC 24 |
| Finished | Sep 10 06:43:51 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100124945 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.3100124945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/50.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.1193090744 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 1054778006 ps |
| CPU time | 51.47 seconds |
| Started | Sep 10 06:44:56 AM UTC 24 |
| Finished | Sep 10 06:45:50 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193090744 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device.1193090744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/51.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2807831851 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 134815303745 ps |
| CPU time | 1874.56 seconds |
| Started | Sep 10 06:44:58 AM UTC 24 |
| Finished | Sep 10 07:16:35 AM UTC 24 |
| Peak memory | 598936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807831851 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device_slow_rsp.2807831851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.743559628 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 258412827 ps |
| CPU time | 35.47 seconds |
| Started | Sep 10 06:45:10 AM UTC 24 |
| Finished | Sep 10 06:45:46 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743559628 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_addr.743559628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.110098566 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 868817325 ps |
| CPU time | 34.03 seconds |
| Started | Sep 10 06:45:01 AM UTC 24 |
| Finished | Sep 10 06:45:36 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110098566 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.110098566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/51.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.3963890896 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 393340946 ps |
| CPU time | 43.3 seconds |
| Started | Sep 10 06:44:37 AM UTC 24 |
| Finished | Sep 10 06:45:22 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963890896 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.3963890896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/51.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.3485534009 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 55730477347 ps |
| CPU time | 560.71 seconds |
| Started | Sep 10 06:44:54 AM UTC 24 |
| Finished | Sep 10 06:54:22 AM UTC 24 |
| Peak memory | 595884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485534009 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.3485534009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/51.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.214653232 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 40110769774 ps |
| CPU time | 656.46 seconds |
| Started | Sep 10 06:44:55 AM UTC 24 |
| Finished | Sep 10 06:55:59 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214653232 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.214653232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/51.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.4200450228 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 107872338 ps |
| CPU time | 14.82 seconds |
| Started | Sep 10 06:44:39 AM UTC 24 |
| Finished | Sep 10 06:44:55 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200450228 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_delays.4200450228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/51.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.2167516405 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 265016170 ps |
| CPU time | 20.99 seconds |
| Started | Sep 10 06:44:59 AM UTC 24 |
| Finished | Sep 10 06:45:21 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167516405 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.2167516405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/51.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.2828750273 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 194357686 ps |
| CPU time | 12.37 seconds |
| Started | Sep 10 06:44:19 AM UTC 24 |
| Finished | Sep 10 06:44:32 AM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828750273 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.2828750273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/51.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.3504073839 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 7851529906 ps |
| CPU time | 86.52 seconds |
| Started | Sep 10 06:44:29 AM UTC 24 |
| Finished | Sep 10 06:45:57 AM UTC 24 |
| Peak memory | 594088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504073839 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.3504073839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/51.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.3258677769 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 4801850419 ps |
| CPU time | 65.04 seconds |
| Started | Sep 10 06:44:31 AM UTC 24 |
| Finished | Sep 10 06:45:38 AM UTC 24 |
| Peak memory | 594072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258677769 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.3258677769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.190875080 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 58596069 ps |
| CPU time | 9.36 seconds |
| Started | Sep 10 06:44:20 AM UTC 24 |
| Finished | Sep 10 06:44:30 AM UTC 24 |
| Peak memory | 593772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190875080 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delays.190875080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/51.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.260131575 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 14523567173 ps |
| CPU time | 545.82 seconds |
| Started | Sep 10 06:45:20 AM UTC 24 |
| Finished | Sep 10 06:54:33 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260131575 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.260131575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/51.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.3287583254 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 1401443766 ps |
| CPU time | 97.39 seconds |
| Started | Sep 10 06:45:23 AM UTC 24 |
| Finished | Sep 10 06:47:03 AM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287583254 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.3287583254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/51.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.3512595951 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 7725409 ps |
| CPU time | 11.31 seconds |
| Started | Sep 10 06:45:20 AM UTC 24 |
| Finished | Sep 10 06:45:32 AM UTC 24 |
| Peak memory | 593700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512595951 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_rand_reset.3512595951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.4215359956 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 3583768684 ps |
| CPU time | 218.44 seconds |
| Started | Sep 10 06:45:33 AM UTC 24 |
| Finished | Sep 10 06:49:15 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215359956 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_reset_error.4215359956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.1717231937 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 159972096 ps |
| CPU time | 13.97 seconds |
| Started | Sep 10 06:45:05 AM UTC 24 |
| Finished | Sep 10 06:45:20 AM UTC 24 |
| Peak memory | 593720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717231937 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.1717231937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/51.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.1158568947 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 379789448 ps |
| CPU time | 17.83 seconds |
| Started | Sep 10 06:46:01 AM UTC 24 |
| Finished | Sep 10 06:46:20 AM UTC 24 |
| Peak memory | 596072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158568947 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device.1158568947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/52.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.2231895665 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 33882925607 ps |
| CPU time | 574.4 seconds |
| Started | Sep 10 06:46:05 AM UTC 24 |
| Finished | Sep 10 06:55:46 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231895665 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device_slow_rsp.2231895665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.4115145728 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 156052473 ps |
| CPU time | 25 seconds |
| Started | Sep 10 06:46:14 AM UTC 24 |
| Finished | Sep 10 06:46:40 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115145728 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_addr.4115145728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.444383909 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 687087762 ps |
| CPU time | 32.07 seconds |
| Started | Sep 10 06:46:13 AM UTC 24 |
| Finished | Sep 10 06:46:46 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444383909 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.444383909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/52.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.163280256 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 583066398 ps |
| CPU time | 61.41 seconds |
| Started | Sep 10 06:45:51 AM UTC 24 |
| Finished | Sep 10 06:46:54 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163280256 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.163280256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/52.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.2795224744 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 82790050124 ps |
| CPU time | 749.06 seconds |
| Started | Sep 10 06:45:55 AM UTC 24 |
| Finished | Sep 10 06:58:32 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795224744 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.2795224744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/52.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.3337956536 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 6949917644 ps |
| CPU time | 127.89 seconds |
| Started | Sep 10 06:46:03 AM UTC 24 |
| Finished | Sep 10 06:48:13 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337956536 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.3337956536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/52.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.1182962297 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 68019371 ps |
| CPU time | 11.69 seconds |
| Started | Sep 10 06:45:56 AM UTC 24 |
| Finished | Sep 10 06:46:09 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182962297 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_delays.1182962297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/52.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.42700477 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 74978501 ps |
| CPU time | 9.8 seconds |
| Started | Sep 10 06:46:09 AM UTC 24 |
| Finished | Sep 10 06:46:20 AM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42700477 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.42700477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/52.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.3978371661 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 232685476 ps |
| CPU time | 13.79 seconds |
| Started | Sep 10 06:45:35 AM UTC 24 |
| Finished | Sep 10 06:45:50 AM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978371661 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.3978371661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/52.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.2009194722 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 8308074484 ps |
| CPU time | 77.63 seconds |
| Started | Sep 10 06:45:46 AM UTC 24 |
| Finished | Sep 10 06:47:05 AM UTC 24 |
| Peak memory | 593904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009194722 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.2009194722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/52.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.2214622241 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 3978029921 ps |
| CPU time | 71.22 seconds |
| Started | Sep 10 06:45:49 AM UTC 24 |
| Finished | Sep 10 06:47:02 AM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214622241 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.2214622241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.881591711 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 53154373 ps |
| CPU time | 6.35 seconds |
| Started | Sep 10 06:45:38 AM UTC 24 |
| Finished | Sep 10 06:45:45 AM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881591711 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delays.881591711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/52.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.2633591179 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 17356967972 ps |
| CPU time | 567.7 seconds |
| Started | Sep 10 06:46:14 AM UTC 24 |
| Finished | Sep 10 06:55:49 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633591179 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.2633591179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/52.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.1985632691 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 554246017 ps |
| CPU time | 57.65 seconds |
| Started | Sep 10 06:46:15 AM UTC 24 |
| Finished | Sep 10 06:47:14 AM UTC 24 |
| Peak memory | 596124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985632691 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.1985632691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/52.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.2654955674 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 8556615357 ps |
| CPU time | 339.06 seconds |
| Started | Sep 10 06:46:14 AM UTC 24 |
| Finished | Sep 10 06:51:58 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654955674 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_rand_reset.2654955674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.3921051935 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 377517424 ps |
| CPU time | 100.78 seconds |
| Started | Sep 10 06:46:20 AM UTC 24 |
| Finished | Sep 10 06:48:03 AM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921051935 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_reset_error.3921051935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.4240537899 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 875054369 ps |
| CPU time | 48.98 seconds |
| Started | Sep 10 06:46:12 AM UTC 24 |
| Finished | Sep 10 06:47:02 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240537899 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.4240537899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/52.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.2800334418 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 3038784759 ps |
| CPU time | 127.38 seconds |
| Started | Sep 10 06:46:57 AM UTC 24 |
| Finished | Sep 10 06:49:07 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800334418 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device.2800334418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/53.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.3298704293 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 109668464794 ps |
| CPU time | 1540.3 seconds |
| Started | Sep 10 06:47:06 AM UTC 24 |
| Finished | Sep 10 07:13:03 AM UTC 24 |
| Peak memory | 596692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298704293 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device_slow_rsp.3298704293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.2493225585 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 780609964 ps |
| CPU time | 38.92 seconds |
| Started | Sep 10 06:47:28 AM UTC 24 |
| Finished | Sep 10 06:48:08 AM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493225585 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_addr.2493225585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.3233152469 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 1211875851 ps |
| CPU time | 48.43 seconds |
| Started | Sep 10 06:47:12 AM UTC 24 |
| Finished | Sep 10 06:48:02 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233152469 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.3233152469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/53.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.1324674899 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 497160274 ps |
| CPU time | 17.65 seconds |
| Started | Sep 10 06:46:44 AM UTC 24 |
| Finished | Sep 10 06:47:03 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324674899 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.1324674899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/53.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.1572752007 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 49332189181 ps |
| CPU time | 497.77 seconds |
| Started | Sep 10 06:46:58 AM UTC 24 |
| Finished | Sep 10 06:55:22 AM UTC 24 |
| Peak memory | 596148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572752007 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.1572752007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/53.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.2391154435 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 7178080491 ps |
| CPU time | 107.18 seconds |
| Started | Sep 10 06:46:59 AM UTC 24 |
| Finished | Sep 10 06:48:48 AM UTC 24 |
| Peak memory | 595980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391154435 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.2391154435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/53.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.3655029077 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 416402716 ps |
| CPU time | 45.1 seconds |
| Started | Sep 10 06:46:44 AM UTC 24 |
| Finished | Sep 10 06:47:31 AM UTC 24 |
| Peak memory | 595964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655029077 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_delays.3655029077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/53.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.2234404063 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 2066388229 ps |
| CPU time | 82.96 seconds |
| Started | Sep 10 06:47:13 AM UTC 24 |
| Finished | Sep 10 06:48:38 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234404063 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.2234404063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/53.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.2038264198 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 47075562 ps |
| CPU time | 5.95 seconds |
| Started | Sep 10 06:46:23 AM UTC 24 |
| Finished | Sep 10 06:46:30 AM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038264198 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.2038264198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/53.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.1804570429 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 9011121278 ps |
| CPU time | 103.88 seconds |
| Started | Sep 10 06:46:27 AM UTC 24 |
| Finished | Sep 10 06:48:13 AM UTC 24 |
| Peak memory | 593704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804570429 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.1804570429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/53.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.4164459836 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 5318154156 ps |
| CPU time | 77.56 seconds |
| Started | Sep 10 06:46:34 AM UTC 24 |
| Finished | Sep 10 06:47:54 AM UTC 24 |
| Peak memory | 593720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164459836 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.4164459836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.2583318748 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 48334408 ps |
| CPU time | 7.05 seconds |
| Started | Sep 10 06:46:26 AM UTC 24 |
| Finished | Sep 10 06:46:34 AM UTC 24 |
| Peak memory | 593784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583318748 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delays.2583318748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/53.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.907459654 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 472246349 ps |
| CPU time | 47.62 seconds |
| Started | Sep 10 06:47:31 AM UTC 24 |
| Finished | Sep 10 06:48:20 AM UTC 24 |
| Peak memory | 595872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907459654 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.907459654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/53.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.13764005 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 452579224 ps |
| CPU time | 34.68 seconds |
| Started | Sep 10 06:47:31 AM UTC 24 |
| Finished | Sep 10 06:48:07 AM UTC 24 |
| Peak memory | 596080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13764005 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.13764005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/53.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.58445392 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 4766534274 ps |
| CPU time | 186.25 seconds |
| Started | Sep 10 06:47:31 AM UTC 24 |
| Finished | Sep 10 06:50:41 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58445392 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_rand_reset.58445392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2721969495 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 322599133 ps |
| CPU time | 84.17 seconds |
| Started | Sep 10 06:47:33 AM UTC 24 |
| Finished | Sep 10 06:48:59 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721969495 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_reset_error.2721969495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.574804839 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 77206977 ps |
| CPU time | 9.19 seconds |
| Started | Sep 10 06:47:21 AM UTC 24 |
| Finished | Sep 10 06:47:31 AM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574804839 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.574804839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/53.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.2283457133 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 111304783 ps |
| CPU time | 12.01 seconds |
| Started | Sep 10 06:48:23 AM UTC 24 |
| Finished | Sep 10 06:48:36 AM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283457133 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device.2283457133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/54.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.4293638623 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 60726672307 ps |
| CPU time | 877.96 seconds |
| Started | Sep 10 06:48:28 AM UTC 24 |
| Finished | Sep 10 07:03:17 AM UTC 24 |
| Peak memory | 596048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293638623 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device_slow_rsp.4293638623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.252251455 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 146525830 ps |
| CPU time | 22.32 seconds |
| Started | Sep 10 06:48:41 AM UTC 24 |
| Finished | Sep 10 06:49:04 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252251455 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_addr.252251455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.2259044783 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 231384641 ps |
| CPU time | 14.62 seconds |
| Started | Sep 10 06:48:34 AM UTC 24 |
| Finished | Sep 10 06:48:50 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259044783 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.2259044783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/54.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.895275112 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 269729185 ps |
| CPU time | 27.42 seconds |
| Started | Sep 10 06:48:00 AM UTC 24 |
| Finished | Sep 10 06:48:28 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895275112 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.895275112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/54.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.3587854316 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 90862112697 ps |
| CPU time | 1091.95 seconds |
| Started | Sep 10 06:48:11 AM UTC 24 |
| Finished | Sep 10 07:06:35 AM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587854316 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.3587854316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/54.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.1353399064 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 28071706786 ps |
| CPU time | 408.72 seconds |
| Started | Sep 10 06:48:19 AM UTC 24 |
| Finished | Sep 10 06:55:14 AM UTC 24 |
| Peak memory | 596012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353399064 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.1353399064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/54.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.3222234202 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 334749819 ps |
| CPU time | 41.05 seconds |
| Started | Sep 10 06:48:08 AM UTC 24 |
| Finished | Sep 10 06:48:51 AM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222234202 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_delays.3222234202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/54.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.3655502413 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 1946506494 ps |
| CPU time | 62.6 seconds |
| Started | Sep 10 06:48:31 AM UTC 24 |
| Finished | Sep 10 06:49:36 AM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655502413 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.3655502413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/54.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.678813671 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 56724160 ps |
| CPU time | 9.7 seconds |
| Started | Sep 10 06:47:33 AM UTC 24 |
| Finished | Sep 10 06:47:43 AM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678813671 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.678813671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/54.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.64473396 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 10282559296 ps |
| CPU time | 107.04 seconds |
| Started | Sep 10 06:47:43 AM UTC 24 |
| Finished | Sep 10 06:49:32 AM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64473396 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.64473396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/54.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.572492733 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 5994390467 ps |
| CPU time | 96.31 seconds |
| Started | Sep 10 06:47:58 AM UTC 24 |
| Finished | Sep 10 06:49:37 AM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572492733 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.572492733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.1784499174 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 45601911 ps |
| CPU time | 8.79 seconds |
| Started | Sep 10 06:47:35 AM UTC 24 |
| Finished | Sep 10 06:47:44 AM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784499174 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delays.1784499174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/54.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.2245575287 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 2232535372 ps |
| CPU time | 83.09 seconds |
| Started | Sep 10 06:48:40 AM UTC 24 |
| Finished | Sep 10 06:50:05 AM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245575287 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.2245575287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/54.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.3026787106 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 3023334087 ps |
| CPU time | 107.95 seconds |
| Started | Sep 10 06:48:52 AM UTC 24 |
| Finished | Sep 10 06:50:42 AM UTC 24 |
| Peak memory | 595996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026787106 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.3026787106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/54.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.2555364303 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 7080599829 ps |
| CPU time | 455.95 seconds |
| Started | Sep 10 06:48:48 AM UTC 24 |
| Finished | Sep 10 06:56:30 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555364303 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_rand_reset.2555364303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.3937828838 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 1755844349 ps |
| CPU time | 227.38 seconds |
| Started | Sep 10 06:48:54 AM UTC 24 |
| Finished | Sep 10 06:52:45 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937828838 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_reset_error.3937828838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.3998902239 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 110863626 ps |
| CPU time | 18.35 seconds |
| Started | Sep 10 06:48:34 AM UTC 24 |
| Finished | Sep 10 06:48:53 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998902239 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.3998902239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/54.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.2786362894 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 3107844045 ps |
| CPU time | 102.06 seconds |
| Started | Sep 10 06:49:20 AM UTC 24 |
| Finished | Sep 10 06:51:04 AM UTC 24 |
| Peak memory | 596144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786362894 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device.2786362894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/55.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.1691797598 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 74443490808 ps |
| CPU time | 1036.82 seconds |
| Started | Sep 10 06:49:24 AM UTC 24 |
| Finished | Sep 10 07:06:53 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691797598 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device_slow_rsp.1691797598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.4063004414 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 946267809 ps |
| CPU time | 34.13 seconds |
| Started | Sep 10 06:49:41 AM UTC 24 |
| Finished | Sep 10 06:50:16 AM UTC 24 |
| Peak memory | 596032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063004414 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_addr.4063004414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.1255113473 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 458636121 ps |
| CPU time | 42.6 seconds |
| Started | Sep 10 06:49:29 AM UTC 24 |
| Finished | Sep 10 06:50:13 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255113473 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.1255113473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/55.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.2323120063 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 117392155 ps |
| CPU time | 9.69 seconds |
| Started | Sep 10 06:49:13 AM UTC 24 |
| Finished | Sep 10 06:49:23 AM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323120063 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.2323120063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/55.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.2672547425 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 22808741781 ps |
| CPU time | 232.29 seconds |
| Started | Sep 10 06:49:16 AM UTC 24 |
| Finished | Sep 10 06:53:11 AM UTC 24 |
| Peak memory | 595756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672547425 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.2672547425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/55.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.2616098667 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 42579277819 ps |
| CPU time | 622.67 seconds |
| Started | Sep 10 06:49:19 AM UTC 24 |
| Finished | Sep 10 06:59:50 AM UTC 24 |
| Peak memory | 596132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616098667 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.2616098667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/55.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.3424255205 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 529350770 ps |
| CPU time | 56.92 seconds |
| Started | Sep 10 06:49:15 AM UTC 24 |
| Finished | Sep 10 06:50:14 AM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424255205 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_delays.3424255205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/55.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.780777110 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 494478472 ps |
| CPU time | 48.24 seconds |
| Started | Sep 10 06:49:25 AM UTC 24 |
| Finished | Sep 10 06:50:15 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780777110 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.780777110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/55.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.3055212725 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 226734064 ps |
| CPU time | 13.07 seconds |
| Started | Sep 10 06:49:02 AM UTC 24 |
| Finished | Sep 10 06:49:16 AM UTC 24 |
| Peak memory | 593636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055212725 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.3055212725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/55.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.736496209 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 6941139024 ps |
| CPU time | 64.31 seconds |
| Started | Sep 10 06:49:14 AM UTC 24 |
| Finished | Sep 10 06:50:20 AM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736496209 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.736496209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/55.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.659135158 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 4085047476 ps |
| CPU time | 53.27 seconds |
| Started | Sep 10 06:49:14 AM UTC 24 |
| Finished | Sep 10 06:50:09 AM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659135158 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.659135158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.3175965762 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 49246550 ps |
| CPU time | 9.13 seconds |
| Started | Sep 10 06:49:03 AM UTC 24 |
| Finished | Sep 10 06:49:13 AM UTC 24 |
| Peak memory | 593888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175965762 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delays.3175965762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/55.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.3552548379 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 7694990519 ps |
| CPU time | 270.24 seconds |
| Started | Sep 10 06:49:40 AM UTC 24 |
| Finished | Sep 10 06:54:14 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552548379 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.3552548379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/55.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.2406603036 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 1269215498 ps |
| CPU time | 90.86 seconds |
| Started | Sep 10 06:49:40 AM UTC 24 |
| Finished | Sep 10 06:51:13 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406603036 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.2406603036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/55.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.3606221072 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 6267200037 ps |
| CPU time | 779.23 seconds |
| Started | Sep 10 06:49:42 AM UTC 24 |
| Finished | Sep 10 07:02:52 AM UTC 24 |
| Peak memory | 596004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606221072 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_rand_reset.3606221072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.3343454224 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 298911704 ps |
| CPU time | 75.83 seconds |
| Started | Sep 10 06:49:46 AM UTC 24 |
| Finished | Sep 10 06:51:03 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343454224 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_reset_error.3343454224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.136156227 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 264571564 ps |
| CPU time | 27.03 seconds |
| Started | Sep 10 06:49:35 AM UTC 24 |
| Finished | Sep 10 06:50:03 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136156227 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.136156227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/55.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.2193375381 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 2799827612 ps |
| CPU time | 127.41 seconds |
| Started | Sep 10 06:50:32 AM UTC 24 |
| Finished | Sep 10 06:52:42 AM UTC 24 |
| Peak memory | 596140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193375381 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device.2193375381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/56.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.2319461296 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 10767884047 ps |
| CPU time | 195.06 seconds |
| Started | Sep 10 06:50:30 AM UTC 24 |
| Finished | Sep 10 06:53:49 AM UTC 24 |
| Peak memory | 596148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319461296 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device_slow_rsp.2319461296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.1475525946 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 1089233143 ps |
| CPU time | 37.25 seconds |
| Started | Sep 10 06:50:38 AM UTC 24 |
| Finished | Sep 10 06:51:17 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475525946 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_addr.1475525946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.2364922873 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 126030815 ps |
| CPU time | 13.84 seconds |
| Started | Sep 10 06:50:40 AM UTC 24 |
| Finished | Sep 10 06:50:54 AM UTC 24 |
| Peak memory | 596076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364922873 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.2364922873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/56.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.718910513 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 124829738 ps |
| CPU time | 17.51 seconds |
| Started | Sep 10 06:50:02 AM UTC 24 |
| Finished | Sep 10 06:50:21 AM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718910513 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.718910513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/56.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.663564377 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 76768872268 ps |
| CPU time | 683.43 seconds |
| Started | Sep 10 06:50:30 AM UTC 24 |
| Finished | Sep 10 07:02:01 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663564377 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.663564377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/56.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.3552560737 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 51773039247 ps |
| CPU time | 685.65 seconds |
| Started | Sep 10 06:50:29 AM UTC 24 |
| Finished | Sep 10 07:02:04 AM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552560737 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.3552560737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/56.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.2958307841 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 246637276 ps |
| CPU time | 23.07 seconds |
| Started | Sep 10 06:50:24 AM UTC 24 |
| Finished | Sep 10 06:50:48 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958307841 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_delays.2958307841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/56.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.242210630 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 2273283314 ps |
| CPU time | 61.58 seconds |
| Started | Sep 10 06:50:33 AM UTC 24 |
| Finished | Sep 10 06:51:36 AM UTC 24 |
| Peak memory | 596204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242210630 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.242210630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/56.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.1266883430 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 46016247 ps |
| CPU time | 7.01 seconds |
| Started | Sep 10 06:49:56 AM UTC 24 |
| Finished | Sep 10 06:50:04 AM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266883430 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.1266883430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/56.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.203624430 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 9181966535 ps |
| CPU time | 107.6 seconds |
| Started | Sep 10 06:50:02 AM UTC 24 |
| Finished | Sep 10 06:51:52 AM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203624430 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.203624430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/56.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.4282932788 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 5299118698 ps |
| CPU time | 93.58 seconds |
| Started | Sep 10 06:50:00 AM UTC 24 |
| Finished | Sep 10 06:51:36 AM UTC 24 |
| Peak memory | 594004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282932788 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.4282932788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.270495421 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 47045462 ps |
| CPU time | 7.44 seconds |
| Started | Sep 10 06:49:58 AM UTC 24 |
| Finished | Sep 10 06:50:06 AM UTC 24 |
| Peak memory | 593784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270495421 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delays.270495421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/56.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.336931101 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 13561939883 ps |
| CPU time | 420.15 seconds |
| Started | Sep 10 06:50:42 AM UTC 24 |
| Finished | Sep 10 06:57:48 AM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336931101 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.336931101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/56.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.604285894 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 1801297796 ps |
| CPU time | 129.23 seconds |
| Started | Sep 10 06:50:42 AM UTC 24 |
| Finished | Sep 10 06:52:55 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604285894 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.604285894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/56.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.2805075643 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 651260239 ps |
| CPU time | 186.62 seconds |
| Started | Sep 10 06:50:46 AM UTC 24 |
| Finished | Sep 10 06:53:55 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805075643 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_rand_reset.2805075643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.3739099279 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 4979072519 ps |
| CPU time | 290.39 seconds |
| Started | Sep 10 06:50:55 AM UTC 24 |
| Finished | Sep 10 06:55:49 AM UTC 24 |
| Peak memory | 596004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739099279 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_reset_error.3739099279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.1187682383 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 1226228492 ps |
| CPU time | 55.4 seconds |
| Started | Sep 10 06:50:42 AM UTC 24 |
| Finished | Sep 10 06:51:39 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187682383 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.1187682383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/56.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.2505876086 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 496516974 ps |
| CPU time | 35.64 seconds |
| Started | Sep 10 06:51:33 AM UTC 24 |
| Finished | Sep 10 06:52:10 AM UTC 24 |
| Peak memory | 596088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505876086 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device.2505876086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/57.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.774221325 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 115698152190 ps |
| CPU time | 1658.34 seconds |
| Started | Sep 10 06:51:40 AM UTC 24 |
| Finished | Sep 10 07:19:37 AM UTC 24 |
| Peak memory | 599180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774221325 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device_slow_rsp.774221325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.3781602214 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 265292849 ps |
| CPU time | 29.64 seconds |
| Started | Sep 10 06:52:03 AM UTC 24 |
| Finished | Sep 10 06:52:34 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781602214 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_addr.3781602214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.3661799598 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 1104344289 ps |
| CPU time | 42.31 seconds |
| Started | Sep 10 06:51:48 AM UTC 24 |
| Finished | Sep 10 06:52:32 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661799598 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.3661799598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/57.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.3404210440 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 1384132920 ps |
| CPU time | 66.81 seconds |
| Started | Sep 10 06:51:15 AM UTC 24 |
| Finished | Sep 10 06:52:23 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404210440 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.3404210440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/57.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.2429146561 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 109050819200 ps |
| CPU time | 1087.7 seconds |
| Started | Sep 10 06:51:31 AM UTC 24 |
| Finished | Sep 10 07:09:52 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429146561 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.2429146561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/57.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.672412042 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 26464677447 ps |
| CPU time | 425.44 seconds |
| Started | Sep 10 06:51:30 AM UTC 24 |
| Finished | Sep 10 06:58:41 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672412042 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.672412042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/57.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.86350678 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 162451530 ps |
| CPU time | 20.65 seconds |
| Started | Sep 10 06:51:22 AM UTC 24 |
| Finished | Sep 10 06:51:43 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86350678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_delays.86350678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/57.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.3367011834 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 188488018 ps |
| CPU time | 9.11 seconds |
| Started | Sep 10 06:51:46 AM UTC 24 |
| Finished | Sep 10 06:51:56 AM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367011834 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.3367011834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/57.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.2451797609 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 165716576 ps |
| CPU time | 11.37 seconds |
| Started | Sep 10 06:51:08 AM UTC 24 |
| Finished | Sep 10 06:51:21 AM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451797609 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.2451797609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/57.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.2566831347 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 5913846208 ps |
| CPU time | 60.47 seconds |
| Started | Sep 10 06:51:08 AM UTC 24 |
| Finished | Sep 10 06:52:10 AM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566831347 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.2566831347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/57.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.1094768741 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 5939412301 ps |
| CPU time | 81.98 seconds |
| Started | Sep 10 06:51:17 AM UTC 24 |
| Finished | Sep 10 06:52:40 AM UTC 24 |
| Peak memory | 594036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094768741 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.1094768741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.1098766374 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 38336736 ps |
| CPU time | 8.41 seconds |
| Started | Sep 10 06:51:10 AM UTC 24 |
| Finished | Sep 10 06:51:19 AM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098766374 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delays.1098766374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/57.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.2844631222 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 1380741258 ps |
| CPU time | 113.92 seconds |
| Started | Sep 10 06:52:00 AM UTC 24 |
| Finished | Sep 10 06:53:56 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844631222 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.2844631222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/57.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.1764722248 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 4126063126 ps |
| CPU time | 141.11 seconds |
| Started | Sep 10 06:52:09 AM UTC 24 |
| Finished | Sep 10 06:54:34 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764722248 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.1764722248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/57.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.574770479 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 289606177 ps |
| CPU time | 97.06 seconds |
| Started | Sep 10 06:52:05 AM UTC 24 |
| Finished | Sep 10 06:53:44 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574770479 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_rand_reset.574770479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.1015265825 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 2063893092 ps |
| CPU time | 135.05 seconds |
| Started | Sep 10 06:52:10 AM UTC 24 |
| Finished | Sep 10 06:54:28 AM UTC 24 |
| Peak memory | 595940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015265825 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_reset_error.1015265825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.713575800 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 127705407 ps |
| CPU time | 14.3 seconds |
| Started | Sep 10 06:51:48 AM UTC 24 |
| Finished | Sep 10 06:52:03 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713575800 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.713575800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/57.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.250624042 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 137657607 ps |
| CPU time | 15.9 seconds |
| Started | Sep 10 06:52:48 AM UTC 24 |
| Finished | Sep 10 06:53:05 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250624042 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device.250624042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/58.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.713162770 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 116675415350 ps |
| CPU time | 1731.21 seconds |
| Started | Sep 10 06:52:47 AM UTC 24 |
| Finished | Sep 10 07:21:58 AM UTC 24 |
| Peak memory | 599148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713162770 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device_slow_rsp.713162770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3294195920 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 692443492 ps |
| CPU time | 38.52 seconds |
| Started | Sep 10 06:53:04 AM UTC 24 |
| Finished | Sep 10 06:53:44 AM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294195920 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_addr.3294195920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.3681625624 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 669805266 ps |
| CPU time | 31.46 seconds |
| Started | Sep 10 06:53:00 AM UTC 24 |
| Finished | Sep 10 06:53:33 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681625624 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.3681625624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/58.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.4222809793 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 134625293 ps |
| CPU time | 15.95 seconds |
| Started | Sep 10 06:52:21 AM UTC 24 |
| Finished | Sep 10 06:52:38 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222809793 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.4222809793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/58.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.4244616383 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 80697486878 ps |
| CPU time | 883.2 seconds |
| Started | Sep 10 06:52:37 AM UTC 24 |
| Finished | Sep 10 07:07:31 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244616383 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.4244616383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/58.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.1099330591 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 12373600812 ps |
| CPU time | 191.63 seconds |
| Started | Sep 10 06:52:37 AM UTC 24 |
| Finished | Sep 10 06:55:52 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099330591 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.1099330591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/58.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.4009366080 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 604881663 ps |
| CPU time | 69.59 seconds |
| Started | Sep 10 06:52:30 AM UTC 24 |
| Finished | Sep 10 06:53:42 AM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009366080 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_delays.4009366080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/58.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.26914950 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 1632099594 ps |
| CPU time | 45.57 seconds |
| Started | Sep 10 06:52:51 AM UTC 24 |
| Finished | Sep 10 06:53:38 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26914950 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.26914950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/58.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.1868081907 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 207857220 ps |
| CPU time | 12.39 seconds |
| Started | Sep 10 06:52:10 AM UTC 24 |
| Finished | Sep 10 06:52:24 AM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868081907 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.1868081907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/58.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.2329939280 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 7835873114 ps |
| CPU time | 93.67 seconds |
| Started | Sep 10 06:52:17 AM UTC 24 |
| Finished | Sep 10 06:53:53 AM UTC 24 |
| Peak memory | 593844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329939280 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.2329939280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/58.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.1138111734 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 4488581713 ps |
| CPU time | 88.78 seconds |
| Started | Sep 10 06:52:23 AM UTC 24 |
| Finished | Sep 10 06:53:54 AM UTC 24 |
| Peak memory | 593704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138111734 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.1138111734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.1643593153 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 46780579 ps |
| CPU time | 6.32 seconds |
| Started | Sep 10 06:52:13 AM UTC 24 |
| Finished | Sep 10 06:52:20 AM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643593153 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delays.1643593153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/58.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.265170226 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 1957070223 ps |
| CPU time | 169.36 seconds |
| Started | Sep 10 06:53:07 AM UTC 24 |
| Finished | Sep 10 06:56:00 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265170226 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.265170226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/58.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.2299177915 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 930366366 ps |
| CPU time | 59.87 seconds |
| Started | Sep 10 06:53:11 AM UTC 24 |
| Finished | Sep 10 06:54:13 AM UTC 24 |
| Peak memory | 596044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299177915 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.2299177915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/58.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.19846375 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 577986003 ps |
| CPU time | 152.68 seconds |
| Started | Sep 10 06:53:10 AM UTC 24 |
| Finished | Sep 10 06:55:45 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19846375 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_rand_reset.19846375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.1394487881 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 1771862970 ps |
| CPU time | 316.91 seconds |
| Started | Sep 10 06:53:23 AM UTC 24 |
| Finished | Sep 10 06:58:45 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394487881 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_reset_error.1394487881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.2374079042 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 926943692 ps |
| CPU time | 43.11 seconds |
| Started | Sep 10 06:53:02 AM UTC 24 |
| Finished | Sep 10 06:53:47 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374079042 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.2374079042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/58.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.1207628217 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 2619165862 ps |
| CPU time | 108.67 seconds |
| Started | Sep 10 06:54:09 AM UTC 24 |
| Finished | Sep 10 06:56:00 AM UTC 24 |
| Peak memory | 596208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207628217 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device.1207628217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/59.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.2870525464 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 5845706876 ps |
| CPU time | 107.42 seconds |
| Started | Sep 10 06:54:14 AM UTC 24 |
| Finished | Sep 10 06:56:04 AM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870525464 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device_slow_rsp.2870525464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.1654926550 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 1204107994 ps |
| CPU time | 57.55 seconds |
| Started | Sep 10 06:54:22 AM UTC 24 |
| Finished | Sep 10 06:55:21 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654926550 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_addr.1654926550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.3740444816 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 401926855 ps |
| CPU time | 19.94 seconds |
| Started | Sep 10 06:54:15 AM UTC 24 |
| Finished | Sep 10 06:54:36 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740444816 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.3740444816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/59.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.140730681 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 778409081 ps |
| CPU time | 27.16 seconds |
| Started | Sep 10 06:54:04 AM UTC 24 |
| Finished | Sep 10 06:54:33 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140730681 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.140730681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/59.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.3439230486 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 91213864320 ps |
| CPU time | 1051.52 seconds |
| Started | Sep 10 06:54:10 AM UTC 24 |
| Finished | Sep 10 07:11:55 AM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439230486 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.3439230486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/59.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.1405668439 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 53792889258 ps |
| CPU time | 765.58 seconds |
| Started | Sep 10 06:54:10 AM UTC 24 |
| Finished | Sep 10 07:07:07 AM UTC 24 |
| Peak memory | 596004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405668439 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.1405668439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/59.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.3157664781 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 492252390 ps |
| CPU time | 37.38 seconds |
| Started | Sep 10 06:54:08 AM UTC 24 |
| Finished | Sep 10 06:54:46 AM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157664781 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_delays.3157664781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/59.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.87131980 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 264463076 ps |
| CPU time | 14.38 seconds |
| Started | Sep 10 06:54:15 AM UTC 24 |
| Finished | Sep 10 06:54:30 AM UTC 24 |
| Peak memory | 595688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87131980 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.87131980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/59.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.1376180220 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 177174058 ps |
| CPU time | 7.95 seconds |
| Started | Sep 10 06:53:31 AM UTC 24 |
| Finished | Sep 10 06:53:40 AM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376180220 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.1376180220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/59.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.274998805 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 8325616739 ps |
| CPU time | 88.64 seconds |
| Started | Sep 10 06:53:52 AM UTC 24 |
| Finished | Sep 10 06:55:23 AM UTC 24 |
| Peak memory | 593784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274998805 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.274998805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/59.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.2914308821 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 4051828542 ps |
| CPU time | 61.48 seconds |
| Started | Sep 10 06:54:01 AM UTC 24 |
| Finished | Sep 10 06:55:04 AM UTC 24 |
| Peak memory | 593704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914308821 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.2914308821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.1375139891 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 40382000 ps |
| CPU time | 8.44 seconds |
| Started | Sep 10 06:53:38 AM UTC 24 |
| Finished | Sep 10 06:53:47 AM UTC 24 |
| Peak memory | 593784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375139891 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delays.1375139891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/59.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.3722850188 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 3020774199 ps |
| CPU time | 248.91 seconds |
| Started | Sep 10 06:54:23 AM UTC 24 |
| Finished | Sep 10 06:58:36 AM UTC 24 |
| Peak memory | 596004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722850188 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.3722850188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/59.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.589551285 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 631678858 ps |
| CPU time | 44.41 seconds |
| Started | Sep 10 06:54:35 AM UTC 24 |
| Finished | Sep 10 06:55:21 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589551285 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.589551285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/59.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.2884642474 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 3688300591 ps |
| CPU time | 419.33 seconds |
| Started | Sep 10 06:54:19 AM UTC 24 |
| Finished | Sep 10 07:01:24 AM UTC 24 |
| Peak memory | 596128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884642474 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_rand_reset.2884642474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1644305418 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 1639297315 ps |
| CPU time | 296.01 seconds |
| Started | Sep 10 06:54:40 AM UTC 24 |
| Finished | Sep 10 06:59:40 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644305418 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_reset_error.1644305418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.3287013989 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 1235894669 ps |
| CPU time | 49.52 seconds |
| Started | Sep 10 06:54:20 AM UTC 24 |
| Finished | Sep 10 06:55:11 AM UTC 24 |
| Peak memory | 595964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287013989 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.3287013989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/59.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.1772075018 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 9477798736 ps |
| CPU time | 891.83 seconds |
| Started | Sep 10 05:18:23 AM UTC 24 |
| Finished | Sep 10 05:33:27 AM UTC 24 |
| Peak memory | 670372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1772075018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 6.chip_csr_mem_rw_with_rand_reset.1772075018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.264192497 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 3735516054 ps |
| CPU time | 319.41 seconds |
| Started | Sep 10 05:18:12 AM UTC 24 |
| Finished | Sep 10 05:23:36 AM UTC 24 |
| Peak memory | 614684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264192497 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.264192497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.832440893 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 27733791508 ps |
| CPU time | 3938.1 seconds |
| Started | Sep 10 05:16:27 AM UTC 24 |
| Finished | Sep 10 06:22:54 AM UTC 24 |
| Peak memory | 614024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=832440893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 6.chip_same_csr_outstanding.832440893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.524215542 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 3203890800 ps |
| CPU time | 325.39 seconds |
| Started | Sep 10 05:16:31 AM UTC 24 |
| Finished | Sep 10 05:22:01 AM UTC 24 |
| Peak memory | 621092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524215542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.524215542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.1755768154 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 991142029 ps |
| CPU time | 57.26 seconds |
| Started | Sep 10 05:16:57 AM UTC 24 |
| Finished | Sep 10 05:17:56 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755768154 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.1755768154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.2138536050 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 50110228289 ps |
| CPU time | 738.71 seconds |
| Started | Sep 10 05:17:03 AM UTC 24 |
| Finished | Sep 10 05:29:31 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138536050 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.2138536050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3000735558 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 22972554 ps |
| CPU time | 8.27 seconds |
| Started | Sep 10 05:17:28 AM UTC 24 |
| Finished | Sep 10 05:17:37 AM UTC 24 |
| Peak memory | 593656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000735558 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3000735558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.3121860904 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 606347471 ps |
| CPU time | 62.88 seconds |
| Started | Sep 10 05:17:06 AM UTC 24 |
| Finished | Sep 10 05:18:10 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121860904 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.3121860904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.891369215 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 1776438053 ps |
| CPU time | 58.42 seconds |
| Started | Sep 10 05:16:44 AM UTC 24 |
| Finished | Sep 10 05:17:44 AM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891369215 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.891369215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.2670813640 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 62038891322 ps |
| CPU time | 616.21 seconds |
| Started | Sep 10 05:16:47 AM UTC 24 |
| Finished | Sep 10 05:27:11 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670813640 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2670813640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.2320290152 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 3065531124 ps |
| CPU time | 67 seconds |
| Started | Sep 10 05:16:53 AM UTC 24 |
| Finished | Sep 10 05:18:02 AM UTC 24 |
| Peak memory | 594108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320290152 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2320290152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.4073337089 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 265466325 ps |
| CPU time | 32.96 seconds |
| Started | Sep 10 05:16:45 AM UTC 24 |
| Finished | Sep 10 05:17:20 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073337089 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.4073337089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.1883056226 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 430391494 ps |
| CPU time | 36.34 seconds |
| Started | Sep 10 05:17:07 AM UTC 24 |
| Finished | Sep 10 05:17:44 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883056226 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.1883056226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.1116269051 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 245055314 ps |
| CPU time | 9.72 seconds |
| Started | Sep 10 05:16:31 AM UTC 24 |
| Finished | Sep 10 05:16:41 AM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116269051 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1116269051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.4154965376 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 7327155146 ps |
| CPU time | 123 seconds |
| Started | Sep 10 05:16:38 AM UTC 24 |
| Finished | Sep 10 05:18:43 AM UTC 24 |
| Peak memory | 593904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154965376 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.4154965376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.3195614780 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 5162868683 ps |
| CPU time | 78.01 seconds |
| Started | Sep 10 05:16:36 AM UTC 24 |
| Finished | Sep 10 05:17:56 AM UTC 24 |
| Peak memory | 593912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195614780 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3195614780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.4266450611 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 55278409 ps |
| CPU time | 9.98 seconds |
| Started | Sep 10 05:16:36 AM UTC 24 |
| Finished | Sep 10 05:16:48 AM UTC 24 |
| Peak memory | 594092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266450611 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.4266450611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.1056272945 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 8843084001 ps |
| CPU time | 337.98 seconds |
| Started | Sep 10 05:17:29 AM UTC 24 |
| Finished | Sep 10 05:23:12 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056272945 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1056272945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.1388359950 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 12029008402 ps |
| CPU time | 565.12 seconds |
| Started | Sep 10 05:18:04 AM UTC 24 |
| Finished | Sep 10 05:27:37 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388359950 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1388359950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.3294879500 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 159962533 ps |
| CPU time | 55.62 seconds |
| Started | Sep 10 05:17:47 AM UTC 24 |
| Finished | Sep 10 05:18:44 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294879500 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.3294879500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3108551978 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 351482108 ps |
| CPU time | 166.23 seconds |
| Started | Sep 10 05:18:11 AM UTC 24 |
| Finished | Sep 10 05:21:00 AM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108551978 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.3108551978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.2097336907 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 873749625 ps |
| CPU time | 49.09 seconds |
| Started | Sep 10 05:17:15 AM UTC 24 |
| Finished | Sep 10 05:18:05 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097336907 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2097336907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.2903647728 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 556348089 ps |
| CPU time | 47.52 seconds |
| Started | Sep 10 06:55:13 AM UTC 24 |
| Finished | Sep 10 06:56:02 AM UTC 24 |
| Peak memory | 596124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903647728 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device.2903647728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/60.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.1512765788 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 26262000521 ps |
| CPU time | 360.91 seconds |
| Started | Sep 10 06:55:23 AM UTC 24 |
| Finished | Sep 10 07:01:28 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512765788 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device_slow_rsp.1512765788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.1749293362 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 1043325716 ps |
| CPU time | 40.92 seconds |
| Started | Sep 10 06:55:36 AM UTC 24 |
| Finished | Sep 10 06:56:18 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749293362 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_addr.1749293362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.178367097 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 2024469504 ps |
| CPU time | 65.46 seconds |
| Started | Sep 10 06:55:32 AM UTC 24 |
| Finished | Sep 10 06:56:39 AM UTC 24 |
| Peak memory | 595940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178367097 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.178367097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/60.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.140897699 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 224600679 ps |
| CPU time | 20.64 seconds |
| Started | Sep 10 06:55:02 AM UTC 24 |
| Finished | Sep 10 06:55:24 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140897699 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.140897699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/60.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.151487079 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 82295267306 ps |
| CPU time | 834.98 seconds |
| Started | Sep 10 06:55:02 AM UTC 24 |
| Finished | Sep 10 07:09:08 AM UTC 24 |
| Peak memory | 596140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151487079 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.151487079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/60.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.43118301 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 14214088501 ps |
| CPU time | 198.37 seconds |
| Started | Sep 10 06:55:02 AM UTC 24 |
| Finished | Sep 10 06:58:24 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43118301 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.43118301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/60.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.1740980916 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 66260855 ps |
| CPU time | 12.22 seconds |
| Started | Sep 10 06:54:59 AM UTC 24 |
| Finished | Sep 10 06:55:13 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740980916 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_delays.1740980916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/60.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.2921406675 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 2411330836 ps |
| CPU time | 66.53 seconds |
| Started | Sep 10 06:55:24 AM UTC 24 |
| Finished | Sep 10 06:56:33 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921406675 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.2921406675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/60.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.1511995125 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 249854608 ps |
| CPU time | 12.06 seconds |
| Started | Sep 10 06:54:42 AM UTC 24 |
| Finished | Sep 10 06:54:55 AM UTC 24 |
| Peak memory | 593636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511995125 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.1511995125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/60.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.4256599594 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 5697838833 ps |
| CPU time | 56.19 seconds |
| Started | Sep 10 06:54:55 AM UTC 24 |
| Finished | Sep 10 06:55:52 AM UTC 24 |
| Peak memory | 593904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256599594 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.4256599594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/60.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.1723336635 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 6297639918 ps |
| CPU time | 95.55 seconds |
| Started | Sep 10 06:54:59 AM UTC 24 |
| Finished | Sep 10 06:56:36 AM UTC 24 |
| Peak memory | 593844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723336635 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.1723336635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.453449695 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 44437973 ps |
| CPU time | 7.4 seconds |
| Started | Sep 10 06:54:49 AM UTC 24 |
| Finished | Sep 10 06:54:58 AM UTC 24 |
| Peak memory | 593776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453449695 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delays.453449695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/60.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.1621168330 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 12648263168 ps |
| CPU time | 441.22 seconds |
| Started | Sep 10 06:55:39 AM UTC 24 |
| Finished | Sep 10 07:03:07 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621168330 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.1621168330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/60.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.1305173257 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 10099933294 ps |
| CPU time | 340.8 seconds |
| Started | Sep 10 06:55:47 AM UTC 24 |
| Finished | Sep 10 07:01:33 AM UTC 24 |
| Peak memory | 596000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305173257 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.1305173257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/60.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.568564822 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 8433144254 ps |
| CPU time | 895.65 seconds |
| Started | Sep 10 06:55:48 AM UTC 24 |
| Finished | Sep 10 07:10:55 AM UTC 24 |
| Peak memory | 596128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568564822 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_rand_reset.568564822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.3150337993 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 8670814628 ps |
| CPU time | 456.46 seconds |
| Started | Sep 10 06:55:49 AM UTC 24 |
| Finished | Sep 10 07:03:31 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150337993 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_reset_error.3150337993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.2159760185 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 124250018 ps |
| CPU time | 15.12 seconds |
| Started | Sep 10 06:55:39 AM UTC 24 |
| Finished | Sep 10 06:55:56 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159760185 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.2159760185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/60.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.2990599101 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 3012138923 ps |
| CPU time | 109.97 seconds |
| Started | Sep 10 06:56:19 AM UTC 24 |
| Finished | Sep 10 06:58:11 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990599101 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device.2990599101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/61.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.1376616453 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 56772289934 ps |
| CPU time | 803.62 seconds |
| Started | Sep 10 06:56:15 AM UTC 24 |
| Finished | Sep 10 07:09:49 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376616453 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device_slow_rsp.1376616453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.1063086872 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 304812220 ps |
| CPU time | 15.25 seconds |
| Started | Sep 10 06:56:24 AM UTC 24 |
| Finished | Sep 10 06:56:41 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063086872 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_addr.1063086872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.2304890594 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 154297932 ps |
| CPU time | 18.46 seconds |
| Started | Sep 10 06:56:22 AM UTC 24 |
| Finished | Sep 10 06:56:42 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304890594 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.2304890594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/61.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.2553137982 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 620589133 ps |
| CPU time | 54.75 seconds |
| Started | Sep 10 06:56:09 AM UTC 24 |
| Finished | Sep 10 06:57:06 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553137982 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.2553137982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/61.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.3905026503 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 33914679179 ps |
| CPU time | 293.24 seconds |
| Started | Sep 10 06:56:13 AM UTC 24 |
| Finished | Sep 10 07:01:10 AM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905026503 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.3905026503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/61.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.2018161768 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 45927273385 ps |
| CPU time | 700.32 seconds |
| Started | Sep 10 06:56:14 AM UTC 24 |
| Finished | Sep 10 07:08:03 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018161768 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.2018161768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/61.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.1046249320 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 190444200 ps |
| CPU time | 19.45 seconds |
| Started | Sep 10 06:56:13 AM UTC 24 |
| Finished | Sep 10 06:56:34 AM UTC 24 |
| Peak memory | 595884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046249320 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_delays.1046249320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/61.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.2418387489 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 178582057 ps |
| CPU time | 16.3 seconds |
| Started | Sep 10 06:56:18 AM UTC 24 |
| Finished | Sep 10 06:56:36 AM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418387489 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.2418387489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/61.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.1981931203 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 44446876 ps |
| CPU time | 6.22 seconds |
| Started | Sep 10 06:55:49 AM UTC 24 |
| Finished | Sep 10 06:55:56 AM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981931203 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.1981931203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/61.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.2550271490 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 8191084332 ps |
| CPU time | 79.22 seconds |
| Started | Sep 10 06:56:01 AM UTC 24 |
| Finished | Sep 10 06:57:22 AM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550271490 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.2550271490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/61.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.1959293826 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 4979722810 ps |
| CPU time | 85.56 seconds |
| Started | Sep 10 06:56:10 AM UTC 24 |
| Finished | Sep 10 06:57:37 AM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959293826 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.1959293826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.2975798400 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 57676311 ps |
| CPU time | 9.91 seconds |
| Started | Sep 10 06:55:52 AM UTC 24 |
| Finished | Sep 10 06:56:03 AM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975798400 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delays.2975798400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/61.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.4114506257 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 2871848628 ps |
| CPU time | 243.45 seconds |
| Started | Sep 10 06:56:21 AM UTC 24 |
| Finished | Sep 10 07:00:28 AM UTC 24 |
| Peak memory | 596192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114506257 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.4114506257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/61.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.1011730622 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 1143468227 ps |
| CPU time | 68.13 seconds |
| Started | Sep 10 06:56:22 AM UTC 24 |
| Finished | Sep 10 06:57:32 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011730622 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.1011730622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/61.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.2994506679 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 1751970155 ps |
| CPU time | 422.79 seconds |
| Started | Sep 10 06:56:26 AM UTC 24 |
| Finished | Sep 10 07:03:35 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994506679 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_rand_reset.2994506679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.3694575346 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 1587304412 ps |
| CPU time | 122.21 seconds |
| Started | Sep 10 06:56:29 AM UTC 24 |
| Finished | Sep 10 06:58:34 AM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694575346 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_reset_error.3694575346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.1338630353 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 1305498838 ps |
| CPU time | 60.94 seconds |
| Started | Sep 10 06:56:21 AM UTC 24 |
| Finished | Sep 10 06:57:24 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338630353 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.1338630353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/61.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.2704662238 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 2496537590 ps |
| CPU time | 122.75 seconds |
| Started | Sep 10 06:57:04 AM UTC 24 |
| Finished | Sep 10 06:59:09 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704662238 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device.2704662238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/62.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.320759692 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 37763288150 ps |
| CPU time | 523.58 seconds |
| Started | Sep 10 06:57:05 AM UTC 24 |
| Finished | Sep 10 07:05:55 AM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320759692 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device_slow_rsp.320759692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.931064412 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 1378599637 ps |
| CPU time | 53.57 seconds |
| Started | Sep 10 06:57:34 AM UTC 24 |
| Finished | Sep 10 06:58:29 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931064412 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_addr.931064412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.1923967134 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 592614726 ps |
| CPU time | 57 seconds |
| Started | Sep 10 06:57:09 AM UTC 24 |
| Finished | Sep 10 06:58:08 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923967134 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.1923967134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/62.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.4005112573 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 685655198 ps |
| CPU time | 25.14 seconds |
| Started | Sep 10 06:56:58 AM UTC 24 |
| Finished | Sep 10 06:57:24 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005112573 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.4005112573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/62.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.1876585764 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 48696094033 ps |
| CPU time | 500.57 seconds |
| Started | Sep 10 06:57:01 AM UTC 24 |
| Finished | Sep 10 07:05:28 AM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876585764 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.1876585764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/62.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.3758720709 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 36859128185 ps |
| CPU time | 592.12 seconds |
| Started | Sep 10 06:57:04 AM UTC 24 |
| Finished | Sep 10 07:07:03 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758720709 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.3758720709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/62.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.576362426 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 349504361 ps |
| CPU time | 29.85 seconds |
| Started | Sep 10 06:57:01 AM UTC 24 |
| Finished | Sep 10 06:57:32 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576362426 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_delays.576362426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/62.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.3406135090 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 1353558478 ps |
| CPU time | 34.65 seconds |
| Started | Sep 10 06:57:08 AM UTC 24 |
| Finished | Sep 10 06:57:44 AM UTC 24 |
| Peak memory | 596032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406135090 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.3406135090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/62.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.705387695 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 37182342 ps |
| CPU time | 8.29 seconds |
| Started | Sep 10 06:56:28 AM UTC 24 |
| Finished | Sep 10 06:56:37 AM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705387695 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.705387695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/62.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.3328097000 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 8049001054 ps |
| CPU time | 73.68 seconds |
| Started | Sep 10 06:56:57 AM UTC 24 |
| Finished | Sep 10 06:58:12 AM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328097000 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.3328097000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/62.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.3392570348 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 5010237558 ps |
| CPU time | 83 seconds |
| Started | Sep 10 06:56:56 AM UTC 24 |
| Finished | Sep 10 06:58:21 AM UTC 24 |
| Peak memory | 594036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392570348 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.3392570348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.2910684235 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 45294976 ps |
| CPU time | 8.49 seconds |
| Started | Sep 10 06:56:45 AM UTC 24 |
| Finished | Sep 10 06:56:54 AM UTC 24 |
| Peak memory | 593880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910684235 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delays.2910684235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/62.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.127073022 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 1299414870 ps |
| CPU time | 114.06 seconds |
| Started | Sep 10 06:57:38 AM UTC 24 |
| Finished | Sep 10 06:59:35 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127073022 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.127073022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/62.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.1326347091 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 3029772652 ps |
| CPU time | 210.01 seconds |
| Started | Sep 10 06:57:52 AM UTC 24 |
| Finished | Sep 10 07:01:25 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326347091 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.1326347091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/62.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.3741759299 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 2430214488 ps |
| CPU time | 222.41 seconds |
| Started | Sep 10 06:57:49 AM UTC 24 |
| Finished | Sep 10 07:01:35 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741759299 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_rand_reset.3741759299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.3983573346 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 243069343 ps |
| CPU time | 79.29 seconds |
| Started | Sep 10 06:57:51 AM UTC 24 |
| Finished | Sep 10 06:59:12 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983573346 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_reset_error.3983573346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.2623147113 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 328660732 ps |
| CPU time | 42.82 seconds |
| Started | Sep 10 06:57:22 AM UTC 24 |
| Finished | Sep 10 06:58:06 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623147113 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.2623147113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/62.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.2911813210 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 1891573539 ps |
| CPU time | 71.91 seconds |
| Started | Sep 10 06:58:33 AM UTC 24 |
| Finished | Sep 10 06:59:47 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911813210 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device.2911813210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/63.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.2791314478 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 117001756728 ps |
| CPU time | 1622.2 seconds |
| Started | Sep 10 06:58:35 AM UTC 24 |
| Finished | Sep 10 07:25:56 AM UTC 24 |
| Peak memory | 598932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791314478 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device_slow_rsp.2791314478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.75328805 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 419455268 ps |
| CPU time | 19.33 seconds |
| Started | Sep 10 06:58:49 AM UTC 24 |
| Finished | Sep 10 06:59:10 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75328805 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_addr.75328805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.2348997101 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 167163388 ps |
| CPU time | 20.94 seconds |
| Started | Sep 10 06:58:39 AM UTC 24 |
| Finished | Sep 10 06:59:01 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348997101 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.2348997101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/63.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.889406860 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 124974600 ps |
| CPU time | 17.45 seconds |
| Started | Sep 10 06:58:17 AM UTC 24 |
| Finished | Sep 10 06:58:35 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889406860 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.889406860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/63.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.1132264812 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 61107985167 ps |
| CPU time | 635.44 seconds |
| Started | Sep 10 06:58:35 AM UTC 24 |
| Finished | Sep 10 07:09:18 AM UTC 24 |
| Peak memory | 595756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132264812 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.1132264812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/63.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.2848421771 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 57846249586 ps |
| CPU time | 963.75 seconds |
| Started | Sep 10 06:58:34 AM UTC 24 |
| Finished | Sep 10 07:14:49 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848421771 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.2848421771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/63.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.1369420939 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 138208786 ps |
| CPU time | 16.99 seconds |
| Started | Sep 10 06:58:19 AM UTC 24 |
| Finished | Sep 10 06:58:37 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369420939 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_delays.1369420939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/63.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.3220971276 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 319738970 ps |
| CPU time | 32.72 seconds |
| Started | Sep 10 06:58:37 AM UTC 24 |
| Finished | Sep 10 06:59:11 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220971276 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.3220971276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/63.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.2240654046 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 174168683 ps |
| CPU time | 10.86 seconds |
| Started | Sep 10 06:57:56 AM UTC 24 |
| Finished | Sep 10 06:58:08 AM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240654046 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.2240654046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/63.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.1667461728 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 6773673005 ps |
| CPU time | 68.05 seconds |
| Started | Sep 10 06:58:05 AM UTC 24 |
| Finished | Sep 10 06:59:15 AM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667461728 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.1667461728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/63.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.1827767249 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 2791067824 ps |
| CPU time | 43.62 seconds |
| Started | Sep 10 06:58:10 AM UTC 24 |
| Finished | Sep 10 06:58:55 AM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827767249 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.1827767249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.1824563244 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 52670157 ps |
| CPU time | 8.71 seconds |
| Started | Sep 10 06:57:58 AM UTC 24 |
| Finished | Sep 10 06:58:07 AM UTC 24 |
| Peak memory | 593784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824563244 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delays.1824563244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/63.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.2168613727 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 1095339207 ps |
| CPU time | 105.35 seconds |
| Started | Sep 10 06:58:50 AM UTC 24 |
| Finished | Sep 10 07:00:38 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168613727 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.2168613727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/63.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.3839992144 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 2149067327 ps |
| CPU time | 75.72 seconds |
| Started | Sep 10 06:58:57 AM UTC 24 |
| Finished | Sep 10 07:00:16 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839992144 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.3839992144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/63.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.2982830655 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 294839765 ps |
| CPU time | 109.67 seconds |
| Started | Sep 10 06:58:53 AM UTC 24 |
| Finished | Sep 10 07:00:45 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982830655 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_rand_reset.2982830655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.2282889513 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 11130037596 ps |
| CPU time | 989.8 seconds |
| Started | Sep 10 06:58:58 AM UTC 24 |
| Finished | Sep 10 07:15:41 AM UTC 24 |
| Peak memory | 616556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282889513 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_reset_error.2282889513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.3709680807 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 705872889 ps |
| CPU time | 36.49 seconds |
| Started | Sep 10 06:58:41 AM UTC 24 |
| Finished | Sep 10 06:59:19 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709680807 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.3709680807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/63.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.1961126115 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 2066775710 ps |
| CPU time | 68.75 seconds |
| Started | Sep 10 06:59:36 AM UTC 24 |
| Finished | Sep 10 07:00:46 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961126115 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device.1961126115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/64.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.1301617434 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 79635970017 ps |
| CPU time | 1382.73 seconds |
| Started | Sep 10 06:59:39 AM UTC 24 |
| Finished | Sep 10 07:22:59 AM UTC 24 |
| Peak memory | 596512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301617434 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device_slow_rsp.1301617434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.446110227 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 247627577 ps |
| CPU time | 32.45 seconds |
| Started | Sep 10 06:59:47 AM UTC 24 |
| Finished | Sep 10 07:00:21 AM UTC 24 |
| Peak memory | 595876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446110227 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_addr.446110227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.3099343842 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 817652522 ps |
| CPU time | 31.04 seconds |
| Started | Sep 10 06:59:37 AM UTC 24 |
| Finished | Sep 10 07:00:09 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099343842 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.3099343842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/64.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.226134664 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 1455034966 ps |
| CPU time | 46.27 seconds |
| Started | Sep 10 06:59:13 AM UTC 24 |
| Finished | Sep 10 07:00:01 AM UTC 24 |
| Peak memory | 596072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226134664 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.226134664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/64.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.119981030 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 94867465434 ps |
| CPU time | 1083.8 seconds |
| Started | Sep 10 06:59:28 AM UTC 24 |
| Finished | Sep 10 07:17:45 AM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119981030 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.119981030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/64.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.618080338 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 47407556520 ps |
| CPU time | 695.63 seconds |
| Started | Sep 10 06:59:38 AM UTC 24 |
| Finished | Sep 10 07:11:22 AM UTC 24 |
| Peak memory | 596196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618080338 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.618080338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/64.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.2470819915 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 320130273 ps |
| CPU time | 27 seconds |
| Started | Sep 10 06:59:21 AM UTC 24 |
| Finished | Sep 10 06:59:49 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470819915 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_delays.2470819915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/64.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.733119228 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 1390102126 ps |
| CPU time | 44.29 seconds |
| Started | Sep 10 06:59:36 AM UTC 24 |
| Finished | Sep 10 07:00:22 AM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733119228 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.733119228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/64.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.139435939 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 255088948 ps |
| CPU time | 13.46 seconds |
| Started | Sep 10 06:59:04 AM UTC 24 |
| Finished | Sep 10 06:59:19 AM UTC 24 |
| Peak memory | 593772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139435939 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.139435939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/64.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.1182417884 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 8054482358 ps |
| CPU time | 99.59 seconds |
| Started | Sep 10 06:59:02 AM UTC 24 |
| Finished | Sep 10 07:00:44 AM UTC 24 |
| Peak memory | 593784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182417884 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.1182417884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/64.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.2416023926 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 6863219002 ps |
| CPU time | 98.79 seconds |
| Started | Sep 10 06:59:09 AM UTC 24 |
| Finished | Sep 10 07:00:50 AM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416023926 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.2416023926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.744781510 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 41849328 ps |
| CPU time | 8.6 seconds |
| Started | Sep 10 06:59:00 AM UTC 24 |
| Finished | Sep 10 06:59:10 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744781510 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delays.744781510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/64.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.466893424 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 8608382442 ps |
| CPU time | 311.89 seconds |
| Started | Sep 10 06:59:43 AM UTC 24 |
| Finished | Sep 10 07:05:00 AM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466893424 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.466893424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/64.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.2992347537 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 10661558457 ps |
| CPU time | 366.34 seconds |
| Started | Sep 10 07:00:08 AM UTC 24 |
| Finished | Sep 10 07:06:19 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992347537 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.2992347537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/64.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.1911645022 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 8847044434 ps |
| CPU time | 487.69 seconds |
| Started | Sep 10 07:00:15 AM UTC 24 |
| Finished | Sep 10 07:08:30 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911645022 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_reset_error.1911645022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.543395215 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 325194516 ps |
| CPU time | 44.98 seconds |
| Started | Sep 10 06:59:42 AM UTC 24 |
| Finished | Sep 10 07:00:28 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543395215 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.543395215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/64.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.2295529032 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 1280512916 ps |
| CPU time | 60.98 seconds |
| Started | Sep 10 07:00:50 AM UTC 24 |
| Finished | Sep 10 07:01:53 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295529032 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device.2295529032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/65.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.954231974 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 48388489368 ps |
| CPU time | 740.24 seconds |
| Started | Sep 10 07:00:53 AM UTC 24 |
| Finished | Sep 10 07:13:23 AM UTC 24 |
| Peak memory | 596144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954231974 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device_slow_rsp.954231974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.1109655251 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 94757537 ps |
| CPU time | 6.78 seconds |
| Started | Sep 10 07:01:11 AM UTC 24 |
| Finished | Sep 10 07:01:18 AM UTC 24 |
| Peak memory | 593844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109655251 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_addr.1109655251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.4104102434 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 194819672 ps |
| CPU time | 21.52 seconds |
| Started | Sep 10 07:01:00 AM UTC 24 |
| Finished | Sep 10 07:01:22 AM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104102434 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.4104102434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/65.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.2894349102 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 167902379 ps |
| CPU time | 8.67 seconds |
| Started | Sep 10 07:00:44 AM UTC 24 |
| Finished | Sep 10 07:00:53 AM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894349102 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.2894349102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/65.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.890979067 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 5228390995 ps |
| CPU time | 79.31 seconds |
| Started | Sep 10 07:00:48 AM UTC 24 |
| Finished | Sep 10 07:02:09 AM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890979067 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.890979067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/65.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.294909816 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 13560682578 ps |
| CPU time | 191.23 seconds |
| Started | Sep 10 07:00:52 AM UTC 24 |
| Finished | Sep 10 07:04:07 AM UTC 24 |
| Peak memory | 596092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294909816 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.294909816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/65.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.2739033422 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 591891730 ps |
| CPU time | 56.02 seconds |
| Started | Sep 10 07:00:48 AM UTC 24 |
| Finished | Sep 10 07:01:46 AM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739033422 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_delays.2739033422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/65.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.4196933900 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 2554801204 ps |
| CPU time | 76.11 seconds |
| Started | Sep 10 07:00:55 AM UTC 24 |
| Finished | Sep 10 07:02:13 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196933900 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.4196933900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/65.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.1864272937 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 41856141 ps |
| CPU time | 6.71 seconds |
| Started | Sep 10 07:00:17 AM UTC 24 |
| Finished | Sep 10 07:00:25 AM UTC 24 |
| Peak memory | 593632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864272937 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.1864272937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/65.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.4283892378 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 6340922033 ps |
| CPU time | 63.95 seconds |
| Started | Sep 10 07:00:25 AM UTC 24 |
| Finished | Sep 10 07:01:31 AM UTC 24 |
| Peak memory | 593788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283892378 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.4283892378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/65.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.1243935969 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 6201001786 ps |
| CPU time | 93.35 seconds |
| Started | Sep 10 07:00:37 AM UTC 24 |
| Finished | Sep 10 07:02:13 AM UTC 24 |
| Peak memory | 594008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243935969 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.1243935969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.2812874284 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 41621937 ps |
| CPU time | 8.61 seconds |
| Started | Sep 10 07:00:16 AM UTC 24 |
| Finished | Sep 10 07:00:25 AM UTC 24 |
| Peak memory | 593760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812874284 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delays.2812874284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/65.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.2789955967 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 3538848834 ps |
| CPU time | 116.68 seconds |
| Started | Sep 10 07:01:12 AM UTC 24 |
| Finished | Sep 10 07:03:11 AM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789955967 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.2789955967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/65.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.3481677002 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 10510874941 ps |
| CPU time | 321.39 seconds |
| Started | Sep 10 07:01:17 AM UTC 24 |
| Finished | Sep 10 07:06:43 AM UTC 24 |
| Peak memory | 596156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481677002 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.3481677002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/65.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.3552530067 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 411978984 ps |
| CPU time | 138.95 seconds |
| Started | Sep 10 07:01:14 AM UTC 24 |
| Finished | Sep 10 07:03:35 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552530067 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_rand_reset.3552530067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.3188748639 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 281934853 ps |
| CPU time | 57.23 seconds |
| Started | Sep 10 07:01:21 AM UTC 24 |
| Finished | Sep 10 07:02:20 AM UTC 24 |
| Peak memory | 596076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188748639 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_reset_error.3188748639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.904737384 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 259475455 ps |
| CPU time | 12.76 seconds |
| Started | Sep 10 07:01:05 AM UTC 24 |
| Finished | Sep 10 07:01:19 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904737384 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.904737384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/65.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.775496243 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 2125639913 ps |
| CPU time | 123.2 seconds |
| Started | Sep 10 07:01:59 AM UTC 24 |
| Finished | Sep 10 07:04:05 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775496243 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device.775496243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/66.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.3481970014 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 33798390591 ps |
| CPU time | 503.08 seconds |
| Started | Sep 10 07:02:01 AM UTC 24 |
| Finished | Sep 10 07:10:30 AM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481970014 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device_slow_rsp.3481970014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.2476934435 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 180779481 ps |
| CPU time | 19.15 seconds |
| Started | Sep 10 07:02:15 AM UTC 24 |
| Finished | Sep 10 07:02:35 AM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476934435 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_addr.2476934435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.3144385566 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 2132886988 ps |
| CPU time | 82.85 seconds |
| Started | Sep 10 07:02:14 AM UTC 24 |
| Finished | Sep 10 07:03:39 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144385566 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.3144385566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/66.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.4072135378 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 134089814 ps |
| CPU time | 17.29 seconds |
| Started | Sep 10 07:01:51 AM UTC 24 |
| Finished | Sep 10 07:02:09 AM UTC 24 |
| Peak memory | 596044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072135378 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.4072135378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/66.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.2347536923 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 86270954031 ps |
| CPU time | 896.17 seconds |
| Started | Sep 10 07:01:54 AM UTC 24 |
| Finished | Sep 10 07:17:01 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347536923 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.2347536923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/66.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.3575195819 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 50918566621 ps |
| CPU time | 714.23 seconds |
| Started | Sep 10 07:01:55 AM UTC 24 |
| Finished | Sep 10 07:13:58 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575195819 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.3575195819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/66.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.1176582231 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 359244682 ps |
| CPU time | 42.71 seconds |
| Started | Sep 10 07:01:51 AM UTC 24 |
| Finished | Sep 10 07:02:35 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176582231 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_delays.1176582231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/66.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.543368600 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 242294208 ps |
| CPU time | 13.68 seconds |
| Started | Sep 10 07:02:03 AM UTC 24 |
| Finished | Sep 10 07:02:17 AM UTC 24 |
| Peak memory | 596084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543368600 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.543368600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/66.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.1523920154 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 231087127 ps |
| CPU time | 11.28 seconds |
| Started | Sep 10 07:01:38 AM UTC 24 |
| Finished | Sep 10 07:01:50 AM UTC 24 |
| Peak memory | 593764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523920154 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.1523920154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/66.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.1133585810 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 9896268471 ps |
| CPU time | 99.66 seconds |
| Started | Sep 10 07:01:46 AM UTC 24 |
| Finished | Sep 10 07:03:28 AM UTC 24 |
| Peak memory | 594092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133585810 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.1133585810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/66.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.1663390746 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 6421955560 ps |
| CPU time | 118.27 seconds |
| Started | Sep 10 07:01:47 AM UTC 24 |
| Finished | Sep 10 07:03:47 AM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663390746 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.1663390746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.4206647658 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 35993851 ps |
| CPU time | 8.22 seconds |
| Started | Sep 10 07:01:39 AM UTC 24 |
| Finished | Sep 10 07:01:48 AM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206647658 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delays.4206647658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/66.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.1458345162 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 990016024 ps |
| CPU time | 81.97 seconds |
| Started | Sep 10 07:02:21 AM UTC 24 |
| Finished | Sep 10 07:03:46 AM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458345162 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.1458345162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/66.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.3710108414 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 12002256236 ps |
| CPU time | 401.16 seconds |
| Started | Sep 10 07:02:31 AM UTC 24 |
| Finished | Sep 10 07:09:18 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710108414 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.3710108414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/66.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.1280490880 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 235759667 ps |
| CPU time | 66.2 seconds |
| Started | Sep 10 07:02:30 AM UTC 24 |
| Finished | Sep 10 07:03:38 AM UTC 24 |
| Peak memory | 596136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280490880 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_rand_reset.1280490880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.3280322601 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 53436992 ps |
| CPU time | 29.64 seconds |
| Started | Sep 10 07:02:37 AM UTC 24 |
| Finished | Sep 10 07:03:08 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280322601 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_reset_error.3280322601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.969188728 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 1376761425 ps |
| CPU time | 71.2 seconds |
| Started | Sep 10 07:02:16 AM UTC 24 |
| Finished | Sep 10 07:03:29 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969188728 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.969188728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/66.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.895927428 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 1157341444 ps |
| CPU time | 97.73 seconds |
| Started | Sep 10 07:03:17 AM UTC 24 |
| Finished | Sep 10 07:04:56 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895927428 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device.895927428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/67.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.816473569 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 72920408539 ps |
| CPU time | 1147.24 seconds |
| Started | Sep 10 07:03:19 AM UTC 24 |
| Finished | Sep 10 07:22:39 AM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816473569 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device_slow_rsp.816473569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.3229221547 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 310392668 ps |
| CPU time | 36.03 seconds |
| Started | Sep 10 07:03:46 AM UTC 24 |
| Finished | Sep 10 07:04:23 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229221547 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_addr.3229221547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.2904293058 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 648854852 ps |
| CPU time | 27.48 seconds |
| Started | Sep 10 07:03:36 AM UTC 24 |
| Finished | Sep 10 07:04:05 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904293058 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.2904293058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/67.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.1765771129 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 1740969716 ps |
| CPU time | 51.37 seconds |
| Started | Sep 10 07:02:49 AM UTC 24 |
| Finished | Sep 10 07:03:42 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765771129 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.1765771129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/67.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.808133088 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 68494358420 ps |
| CPU time | 582.6 seconds |
| Started | Sep 10 07:03:03 AM UTC 24 |
| Finished | Sep 10 07:12:53 AM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808133088 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.808133088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/67.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.3664730403 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 20491275485 ps |
| CPU time | 321.13 seconds |
| Started | Sep 10 07:03:16 AM UTC 24 |
| Finished | Sep 10 07:08:42 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664730403 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.3664730403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/67.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.1336013384 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 351744362 ps |
| CPU time | 31.5 seconds |
| Started | Sep 10 07:03:03 AM UTC 24 |
| Finished | Sep 10 07:03:36 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336013384 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_delays.1336013384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/67.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.4127916145 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 601576455 ps |
| CPU time | 45.3 seconds |
| Started | Sep 10 07:03:34 AM UTC 24 |
| Finished | Sep 10 07:04:20 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127916145 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.4127916145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/67.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.275344617 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 153694103 ps |
| CPU time | 10.71 seconds |
| Started | Sep 10 07:02:38 AM UTC 24 |
| Finished | Sep 10 07:02:49 AM UTC 24 |
| Peak memory | 593776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275344617 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.275344617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/67.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.459156637 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 6363038896 ps |
| CPU time | 68.28 seconds |
| Started | Sep 10 07:02:40 AM UTC 24 |
| Finished | Sep 10 07:03:50 AM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459156637 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.459156637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/67.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.2315940322 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 4738266148 ps |
| CPU time | 90.02 seconds |
| Started | Sep 10 07:02:45 AM UTC 24 |
| Finished | Sep 10 07:04:17 AM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315940322 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.2315940322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.247382439 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 51794799 ps |
| CPU time | 9.57 seconds |
| Started | Sep 10 07:02:40 AM UTC 24 |
| Finished | Sep 10 07:02:51 AM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247382439 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delays.247382439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/67.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.1858495804 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 1348771468 ps |
| CPU time | 127.49 seconds |
| Started | Sep 10 07:03:53 AM UTC 24 |
| Finished | Sep 10 07:06:03 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858495804 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.1858495804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/67.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.1435593628 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 3831989929 ps |
| CPU time | 338.78 seconds |
| Started | Sep 10 07:03:58 AM UTC 24 |
| Finished | Sep 10 07:09:42 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435593628 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.1435593628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/67.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.2373324204 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 13696429708 ps |
| CPU time | 679.35 seconds |
| Started | Sep 10 07:03:53 AM UTC 24 |
| Finished | Sep 10 07:15:21 AM UTC 24 |
| Peak memory | 596000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373324204 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_rand_reset.2373324204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.3232889756 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 4086905554 ps |
| CPU time | 270.92 seconds |
| Started | Sep 10 07:03:59 AM UTC 24 |
| Finished | Sep 10 07:08:34 AM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232889756 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_reset_error.3232889756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.1049298299 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 25135666 ps |
| CPU time | 8.07 seconds |
| Started | Sep 10 07:03:40 AM UTC 24 |
| Finished | Sep 10 07:03:49 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049298299 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.1049298299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/67.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.2737882789 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 702494878 ps |
| CPU time | 58.94 seconds |
| Started | Sep 10 07:04:11 AM UTC 24 |
| Finished | Sep 10 07:05:12 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737882789 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device.2737882789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/68.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3449911068 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 117590176940 ps |
| CPU time | 1775.78 seconds |
| Started | Sep 10 07:04:30 AM UTC 24 |
| Finished | Sep 10 07:34:27 AM UTC 24 |
| Peak memory | 598936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449911068 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device_slow_rsp.3449911068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.3927064959 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 70033827 ps |
| CPU time | 8.81 seconds |
| Started | Sep 10 07:04:39 AM UTC 24 |
| Finished | Sep 10 07:04:49 AM UTC 24 |
| Peak memory | 593860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927064959 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_addr.3927064959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.595243090 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 578366160 ps |
| CPU time | 45.16 seconds |
| Started | Sep 10 07:04:35 AM UTC 24 |
| Finished | Sep 10 07:05:22 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595243090 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.595243090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/68.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.457365401 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 490540756 ps |
| CPU time | 19.79 seconds |
| Started | Sep 10 07:04:08 AM UTC 24 |
| Finished | Sep 10 07:04:30 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457365401 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.457365401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/68.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.705312602 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 26885597629 ps |
| CPU time | 280.9 seconds |
| Started | Sep 10 07:04:10 AM UTC 24 |
| Finished | Sep 10 07:08:55 AM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705312602 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.705312602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/68.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.916209219 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 4169792676 ps |
| CPU time | 71.53 seconds |
| Started | Sep 10 07:04:12 AM UTC 24 |
| Finished | Sep 10 07:05:25 AM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916209219 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.916209219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/68.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.3107251936 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 440878153 ps |
| CPU time | 42.34 seconds |
| Started | Sep 10 07:04:12 AM UTC 24 |
| Finished | Sep 10 07:04:55 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107251936 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_delays.3107251936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/68.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.1873488382 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 837382152 ps |
| CPU time | 26.78 seconds |
| Started | Sep 10 07:04:27 AM UTC 24 |
| Finished | Sep 10 07:04:55 AM UTC 24 |
| Peak memory | 595692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873488382 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.1873488382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/68.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.1941046657 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 45105305 ps |
| CPU time | 5.67 seconds |
| Started | Sep 10 07:04:00 AM UTC 24 |
| Finished | Sep 10 07:04:07 AM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941046657 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.1941046657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/68.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.1105820330 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 7780685064 ps |
| CPU time | 104.35 seconds |
| Started | Sep 10 07:04:05 AM UTC 24 |
| Finished | Sep 10 07:05:52 AM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105820330 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.1105820330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/68.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.3789889902 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 6593279799 ps |
| CPU time | 96.35 seconds |
| Started | Sep 10 07:04:07 AM UTC 24 |
| Finished | Sep 10 07:05:45 AM UTC 24 |
| Peak memory | 593944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789889902 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.3789889902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.2553964551 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 42407645 ps |
| CPU time | 9.07 seconds |
| Started | Sep 10 07:04:02 AM UTC 24 |
| Finished | Sep 10 07:04:13 AM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553964551 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delays.2553964551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/68.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.1348569070 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 702184085 ps |
| CPU time | 89.64 seconds |
| Started | Sep 10 07:04:45 AM UTC 24 |
| Finished | Sep 10 07:06:17 AM UTC 24 |
| Peak memory | 596120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348569070 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.1348569070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/68.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.2777584626 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 278640535 ps |
| CPU time | 110.15 seconds |
| Started | Sep 10 07:04:49 AM UTC 24 |
| Finished | Sep 10 07:06:41 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777584626 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_rand_reset.2777584626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.2771811962 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 7086366782 ps |
| CPU time | 617.46 seconds |
| Started | Sep 10 07:04:59 AM UTC 24 |
| Finished | Sep 10 07:15:24 AM UTC 24 |
| Peak memory | 600172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771811962 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_reset_error.2771811962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.1167489089 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 171218814 ps |
| CPU time | 14.98 seconds |
| Started | Sep 10 07:04:35 AM UTC 24 |
| Finished | Sep 10 07:04:52 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167489089 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.1167489089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/68.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.2294987947 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 282977907 ps |
| CPU time | 31.04 seconds |
| Started | Sep 10 07:05:50 AM UTC 24 |
| Finished | Sep 10 07:06:23 AM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294987947 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device.2294987947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/69.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.708432614 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 111951533205 ps |
| CPU time | 1798.35 seconds |
| Started | Sep 10 07:05:53 AM UTC 24 |
| Finished | Sep 10 07:36:12 AM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708432614 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device_slow_rsp.708432614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.1067374516 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 964484966 ps |
| CPU time | 47.08 seconds |
| Started | Sep 10 07:06:20 AM UTC 24 |
| Finished | Sep 10 07:07:09 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067374516 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_addr.1067374516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.1224821586 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 430141985 ps |
| CPU time | 34.55 seconds |
| Started | Sep 10 07:05:57 AM UTC 24 |
| Finished | Sep 10 07:06:33 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224821586 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.1224821586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/69.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.1108383908 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 572200911 ps |
| CPU time | 48.85 seconds |
| Started | Sep 10 07:05:22 AM UTC 24 |
| Finished | Sep 10 07:06:12 AM UTC 24 |
| Peak memory | 595876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108383908 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.1108383908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/69.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.740333214 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 107392905647 ps |
| CPU time | 1081.75 seconds |
| Started | Sep 10 07:05:40 AM UTC 24 |
| Finished | Sep 10 07:23:55 AM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740333214 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.740333214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/69.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.1588688421 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 30645547200 ps |
| CPU time | 451.81 seconds |
| Started | Sep 10 07:05:50 AM UTC 24 |
| Finished | Sep 10 07:13:28 AM UTC 24 |
| Peak memory | 595980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588688421 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.1588688421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/69.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.2859487311 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 496796227 ps |
| CPU time | 56.74 seconds |
| Started | Sep 10 07:05:25 AM UTC 24 |
| Finished | Sep 10 07:06:23 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859487311 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_delays.2859487311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/69.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.698813448 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 867189968 ps |
| CPU time | 35.25 seconds |
| Started | Sep 10 07:05:56 AM UTC 24 |
| Finished | Sep 10 07:06:33 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698813448 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.698813448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/69.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.2313645504 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 187078727 ps |
| CPU time | 9.72 seconds |
| Started | Sep 10 07:05:16 AM UTC 24 |
| Finished | Sep 10 07:05:27 AM UTC 24 |
| Peak memory | 593784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313645504 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.2313645504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/69.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.1969947772 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 8176779797 ps |
| CPU time | 115.03 seconds |
| Started | Sep 10 07:05:23 AM UTC 24 |
| Finished | Sep 10 07:07:21 AM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969947772 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.1969947772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/69.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.2842107477 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 4678894733 ps |
| CPU time | 76.69 seconds |
| Started | Sep 10 07:05:17 AM UTC 24 |
| Finished | Sep 10 07:06:35 AM UTC 24 |
| Peak memory | 593900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842107477 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.2842107477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.398855297 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 50303187 ps |
| CPU time | 7.44 seconds |
| Started | Sep 10 07:05:15 AM UTC 24 |
| Finished | Sep 10 07:05:23 AM UTC 24 |
| Peak memory | 593804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398855297 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delays.398855297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/69.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.2591980438 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 715044942 ps |
| CPU time | 63.59 seconds |
| Started | Sep 10 07:06:23 AM UTC 24 |
| Finished | Sep 10 07:07:28 AM UTC 24 |
| Peak memory | 596052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591980438 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.2591980438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/69.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.1976265120 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 1554305413 ps |
| CPU time | 122.85 seconds |
| Started | Sep 10 07:06:39 AM UTC 24 |
| Finished | Sep 10 07:08:45 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976265120 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.1976265120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/69.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.3416551832 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 12447000092 ps |
| CPU time | 656.5 seconds |
| Started | Sep 10 07:06:31 AM UTC 24 |
| Finished | Sep 10 07:17:37 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416551832 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_rand_reset.3416551832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.129919464 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 354722821 ps |
| CPU time | 124.34 seconds |
| Started | Sep 10 07:06:45 AM UTC 24 |
| Finished | Sep 10 07:08:52 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129919464 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_reset_error.129919464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.3446239480 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 119677697 ps |
| CPU time | 21.19 seconds |
| Started | Sep 10 07:06:14 AM UTC 24 |
| Finished | Sep 10 07:06:36 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446239480 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.3446239480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/69.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.197696496 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 5631204216 ps |
| CPU time | 619.24 seconds |
| Started | Sep 10 05:21:22 AM UTC 24 |
| Finished | Sep 10 05:31:50 AM UTC 24 |
| Peak memory | 664100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=197696496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_mem_rw_with_rand_reset.197696496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.2852239197 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 5890471452 ps |
| CPU time | 626.59 seconds |
| Started | Sep 10 05:21:17 AM UTC 24 |
| Finished | Sep 10 05:31:51 AM UTC 24 |
| Peak memory | 618776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852239197 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.2852239197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.4025291776 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 29452803115 ps |
| CPU time | 3807.4 seconds |
| Started | Sep 10 05:18:23 AM UTC 24 |
| Finished | Sep 10 06:22:37 AM UTC 24 |
| Peak memory | 613956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=4025291776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.chip_same_csr_outstanding.4025291776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.2395367488 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 1492049262 ps |
| CPU time | 83.1 seconds |
| Started | Sep 10 05:19:53 AM UTC 24 |
| Finished | Sep 10 05:21:18 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395367488 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.2395367488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.2669564680 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 50756585097 ps |
| CPU time | 748.18 seconds |
| Started | Sep 10 05:19:56 AM UTC 24 |
| Finished | Sep 10 05:32:33 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669564680 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.2669564680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.3307059043 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 724056366 ps |
| CPU time | 35.37 seconds |
| Started | Sep 10 05:20:19 AM UTC 24 |
| Finished | Sep 10 05:20:56 AM UTC 24 |
| Peak memory | 596092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307059043 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.3307059043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.241701175 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 487847366 ps |
| CPU time | 55.46 seconds |
| Started | Sep 10 05:20:21 AM UTC 24 |
| Finished | Sep 10 05:21:18 AM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241701175 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.241701175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.3143532348 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 1819187735 ps |
| CPU time | 72.11 seconds |
| Started | Sep 10 05:19:12 AM UTC 24 |
| Finished | Sep 10 05:20:26 AM UTC 24 |
| Peak memory | 596088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143532348 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.3143532348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.221602871 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 82096682645 ps |
| CPU time | 813.25 seconds |
| Started | Sep 10 05:19:16 AM UTC 24 |
| Finished | Sep 10 05:32:59 AM UTC 24 |
| Peak memory | 596028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221602871 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.221602871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.3412722768 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 46647631153 ps |
| CPU time | 655.14 seconds |
| Started | Sep 10 05:19:42 AM UTC 24 |
| Finished | Sep 10 05:30:45 AM UTC 24 |
| Peak memory | 596136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412722768 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3412722768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.706866419 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 389803902 ps |
| CPU time | 38.25 seconds |
| Started | Sep 10 05:19:14 AM UTC 24 |
| Finished | Sep 10 05:19:53 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706866419 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.706866419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.574957073 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 131197670 ps |
| CPU time | 17.36 seconds |
| Started | Sep 10 05:20:07 AM UTC 24 |
| Finished | Sep 10 05:20:25 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574957073 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.574957073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.499661037 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 230618763 ps |
| CPU time | 14.12 seconds |
| Started | Sep 10 05:18:33 AM UTC 24 |
| Finished | Sep 10 05:18:48 AM UTC 24 |
| Peak memory | 593904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499661037 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.499661037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.2279502470 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 9823996178 ps |
| CPU time | 154.93 seconds |
| Started | Sep 10 05:18:48 AM UTC 24 |
| Finished | Sep 10 05:21:25 AM UTC 24 |
| Peak memory | 593956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279502470 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2279502470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.554664712 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 2963223211 ps |
| CPU time | 67.02 seconds |
| Started | Sep 10 05:19:11 AM UTC 24 |
| Finished | Sep 10 05:20:20 AM UTC 24 |
| Peak memory | 594156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554664712 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.554664712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.2507500970 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 42611878 ps |
| CPU time | 8.44 seconds |
| Started | Sep 10 05:18:36 AM UTC 24 |
| Finished | Sep 10 05:18:46 AM UTC 24 |
| Peak memory | 593776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507500970 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2507500970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.1066142600 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 477815193 ps |
| CPU time | 69.41 seconds |
| Started | Sep 10 05:20:48 AM UTC 24 |
| Finished | Sep 10 05:21:59 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066142600 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1066142600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.271501304 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 5996589929 ps |
| CPU time | 192.27 seconds |
| Started | Sep 10 05:20:53 AM UTC 24 |
| Finished | Sep 10 05:24:09 AM UTC 24 |
| Peak memory | 596168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271501304 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.271501304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.851712728 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 391837347 ps |
| CPU time | 211.79 seconds |
| Started | Sep 10 05:20:53 AM UTC 24 |
| Finished | Sep 10 05:24:28 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851712728 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.851712728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.3217633626 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 894490605 ps |
| CPU time | 50.34 seconds |
| Started | Sep 10 05:20:21 AM UTC 24 |
| Finished | Sep 10 05:21:13 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217633626 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3217633626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.3936662777 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 1508730530 ps |
| CPU time | 79.85 seconds |
| Started | Sep 10 07:07:02 AM UTC 24 |
| Finished | Sep 10 07:08:24 AM UTC 24 |
| Peak memory | 596064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936662777 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device.3936662777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/70.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.1869359023 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 127435650487 ps |
| CPU time | 1868.73 seconds |
| Started | Sep 10 07:07:09 AM UTC 24 |
| Finished | Sep 10 07:38:39 AM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869359023 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device_slow_rsp.1869359023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.1247416485 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 451644933 ps |
| CPU time | 27.58 seconds |
| Started | Sep 10 07:07:27 AM UTC 24 |
| Finished | Sep 10 07:07:56 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247416485 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_addr.1247416485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.1014900983 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 1646590270 ps |
| CPU time | 50.9 seconds |
| Started | Sep 10 07:07:20 AM UTC 24 |
| Finished | Sep 10 07:08:12 AM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014900983 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.1014900983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/70.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.1740687506 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 56624905 ps |
| CPU time | 8.69 seconds |
| Started | Sep 10 07:06:59 AM UTC 24 |
| Finished | Sep 10 07:07:09 AM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740687506 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.1740687506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/70.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.478922847 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 51063229946 ps |
| CPU time | 494.09 seconds |
| Started | Sep 10 07:07:01 AM UTC 24 |
| Finished | Sep 10 07:15:21 AM UTC 24 |
| Peak memory | 595756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478922847 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.478922847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/70.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.2226186848 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 66098681377 ps |
| CPU time | 1065 seconds |
| Started | Sep 10 07:07:02 AM UTC 24 |
| Finished | Sep 10 07:24:59 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226186848 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.2226186848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/70.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.46604054 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 474505258 ps |
| CPU time | 40.03 seconds |
| Started | Sep 10 07:07:01 AM UTC 24 |
| Finished | Sep 10 07:07:42 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46604054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_delays.46604054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/70.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.3720018868 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 45294754 ps |
| CPU time | 9.29 seconds |
| Started | Sep 10 07:07:09 AM UTC 24 |
| Finished | Sep 10 07:07:20 AM UTC 24 |
| Peak memory | 593808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720018868 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.3720018868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/70.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.777697042 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 156976264 ps |
| CPU time | 7.58 seconds |
| Started | Sep 10 07:06:46 AM UTC 24 |
| Finished | Sep 10 07:06:55 AM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777697042 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.777697042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/70.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.2204899367 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 9896538510 ps |
| CPU time | 120.91 seconds |
| Started | Sep 10 07:06:50 AM UTC 24 |
| Finished | Sep 10 07:08:53 AM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204899367 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.2204899367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/70.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.3814287352 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 3434914495 ps |
| CPU time | 77.59 seconds |
| Started | Sep 10 07:07:00 AM UTC 24 |
| Finished | Sep 10 07:08:19 AM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814287352 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.3814287352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.1536294979 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 49325889 ps |
| CPU time | 8.61 seconds |
| Started | Sep 10 07:06:49 AM UTC 24 |
| Finished | Sep 10 07:06:59 AM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536294979 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delays.1536294979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/70.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.2943568654 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 2542640070 ps |
| CPU time | 95.49 seconds |
| Started | Sep 10 07:07:32 AM UTC 24 |
| Finished | Sep 10 07:09:10 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943568654 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.2943568654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/70.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.979628178 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 2944896314 ps |
| CPU time | 108.26 seconds |
| Started | Sep 10 07:07:34 AM UTC 24 |
| Finished | Sep 10 07:09:24 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979628178 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.979628178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/70.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.3487148657 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 3832872420 ps |
| CPU time | 603 seconds |
| Started | Sep 10 07:07:34 AM UTC 24 |
| Finished | Sep 10 07:17:46 AM UTC 24 |
| Peak memory | 596124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487148657 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_rand_reset.3487148657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.286763118 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 7433831771 ps |
| CPU time | 427.12 seconds |
| Started | Sep 10 07:07:37 AM UTC 24 |
| Finished | Sep 10 07:14:50 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286763118 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_reset_error.286763118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.3649868673 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 1009256154 ps |
| CPU time | 42.48 seconds |
| Started | Sep 10 07:07:22 AM UTC 24 |
| Finished | Sep 10 07:08:07 AM UTC 24 |
| Peak memory | 595980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649868673 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.3649868673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/70.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.2583145433 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 2590714796 ps |
| CPU time | 101.59 seconds |
| Started | Sep 10 07:08:31 AM UTC 24 |
| Finished | Sep 10 07:10:15 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583145433 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device.2583145433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/71.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.2781282452 |
| Short name | T2904 |
| Test name | |
| Test status | |
| Simulation time | 132881972289 ps |
| CPU time | 2258.85 seconds |
| Started | Sep 10 07:08:36 AM UTC 24 |
| Finished | Sep 10 07:46:41 AM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781282452 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device_slow_rsp.2781282452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.4135731119 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 223263848 ps |
| CPU time | 15.35 seconds |
| Started | Sep 10 07:08:56 AM UTC 24 |
| Finished | Sep 10 07:09:13 AM UTC 24 |
| Peak memory | 596072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135731119 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_addr.4135731119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.369238355 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 1029350602 ps |
| CPU time | 33.05 seconds |
| Started | Sep 10 07:08:48 AM UTC 24 |
| Finished | Sep 10 07:09:23 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369238355 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.369238355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/71.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.3256675742 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 2012019262 ps |
| CPU time | 73.47 seconds |
| Started | Sep 10 07:08:09 AM UTC 24 |
| Finished | Sep 10 07:09:25 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256675742 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.3256675742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/71.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.1373594051 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 33303995138 ps |
| CPU time | 338.61 seconds |
| Started | Sep 10 07:08:25 AM UTC 24 |
| Finished | Sep 10 07:14:08 AM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373594051 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.1373594051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/71.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.3941067175 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 45902260257 ps |
| CPU time | 726.9 seconds |
| Started | Sep 10 07:08:29 AM UTC 24 |
| Finished | Sep 10 07:20:45 AM UTC 24 |
| Peak memory | 595964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941067175 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.3941067175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/71.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.130063374 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 340507203 ps |
| CPU time | 30.8 seconds |
| Started | Sep 10 07:08:24 AM UTC 24 |
| Finished | Sep 10 07:08:56 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130063374 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_delays.130063374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/71.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.305981593 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 201694243 ps |
| CPU time | 18.62 seconds |
| Started | Sep 10 07:08:35 AM UTC 24 |
| Finished | Sep 10 07:08:55 AM UTC 24 |
| Peak memory | 596056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305981593 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.305981593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/71.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.2539910913 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 228529412 ps |
| CPU time | 13 seconds |
| Started | Sep 10 07:07:49 AM UTC 24 |
| Finished | Sep 10 07:08:03 AM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539910913 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.2539910913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/71.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.867535582 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 6726130323 ps |
| CPU time | 109.9 seconds |
| Started | Sep 10 07:07:56 AM UTC 24 |
| Finished | Sep 10 07:09:48 AM UTC 24 |
| Peak memory | 593836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867535582 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.867535582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/71.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.1243035734 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 6176416633 ps |
| CPU time | 98.84 seconds |
| Started | Sep 10 07:07:58 AM UTC 24 |
| Finished | Sep 10 07:09:39 AM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243035734 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.1243035734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.2964351158 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 45232655 ps |
| CPU time | 9.01 seconds |
| Started | Sep 10 07:07:49 AM UTC 24 |
| Finished | Sep 10 07:07:59 AM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964351158 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delays.2964351158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/71.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.597342367 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 1851130397 ps |
| CPU time | 154.36 seconds |
| Started | Sep 10 07:08:59 AM UTC 24 |
| Finished | Sep 10 07:11:36 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597342367 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.597342367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/71.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.1682892326 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 15454885474 ps |
| CPU time | 438.42 seconds |
| Started | Sep 10 07:09:10 AM UTC 24 |
| Finished | Sep 10 07:16:34 AM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682892326 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.1682892326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/71.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.2642055305 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 890563578 ps |
| CPU time | 287.15 seconds |
| Started | Sep 10 07:09:00 AM UTC 24 |
| Finished | Sep 10 07:13:51 AM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642055305 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_rand_reset.2642055305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.189641990 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 186386381 ps |
| CPU time | 27.83 seconds |
| Started | Sep 10 07:08:46 AM UTC 24 |
| Finished | Sep 10 07:09:15 AM UTC 24 |
| Peak memory | 596036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189641990 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.189641990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/71.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.785254533 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 2337141683 ps |
| CPU time | 100.08 seconds |
| Started | Sep 10 07:09:39 AM UTC 24 |
| Finished | Sep 10 07:11:22 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785254533 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device.785254533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/72.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.3648424253 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 104241847417 ps |
| CPU time | 1663.36 seconds |
| Started | Sep 10 07:09:41 AM UTC 24 |
| Finished | Sep 10 07:37:44 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648424253 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device_slow_rsp.3648424253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.3300561173 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 420192169 ps |
| CPU time | 23.77 seconds |
| Started | Sep 10 07:09:47 AM UTC 24 |
| Finished | Sep 10 07:10:12 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300561173 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_addr.3300561173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.367355172 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 913654575 ps |
| CPU time | 40.9 seconds |
| Started | Sep 10 07:09:43 AM UTC 24 |
| Finished | Sep 10 07:10:25 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367355172 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.367355172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/72.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.4106006626 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 85181821 ps |
| CPU time | 7.94 seconds |
| Started | Sep 10 07:09:22 AM UTC 24 |
| Finished | Sep 10 07:09:31 AM UTC 24 |
| Peak memory | 596040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106006626 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.4106006626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/72.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.4019468202 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 7143186380 ps |
| CPU time | 71.18 seconds |
| Started | Sep 10 07:09:35 AM UTC 24 |
| Finished | Sep 10 07:10:48 AM UTC 24 |
| Peak memory | 594112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019468202 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.4019468202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/72.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.619643767 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 71357975782 ps |
| CPU time | 1229.53 seconds |
| Started | Sep 10 07:09:37 AM UTC 24 |
| Finished | Sep 10 07:30:21 AM UTC 24 |
| Peak memory | 596052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619643767 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.619643767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/72.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.694603779 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 284434689 ps |
| CPU time | 28.89 seconds |
| Started | Sep 10 07:09:24 AM UTC 24 |
| Finished | Sep 10 07:09:55 AM UTC 24 |
| Peak memory | 596040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694603779 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_delays.694603779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/72.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.536760435 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 2236013561 ps |
| CPU time | 54.16 seconds |
| Started | Sep 10 07:09:44 AM UTC 24 |
| Finished | Sep 10 07:10:40 AM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536760435 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.536760435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/72.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.1561899436 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 171557882 ps |
| CPU time | 10.34 seconds |
| Started | Sep 10 07:09:12 AM UTC 24 |
| Finished | Sep 10 07:09:24 AM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561899436 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.1561899436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/72.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.1555579570 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 7338097038 ps |
| CPU time | 71.47 seconds |
| Started | Sep 10 07:09:20 AM UTC 24 |
| Finished | Sep 10 07:10:33 AM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555579570 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.1555579570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/72.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.411547746 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 6464274083 ps |
| CPU time | 108.15 seconds |
| Started | Sep 10 07:09:22 AM UTC 24 |
| Finished | Sep 10 07:11:12 AM UTC 24 |
| Peak memory | 593780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411547746 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.411547746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.778981912 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 42466053 ps |
| CPU time | 8.48 seconds |
| Started | Sep 10 07:09:19 AM UTC 24 |
| Finished | Sep 10 07:09:28 AM UTC 24 |
| Peak memory | 593812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778981912 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delays.778981912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/72.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.1431007619 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 2398543222 ps |
| CPU time | 178.86 seconds |
| Started | Sep 10 07:09:49 AM UTC 24 |
| Finished | Sep 10 07:12:51 AM UTC 24 |
| Peak memory | 596120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431007619 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.1431007619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/72.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.2023773286 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 1122036994 ps |
| CPU time | 67.31 seconds |
| Started | Sep 10 07:09:53 AM UTC 24 |
| Finished | Sep 10 07:11:02 AM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023773286 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.2023773286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/72.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.62775698 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 4304830803 ps |
| CPU time | 436.37 seconds |
| Started | Sep 10 07:09:48 AM UTC 24 |
| Finished | Sep 10 07:17:11 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62775698 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_rand_reset.62775698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.397121302 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 6864148100 ps |
| CPU time | 586.1 seconds |
| Started | Sep 10 07:09:58 AM UTC 24 |
| Finished | Sep 10 07:19:52 AM UTC 24 |
| Peak memory | 600104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397121302 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_reset_error.397121302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.2283531104 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 216734307 ps |
| CPU time | 11.8 seconds |
| Started | Sep 10 07:09:51 AM UTC 24 |
| Finished | Sep 10 07:10:03 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283531104 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.2283531104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/72.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.3545941841 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 4285220128 ps |
| CPU time | 165.91 seconds |
| Started | Sep 10 07:10:41 AM UTC 24 |
| Finished | Sep 10 07:13:30 AM UTC 24 |
| Peak memory | 596032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545941841 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device.3545941841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/73.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.2809656386 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 117805018332 ps |
| CPU time | 1808.22 seconds |
| Started | Sep 10 07:10:42 AM UTC 24 |
| Finished | Sep 10 07:41:11 AM UTC 24 |
| Peak memory | 596204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809656386 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device_slow_rsp.2809656386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.2528383213 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 233720351 ps |
| CPU time | 25.42 seconds |
| Started | Sep 10 07:10:58 AM UTC 24 |
| Finished | Sep 10 07:11:24 AM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528383213 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_addr.2528383213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.1534793843 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 550225694 ps |
| CPU time | 39.49 seconds |
| Started | Sep 10 07:10:54 AM UTC 24 |
| Finished | Sep 10 07:11:35 AM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534793843 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.1534793843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/73.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.3922420502 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 1086354291 ps |
| CPU time | 31.95 seconds |
| Started | Sep 10 07:10:17 AM UTC 24 |
| Finished | Sep 10 07:10:50 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922420502 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.3922420502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/73.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.101109983 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 25320705728 ps |
| CPU time | 225.12 seconds |
| Started | Sep 10 07:10:32 AM UTC 24 |
| Finished | Sep 10 07:14:20 AM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101109983 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.101109983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/73.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.3670093952 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 46148505894 ps |
| CPU time | 631.94 seconds |
| Started | Sep 10 07:10:36 AM UTC 24 |
| Finished | Sep 10 07:21:16 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670093952 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.3670093952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/73.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.3287795944 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 332174653 ps |
| CPU time | 33.97 seconds |
| Started | Sep 10 07:10:23 AM UTC 24 |
| Finished | Sep 10 07:10:58 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287795944 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_delays.3287795944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/73.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.4063424686 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 215717204 ps |
| CPU time | 11.01 seconds |
| Started | Sep 10 07:10:45 AM UTC 24 |
| Finished | Sep 10 07:10:58 AM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063424686 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.4063424686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/73.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.1306245182 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 52434433 ps |
| CPU time | 9.39 seconds |
| Started | Sep 10 07:10:02 AM UTC 24 |
| Finished | Sep 10 07:10:13 AM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306245182 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.1306245182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/73.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.1950809160 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 9630274596 ps |
| CPU time | 100.73 seconds |
| Started | Sep 10 07:10:16 AM UTC 24 |
| Finished | Sep 10 07:11:59 AM UTC 24 |
| Peak memory | 593704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950809160 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.1950809160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/73.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.2432932876 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 6491549409 ps |
| CPU time | 96.65 seconds |
| Started | Sep 10 07:10:17 AM UTC 24 |
| Finished | Sep 10 07:11:55 AM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432932876 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.2432932876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.3882126412 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 48467413 ps |
| CPU time | 9.16 seconds |
| Started | Sep 10 07:10:07 AM UTC 24 |
| Finished | Sep 10 07:10:17 AM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882126412 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delays.3882126412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/73.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.2278976995 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 4614169445 ps |
| CPU time | 344.61 seconds |
| Started | Sep 10 07:11:08 AM UTC 24 |
| Finished | Sep 10 07:16:58 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278976995 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.2278976995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/73.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.1941907157 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 2891774191 ps |
| CPU time | 189.78 seconds |
| Started | Sep 10 07:11:14 AM UTC 24 |
| Finished | Sep 10 07:14:27 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941907157 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.1941907157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/73.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.1775855509 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 235043435 ps |
| CPU time | 147.67 seconds |
| Started | Sep 10 07:11:16 AM UTC 24 |
| Finished | Sep 10 07:13:47 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775855509 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_rand_reset.1775855509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.1466157331 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 2290767155 ps |
| CPU time | 295.62 seconds |
| Started | Sep 10 07:11:24 AM UTC 24 |
| Finished | Sep 10 07:16:24 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466157331 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_reset_error.1466157331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.629882483 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 396921509 ps |
| CPU time | 19.27 seconds |
| Started | Sep 10 07:10:58 AM UTC 24 |
| Finished | Sep 10 07:11:18 AM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629882483 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.629882483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/73.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.1982078576 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 818923353 ps |
| CPU time | 56.86 seconds |
| Started | Sep 10 07:11:55 AM UTC 24 |
| Finished | Sep 10 07:12:53 AM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982078576 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device.1982078576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/74.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.901036772 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 64664316957 ps |
| CPU time | 904.25 seconds |
| Started | Sep 10 07:11:56 AM UTC 24 |
| Finished | Sep 10 07:27:11 AM UTC 24 |
| Peak memory | 596012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901036772 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device_slow_rsp.901036772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.415128011 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 828537533 ps |
| CPU time | 40.17 seconds |
| Started | Sep 10 07:12:20 AM UTC 24 |
| Finished | Sep 10 07:13:01 AM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415128011 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_addr.415128011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.48523181 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 539185226 ps |
| CPU time | 23.24 seconds |
| Started | Sep 10 07:12:01 AM UTC 24 |
| Finished | Sep 10 07:12:25 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48523181 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.48523181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/74.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.2438605225 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 1294947182 ps |
| CPU time | 43.94 seconds |
| Started | Sep 10 07:11:42 AM UTC 24 |
| Finished | Sep 10 07:12:27 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438605225 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.2438605225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/74.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.1970885086 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 54368959704 ps |
| CPU time | 620.89 seconds |
| Started | Sep 10 07:11:44 AM UTC 24 |
| Finished | Sep 10 07:22:13 AM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970885086 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.1970885086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/74.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.3942370466 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 2784830700 ps |
| CPU time | 35.1 seconds |
| Started | Sep 10 07:11:51 AM UTC 24 |
| Finished | Sep 10 07:12:27 AM UTC 24 |
| Peak memory | 594080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942370466 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.3942370466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/74.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.2623432087 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 41676382 ps |
| CPU time | 7.88 seconds |
| Started | Sep 10 07:11:51 AM UTC 24 |
| Finished | Sep 10 07:11:59 AM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623432087 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_delays.2623432087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/74.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.1386524874 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 215863841 ps |
| CPU time | 20.52 seconds |
| Started | Sep 10 07:11:59 AM UTC 24 |
| Finished | Sep 10 07:12:21 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386524874 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.1386524874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/74.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.3601471422 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 54449116 ps |
| CPU time | 6.1 seconds |
| Started | Sep 10 07:11:21 AM UTC 24 |
| Finished | Sep 10 07:11:28 AM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601471422 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.3601471422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/74.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.3589141341 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 8441011953 ps |
| CPU time | 83.71 seconds |
| Started | Sep 10 07:11:30 AM UTC 24 |
| Finished | Sep 10 07:12:56 AM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589141341 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.3589141341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/74.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.654630527 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 4511812548 ps |
| CPU time | 103.23 seconds |
| Started | Sep 10 07:11:40 AM UTC 24 |
| Finished | Sep 10 07:13:25 AM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654630527 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.654630527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.2837206981 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 46335284 ps |
| CPU time | 8.58 seconds |
| Started | Sep 10 07:11:23 AM UTC 24 |
| Finished | Sep 10 07:11:32 AM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837206981 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delays.2837206981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/74.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.1657087898 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 414201587 ps |
| CPU time | 46.92 seconds |
| Started | Sep 10 07:12:22 AM UTC 24 |
| Finished | Sep 10 07:13:10 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657087898 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.1657087898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/74.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.1360612465 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 1387894927 ps |
| CPU time | 89.41 seconds |
| Started | Sep 10 07:12:27 AM UTC 24 |
| Finished | Sep 10 07:13:58 AM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360612465 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.1360612465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/74.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.3216147122 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 2497405470 ps |
| CPU time | 240.06 seconds |
| Started | Sep 10 07:12:26 AM UTC 24 |
| Finished | Sep 10 07:16:30 AM UTC 24 |
| Peak memory | 595996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216147122 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_rand_reset.3216147122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3916628088 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 7166899551 ps |
| CPU time | 359.54 seconds |
| Started | Sep 10 07:12:46 AM UTC 24 |
| Finished | Sep 10 07:18:51 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916628088 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_reset_error.3916628088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.562111469 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 93708382 ps |
| CPU time | 17.13 seconds |
| Started | Sep 10 07:12:09 AM UTC 24 |
| Finished | Sep 10 07:12:27 AM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562111469 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.562111469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/74.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.3598750261 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 3513444218 ps |
| CPU time | 154.64 seconds |
| Started | Sep 10 07:13:25 AM UTC 24 |
| Finished | Sep 10 07:16:03 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598750261 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device.3598750261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/75.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.393056882 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 130779289993 ps |
| CPU time | 1729.31 seconds |
| Started | Sep 10 07:13:30 AM UTC 24 |
| Finished | Sep 10 07:42:39 AM UTC 24 |
| Peak memory | 596664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393056882 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device_slow_rsp.393056882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.3435870621 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 237551793 ps |
| CPU time | 17.42 seconds |
| Started | Sep 10 07:13:48 AM UTC 24 |
| Finished | Sep 10 07:14:06 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435870621 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_addr.3435870621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.26226458 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 1000164023 ps |
| CPU time | 33.26 seconds |
| Started | Sep 10 07:13:31 AM UTC 24 |
| Finished | Sep 10 07:14:06 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26226458 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.26226458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/75.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.3176273199 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 203828470 ps |
| CPU time | 24.54 seconds |
| Started | Sep 10 07:13:19 AM UTC 24 |
| Finished | Sep 10 07:13:45 AM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176273199 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.3176273199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/75.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.3491570163 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 89711064480 ps |
| CPU time | 1061.4 seconds |
| Started | Sep 10 07:13:21 AM UTC 24 |
| Finished | Sep 10 07:31:15 AM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491570163 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.3491570163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/75.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.2346054178 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 37462912748 ps |
| CPU time | 496.28 seconds |
| Started | Sep 10 07:13:23 AM UTC 24 |
| Finished | Sep 10 07:21:46 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346054178 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.2346054178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/75.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.3873589704 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 211354622 ps |
| CPU time | 23.88 seconds |
| Started | Sep 10 07:13:22 AM UTC 24 |
| Finished | Sep 10 07:13:47 AM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873589704 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_delays.3873589704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/75.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.391519324 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 77222839 ps |
| CPU time | 11.59 seconds |
| Started | Sep 10 07:13:32 AM UTC 24 |
| Finished | Sep 10 07:13:44 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391519324 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.391519324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/75.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.2481234562 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 157702302 ps |
| CPU time | 11.22 seconds |
| Started | Sep 10 07:12:51 AM UTC 24 |
| Finished | Sep 10 07:13:04 AM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481234562 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.2481234562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/75.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.378160335 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 9827190622 ps |
| CPU time | 106.43 seconds |
| Started | Sep 10 07:12:53 AM UTC 24 |
| Finished | Sep 10 07:14:41 AM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378160335 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.378160335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/75.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.983175810 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 5515483416 ps |
| CPU time | 88.77 seconds |
| Started | Sep 10 07:12:54 AM UTC 24 |
| Finished | Sep 10 07:14:24 AM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983175810 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.983175810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.2423293192 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 50359512 ps |
| CPU time | 9.26 seconds |
| Started | Sep 10 07:12:47 AM UTC 24 |
| Finished | Sep 10 07:12:57 AM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423293192 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delays.2423293192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/75.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.2595628097 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 4497854702 ps |
| CPU time | 174.02 seconds |
| Started | Sep 10 07:13:54 AM UTC 24 |
| Finished | Sep 10 07:16:51 AM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595628097 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.2595628097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/75.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.913462959 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 899103784 ps |
| CPU time | 38.32 seconds |
| Started | Sep 10 07:13:58 AM UTC 24 |
| Finished | Sep 10 07:14:38 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913462959 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.913462959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/75.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.1545529339 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 1264581753 ps |
| CPU time | 229.14 seconds |
| Started | Sep 10 07:13:53 AM UTC 24 |
| Finished | Sep 10 07:17:45 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545529339 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_rand_reset.1545529339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.3154089733 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 5020590490 ps |
| CPU time | 284.14 seconds |
| Started | Sep 10 07:14:10 AM UTC 24 |
| Finished | Sep 10 07:18:59 AM UTC 24 |
| Peak memory | 596004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154089733 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_reset_error.3154089733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.3824828470 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 1310386980 ps |
| CPU time | 62.74 seconds |
| Started | Sep 10 07:13:34 AM UTC 24 |
| Finished | Sep 10 07:14:38 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824828470 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.3824828470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/75.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.3383304334 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 576063758 ps |
| CPU time | 50.42 seconds |
| Started | Sep 10 07:14:35 AM UTC 24 |
| Finished | Sep 10 07:15:27 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383304334 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device.3383304334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/76.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.1596339514 |
| Short name | T2914 |
| Test name | |
| Test status | |
| Simulation time | 132284821134 ps |
| CPU time | 2080.81 seconds |
| Started | Sep 10 07:14:35 AM UTC 24 |
| Finished | Sep 10 07:49:40 AM UTC 24 |
| Peak memory | 599004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596339514 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device_slow_rsp.1596339514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.1318009429 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 604276377 ps |
| CPU time | 33.14 seconds |
| Started | Sep 10 07:14:53 AM UTC 24 |
| Finished | Sep 10 07:15:27 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318009429 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_addr.1318009429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.1609331575 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 2286661616 ps |
| CPU time | 62.78 seconds |
| Started | Sep 10 07:14:46 AM UTC 24 |
| Finished | Sep 10 07:15:51 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609331575 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.1609331575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/76.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.571042208 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 1099297449 ps |
| CPU time | 45.01 seconds |
| Started | Sep 10 07:14:24 AM UTC 24 |
| Finished | Sep 10 07:15:10 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571042208 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.571042208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/76.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.3964668351 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 51082827843 ps |
| CPU time | 579.67 seconds |
| Started | Sep 10 07:14:34 AM UTC 24 |
| Finished | Sep 10 07:24:21 AM UTC 24 |
| Peak memory | 596108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964668351 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.3964668351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/76.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.1250733619 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 39626542289 ps |
| CPU time | 609.3 seconds |
| Started | Sep 10 07:14:33 AM UTC 24 |
| Finished | Sep 10 07:24:50 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250733619 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.1250733619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/76.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.1158654266 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 234930864 ps |
| CPU time | 30 seconds |
| Started | Sep 10 07:14:24 AM UTC 24 |
| Finished | Sep 10 07:14:56 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158654266 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_delays.1158654266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/76.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.1626016535 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 447419154 ps |
| CPU time | 14.1 seconds |
| Started | Sep 10 07:14:48 AM UTC 24 |
| Finished | Sep 10 07:15:03 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626016535 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.1626016535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/76.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.946752769 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 63479368 ps |
| CPU time | 6.66 seconds |
| Started | Sep 10 07:14:13 AM UTC 24 |
| Finished | Sep 10 07:14:20 AM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946752769 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.946752769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/76.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.425941631 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 6608898307 ps |
| CPU time | 62.02 seconds |
| Started | Sep 10 07:14:08 AM UTC 24 |
| Finished | Sep 10 07:15:12 AM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425941631 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.425941631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/76.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.2734770134 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 5292572400 ps |
| CPU time | 74.89 seconds |
| Started | Sep 10 07:14:20 AM UTC 24 |
| Finished | Sep 10 07:15:37 AM UTC 24 |
| Peak memory | 593884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734770134 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.2734770134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.866097320 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 46917604 ps |
| CPU time | 9.25 seconds |
| Started | Sep 10 07:14:11 AM UTC 24 |
| Finished | Sep 10 07:14:22 AM UTC 24 |
| Peak memory | 594004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866097320 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays.866097320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/76.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.2329370037 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 4208476986 ps |
| CPU time | 346.37 seconds |
| Started | Sep 10 07:14:49 AM UTC 24 |
| Finished | Sep 10 07:20:41 AM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329370037 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.2329370037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/76.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.618646283 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 1588902936 ps |
| CPU time | 75.62 seconds |
| Started | Sep 10 07:15:04 AM UTC 24 |
| Finished | Sep 10 07:16:21 AM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618646283 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.618646283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/76.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.635216161 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 12791626122 ps |
| CPU time | 623.38 seconds |
| Started | Sep 10 07:15:05 AM UTC 24 |
| Finished | Sep 10 07:25:36 AM UTC 24 |
| Peak memory | 596032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635216161 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_rand_reset.635216161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.3740603765 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 1743063191 ps |
| CPU time | 254.77 seconds |
| Started | Sep 10 07:15:09 AM UTC 24 |
| Finished | Sep 10 07:19:28 AM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740603765 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_reset_error.3740603765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.1129012231 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 262236801 ps |
| CPU time | 39.08 seconds |
| Started | Sep 10 07:14:49 AM UTC 24 |
| Finished | Sep 10 07:15:30 AM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129012231 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.1129012231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/76.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.3124459163 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 1715016616 ps |
| CPU time | 80.5 seconds |
| Started | Sep 10 07:15:45 AM UTC 24 |
| Finished | Sep 10 07:17:08 AM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124459163 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device.3124459163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/77.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.1236683339 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 10198712199 ps |
| CPU time | 135.29 seconds |
| Started | Sep 10 07:15:50 AM UTC 24 |
| Finished | Sep 10 07:18:08 AM UTC 24 |
| Peak memory | 593992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236683339 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device_slow_rsp.1236683339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.3568503248 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 336808240 ps |
| CPU time | 46.41 seconds |
| Started | Sep 10 07:15:56 AM UTC 24 |
| Finished | Sep 10 07:16:44 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568503248 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_addr.3568503248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.2040027289 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 580289826 ps |
| CPU time | 39.92 seconds |
| Started | Sep 10 07:15:53 AM UTC 24 |
| Finished | Sep 10 07:16:34 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040027289 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.2040027289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/77.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.3848589456 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 543645409 ps |
| CPU time | 55.41 seconds |
| Started | Sep 10 07:15:31 AM UTC 24 |
| Finished | Sep 10 07:16:28 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848589456 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.3848589456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/77.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.2425058642 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 77549305805 ps |
| CPU time | 772.85 seconds |
| Started | Sep 10 07:15:36 AM UTC 24 |
| Finished | Sep 10 07:28:38 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425058642 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.2425058642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/77.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.1121605460 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 56781131648 ps |
| CPU time | 860.82 seconds |
| Started | Sep 10 07:15:42 AM UTC 24 |
| Finished | Sep 10 07:30:14 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121605460 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.1121605460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/77.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.418466582 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 201927302 ps |
| CPU time | 24.08 seconds |
| Started | Sep 10 07:15:37 AM UTC 24 |
| Finished | Sep 10 07:16:02 AM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418466582 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_delays.418466582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/77.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.1314886889 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 671669419 ps |
| CPU time | 24.85 seconds |
| Started | Sep 10 07:15:54 AM UTC 24 |
| Finished | Sep 10 07:16:20 AM UTC 24 |
| Peak memory | 595684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314886889 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.1314886889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/77.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.1993609720 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 209439910 ps |
| CPU time | 12.54 seconds |
| Started | Sep 10 07:15:14 AM UTC 24 |
| Finished | Sep 10 07:15:28 AM UTC 24 |
| Peak memory | 593908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993609720 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.1993609720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/77.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.2361365565 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 7732106156 ps |
| CPU time | 100.15 seconds |
| Started | Sep 10 07:15:23 AM UTC 24 |
| Finished | Sep 10 07:17:05 AM UTC 24 |
| Peak memory | 594012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361365565 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.2361365565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/77.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.1364706476 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 5226642629 ps |
| CPU time | 82.09 seconds |
| Started | Sep 10 07:15:32 AM UTC 24 |
| Finished | Sep 10 07:16:56 AM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364706476 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.1364706476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.4268834314 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 38500997 ps |
| CPU time | 8.43 seconds |
| Started | Sep 10 07:15:19 AM UTC 24 |
| Finished | Sep 10 07:15:28 AM UTC 24 |
| Peak memory | 594032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268834314 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delays.4268834314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/77.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.1780351019 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 1765800844 ps |
| CPU time | 49.73 seconds |
| Started | Sep 10 07:15:53 AM UTC 24 |
| Finished | Sep 10 07:16:44 AM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780351019 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.1780351019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/77.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.1859520916 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 5326443817 ps |
| CPU time | 167.78 seconds |
| Started | Sep 10 07:16:01 AM UTC 24 |
| Finished | Sep 10 07:18:51 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859520916 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.1859520916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/77.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.2652657350 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 94549466 ps |
| CPU time | 16.88 seconds |
| Started | Sep 10 07:16:04 AM UTC 24 |
| Finished | Sep 10 07:16:22 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652657350 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_rand_reset.2652657350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.2110807252 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 5912423115 ps |
| CPU time | 277.87 seconds |
| Started | Sep 10 07:16:16 AM UTC 24 |
| Finished | Sep 10 07:20:58 AM UTC 24 |
| Peak memory | 596000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110807252 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_reset_error.2110807252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.469479660 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 1205601359 ps |
| CPU time | 55.83 seconds |
| Started | Sep 10 07:15:55 AM UTC 24 |
| Finished | Sep 10 07:16:53 AM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469479660 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.469479660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/77.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.1718170052 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 611130433 ps |
| CPU time | 48.19 seconds |
| Started | Sep 10 07:17:02 AM UTC 24 |
| Finished | Sep 10 07:17:52 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718170052 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device.1718170052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/78.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.1331863786 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 37250841204 ps |
| CPU time | 528.41 seconds |
| Started | Sep 10 07:17:01 AM UTC 24 |
| Finished | Sep 10 07:25:56 AM UTC 24 |
| Peak memory | 596072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331863786 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device_slow_rsp.1331863786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.3228347183 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 1251211906 ps |
| CPU time | 44.6 seconds |
| Started | Sep 10 07:17:10 AM UTC 24 |
| Finished | Sep 10 07:17:56 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228347183 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_addr.3228347183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.2641458470 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 245834087 ps |
| CPU time | 21.85 seconds |
| Started | Sep 10 07:17:04 AM UTC 24 |
| Finished | Sep 10 07:17:27 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641458470 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.2641458470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/78.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.3164268198 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 1914489449 ps |
| CPU time | 86.18 seconds |
| Started | Sep 10 07:16:49 AM UTC 24 |
| Finished | Sep 10 07:18:17 AM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164268198 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.3164268198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/78.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_large_delays.3776253438 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 93655217496 ps |
| CPU time | 1065.02 seconds |
| Started | Sep 10 07:16:56 AM UTC 24 |
| Finished | Sep 10 07:34:54 AM UTC 24 |
| Peak memory | 596040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776253438 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.3776253438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/78.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.307173215 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 27249846729 ps |
| CPU time | 401.5 seconds |
| Started | Sep 10 07:16:58 AM UTC 24 |
| Finished | Sep 10 07:23:45 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307173215 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.307173215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/78.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.2088543549 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 296070889 ps |
| CPU time | 23.7 seconds |
| Started | Sep 10 07:16:51 AM UTC 24 |
| Finished | Sep 10 07:17:16 AM UTC 24 |
| Peak memory | 596116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088543549 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_delays.2088543549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/78.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.443827434 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 178510913 ps |
| CPU time | 15.47 seconds |
| Started | Sep 10 07:17:00 AM UTC 24 |
| Finished | Sep 10 07:17:17 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443827434 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.443827434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/78.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.4052332858 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 48366475 ps |
| CPU time | 9.17 seconds |
| Started | Sep 10 07:16:28 AM UTC 24 |
| Finished | Sep 10 07:16:38 AM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052332858 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.4052332858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/78.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.470554105 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 9483033690 ps |
| CPU time | 95.1 seconds |
| Started | Sep 10 07:16:46 AM UTC 24 |
| Finished | Sep 10 07:18:23 AM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470554105 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.470554105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/78.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.1890349591 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 5146145840 ps |
| CPU time | 74.61 seconds |
| Started | Sep 10 07:16:48 AM UTC 24 |
| Finished | Sep 10 07:18:04 AM UTC 24 |
| Peak memory | 593976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890349591 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.1890349591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.954974065 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 38487164 ps |
| CPU time | 7.59 seconds |
| Started | Sep 10 07:16:32 AM UTC 24 |
| Finished | Sep 10 07:16:40 AM UTC 24 |
| Peak memory | 593876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954974065 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delays.954974065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/78.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.1347545232 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 4185120911 ps |
| CPU time | 136.26 seconds |
| Started | Sep 10 07:17:08 AM UTC 24 |
| Finished | Sep 10 07:19:26 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347545232 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.1347545232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/78.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.1253952483 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 2596733810 ps |
| CPU time | 211.01 seconds |
| Started | Sep 10 07:17:18 AM UTC 24 |
| Finished | Sep 10 07:20:52 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253952483 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.1253952483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/78.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.396295122 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 5029992726 ps |
| CPU time | 667.38 seconds |
| Started | Sep 10 07:17:16 AM UTC 24 |
| Finished | Sep 10 07:28:32 AM UTC 24 |
| Peak memory | 596012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396295122 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_rand_reset.396295122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1055753499 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 206361537 ps |
| CPU time | 53.53 seconds |
| Started | Sep 10 07:17:21 AM UTC 24 |
| Finished | Sep 10 07:18:16 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055753499 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_reset_error.1055753499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.764523082 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 923205794 ps |
| CPU time | 32.55 seconds |
| Started | Sep 10 07:17:05 AM UTC 24 |
| Finished | Sep 10 07:17:39 AM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764523082 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.764523082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/78.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.1062991332 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 809165554 ps |
| CPU time | 48.04 seconds |
| Started | Sep 10 07:17:53 AM UTC 24 |
| Finished | Sep 10 07:18:42 AM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062991332 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device.1062991332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/79.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.1875896015 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 17886918960 ps |
| CPU time | 299.31 seconds |
| Started | Sep 10 07:17:59 AM UTC 24 |
| Finished | Sep 10 07:23:02 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875896015 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device_slow_rsp.1875896015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.337259605 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 571550708 ps |
| CPU time | 29 seconds |
| Started | Sep 10 07:18:11 AM UTC 24 |
| Finished | Sep 10 07:18:41 AM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337259605 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_addr.337259605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.536790117 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 2216943422 ps |
| CPU time | 68.75 seconds |
| Started | Sep 10 07:18:03 AM UTC 24 |
| Finished | Sep 10 07:19:14 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536790117 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.536790117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/79.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.3599231793 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 2217778066 ps |
| CPU time | 78.09 seconds |
| Started | Sep 10 07:17:35 AM UTC 24 |
| Finished | Sep 10 07:18:55 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599231793 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.3599231793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/79.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_large_delays.3947729552 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 48639028243 ps |
| CPU time | 435.74 seconds |
| Started | Sep 10 07:17:45 AM UTC 24 |
| Finished | Sep 10 07:25:06 AM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947729552 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.3947729552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/79.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_slow_rsp.3588268151 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 36391844117 ps |
| CPU time | 606.14 seconds |
| Started | Sep 10 07:17:43 AM UTC 24 |
| Finished | Sep 10 07:27:57 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588268151 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.3588268151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/79.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.2752129059 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 483700833 ps |
| CPU time | 41.87 seconds |
| Started | Sep 10 07:17:39 AM UTC 24 |
| Finished | Sep 10 07:18:22 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752129059 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_delays.2752129059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/79.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.4259899611 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 333458929 ps |
| CPU time | 25.41 seconds |
| Started | Sep 10 07:17:57 AM UTC 24 |
| Finished | Sep 10 07:18:24 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259899611 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.4259899611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/79.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.2284336010 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 121777516 ps |
| CPU time | 10.16 seconds |
| Started | Sep 10 07:17:20 AM UTC 24 |
| Finished | Sep 10 07:17:31 AM UTC 24 |
| Peak memory | 593780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284336010 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.2284336010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/79.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.1953052227 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 10809762733 ps |
| CPU time | 117.36 seconds |
| Started | Sep 10 07:17:27 AM UTC 24 |
| Finished | Sep 10 07:19:27 AM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953052227 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.1953052227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/79.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.766214908 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 5599932697 ps |
| CPU time | 111.3 seconds |
| Started | Sep 10 07:17:30 AM UTC 24 |
| Finished | Sep 10 07:19:24 AM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766214908 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.766214908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.828502419 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 40139561 ps |
| CPU time | 5.69 seconds |
| Started | Sep 10 07:17:24 AM UTC 24 |
| Finished | Sep 10 07:17:31 AM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828502419 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delays.828502419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/79.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.2894292986 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 7705420247 ps |
| CPU time | 303.62 seconds |
| Started | Sep 10 07:18:12 AM UTC 24 |
| Finished | Sep 10 07:23:20 AM UTC 24 |
| Peak memory | 596120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894292986 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.2894292986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/79.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.1412262855 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 13041028305 ps |
| CPU time | 371.37 seconds |
| Started | Sep 10 07:18:18 AM UTC 24 |
| Finished | Sep 10 07:24:34 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412262855 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.1412262855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/79.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1214279487 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 6335925015 ps |
| CPU time | 407 seconds |
| Started | Sep 10 07:18:10 AM UTC 24 |
| Finished | Sep 10 07:25:03 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214279487 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_rand_reset.1214279487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.2396240036 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 4203784984 ps |
| CPU time | 460.51 seconds |
| Started | Sep 10 07:18:21 AM UTC 24 |
| Finished | Sep 10 07:26:08 AM UTC 24 |
| Peak memory | 596004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396240036 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_reset_error.2396240036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.4034635579 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 426798092 ps |
| CPU time | 23.04 seconds |
| Started | Sep 10 07:18:05 AM UTC 24 |
| Finished | Sep 10 07:18:29 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034635579 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.4034635579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/79.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.3379732079 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 9966792216 ps |
| CPU time | 832.11 seconds |
| Started | Sep 10 05:24:34 AM UTC 24 |
| Finished | Sep 10 05:38:37 AM UTC 24 |
| Peak memory | 670368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3379732079 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 8.chip_csr_mem_rw_with_rand_reset.3379732079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.3872057277 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 3869538728 ps |
| CPU time | 261.81 seconds |
| Started | Sep 10 05:24:03 AM UTC 24 |
| Finished | Sep 10 05:28:28 AM UTC 24 |
| Peak memory | 612640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872057277 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.3872057277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.4163478683 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 29748055093 ps |
| CPU time | 4351.27 seconds |
| Started | Sep 10 05:21:27 AM UTC 24 |
| Finished | Sep 10 06:34:50 AM UTC 24 |
| Peak memory | 613964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=4163478683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.chip_same_csr_outstanding.4163478683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.3931046815 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 2405608134 ps |
| CPU time | 121.75 seconds |
| Started | Sep 10 05:22:25 AM UTC 24 |
| Finished | Sep 10 05:24:30 AM UTC 24 |
| Peak memory | 596040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931046815 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.3931046815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.3108381236 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 81288112702 ps |
| CPU time | 1239.78 seconds |
| Started | Sep 10 05:22:26 AM UTC 24 |
| Finished | Sep 10 05:43:20 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108381236 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.3108381236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.2385172516 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 173642691 ps |
| CPU time | 29.34 seconds |
| Started | Sep 10 05:23:39 AM UTC 24 |
| Finished | Sep 10 05:24:10 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385172516 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.2385172516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.103654090 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 100744344 ps |
| CPU time | 14.75 seconds |
| Started | Sep 10 05:23:04 AM UTC 24 |
| Finished | Sep 10 05:23:20 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103654090 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.103654090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.1348227181 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1176469309 ps |
| CPU time | 58.92 seconds |
| Started | Sep 10 05:22:20 AM UTC 24 |
| Finished | Sep 10 05:23:21 AM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348227181 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.1348227181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.667036917 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 66054996482 ps |
| CPU time | 788.97 seconds |
| Started | Sep 10 05:22:24 AM UTC 24 |
| Finished | Sep 10 05:35:43 AM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667036917 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.667036917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.3722832689 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 22959198964 ps |
| CPU time | 435.39 seconds |
| Started | Sep 10 05:22:25 AM UTC 24 |
| Finished | Sep 10 05:29:47 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722832689 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3722832689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.3217931702 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 177196097 ps |
| CPU time | 24.61 seconds |
| Started | Sep 10 05:22:23 AM UTC 24 |
| Finished | Sep 10 05:22:49 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217931702 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.3217931702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.2908292655 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 2476493919 ps |
| CPU time | 74.66 seconds |
| Started | Sep 10 05:22:54 AM UTC 24 |
| Finished | Sep 10 05:24:10 AM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908292655 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2908292655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.145984576 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 230945695 ps |
| CPU time | 15.12 seconds |
| Started | Sep 10 05:21:46 AM UTC 24 |
| Finished | Sep 10 05:22:02 AM UTC 24 |
| Peak memory | 593788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145984576 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.145984576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.3999898787 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 6946860570 ps |
| CPU time | 96.86 seconds |
| Started | Sep 10 05:21:54 AM UTC 24 |
| Finished | Sep 10 05:23:34 AM UTC 24 |
| Peak memory | 593912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999898787 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3999898787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.2179551321 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 5729791375 ps |
| CPU time | 140.56 seconds |
| Started | Sep 10 05:22:12 AM UTC 24 |
| Finished | Sep 10 05:24:35 AM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179551321 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2179551321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.526966521 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 46705019 ps |
| CPU time | 9.44 seconds |
| Started | Sep 10 05:21:46 AM UTC 24 |
| Finished | Sep 10 05:21:56 AM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526966521 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.526966521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.2196095551 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 10636330878 ps |
| CPU time | 424.39 seconds |
| Started | Sep 10 05:23:47 AM UTC 24 |
| Finished | Sep 10 05:30:58 AM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196095551 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2196095551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.2758513769 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 5237760150 ps |
| CPU time | 180.38 seconds |
| Started | Sep 10 05:24:02 AM UTC 24 |
| Finished | Sep 10 05:27:05 AM UTC 24 |
| Peak memory | 596032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758513769 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2758513769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.3581499291 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 47162243 ps |
| CPU time | 24.9 seconds |
| Started | Sep 10 05:24:00 AM UTC 24 |
| Finished | Sep 10 05:24:26 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581499291 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.3581499291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.2177669015 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 74036294 ps |
| CPU time | 16.9 seconds |
| Started | Sep 10 05:23:16 AM UTC 24 |
| Finished | Sep 10 05:23:34 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177669015 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2177669015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.882076934 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 355335301 ps |
| CPU time | 23.1 seconds |
| Started | Sep 10 07:19:08 AM UTC 24 |
| Finished | Sep 10 07:19:32 AM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882076934 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device.882076934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/80.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.2042411831 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 63453870725 ps |
| CPU time | 929.43 seconds |
| Started | Sep 10 07:19:11 AM UTC 24 |
| Finished | Sep 10 07:34:51 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042411831 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device_slow_rsp.2042411831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.2387856591 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 158875549 ps |
| CPU time | 17.62 seconds |
| Started | Sep 10 07:19:20 AM UTC 24 |
| Finished | Sep 10 07:19:39 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387856591 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_addr.2387856591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.1933869801 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 2000336505 ps |
| CPU time | 73.05 seconds |
| Started | Sep 10 07:19:10 AM UTC 24 |
| Finished | Sep 10 07:20:25 AM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933869801 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.1933869801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/80.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.1656669654 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 1266122855 ps |
| CPU time | 49.77 seconds |
| Started | Sep 10 07:18:50 AM UTC 24 |
| Finished | Sep 10 07:19:41 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656669654 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.1656669654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/80.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_large_delays.1344356310 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 78143588270 ps |
| CPU time | 769.89 seconds |
| Started | Sep 10 07:18:52 AM UTC 24 |
| Finished | Sep 10 07:31:51 AM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344356310 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.1344356310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/80.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_slow_rsp.1297387593 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 39679944866 ps |
| CPU time | 547.93 seconds |
| Started | Sep 10 07:18:57 AM UTC 24 |
| Finished | Sep 10 07:28:12 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297387593 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.1297387593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/80.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.3819619154 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 483929052 ps |
| CPU time | 43.35 seconds |
| Started | Sep 10 07:18:50 AM UTC 24 |
| Finished | Sep 10 07:19:35 AM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819619154 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_delays.3819619154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/80.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.24906297 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 852675831 ps |
| CPU time | 27.25 seconds |
| Started | Sep 10 07:19:11 AM UTC 24 |
| Finished | Sep 10 07:19:39 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24906297 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.24906297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/80.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.1379530795 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 236875515 ps |
| CPU time | 13.18 seconds |
| Started | Sep 10 07:18:31 AM UTC 24 |
| Finished | Sep 10 07:18:45 AM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379530795 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.1379530795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/80.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.1344224854 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 8601788439 ps |
| CPU time | 94.33 seconds |
| Started | Sep 10 07:18:43 AM UTC 24 |
| Finished | Sep 10 07:20:19 AM UTC 24 |
| Peak memory | 594056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344224854 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.1344224854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/80.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.4174826663 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 4258486267 ps |
| CPU time | 76.6 seconds |
| Started | Sep 10 07:18:45 AM UTC 24 |
| Finished | Sep 10 07:20:04 AM UTC 24 |
| Peak memory | 593976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174826663 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.4174826663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.2753201047 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 39515215 ps |
| CPU time | 8.56 seconds |
| Started | Sep 10 07:18:36 AM UTC 24 |
| Finished | Sep 10 07:18:45 AM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753201047 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delays.2753201047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/80.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.3299040392 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 2981939033 ps |
| CPU time | 263.91 seconds |
| Started | Sep 10 07:19:21 AM UTC 24 |
| Finished | Sep 10 07:23:49 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299040392 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.3299040392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/80.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.1578911397 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 13122356165 ps |
| CPU time | 400.41 seconds |
| Started | Sep 10 07:19:42 AM UTC 24 |
| Finished | Sep 10 07:26:28 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578911397 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.1578911397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/80.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.519932380 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 225944748 ps |
| CPU time | 94.98 seconds |
| Started | Sep 10 07:19:24 AM UTC 24 |
| Finished | Sep 10 07:21:01 AM UTC 24 |
| Peak memory | 595880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519932380 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_rand_reset.519932380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.2920398557 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 3548166773 ps |
| CPU time | 464.51 seconds |
| Started | Sep 10 07:19:52 AM UTC 24 |
| Finished | Sep 10 07:27:43 AM UTC 24 |
| Peak memory | 597816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920398557 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_reset_error.2920398557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.1841813386 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 976398799 ps |
| CPU time | 51.29 seconds |
| Started | Sep 10 07:19:17 AM UTC 24 |
| Finished | Sep 10 07:20:10 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841813386 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.1841813386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/80.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.1868510674 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 446515708 ps |
| CPU time | 57.74 seconds |
| Started | Sep 10 07:20:08 AM UTC 24 |
| Finished | Sep 10 07:21:07 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868510674 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device.1868510674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/81.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.538124787 |
| Short name | T2923 |
| Test name | |
| Test status | |
| Simulation time | 188708576641 ps |
| CPU time | 2365.73 seconds |
| Started | Sep 10 07:20:19 AM UTC 24 |
| Finished | Sep 10 08:00:09 AM UTC 24 |
| Peak memory | 598932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538124787 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device_slow_rsp.538124787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.4164352657 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 87538195 ps |
| CPU time | 13.92 seconds |
| Started | Sep 10 07:20:38 AM UTC 24 |
| Finished | Sep 10 07:20:53 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164352657 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_addr.4164352657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.3126338969 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 423619289 ps |
| CPU time | 18.97 seconds |
| Started | Sep 10 07:20:30 AM UTC 24 |
| Finished | Sep 10 07:20:50 AM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126338969 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.3126338969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/81.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.2814104440 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 1148678199 ps |
| CPU time | 38.9 seconds |
| Started | Sep 10 07:20:04 AM UTC 24 |
| Finished | Sep 10 07:20:44 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814104440 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.2814104440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/81.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_large_delays.2681631074 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 64727335042 ps |
| CPU time | 556.34 seconds |
| Started | Sep 10 07:20:06 AM UTC 24 |
| Finished | Sep 10 07:29:29 AM UTC 24 |
| Peak memory | 596064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681631074 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.2681631074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/81.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_slow_rsp.1037468542 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 48003164377 ps |
| CPU time | 752.13 seconds |
| Started | Sep 10 07:20:07 AM UTC 24 |
| Finished | Sep 10 07:32:49 AM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037468542 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.1037468542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/81.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.948669498 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 414683094 ps |
| CPU time | 46.41 seconds |
| Started | Sep 10 07:20:04 AM UTC 24 |
| Finished | Sep 10 07:20:52 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948669498 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_delays.948669498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/81.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.2019598841 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 52627827 ps |
| CPU time | 9.54 seconds |
| Started | Sep 10 07:20:32 AM UTC 24 |
| Finished | Sep 10 07:20:43 AM UTC 24 |
| Peak memory | 593888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019598841 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.2019598841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/81.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.3005509738 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 43570982 ps |
| CPU time | 8.63 seconds |
| Started | Sep 10 07:19:55 AM UTC 24 |
| Finished | Sep 10 07:20:04 AM UTC 24 |
| Peak memory | 593916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005509738 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.3005509738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/81.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.4173430014 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 9698212169 ps |
| CPU time | 91.64 seconds |
| Started | Sep 10 07:19:56 AM UTC 24 |
| Finished | Sep 10 07:21:30 AM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173430014 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.4173430014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/81.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.2170060176 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 6241590555 ps |
| CPU time | 106.37 seconds |
| Started | Sep 10 07:19:57 AM UTC 24 |
| Finished | Sep 10 07:21:46 AM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170060176 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.2170060176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.2820885877 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 45894952 ps |
| CPU time | 8.76 seconds |
| Started | Sep 10 07:19:55 AM UTC 24 |
| Finished | Sep 10 07:20:05 AM UTC 24 |
| Peak memory | 593636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820885877 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delays.2820885877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/81.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.3866464150 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 5125873748 ps |
| CPU time | 164.14 seconds |
| Started | Sep 10 07:20:46 AM UTC 24 |
| Finished | Sep 10 07:23:34 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866464150 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.3866464150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/81.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.1608643804 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 4529007548 ps |
| CPU time | 151.26 seconds |
| Started | Sep 10 07:21:04 AM UTC 24 |
| Finished | Sep 10 07:23:38 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608643804 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.1608643804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/81.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.1520285314 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 2800755712 ps |
| CPU time | 296.63 seconds |
| Started | Sep 10 07:20:53 AM UTC 24 |
| Finished | Sep 10 07:25:55 AM UTC 24 |
| Peak memory | 596000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520285314 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_rand_reset.1520285314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.3839084807 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 626606936 ps |
| CPU time | 223.11 seconds |
| Started | Sep 10 07:21:09 AM UTC 24 |
| Finished | Sep 10 07:24:55 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839084807 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_reset_error.3839084807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.4061604168 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 1210251040 ps |
| CPU time | 50.21 seconds |
| Started | Sep 10 07:20:32 AM UTC 24 |
| Finished | Sep 10 07:21:24 AM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061604168 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.4061604168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/81.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.1316926848 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 670892612 ps |
| CPU time | 68.86 seconds |
| Started | Sep 10 07:21:29 AM UTC 24 |
| Finished | Sep 10 07:22:40 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316926848 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device.1316926848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/82.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.1562323698 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 23656628429 ps |
| CPU time | 338.47 seconds |
| Started | Sep 10 07:21:40 AM UTC 24 |
| Finished | Sep 10 07:27:23 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562323698 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device_slow_rsp.1562323698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.1725614394 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 561047369 ps |
| CPU time | 29.81 seconds |
| Started | Sep 10 07:21:57 AM UTC 24 |
| Finished | Sep 10 07:22:28 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725614394 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_addr.1725614394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.626456273 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 1229587812 ps |
| CPU time | 45.55 seconds |
| Started | Sep 10 07:21:48 AM UTC 24 |
| Finished | Sep 10 07:22:35 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626456273 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.626456273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/82.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.3026492159 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 402368138 ps |
| CPU time | 22.68 seconds |
| Started | Sep 10 07:21:19 AM UTC 24 |
| Finished | Sep 10 07:21:43 AM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026492159 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.3026492159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/82.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_large_delays.1943393823 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 66517880811 ps |
| CPU time | 616.28 seconds |
| Started | Sep 10 07:21:25 AM UTC 24 |
| Finished | Sep 10 07:31:49 AM UTC 24 |
| Peak memory | 596100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943393823 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.1943393823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/82.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_slow_rsp.3643735011 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 2357831081 ps |
| CPU time | 36.12 seconds |
| Started | Sep 10 07:21:28 AM UTC 24 |
| Finished | Sep 10 07:22:06 AM UTC 24 |
| Peak memory | 593720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643735011 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.3643735011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/82.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.4204702020 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 303397233 ps |
| CPU time | 32.89 seconds |
| Started | Sep 10 07:21:20 AM UTC 24 |
| Finished | Sep 10 07:21:54 AM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204702020 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_delays.4204702020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/82.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.3195855464 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 2226476473 ps |
| CPU time | 81.47 seconds |
| Started | Sep 10 07:21:40 AM UTC 24 |
| Finished | Sep 10 07:23:04 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195855464 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.3195855464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/82.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.3947879344 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 48076050 ps |
| CPU time | 8.72 seconds |
| Started | Sep 10 07:21:07 AM UTC 24 |
| Finished | Sep 10 07:21:17 AM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947879344 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.3947879344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/82.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.391076164 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 7655021903 ps |
| CPU time | 66.9 seconds |
| Started | Sep 10 07:21:15 AM UTC 24 |
| Finished | Sep 10 07:22:24 AM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391076164 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.391076164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/82.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.3948683106 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 6276115676 ps |
| CPU time | 95.48 seconds |
| Started | Sep 10 07:21:18 AM UTC 24 |
| Finished | Sep 10 07:22:55 AM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948683106 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.3948683106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.2595169803 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 49853191 ps |
| CPU time | 9.13 seconds |
| Started | Sep 10 07:21:11 AM UTC 24 |
| Finished | Sep 10 07:21:22 AM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595169803 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delays.2595169803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/82.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.4020856166 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 6013311801 ps |
| CPU time | 218.66 seconds |
| Started | Sep 10 07:22:10 AM UTC 24 |
| Finished | Sep 10 07:25:52 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020856166 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.4020856166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/82.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.369382139 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 310001723 ps |
| CPU time | 28.82 seconds |
| Started | Sep 10 07:22:14 AM UTC 24 |
| Finished | Sep 10 07:22:44 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369382139 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.369382139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/82.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.2113315770 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 16828266925 ps |
| CPU time | 861.4 seconds |
| Started | Sep 10 07:22:14 AM UTC 24 |
| Finished | Sep 10 07:36:46 AM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113315770 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_rand_reset.2113315770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.388681217 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 6935784815 ps |
| CPU time | 529.13 seconds |
| Started | Sep 10 07:22:20 AM UTC 24 |
| Finished | Sep 10 07:31:16 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388681217 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_reset_error.388681217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.3550087046 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 1296840533 ps |
| CPU time | 68.67 seconds |
| Started | Sep 10 07:21:52 AM UTC 24 |
| Finished | Sep 10 07:23:03 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550087046 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.3550087046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/82.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.2700142934 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 1136191788 ps |
| CPU time | 85.16 seconds |
| Started | Sep 10 07:23:06 AM UTC 24 |
| Finished | Sep 10 07:24:33 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700142934 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device.2700142934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/83.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.3638051068 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 89118725711 ps |
| CPU time | 1270.45 seconds |
| Started | Sep 10 07:23:11 AM UTC 24 |
| Finished | Sep 10 07:44:35 AM UTC 24 |
| Peak memory | 596212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638051068 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device_slow_rsp.3638051068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.970851223 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 360946365 ps |
| CPU time | 20.11 seconds |
| Started | Sep 10 07:23:29 AM UTC 24 |
| Finished | Sep 10 07:23:51 AM UTC 24 |
| Peak memory | 596096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970851223 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_addr.970851223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.1670341373 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 152879467 ps |
| CPU time | 19.58 seconds |
| Started | Sep 10 07:23:22 AM UTC 24 |
| Finished | Sep 10 07:23:43 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670341373 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.1670341373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/83.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.1933158203 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 2158242214 ps |
| CPU time | 79.29 seconds |
| Started | Sep 10 07:22:57 AM UTC 24 |
| Finished | Sep 10 07:24:18 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933158203 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.1933158203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/83.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_large_delays.2033329777 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 40804196238 ps |
| CPU time | 487.72 seconds |
| Started | Sep 10 07:23:02 AM UTC 24 |
| Finished | Sep 10 07:31:16 AM UTC 24 |
| Peak memory | 595980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033329777 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.2033329777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/83.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_slow_rsp.1055418370 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 29356852569 ps |
| CPU time | 434.65 seconds |
| Started | Sep 10 07:23:07 AM UTC 24 |
| Finished | Sep 10 07:30:28 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055418370 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.1055418370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/83.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.2126942321 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 121133258 ps |
| CPU time | 15.23 seconds |
| Started | Sep 10 07:23:00 AM UTC 24 |
| Finished | Sep 10 07:23:16 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126942321 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_delays.2126942321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/83.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.2426981337 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 239755335 ps |
| CPU time | 18.03 seconds |
| Started | Sep 10 07:23:08 AM UTC 24 |
| Finished | Sep 10 07:23:27 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426981337 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.2426981337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/83.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.998758041 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 188805584 ps |
| CPU time | 7.94 seconds |
| Started | Sep 10 07:22:26 AM UTC 24 |
| Finished | Sep 10 07:22:35 AM UTC 24 |
| Peak memory | 594024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998758041 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.998758041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/83.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.1784777450 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 6723144856 ps |
| CPU time | 69.53 seconds |
| Started | Sep 10 07:22:40 AM UTC 24 |
| Finished | Sep 10 07:23:51 AM UTC 24 |
| Peak memory | 593912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784777450 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.1784777450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/83.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.3108095872 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 4679483446 ps |
| CPU time | 98.61 seconds |
| Started | Sep 10 07:22:51 AM UTC 24 |
| Finished | Sep 10 07:24:32 AM UTC 24 |
| Peak memory | 593836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108095872 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.3108095872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.1216167096 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 42083597 ps |
| CPU time | 8.8 seconds |
| Started | Sep 10 07:22:34 AM UTC 24 |
| Finished | Sep 10 07:22:44 AM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216167096 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delays.1216167096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/83.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.3113414437 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 3523992139 ps |
| CPU time | 284.07 seconds |
| Started | Sep 10 07:23:32 AM UTC 24 |
| Finished | Sep 10 07:28:20 AM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113414437 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.3113414437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/83.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.3605651260 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 14731189252 ps |
| CPU time | 497.68 seconds |
| Started | Sep 10 07:23:44 AM UTC 24 |
| Finished | Sep 10 07:32:09 AM UTC 24 |
| Peak memory | 596012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605651260 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.3605651260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/83.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3769269025 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 2276342715 ps |
| CPU time | 383.1 seconds |
| Started | Sep 10 07:23:33 AM UTC 24 |
| Finished | Sep 10 07:30:01 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769269025 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_rand_reset.3769269025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3095319029 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 8039780331 ps |
| CPU time | 429.71 seconds |
| Started | Sep 10 07:23:48 AM UTC 24 |
| Finished | Sep 10 07:31:03 AM UTC 24 |
| Peak memory | 596000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095319029 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_reset_error.3095319029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.3965184389 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 523803341 ps |
| CPU time | 30.29 seconds |
| Started | Sep 10 07:23:27 AM UTC 24 |
| Finished | Sep 10 07:23:59 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965184389 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.3965184389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/83.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.1539878589 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 1204149581 ps |
| CPU time | 108.46 seconds |
| Started | Sep 10 07:24:22 AM UTC 24 |
| Finished | Sep 10 07:26:13 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539878589 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device.1539878589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/84.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.1022545240 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 87839303445 ps |
| CPU time | 1223.75 seconds |
| Started | Sep 10 07:24:25 AM UTC 24 |
| Finished | Sep 10 07:45:02 AM UTC 24 |
| Peak memory | 596036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022545240 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device_slow_rsp.1022545240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.3174169044 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 200448885 ps |
| CPU time | 22.98 seconds |
| Started | Sep 10 07:24:48 AM UTC 24 |
| Finished | Sep 10 07:25:12 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174169044 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_addr.3174169044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.3880519757 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 134016753 ps |
| CPU time | 17.16 seconds |
| Started | Sep 10 07:24:40 AM UTC 24 |
| Finished | Sep 10 07:24:58 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880519757 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.3880519757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/84.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.808146221 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 170379146 ps |
| CPU time | 11.99 seconds |
| Started | Sep 10 07:24:13 AM UTC 24 |
| Finished | Sep 10 07:24:26 AM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808146221 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.808146221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/84.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_large_delays.681073594 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 49662874268 ps |
| CPU time | 590.01 seconds |
| Started | Sep 10 07:24:17 AM UTC 24 |
| Finished | Sep 10 07:34:14 AM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681073594 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.681073594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/84.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_slow_rsp.3727722212 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 45003882502 ps |
| CPU time | 625.98 seconds |
| Started | Sep 10 07:24:19 AM UTC 24 |
| Finished | Sep 10 07:34:53 AM UTC 24 |
| Peak memory | 595996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727722212 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.3727722212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/84.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.3052034282 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 229862897 ps |
| CPU time | 28.61 seconds |
| Started | Sep 10 07:24:16 AM UTC 24 |
| Finished | Sep 10 07:24:46 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052034282 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_delays.3052034282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/84.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.3171685018 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 1256502117 ps |
| CPU time | 47.61 seconds |
| Started | Sep 10 07:24:36 AM UTC 24 |
| Finished | Sep 10 07:25:25 AM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171685018 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.3171685018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/84.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.3215709813 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 217755964 ps |
| CPU time | 12.7 seconds |
| Started | Sep 10 07:23:54 AM UTC 24 |
| Finished | Sep 10 07:24:08 AM UTC 24 |
| Peak memory | 593780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215709813 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.3215709813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/84.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.1003650867 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 11069873686 ps |
| CPU time | 113.84 seconds |
| Started | Sep 10 07:24:06 AM UTC 24 |
| Finished | Sep 10 07:26:02 AM UTC 24 |
| Peak memory | 593864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003650867 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.1003650867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/84.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.738509568 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 6848620500 ps |
| CPU time | 102.04 seconds |
| Started | Sep 10 07:24:11 AM UTC 24 |
| Finished | Sep 10 07:25:55 AM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738509568 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.738509568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.1725347348 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 48560935 ps |
| CPU time | 9.08 seconds |
| Started | Sep 10 07:24:02 AM UTC 24 |
| Finished | Sep 10 07:24:12 AM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725347348 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delays.1725347348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/84.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.1044092132 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 3211457569 ps |
| CPU time | 108.28 seconds |
| Started | Sep 10 07:24:54 AM UTC 24 |
| Finished | Sep 10 07:26:44 AM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044092132 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.1044092132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/84.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.429970871 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 3389544922 ps |
| CPU time | 139.06 seconds |
| Started | Sep 10 07:25:00 AM UTC 24 |
| Finished | Sep 10 07:27:21 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429970871 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.429970871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/84.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.1664617380 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 6174726803 ps |
| CPU time | 478.34 seconds |
| Started | Sep 10 07:24:57 AM UTC 24 |
| Finished | Sep 10 07:33:01 AM UTC 24 |
| Peak memory | 596000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664617380 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_rand_reset.1664617380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.2192550224 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 13491306848 ps |
| CPU time | 1096.88 seconds |
| Started | Sep 10 07:25:03 AM UTC 24 |
| Finished | Sep 10 07:43:34 AM UTC 24 |
| Peak memory | 614332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192550224 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_reset_error.2192550224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.1646377544 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 51657775 ps |
| CPU time | 8.55 seconds |
| Started | Sep 10 07:24:45 AM UTC 24 |
| Finished | Sep 10 07:24:54 AM UTC 24 |
| Peak memory | 593780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646377544 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.1646377544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/84.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.1647327860 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 1483182433 ps |
| CPU time | 70.19 seconds |
| Started | Sep 10 07:25:39 AM UTC 24 |
| Finished | Sep 10 07:26:51 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647327860 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device.1647327860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/85.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.990567574 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 71565366568 ps |
| CPU time | 1129.11 seconds |
| Started | Sep 10 07:25:52 AM UTC 24 |
| Finished | Sep 10 07:44:56 AM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990567574 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device_slow_rsp.990567574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.2555969355 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 273582292 ps |
| CPU time | 12.26 seconds |
| Started | Sep 10 07:26:04 AM UTC 24 |
| Finished | Sep 10 07:26:18 AM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555969355 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_addr.2555969355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.1421647909 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 994230379 ps |
| CPU time | 34.78 seconds |
| Started | Sep 10 07:25:52 AM UTC 24 |
| Finished | Sep 10 07:26:30 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421647909 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.1421647909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/85.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.188765030 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 135827936 ps |
| CPU time | 11.59 seconds |
| Started | Sep 10 07:25:22 AM UTC 24 |
| Finished | Sep 10 07:25:35 AM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188765030 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.188765030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/85.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_large_delays.2012492350 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 18337351703 ps |
| CPU time | 203.5 seconds |
| Started | Sep 10 07:25:30 AM UTC 24 |
| Finished | Sep 10 07:28:56 AM UTC 24 |
| Peak memory | 596104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012492350 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.2012492350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/85.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_slow_rsp.2464228936 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 27769286541 ps |
| CPU time | 486.23 seconds |
| Started | Sep 10 07:25:31 AM UTC 24 |
| Finished | Sep 10 07:33:44 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464228936 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.2464228936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/85.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.1333371567 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 525900821 ps |
| CPU time | 49.44 seconds |
| Started | Sep 10 07:25:26 AM UTC 24 |
| Finished | Sep 10 07:26:17 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333371567 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_delays.1333371567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/85.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.3551694982 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 78224889 ps |
| CPU time | 11.69 seconds |
| Started | Sep 10 07:25:53 AM UTC 24 |
| Finished | Sep 10 07:26:06 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551694982 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.3551694982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/85.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.2430800978 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 43011520 ps |
| CPU time | 8.77 seconds |
| Started | Sep 10 07:25:14 AM UTC 24 |
| Finished | Sep 10 07:25:24 AM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430800978 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.2430800978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/85.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.1393733628 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 9424689165 ps |
| CPU time | 98.25 seconds |
| Started | Sep 10 07:25:21 AM UTC 24 |
| Finished | Sep 10 07:27:01 AM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393733628 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.1393733628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/85.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.337582307 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 5854460902 ps |
| CPU time | 129.1 seconds |
| Started | Sep 10 07:25:22 AM UTC 24 |
| Finished | Sep 10 07:27:33 AM UTC 24 |
| Peak memory | 593780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337582307 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.337582307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.960836791 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 36464064 ps |
| CPU time | 6.37 seconds |
| Started | Sep 10 07:25:18 AM UTC 24 |
| Finished | Sep 10 07:25:26 AM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960836791 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delays.960836791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/85.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all.872607570 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 3062401795 ps |
| CPU time | 245.02 seconds |
| Started | Sep 10 07:26:19 AM UTC 24 |
| Finished | Sep 10 07:30:28 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872607570 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.872607570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/85.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_error.2594197527 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 5888405900 ps |
| CPU time | 223.34 seconds |
| Started | Sep 10 07:26:24 AM UTC 24 |
| Finished | Sep 10 07:30:11 AM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594197527 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.2594197527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/85.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.3670601123 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 5228392113 ps |
| CPU time | 366.58 seconds |
| Started | Sep 10 07:26:22 AM UTC 24 |
| Finished | Sep 10 07:32:34 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670601123 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_rand_reset.3670601123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.705111330 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 6166327042 ps |
| CPU time | 314.92 seconds |
| Started | Sep 10 07:26:24 AM UTC 24 |
| Finished | Sep 10 07:31:44 AM UTC 24 |
| Peak memory | 596128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705111330 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_reset_error.705111330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.3604041149 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 282528287 ps |
| CPU time | 42.58 seconds |
| Started | Sep 10 07:26:04 AM UTC 24 |
| Finished | Sep 10 07:26:48 AM UTC 24 |
| Peak memory | 596084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604041149 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.3604041149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/85.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.3743253202 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 965064660 ps |
| CPU time | 74.13 seconds |
| Started | Sep 10 07:26:58 AM UTC 24 |
| Finished | Sep 10 07:28:14 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743253202 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device.3743253202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/86.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.2998267290 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 56456559421 ps |
| CPU time | 791.84 seconds |
| Started | Sep 10 07:27:02 AM UTC 24 |
| Finished | Sep 10 07:40:23 AM UTC 24 |
| Peak memory | 596036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998267290 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device_slow_rsp.2998267290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.1228905578 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 124213510 ps |
| CPU time | 16.23 seconds |
| Started | Sep 10 07:27:18 AM UTC 24 |
| Finished | Sep 10 07:27:35 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228905578 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_addr.1228905578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.2704960973 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 781112849 ps |
| CPU time | 28.23 seconds |
| Started | Sep 10 07:27:11 AM UTC 24 |
| Finished | Sep 10 07:27:41 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704960973 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.2704960973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/86.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.1577427991 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 1897461891 ps |
| CPU time | 69.96 seconds |
| Started | Sep 10 07:26:42 AM UTC 24 |
| Finished | Sep 10 07:27:53 AM UTC 24 |
| Peak memory | 595964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577427991 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.1577427991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/86.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_large_delays.3734332504 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 3923708185 ps |
| CPU time | 49.88 seconds |
| Started | Sep 10 07:26:46 AM UTC 24 |
| Finished | Sep 10 07:27:37 AM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734332504 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.3734332504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/86.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_slow_rsp.3474310770 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 16444588132 ps |
| CPU time | 230.93 seconds |
| Started | Sep 10 07:26:53 AM UTC 24 |
| Finished | Sep 10 07:30:47 AM UTC 24 |
| Peak memory | 596000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474310770 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.3474310770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/86.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.4129597411 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 434426293 ps |
| CPU time | 47.32 seconds |
| Started | Sep 10 07:26:46 AM UTC 24 |
| Finished | Sep 10 07:27:34 AM UTC 24 |
| Peak memory | 595812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129597411 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_delays.4129597411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/86.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.3256956347 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 72397817 ps |
| CPU time | 10.54 seconds |
| Started | Sep 10 07:27:03 AM UTC 24 |
| Finished | Sep 10 07:27:15 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256956347 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.3256956347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/86.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.162652053 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 220728345 ps |
| CPU time | 12.85 seconds |
| Started | Sep 10 07:26:22 AM UTC 24 |
| Finished | Sep 10 07:26:36 AM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162652053 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.162652053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/86.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.4177957544 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 8513661962 ps |
| CPU time | 84.11 seconds |
| Started | Sep 10 07:26:35 AM UTC 24 |
| Finished | Sep 10 07:28:01 AM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177957544 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.4177957544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/86.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.2879066691 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 4845202245 ps |
| CPU time | 100.4 seconds |
| Started | Sep 10 07:26:37 AM UTC 24 |
| Finished | Sep 10 07:28:19 AM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879066691 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.2879066691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.3714146000 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 52386427 ps |
| CPU time | 9.45 seconds |
| Started | Sep 10 07:26:27 AM UTC 24 |
| Finished | Sep 10 07:26:37 AM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714146000 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delays.3714146000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/86.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.1264182459 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 6796322908 ps |
| CPU time | 203.63 seconds |
| Started | Sep 10 07:27:26 AM UTC 24 |
| Finished | Sep 10 07:30:53 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264182459 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.1264182459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/86.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_error.1415275648 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 7434051631 ps |
| CPU time | 272.38 seconds |
| Started | Sep 10 07:27:43 AM UTC 24 |
| Finished | Sep 10 07:32:20 AM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415275648 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.1415275648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/86.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.2328945596 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 8163620282 ps |
| CPU time | 958.43 seconds |
| Started | Sep 10 07:27:38 AM UTC 24 |
| Finished | Sep 10 07:43:50 AM UTC 24 |
| Peak memory | 596124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328945596 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_rand_reset.2328945596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.1794854146 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 1590629260 ps |
| CPU time | 180.8 seconds |
| Started | Sep 10 07:27:48 AM UTC 24 |
| Finished | Sep 10 07:30:51 AM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794854146 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_reset_error.1794854146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.2084684362 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 213762690 ps |
| CPU time | 34.56 seconds |
| Started | Sep 10 07:27:15 AM UTC 24 |
| Finished | Sep 10 07:27:51 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084684362 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.2084684362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/86.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.2320045796 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 262246280 ps |
| CPU time | 16.68 seconds |
| Started | Sep 10 07:28:20 AM UTC 24 |
| Finished | Sep 10 07:28:38 AM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320045796 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device.2320045796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/87.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.3983830789 |
| Short name | T2915 |
| Test name | |
| Test status | |
| Simulation time | 91869240225 ps |
| CPU time | 1276.06 seconds |
| Started | Sep 10 07:28:24 AM UTC 24 |
| Finished | Sep 10 07:49:54 AM UTC 24 |
| Peak memory | 596408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983830789 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device_slow_rsp.3983830789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.1939659711 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 1266225741 ps |
| CPU time | 43.7 seconds |
| Started | Sep 10 07:28:39 AM UTC 24 |
| Finished | Sep 10 07:29:24 AM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939659711 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_addr.1939659711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.882974516 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 2045153474 ps |
| CPU time | 62.55 seconds |
| Started | Sep 10 07:28:26 AM UTC 24 |
| Finished | Sep 10 07:29:31 AM UTC 24 |
| Peak memory | 596032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882974516 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.882974516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/87.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.3175668731 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 592527489 ps |
| CPU time | 54.04 seconds |
| Started | Sep 10 07:28:05 AM UTC 24 |
| Finished | Sep 10 07:29:01 AM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175668731 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.3175668731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/87.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_large_delays.389780834 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 88032272750 ps |
| CPU time | 909.15 seconds |
| Started | Sep 10 07:28:10 AM UTC 24 |
| Finished | Sep 10 07:43:30 AM UTC 24 |
| Peak memory | 596100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389780834 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.389780834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/87.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_slow_rsp.3631168987 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 66939983280 ps |
| CPU time | 959.93 seconds |
| Started | Sep 10 07:28:18 AM UTC 24 |
| Finished | Sep 10 07:44:29 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631168987 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.3631168987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/87.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.4204161733 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 339645289 ps |
| CPU time | 39.71 seconds |
| Started | Sep 10 07:28:09 AM UTC 24 |
| Finished | Sep 10 07:28:50 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204161733 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_delays.4204161733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/87.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.2833705349 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 2310296456 ps |
| CPU time | 56.66 seconds |
| Started | Sep 10 07:28:25 AM UTC 24 |
| Finished | Sep 10 07:29:24 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833705349 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.2833705349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/87.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.1202576830 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 48385080 ps |
| CPU time | 8.83 seconds |
| Started | Sep 10 07:27:48 AM UTC 24 |
| Finished | Sep 10 07:27:58 AM UTC 24 |
| Peak memory | 594076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202576830 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.1202576830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/87.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.1522235746 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 4450071808 ps |
| CPU time | 41.34 seconds |
| Started | Sep 10 07:27:59 AM UTC 24 |
| Finished | Sep 10 07:28:42 AM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522235746 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.1522235746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/87.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.4023611208 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 4580503963 ps |
| CPU time | 70.03 seconds |
| Started | Sep 10 07:28:04 AM UTC 24 |
| Finished | Sep 10 07:29:16 AM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023611208 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.4023611208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.3046707618 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 55009383 ps |
| CPU time | 9.44 seconds |
| Started | Sep 10 07:27:59 AM UTC 24 |
| Finished | Sep 10 07:28:10 AM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046707618 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delays.3046707618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/87.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all.2462923838 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 1483396276 ps |
| CPU time | 114.69 seconds |
| Started | Sep 10 07:28:41 AM UTC 24 |
| Finished | Sep 10 07:30:38 AM UTC 24 |
| Peak memory | 596120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462923838 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.2462923838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/87.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_error.2806544982 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 2068551734 ps |
| CPU time | 146.14 seconds |
| Started | Sep 10 07:28:45 AM UTC 24 |
| Finished | Sep 10 07:31:13 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806544982 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.2806544982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/87.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.250310904 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 12604907719 ps |
| CPU time | 497.42 seconds |
| Started | Sep 10 07:28:46 AM UTC 24 |
| Finished | Sep 10 07:37:10 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250310904 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_rand_reset.250310904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.531577225 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 13593686792 ps |
| CPU time | 564.15 seconds |
| Started | Sep 10 07:28:56 AM UTC 24 |
| Finished | Sep 10 07:38:28 AM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531577225 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_reset_error.531577225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.408977461 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 38020580 ps |
| CPU time | 10.32 seconds |
| Started | Sep 10 07:28:36 AM UTC 24 |
| Finished | Sep 10 07:28:47 AM UTC 24 |
| Peak memory | 593656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408977461 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.408977461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/87.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.1863638772 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 103257448 ps |
| CPU time | 12.91 seconds |
| Started | Sep 10 07:29:40 AM UTC 24 |
| Finished | Sep 10 07:29:54 AM UTC 24 |
| Peak memory | 594016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863638772 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device.1863638772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/88.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.618533467 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 67777665638 ps |
| CPU time | 980.51 seconds |
| Started | Sep 10 07:29:42 AM UTC 24 |
| Finished | Sep 10 07:46:15 AM UTC 24 |
| Peak memory | 595984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618533467 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device_slow_rsp.618533467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.373076253 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 68902222 ps |
| CPU time | 9.86 seconds |
| Started | Sep 10 07:29:55 AM UTC 24 |
| Finished | Sep 10 07:30:06 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373076253 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_addr.373076253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.1419311800 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 1480487557 ps |
| CPU time | 47.63 seconds |
| Started | Sep 10 07:29:52 AM UTC 24 |
| Finished | Sep 10 07:30:41 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419311800 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.1419311800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/88.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.2956831690 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 2116966021 ps |
| CPU time | 75.58 seconds |
| Started | Sep 10 07:29:14 AM UTC 24 |
| Finished | Sep 10 07:30:32 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956831690 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.2956831690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/88.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_large_delays.2669536362 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 24920502350 ps |
| CPU time | 275.18 seconds |
| Started | Sep 10 07:29:24 AM UTC 24 |
| Finished | Sep 10 07:34:03 AM UTC 24 |
| Peak memory | 596152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669536362 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.2669536362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/88.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_slow_rsp.141798183 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 2598425625 ps |
| CPU time | 52.67 seconds |
| Started | Sep 10 07:29:29 AM UTC 24 |
| Finished | Sep 10 07:30:23 AM UTC 24 |
| Peak memory | 594060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141798183 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.141798183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/88.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.2099224508 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 111720148 ps |
| CPU time | 16.98 seconds |
| Started | Sep 10 07:29:16 AM UTC 24 |
| Finished | Sep 10 07:29:34 AM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099224508 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_delays.2099224508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/88.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.863364818 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 2016608141 ps |
| CPU time | 76.14 seconds |
| Started | Sep 10 07:29:44 AM UTC 24 |
| Finished | Sep 10 07:31:02 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863364818 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.863364818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/88.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.4251463304 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 166536416 ps |
| CPU time | 11.57 seconds |
| Started | Sep 10 07:28:59 AM UTC 24 |
| Finished | Sep 10 07:29:11 AM UTC 24 |
| Peak memory | 593780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251463304 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.4251463304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/88.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.903389874 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 6333997102 ps |
| CPU time | 81.02 seconds |
| Started | Sep 10 07:29:01 AM UTC 24 |
| Finished | Sep 10 07:30:24 AM UTC 24 |
| Peak memory | 594084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903389874 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.903389874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/88.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.3910750125 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 4647451900 ps |
| CPU time | 95.18 seconds |
| Started | Sep 10 07:29:08 AM UTC 24 |
| Finished | Sep 10 07:30:45 AM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910750125 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.3910750125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.3194599880 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 44476601 ps |
| CPU time | 9.35 seconds |
| Started | Sep 10 07:29:04 AM UTC 24 |
| Finished | Sep 10 07:29:15 AM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194599880 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delays.3194599880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/88.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all.371006171 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 18822786005 ps |
| CPU time | 672.1 seconds |
| Started | Sep 10 07:29:56 AM UTC 24 |
| Finished | Sep 10 07:41:18 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371006171 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.371006171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/88.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_error.3152923085 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 3863243752 ps |
| CPU time | 303.65 seconds |
| Started | Sep 10 07:30:21 AM UTC 24 |
| Finished | Sep 10 07:35:30 AM UTC 24 |
| Peak memory | 595920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152923085 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.3152923085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/88.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.117398273 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 93560773 ps |
| CPU time | 84.37 seconds |
| Started | Sep 10 07:30:02 AM UTC 24 |
| Finished | Sep 10 07:31:29 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117398273 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_rand_reset.117398273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.3446402162 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 150899533 ps |
| CPU time | 61.22 seconds |
| Started | Sep 10 07:30:29 AM UTC 24 |
| Finished | Sep 10 07:31:32 AM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446402162 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_reset_error.3446402162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.4044658270 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 242736352 ps |
| CPU time | 34.44 seconds |
| Started | Sep 10 07:29:51 AM UTC 24 |
| Finished | Sep 10 07:30:27 AM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044658270 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.4044658270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/88.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.2639032813 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 2777900754 ps |
| CPU time | 127.06 seconds |
| Started | Sep 10 07:30:57 AM UTC 24 |
| Finished | Sep 10 07:33:07 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639032813 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device.2639032813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/89.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.1306387824 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 59894148177 ps |
| CPU time | 835.13 seconds |
| Started | Sep 10 07:31:00 AM UTC 24 |
| Finished | Sep 10 07:45:05 AM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306387824 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device_slow_rsp.1306387824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.97919167 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 261569489 ps |
| CPU time | 34.61 seconds |
| Started | Sep 10 07:31:14 AM UTC 24 |
| Finished | Sep 10 07:31:50 AM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97919167 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_addr.97919167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.2650158715 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 2263267800 ps |
| CPU time | 71.26 seconds |
| Started | Sep 10 07:31:10 AM UTC 24 |
| Finished | Sep 10 07:32:23 AM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650158715 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.2650158715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/89.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.1185929961 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 118401691 ps |
| CPU time | 12.24 seconds |
| Started | Sep 10 07:30:51 AM UTC 24 |
| Finished | Sep 10 07:31:04 AM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185929961 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.1185929961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/89.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_large_delays.3364309195 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 83540480126 ps |
| CPU time | 758.29 seconds |
| Started | Sep 10 07:30:53 AM UTC 24 |
| Finished | Sep 10 07:43:41 AM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364309195 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.3364309195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/89.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_slow_rsp.2698443382 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 56624247335 ps |
| CPU time | 813.42 seconds |
| Started | Sep 10 07:30:52 AM UTC 24 |
| Finished | Sep 10 07:44:35 AM UTC 24 |
| Peak memory | 595980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698443382 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.2698443382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/89.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.869430522 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 235832647 ps |
| CPU time | 24.36 seconds |
| Started | Sep 10 07:30:50 AM UTC 24 |
| Finished | Sep 10 07:31:16 AM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869430522 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_delays.869430522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/89.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.2842873201 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 65316407 ps |
| CPU time | 8.18 seconds |
| Started | Sep 10 07:31:07 AM UTC 24 |
| Finished | Sep 10 07:31:16 AM UTC 24 |
| Peak memory | 596080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842873201 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.2842873201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/89.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.4137272917 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 192305037 ps |
| CPU time | 12 seconds |
| Started | Sep 10 07:30:34 AM UTC 24 |
| Finished | Sep 10 07:30:47 AM UTC 24 |
| Peak memory | 593780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137272917 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.4137272917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/89.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.408694649 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 8131936676 ps |
| CPU time | 85.51 seconds |
| Started | Sep 10 07:30:42 AM UTC 24 |
| Finished | Sep 10 07:32:10 AM UTC 24 |
| Peak memory | 593904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408694649 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.408694649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/89.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.3408084047 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 4534231041 ps |
| CPU time | 65.98 seconds |
| Started | Sep 10 07:30:48 AM UTC 24 |
| Finished | Sep 10 07:31:56 AM UTC 24 |
| Peak memory | 593844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408084047 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.3408084047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.1352794930 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 54409654 ps |
| CPU time | 9.48 seconds |
| Started | Sep 10 07:30:40 AM UTC 24 |
| Finished | Sep 10 07:30:50 AM UTC 24 |
| Peak memory | 593812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352794930 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delays.1352794930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/89.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all.2117743326 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 3699803020 ps |
| CPU time | 312.72 seconds |
| Started | Sep 10 07:31:13 AM UTC 24 |
| Finished | Sep 10 07:36:31 AM UTC 24 |
| Peak memory | 595940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117743326 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.2117743326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/89.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_error.364743585 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 14049151196 ps |
| CPU time | 415.67 seconds |
| Started | Sep 10 07:31:17 AM UTC 24 |
| Finished | Sep 10 07:38:19 AM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364743585 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.364743585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/89.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.166436624 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 89420006 ps |
| CPU time | 53.88 seconds |
| Started | Sep 10 07:31:14 AM UTC 24 |
| Finished | Sep 10 07:32:09 AM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166436624 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_rand_reset.166436624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.3568609861 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 16576626 ps |
| CPU time | 25.89 seconds |
| Started | Sep 10 07:31:20 AM UTC 24 |
| Finished | Sep 10 07:31:47 AM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568609861 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_reset_error.3568609861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.3846683257 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 254331206 ps |
| CPU time | 28.93 seconds |
| Started | Sep 10 07:31:10 AM UTC 24 |
| Finished | Sep 10 07:31:40 AM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846683257 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.3846683257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/89.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.803818399 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 6190600846 ps |
| CPU time | 591.09 seconds |
| Started | Sep 10 05:27:43 AM UTC 24 |
| Finished | Sep 10 05:37:42 AM UTC 24 |
| Peak memory | 653732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=803818399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.803818399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.489709298 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 6346092618 ps |
| CPU time | 692.64 seconds |
| Started | Sep 10 05:27:38 AM UTC 24 |
| Finished | Sep 10 05:39:20 AM UTC 24 |
| Peak memory | 617008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489709298 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.489709298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.2690281254 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 16889597446 ps |
| CPU time | 2437.34 seconds |
| Started | Sep 10 05:24:36 AM UTC 24 |
| Finished | Sep 10 06:05:44 AM UTC 24 |
| Peak memory | 614060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2690281254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.chip_same_csr_outstanding.2690281254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.755585176 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 1315125752 ps |
| CPU time | 52.18 seconds |
| Started | Sep 10 05:26:42 AM UTC 24 |
| Finished | Sep 10 05:27:35 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755585176 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.755585176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.2533744404 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 208240987 ps |
| CPU time | 24.24 seconds |
| Started | Sep 10 05:26:03 AM UTC 24 |
| Finished | Sep 10 05:26:29 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533744404 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2533744404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.1256840782 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 471205888 ps |
| CPU time | 24.38 seconds |
| Started | Sep 10 05:24:51 AM UTC 24 |
| Finished | Sep 10 05:25:17 AM UTC 24 |
| Peak memory | 595720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256840782 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.1256840782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.4179682315 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 42328221186 ps |
| CPU time | 427.01 seconds |
| Started | Sep 10 05:25:01 AM UTC 24 |
| Finished | Sep 10 05:32:14 AM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179682315 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.4179682315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.2434649574 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 31020941378 ps |
| CPU time | 561.68 seconds |
| Started | Sep 10 05:25:25 AM UTC 24 |
| Finished | Sep 10 05:34:55 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434649574 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2434649574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.2867723173 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 269297535 ps |
| CPU time | 33.22 seconds |
| Started | Sep 10 05:25:01 AM UTC 24 |
| Finished | Sep 10 05:25:36 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867723173 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.2867723173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.3351283027 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 208836903 ps |
| CPU time | 13.26 seconds |
| Started | Sep 10 05:25:44 AM UTC 24 |
| Finished | Sep 10 05:25:58 AM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351283027 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3351283027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.146668013 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 41395993 ps |
| CPU time | 8.26 seconds |
| Started | Sep 10 05:24:48 AM UTC 24 |
| Finished | Sep 10 05:24:57 AM UTC 24 |
| Peak memory | 593776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146668013 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.146668013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.3892481936 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 9099430867 ps |
| CPU time | 83.08 seconds |
| Started | Sep 10 05:24:50 AM UTC 24 |
| Finished | Sep 10 05:26:15 AM UTC 24 |
| Peak memory | 593904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892481936 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3892481936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.3704404593 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 5365891896 ps |
| CPU time | 104.95 seconds |
| Started | Sep 10 05:24:55 AM UTC 24 |
| Finished | Sep 10 05:26:42 AM UTC 24 |
| Peak memory | 593844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704404593 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3704404593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.1775556655 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 45924419 ps |
| CPU time | 9.55 seconds |
| Started | Sep 10 05:24:50 AM UTC 24 |
| Finished | Sep 10 05:25:00 AM UTC 24 |
| Peak memory | 593720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775556655 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.1775556655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.2578104864 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 449572618 ps |
| CPU time | 44.92 seconds |
| Started | Sep 10 05:27:17 AM UTC 24 |
| Finished | Sep 10 05:28:04 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578104864 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2578104864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.2114297045 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 609102469 ps |
| CPU time | 60.77 seconds |
| Started | Sep 10 05:27:10 AM UTC 24 |
| Finished | Sep 10 05:28:13 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114297045 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.2114297045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.1214433581 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 4768706567 ps |
| CPU time | 506.43 seconds |
| Started | Sep 10 05:27:31 AM UTC 24 |
| Finished | Sep 10 05:36:06 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214433581 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.1214433581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.3206154889 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 1305202175 ps |
| CPU time | 78.06 seconds |
| Started | Sep 10 05:26:25 AM UTC 24 |
| Finished | Sep 10 05:27:46 AM UTC 24 |
| Peak memory | 596084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206154889 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3206154889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.2856187638 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 266537003 ps |
| CPU time | 32.06 seconds |
| Started | Sep 10 07:31:43 AM UTC 24 |
| Finished | Sep 10 07:32:16 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856187638 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device.2856187638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/90.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.2546206577 |
| Short name | T2921 |
| Test name | |
| Test status | |
| Simulation time | 90470056981 ps |
| CPU time | 1227.99 seconds |
| Started | Sep 10 07:31:54 AM UTC 24 |
| Finished | Sep 10 07:52:35 AM UTC 24 |
| Peak memory | 598868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546206577 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device_slow_rsp.2546206577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.898821623 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 69306683 ps |
| CPU time | 8.07 seconds |
| Started | Sep 10 07:32:05 AM UTC 24 |
| Finished | Sep 10 07:32:14 AM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898821623 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_addr.898821623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.427153935 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 587507106 ps |
| CPU time | 44.93 seconds |
| Started | Sep 10 07:32:02 AM UTC 24 |
| Finished | Sep 10 07:32:48 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427153935 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.427153935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/90.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.1467457777 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 1870127828 ps |
| CPU time | 54.79 seconds |
| Started | Sep 10 07:31:39 AM UTC 24 |
| Finished | Sep 10 07:32:36 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467457777 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.1467457777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/90.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_large_delays.1625005493 |
| Short name | T2909 |
| Test name | |
| Test status | |
| Simulation time | 100731336831 ps |
| CPU time | 980.39 seconds |
| Started | Sep 10 07:31:37 AM UTC 24 |
| Finished | Sep 10 07:48:09 AM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625005493 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.1625005493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/90.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_slow_rsp.630330308 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 32729216514 ps |
| CPU time | 445.06 seconds |
| Started | Sep 10 07:31:39 AM UTC 24 |
| Finished | Sep 10 07:39:10 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630330308 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.630330308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/90.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.2838640504 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 292917562 ps |
| CPU time | 28.15 seconds |
| Started | Sep 10 07:31:40 AM UTC 24 |
| Finished | Sep 10 07:32:09 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838640504 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_delays.2838640504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/90.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.280191565 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 72780849 ps |
| CPU time | 11.51 seconds |
| Started | Sep 10 07:31:58 AM UTC 24 |
| Finished | Sep 10 07:32:11 AM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280191565 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.280191565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/90.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.984215627 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 43173232 ps |
| CPU time | 8.41 seconds |
| Started | Sep 10 07:31:29 AM UTC 24 |
| Finished | Sep 10 07:31:38 AM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984215627 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.984215627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/90.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.3416837091 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 5690625269 ps |
| CPU time | 81.52 seconds |
| Started | Sep 10 07:31:31 AM UTC 24 |
| Finished | Sep 10 07:32:54 AM UTC 24 |
| Peak memory | 594152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416837091 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.3416837091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/90.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.2945313244 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 6649314593 ps |
| CPU time | 89.2 seconds |
| Started | Sep 10 07:31:36 AM UTC 24 |
| Finished | Sep 10 07:33:07 AM UTC 24 |
| Peak memory | 594040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945313244 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.2945313244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.2883847880 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 43029145 ps |
| CPU time | 5.61 seconds |
| Started | Sep 10 07:31:29 AM UTC 24 |
| Finished | Sep 10 07:31:36 AM UTC 24 |
| Peak memory | 594016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883847880 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delays.2883847880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/90.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all.1204747797 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 4553014936 ps |
| CPU time | 396.74 seconds |
| Started | Sep 10 07:32:12 AM UTC 24 |
| Finished | Sep 10 07:38:55 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204747797 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.1204747797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/90.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_error.1345963543 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 2419207762 ps |
| CPU time | 165.97 seconds |
| Started | Sep 10 07:32:16 AM UTC 24 |
| Finished | Sep 10 07:35:06 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345963543 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.1345963543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/90.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.3145356068 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 102091073 ps |
| CPU time | 105.06 seconds |
| Started | Sep 10 07:32:14 AM UTC 24 |
| Finished | Sep 10 07:34:02 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145356068 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_rand_reset.3145356068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.1190527371 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 2262458208 ps |
| CPU time | 263.98 seconds |
| Started | Sep 10 07:32:19 AM UTC 24 |
| Finished | Sep 10 07:36:47 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190527371 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_reset_error.1190527371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.2847390372 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 220063776 ps |
| CPU time | 28.7 seconds |
| Started | Sep 10 07:32:06 AM UTC 24 |
| Finished | Sep 10 07:32:36 AM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847390372 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.2847390372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/90.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.2496815159 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 1781898271 ps |
| CPU time | 58.98 seconds |
| Started | Sep 10 07:32:43 AM UTC 24 |
| Finished | Sep 10 07:33:43 AM UTC 24 |
| Peak memory | 596028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496815159 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device.2496815159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/91.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.846930675 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 16203263801 ps |
| CPU time | 245.38 seconds |
| Started | Sep 10 07:32:49 AM UTC 24 |
| Finished | Sep 10 07:36:58 AM UTC 24 |
| Peak memory | 596000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846930675 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device_slow_rsp.846930675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.460531631 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 707636927 ps |
| CPU time | 35.4 seconds |
| Started | Sep 10 07:32:57 AM UTC 24 |
| Finished | Sep 10 07:33:34 AM UTC 24 |
| Peak memory | 596036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460531631 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_addr.460531631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.513902863 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 400770482 ps |
| CPU time | 41.15 seconds |
| Started | Sep 10 07:32:49 AM UTC 24 |
| Finished | Sep 10 07:33:32 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513902863 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.513902863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/91.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.2565969758 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 569711081 ps |
| CPU time | 57.08 seconds |
| Started | Sep 10 07:32:35 AM UTC 24 |
| Finished | Sep 10 07:33:34 AM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565969758 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.2565969758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/91.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_large_delays.2839318702 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 6935027200 ps |
| CPU time | 65.84 seconds |
| Started | Sep 10 07:32:40 AM UTC 24 |
| Finished | Sep 10 07:33:47 AM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839318702 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.2839318702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/91.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_slow_rsp.194834394 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 2383132741 ps |
| CPU time | 51.76 seconds |
| Started | Sep 10 07:32:40 AM UTC 24 |
| Finished | Sep 10 07:33:34 AM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194834394 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.194834394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/91.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.2789849679 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 562352688 ps |
| CPU time | 53.48 seconds |
| Started | Sep 10 07:32:39 AM UTC 24 |
| Finished | Sep 10 07:33:34 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789849679 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_delays.2789849679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/91.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.1255825821 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 1015419923 ps |
| CPU time | 41.85 seconds |
| Started | Sep 10 07:32:50 AM UTC 24 |
| Finished | Sep 10 07:33:33 AM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255825821 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.1255825821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/91.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.2007271210 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 48998784 ps |
| CPU time | 8.57 seconds |
| Started | Sep 10 07:32:13 AM UTC 24 |
| Finished | Sep 10 07:32:23 AM UTC 24 |
| Peak memory | 593752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007271210 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.2007271210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/91.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.3100595967 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 9311178382 ps |
| CPU time | 130.49 seconds |
| Started | Sep 10 07:32:37 AM UTC 24 |
| Finished | Sep 10 07:34:50 AM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100595967 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.3100595967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/91.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.4035728883 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 4707495847 ps |
| CPU time | 66.86 seconds |
| Started | Sep 10 07:32:37 AM UTC 24 |
| Finished | Sep 10 07:33:46 AM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035728883 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.4035728883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.690786542 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 58241869 ps |
| CPU time | 9.86 seconds |
| Started | Sep 10 07:32:19 AM UTC 24 |
| Finished | Sep 10 07:32:30 AM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690786542 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delays.690786542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/91.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all.261149308 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 4129313500 ps |
| CPU time | 124.72 seconds |
| Started | Sep 10 07:33:05 AM UTC 24 |
| Finished | Sep 10 07:35:12 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261149308 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.261149308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/91.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_error.630819076 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 2799762002 ps |
| CPU time | 177.5 seconds |
| Started | Sep 10 07:33:15 AM UTC 24 |
| Finished | Sep 10 07:36:16 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630819076 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.630819076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/91.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.1297603123 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 6378981945 ps |
| CPU time | 726.49 seconds |
| Started | Sep 10 07:33:05 AM UTC 24 |
| Finished | Sep 10 07:45:21 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297603123 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_rand_reset.1297603123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.4250558694 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 104709912 ps |
| CPU time | 30.28 seconds |
| Started | Sep 10 07:33:15 AM UTC 24 |
| Finished | Sep 10 07:33:47 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250558694 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_reset_error.4250558694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.1603376800 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 452083480 ps |
| CPU time | 26.26 seconds |
| Started | Sep 10 07:32:56 AM UTC 24 |
| Finished | Sep 10 07:33:24 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603376800 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.1603376800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/91.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device.1402551949 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 358379044 ps |
| CPU time | 17.9 seconds |
| Started | Sep 10 07:33:58 AM UTC 24 |
| Finished | Sep 10 07:34:17 AM UTC 24 |
| Peak memory | 596060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402551949 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device.1402551949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/92.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.4024143987 |
| Short name | T2920 |
| Test name | |
| Test status | |
| Simulation time | 82653907286 ps |
| CPU time | 1087.83 seconds |
| Started | Sep 10 07:33:58 AM UTC 24 |
| Finished | Sep 10 07:52:17 AM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024143987 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device_slow_rsp.4024143987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.2570297707 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 354663116 ps |
| CPU time | 20.14 seconds |
| Started | Sep 10 07:34:07 AM UTC 24 |
| Finished | Sep 10 07:34:29 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570297707 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_addr.2570297707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random.190599891 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 689726902 ps |
| CPU time | 24.84 seconds |
| Started | Sep 10 07:33:52 AM UTC 24 |
| Finished | Sep 10 07:34:18 AM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190599891 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.190599891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/92.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_large_delays.149753128 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 48220420682 ps |
| CPU time | 471.53 seconds |
| Started | Sep 10 07:33:58 AM UTC 24 |
| Finished | Sep 10 07:41:56 AM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149753128 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.149753128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/92.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_slow_rsp.2124674865 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 31727700708 ps |
| CPU time | 438.48 seconds |
| Started | Sep 10 07:33:56 AM UTC 24 |
| Finished | Sep 10 07:41:20 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124674865 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.2124674865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/92.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_zero_delays.2750890471 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 40995065 ps |
| CPU time | 8.95 seconds |
| Started | Sep 10 07:33:57 AM UTC 24 |
| Finished | Sep 10 07:34:07 AM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750890471 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_delays.2750890471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/92.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_same_source.804262847 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 2225494484 ps |
| CPU time | 73.56 seconds |
| Started | Sep 10 07:33:59 AM UTC 24 |
| Finished | Sep 10 07:35:15 AM UTC 24 |
| Peak memory | 595756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804262847 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.804262847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/92.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.3385268571 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 210931309 ps |
| CPU time | 12.87 seconds |
| Started | Sep 10 07:33:22 AM UTC 24 |
| Finished | Sep 10 07:33:36 AM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385268571 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.3385268571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/92.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_large_delays.2775850027 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 6128138602 ps |
| CPU time | 75.24 seconds |
| Started | Sep 10 07:33:32 AM UTC 24 |
| Finished | Sep 10 07:34:50 AM UTC 24 |
| Peak memory | 593944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775850027 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.2775850027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/92.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.3612281499 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 5909558473 ps |
| CPU time | 101.83 seconds |
| Started | Sep 10 07:33:32 AM UTC 24 |
| Finished | Sep 10 07:35:17 AM UTC 24 |
| Peak memory | 593980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612281499 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.3612281499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.3430141546 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 50714491 ps |
| CPU time | 8.95 seconds |
| Started | Sep 10 07:33:29 AM UTC 24 |
| Finished | Sep 10 07:33:39 AM UTC 24 |
| Peak memory | 593804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430141546 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delays.3430141546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/92.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all.3166452672 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 2047522459 ps |
| CPU time | 73.21 seconds |
| Started | Sep 10 07:34:06 AM UTC 24 |
| Finished | Sep 10 07:35:22 AM UTC 24 |
| Peak memory | 595884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166452672 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.3166452672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/92.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_error.3682113123 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 243039096 ps |
| CPU time | 24.1 seconds |
| Started | Sep 10 07:34:12 AM UTC 24 |
| Finished | Sep 10 07:34:38 AM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682113123 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.3682113123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/92.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.3946750093 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 1236987408 ps |
| CPU time | 96.71 seconds |
| Started | Sep 10 07:34:11 AM UTC 24 |
| Finished | Sep 10 07:35:50 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946750093 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_rand_reset.3946750093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.2118029677 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 3763667408 ps |
| CPU time | 228.18 seconds |
| Started | Sep 10 07:34:13 AM UTC 24 |
| Finished | Sep 10 07:38:05 AM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118029677 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_reset_error.2118029677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_unmapped_addr.1628710067 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 1045656775 ps |
| CPU time | 58.38 seconds |
| Started | Sep 10 07:34:03 AM UTC 24 |
| Finished | Sep 10 07:35:03 AM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628710067 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.1628710067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/92.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device.1562953002 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 1261896854 ps |
| CPU time | 105.49 seconds |
| Started | Sep 10 07:34:59 AM UTC 24 |
| Finished | Sep 10 07:36:46 AM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562953002 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device.1562953002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/93.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.3886271436 |
| Short name | T2916 |
| Test name | |
| Test status | |
| Simulation time | 58404318658 ps |
| CPU time | 888.21 seconds |
| Started | Sep 10 07:35:03 AM UTC 24 |
| Finished | Sep 10 07:50:02 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886271436 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device_slow_rsp.3886271436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.3617138281 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 302059112 ps |
| CPU time | 18.95 seconds |
| Started | Sep 10 07:35:11 AM UTC 24 |
| Finished | Sep 10 07:35:31 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617138281 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_addr.3617138281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_random.3193008632 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 448329692 ps |
| CPU time | 36.77 seconds |
| Started | Sep 10 07:35:15 AM UTC 24 |
| Finished | Sep 10 07:35:53 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193008632 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.3193008632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/93.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random.1015364934 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 1552361457 ps |
| CPU time | 61.94 seconds |
| Started | Sep 10 07:34:44 AM UTC 24 |
| Finished | Sep 10 07:35:48 AM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015364934 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.1015364934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/93.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_large_delays.1890972976 |
| Short name | T2908 |
| Test name | |
| Test status | |
| Simulation time | 91063614980 ps |
| CPU time | 780.59 seconds |
| Started | Sep 10 07:34:55 AM UTC 24 |
| Finished | Sep 10 07:48:04 AM UTC 24 |
| Peak memory | 595980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890972976 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.1890972976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/93.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_slow_rsp.3241726378 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 28664096354 ps |
| CPU time | 497.43 seconds |
| Started | Sep 10 07:34:57 AM UTC 24 |
| Finished | Sep 10 07:43:21 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241726378 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.3241726378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/93.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_zero_delays.1274131820 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 264176438 ps |
| CPU time | 26.93 seconds |
| Started | Sep 10 07:34:43 AM UTC 24 |
| Finished | Sep 10 07:35:11 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274131820 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_delays.1274131820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/93.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_same_source.3056612194 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 349141221 ps |
| CPU time | 16.07 seconds |
| Started | Sep 10 07:35:07 AM UTC 24 |
| Finished | Sep 10 07:35:24 AM UTC 24 |
| Peak memory | 595876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056612194 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.3056612194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/93.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.1158236279 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 55271254 ps |
| CPU time | 9.77 seconds |
| Started | Sep 10 07:34:30 AM UTC 24 |
| Finished | Sep 10 07:34:42 AM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158236279 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.1158236279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/93.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_large_delays.1775242817 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 9545056911 ps |
| CPU time | 106.16 seconds |
| Started | Sep 10 07:34:35 AM UTC 24 |
| Finished | Sep 10 07:36:23 AM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775242817 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.1775242817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/93.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.2990573211 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 5393510066 ps |
| CPU time | 94.81 seconds |
| Started | Sep 10 07:34:40 AM UTC 24 |
| Finished | Sep 10 07:36:17 AM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990573211 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.2990573211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_zero_delays.433699743 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 44073762 ps |
| CPU time | 6.03 seconds |
| Started | Sep 10 07:34:28 AM UTC 24 |
| Finished | Sep 10 07:34:35 AM UTC 24 |
| Peak memory | 593900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433699743 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delays.433699743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/93.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all.3885144677 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 7959705390 ps |
| CPU time | 314.02 seconds |
| Started | Sep 10 07:35:16 AM UTC 24 |
| Finished | Sep 10 07:40:35 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885144677 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.3885144677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/93.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_error.4021249753 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 13173657047 ps |
| CPU time | 371.26 seconds |
| Started | Sep 10 07:35:28 AM UTC 24 |
| Finished | Sep 10 07:41:44 AM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021249753 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.4021249753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/93.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.2367077074 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 405469386 ps |
| CPU time | 98.2 seconds |
| Started | Sep 10 07:35:20 AM UTC 24 |
| Finished | Sep 10 07:37:00 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367077074 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_rand_reset.2367077074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.2661274631 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 8530317701 ps |
| CPU time | 375.07 seconds |
| Started | Sep 10 07:35:33 AM UTC 24 |
| Finished | Sep 10 07:41:53 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661274631 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_reset_error.2661274631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_unmapped_addr.3548635631 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 431738466 ps |
| CPU time | 18.28 seconds |
| Started | Sep 10 07:35:13 AM UTC 24 |
| Finished | Sep 10 07:35:32 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548635631 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.3548635631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/93.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device.2122862594 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 26660825 ps |
| CPU time | 10.06 seconds |
| Started | Sep 10 07:35:56 AM UTC 24 |
| Finished | Sep 10 07:36:07 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122862594 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device.2122862594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/94.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.2646966210 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 32169597255 ps |
| CPU time | 490.08 seconds |
| Started | Sep 10 07:35:58 AM UTC 24 |
| Finished | Sep 10 07:44:14 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646966210 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device_slow_rsp.2646966210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.1087912607 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 315390276 ps |
| CPU time | 46.12 seconds |
| Started | Sep 10 07:36:17 AM UTC 24 |
| Finished | Sep 10 07:37:05 AM UTC 24 |
| Peak memory | 595920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087912607 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_addr.1087912607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_random.3170950454 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 2352728503 ps |
| CPU time | 86.17 seconds |
| Started | Sep 10 07:36:11 AM UTC 24 |
| Finished | Sep 10 07:37:39 AM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170950454 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.3170950454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/94.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random.412030370 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 160507625 ps |
| CPU time | 15.28 seconds |
| Started | Sep 10 07:35:46 AM UTC 24 |
| Finished | Sep 10 07:36:03 AM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412030370 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.412030370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/94.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_large_delays.1067048476 |
| Short name | T2918 |
| Test name | |
| Test status | |
| Simulation time | 102409084399 ps |
| CPU time | 912.02 seconds |
| Started | Sep 10 07:35:52 AM UTC 24 |
| Finished | Sep 10 07:51:14 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067048476 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.1067048476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/94.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_slow_rsp.4036224089 |
| Short name | T2917 |
| Test name | |
| Test status | |
| Simulation time | 64735645449 ps |
| CPU time | 855.18 seconds |
| Started | Sep 10 07:35:55 AM UTC 24 |
| Finished | Sep 10 07:50:19 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036224089 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.4036224089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/94.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_zero_delays.4038293651 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 553971401 ps |
| CPU time | 58.71 seconds |
| Started | Sep 10 07:35:50 AM UTC 24 |
| Finished | Sep 10 07:36:50 AM UTC 24 |
| Peak memory | 596036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038293651 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_delays.4038293651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/94.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_same_source.3710488745 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 1400607587 ps |
| CPU time | 35.39 seconds |
| Started | Sep 10 07:36:12 AM UTC 24 |
| Finished | Sep 10 07:36:49 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710488745 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.3710488745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/94.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke.1339902400 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 155789653 ps |
| CPU time | 9.63 seconds |
| Started | Sep 10 07:35:38 AM UTC 24 |
| Finished | Sep 10 07:35:48 AM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339902400 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.1339902400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/94.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_large_delays.1461445676 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 8321308387 ps |
| CPU time | 104.48 seconds |
| Started | Sep 10 07:35:42 AM UTC 24 |
| Finished | Sep 10 07:37:29 AM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461445676 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.1461445676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/94.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.3877410055 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 4855972869 ps |
| CPU time | 115.35 seconds |
| Started | Sep 10 07:35:43 AM UTC 24 |
| Finished | Sep 10 07:37:41 AM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877410055 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.3877410055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_zero_delays.2242892901 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 45158815 ps |
| CPU time | 9.03 seconds |
| Started | Sep 10 07:35:34 AM UTC 24 |
| Finished | Sep 10 07:35:44 AM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242892901 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delays.2242892901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/94.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all.951660807 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 15369431842 ps |
| CPU time | 500.56 seconds |
| Started | Sep 10 07:36:20 AM UTC 24 |
| Finished | Sep 10 07:44:47 AM UTC 24 |
| Peak memory | 596156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951660807 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.951660807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/94.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_error.3297695272 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 4140044804 ps |
| CPU time | 142 seconds |
| Started | Sep 10 07:36:32 AM UTC 24 |
| Finished | Sep 10 07:38:57 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297695272 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.3297695272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/94.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.695487470 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 118798032 ps |
| CPU time | 62.71 seconds |
| Started | Sep 10 07:36:31 AM UTC 24 |
| Finished | Sep 10 07:37:35 AM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695487470 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_rand_reset.695487470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.664828816 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 67398967 ps |
| CPU time | 28.74 seconds |
| Started | Sep 10 07:36:40 AM UTC 24 |
| Finished | Sep 10 07:37:10 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664828816 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_reset_error.664828816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_unmapped_addr.1729994048 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 1041794330 ps |
| CPU time | 50.64 seconds |
| Started | Sep 10 07:36:16 AM UTC 24 |
| Finished | Sep 10 07:37:08 AM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729994048 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.1729994048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/94.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device.3100566410 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 851831447 ps |
| CPU time | 39.59 seconds |
| Started | Sep 10 07:37:18 AM UTC 24 |
| Finished | Sep 10 07:37:59 AM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100566410 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device.3100566410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/95.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.531355254 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 33194916068 ps |
| CPU time | 458.76 seconds |
| Started | Sep 10 07:37:15 AM UTC 24 |
| Finished | Sep 10 07:45:00 AM UTC 24 |
| Peak memory | 596036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531355254 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device_slow_rsp.531355254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.1426464825 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 353499437 ps |
| CPU time | 16.5 seconds |
| Started | Sep 10 07:37:27 AM UTC 24 |
| Finished | Sep 10 07:37:45 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426464825 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_addr.1426464825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_random.1929920691 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 293924099 ps |
| CPU time | 22.01 seconds |
| Started | Sep 10 07:37:24 AM UTC 24 |
| Finished | Sep 10 07:37:50 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929920691 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.1929920691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/95.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random.2305178459 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 1963668230 ps |
| CPU time | 64.94 seconds |
| Started | Sep 10 07:37:13 AM UTC 24 |
| Finished | Sep 10 07:38:20 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305178459 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.2305178459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/95.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_large_delays.19298686 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 25079206648 ps |
| CPU time | 307.12 seconds |
| Started | Sep 10 07:37:15 AM UTC 24 |
| Finished | Sep 10 07:42:27 AM UTC 24 |
| Peak memory | 596136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19298686 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.19298686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/95.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_slow_rsp.263025824 |
| Short name | T2911 |
| Test name | |
| Test status | |
| Simulation time | 47556830532 ps |
| CPU time | 713.07 seconds |
| Started | Sep 10 07:37:13 AM UTC 24 |
| Finished | Sep 10 07:49:14 AM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263025824 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.263025824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/95.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_zero_delays.2511721396 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 82341334 ps |
| CPU time | 12.02 seconds |
| Started | Sep 10 07:37:15 AM UTC 24 |
| Finished | Sep 10 07:37:28 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511721396 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_delays.2511721396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/95.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_same_source.3340748850 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 2331325731 ps |
| CPU time | 70.81 seconds |
| Started | Sep 10 07:37:20 AM UTC 24 |
| Finished | Sep 10 07:38:33 AM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340748850 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.3340748850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/95.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke.3273341574 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 189035433 ps |
| CPU time | 11.47 seconds |
| Started | Sep 10 07:36:43 AM UTC 24 |
| Finished | Sep 10 07:36:56 AM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273341574 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.3273341574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/95.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_large_delays.2540054898 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 8123793476 ps |
| CPU time | 101 seconds |
| Started | Sep 10 07:36:50 AM UTC 24 |
| Finished | Sep 10 07:38:34 AM UTC 24 |
| Peak memory | 594076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540054898 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.2540054898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/95.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.1471618524 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 5128869633 ps |
| CPU time | 109.16 seconds |
| Started | Sep 10 07:36:57 AM UTC 24 |
| Finished | Sep 10 07:38:48 AM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471618524 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.1471618524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_zero_delays.1362991461 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 46696766 ps |
| CPU time | 8.54 seconds |
| Started | Sep 10 07:36:42 AM UTC 24 |
| Finished | Sep 10 07:36:52 AM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362991461 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delays.1362991461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/95.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all.3944038229 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 9149634786 ps |
| CPU time | 319.87 seconds |
| Started | Sep 10 07:37:35 AM UTC 24 |
| Finished | Sep 10 07:43:00 AM UTC 24 |
| Peak memory | 595864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944038229 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.3944038229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/95.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_error.2868353712 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 13307549680 ps |
| CPU time | 382.79 seconds |
| Started | Sep 10 07:37:32 AM UTC 24 |
| Finished | Sep 10 07:44:01 AM UTC 24 |
| Peak memory | 595816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868353712 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.2868353712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/95.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.433197829 |
| Short name | T2903 |
| Test name | |
| Test status | |
| Simulation time | 9497705086 ps |
| CPU time | 539.42 seconds |
| Started | Sep 10 07:37:32 AM UTC 24 |
| Finished | Sep 10 07:46:39 AM UTC 24 |
| Peak memory | 596012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433197829 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_rand_reset.433197829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.2144047222 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 7583754782 ps |
| CPU time | 475.46 seconds |
| Started | Sep 10 07:37:57 AM UTC 24 |
| Finished | Sep 10 07:45:59 AM UTC 24 |
| Peak memory | 595996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144047222 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_reset_error.2144047222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_unmapped_addr.4111213163 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 629513216 ps |
| CPU time | 23.38 seconds |
| Started | Sep 10 07:37:23 AM UTC 24 |
| Finished | Sep 10 07:37:50 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111213163 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.4111213163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/95.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device.2301779317 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 872554861 ps |
| CPU time | 65.24 seconds |
| Started | Sep 10 07:38:28 AM UTC 24 |
| Finished | Sep 10 07:39:35 AM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301779317 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device.2301779317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/96.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2219320153 |
| Short name | T2924 |
| Test name | |
| Test status | |
| Simulation time | 107082214918 ps |
| CPU time | 1310.56 seconds |
| Started | Sep 10 07:38:32 AM UTC 24 |
| Finished | Sep 10 08:00:35 AM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219320153 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device_slow_rsp.2219320153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.285778799 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 1350608818 ps |
| CPU time | 68.49 seconds |
| Started | Sep 10 07:38:47 AM UTC 24 |
| Finished | Sep 10 07:39:57 AM UTC 24 |
| Peak memory | 595820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285778799 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_addr.285778799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_random.2171435269 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 35002275 ps |
| CPU time | 6.92 seconds |
| Started | Sep 10 07:38:39 AM UTC 24 |
| Finished | Sep 10 07:38:47 AM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171435269 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.2171435269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/96.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random.601612295 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 236153073 ps |
| CPU time | 22.73 seconds |
| Started | Sep 10 07:38:10 AM UTC 24 |
| Finished | Sep 10 07:38:34 AM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601612295 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.601612295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/96.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_large_delays.518006148 |
| Short name | T2910 |
| Test name | |
| Test status | |
| Simulation time | 70076186138 ps |
| CPU time | 628.46 seconds |
| Started | Sep 10 07:38:17 AM UTC 24 |
| Finished | Sep 10 07:48:52 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518006148 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.518006148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/96.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_slow_rsp.2985616783 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 7055889025 ps |
| CPU time | 144.78 seconds |
| Started | Sep 10 07:38:16 AM UTC 24 |
| Finished | Sep 10 07:40:43 AM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985616783 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.2985616783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/96.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_zero_delays.3118141356 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 385689628 ps |
| CPU time | 39.55 seconds |
| Started | Sep 10 07:38:12 AM UTC 24 |
| Finished | Sep 10 07:38:53 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118141356 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_delays.3118141356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/96.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_same_source.3367393683 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 116261723 ps |
| CPU time | 15.31 seconds |
| Started | Sep 10 07:38:34 AM UTC 24 |
| Finished | Sep 10 07:38:50 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367393683 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.3367393683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/96.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke.3308928394 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 214582484 ps |
| CPU time | 10.35 seconds |
| Started | Sep 10 07:37:55 AM UTC 24 |
| Finished | Sep 10 07:38:07 AM UTC 24 |
| Peak memory | 593892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308928394 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.3308928394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/96.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_large_delays.397002606 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 7499614087 ps |
| CPU time | 65.24 seconds |
| Started | Sep 10 07:38:06 AM UTC 24 |
| Finished | Sep 10 07:39:13 AM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397002606 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.397002606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/96.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.3331359203 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 6336368157 ps |
| CPU time | 120.22 seconds |
| Started | Sep 10 07:38:10 AM UTC 24 |
| Finished | Sep 10 07:40:12 AM UTC 24 |
| Peak memory | 593720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331359203 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.3331359203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_zero_delays.328798520 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 51562529 ps |
| CPU time | 8.82 seconds |
| Started | Sep 10 07:38:03 AM UTC 24 |
| Finished | Sep 10 07:38:13 AM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328798520 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delays.328798520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/96.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all.3596329799 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 8370940816 ps |
| CPU time | 274.72 seconds |
| Started | Sep 10 07:38:54 AM UTC 24 |
| Finished | Sep 10 07:43:32 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596329799 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.3596329799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/96.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_error.289811377 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 12060700795 ps |
| CPU time | 353.76 seconds |
| Started | Sep 10 07:39:01 AM UTC 24 |
| Finished | Sep 10 07:44:59 AM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289811377 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.289811377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/96.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.3774280481 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 703091578 ps |
| CPU time | 207.4 seconds |
| Started | Sep 10 07:39:00 AM UTC 24 |
| Finished | Sep 10 07:42:30 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774280481 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_rand_reset.3774280481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.856766289 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 10176136480 ps |
| CPU time | 433.16 seconds |
| Started | Sep 10 07:38:59 AM UTC 24 |
| Finished | Sep 10 07:46:18 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856766289 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_reset_error.856766289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_unmapped_addr.2233108888 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 602700488 ps |
| CPU time | 24.78 seconds |
| Started | Sep 10 07:38:45 AM UTC 24 |
| Finished | Sep 10 07:39:11 AM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233108888 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.2233108888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/96.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device.886920478 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 451823686 ps |
| CPU time | 45.98 seconds |
| Started | Sep 10 07:39:40 AM UTC 24 |
| Finished | Sep 10 07:40:27 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886920478 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device.886920478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/97.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.827520275 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 12250866930 ps |
| CPU time | 190.56 seconds |
| Started | Sep 10 07:39:41 AM UTC 24 |
| Finished | Sep 10 07:42:55 AM UTC 24 |
| Peak memory | 596144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827520275 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device_slow_rsp.827520275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.125981347 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 870272395 ps |
| CPU time | 46.88 seconds |
| Started | Sep 10 07:40:14 AM UTC 24 |
| Finished | Sep 10 07:41:03 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125981347 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_addr.125981347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_random.3035408900 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 2166920625 ps |
| CPU time | 79.42 seconds |
| Started | Sep 10 07:39:54 AM UTC 24 |
| Finished | Sep 10 07:41:15 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035408900 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.3035408900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/97.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random.3417604749 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 1215404897 ps |
| CPU time | 56.76 seconds |
| Started | Sep 10 07:39:22 AM UTC 24 |
| Finished | Sep 10 07:40:21 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417604749 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.3417604749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/97.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_large_delays.3774098563 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 13246088987 ps |
| CPU time | 129.05 seconds |
| Started | Sep 10 07:39:24 AM UTC 24 |
| Finished | Sep 10 07:41:36 AM UTC 24 |
| Peak memory | 595756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774098563 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.3774098563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/97.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_slow_rsp.4277908757 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 3693079464 ps |
| CPU time | 47 seconds |
| Started | Sep 10 07:39:38 AM UTC 24 |
| Finished | Sep 10 07:40:27 AM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277908757 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.4277908757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/97.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_zero_delays.1030777058 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 172275353 ps |
| CPU time | 21.83 seconds |
| Started | Sep 10 07:39:23 AM UTC 24 |
| Finished | Sep 10 07:39:46 AM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030777058 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_delays.1030777058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/97.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_same_source.1307069105 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 702210578 ps |
| CPU time | 32.76 seconds |
| Started | Sep 10 07:39:45 AM UTC 24 |
| Finished | Sep 10 07:40:20 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307069105 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.1307069105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/97.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke.4281191229 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 170053914 ps |
| CPU time | 8.06 seconds |
| Started | Sep 10 07:39:07 AM UTC 24 |
| Finished | Sep 10 07:39:16 AM UTC 24 |
| Peak memory | 593784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281191229 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.4281191229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/97.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_large_delays.2632201965 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 9976366610 ps |
| CPU time | 102.03 seconds |
| Started | Sep 10 07:39:14 AM UTC 24 |
| Finished | Sep 10 07:40:58 AM UTC 24 |
| Peak memory | 593704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632201965 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.2632201965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/97.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.3190474365 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 4416725724 ps |
| CPU time | 99.4 seconds |
| Started | Sep 10 07:39:19 AM UTC 24 |
| Finished | Sep 10 07:41:01 AM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190474365 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.3190474365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_zero_delays.1644316011 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 44351831 ps |
| CPU time | 9.02 seconds |
| Started | Sep 10 07:39:14 AM UTC 24 |
| Finished | Sep 10 07:39:25 AM UTC 24 |
| Peak memory | 593804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644316011 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delays.1644316011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/97.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all.2541590913 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 232287619 ps |
| CPU time | 36.8 seconds |
| Started | Sep 10 07:40:26 AM UTC 24 |
| Finished | Sep 10 07:41:04 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541590913 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.2541590913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/97.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.883619386 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 2845848574 ps |
| CPU time | 276.4 seconds |
| Started | Sep 10 07:40:41 AM UTC 24 |
| Finished | Sep 10 07:45:21 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883619386 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_rand_reset.883619386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.3255572642 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 4238083317 ps |
| CPU time | 173.7 seconds |
| Started | Sep 10 07:40:48 AM UTC 24 |
| Finished | Sep 10 07:43:45 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255572642 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_reset_error.3255572642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_unmapped_addr.2192009219 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 865807541 ps |
| CPU time | 40.52 seconds |
| Started | Sep 10 07:40:04 AM UTC 24 |
| Finished | Sep 10 07:40:46 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192009219 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.2192009219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/97.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device.749393423 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 444083261 ps |
| CPU time | 26.01 seconds |
| Started | Sep 10 07:41:26 AM UTC 24 |
| Finished | Sep 10 07:41:54 AM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749393423 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device.749393423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/98.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.421435368 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 24628574948 ps |
| CPU time | 296.99 seconds |
| Started | Sep 10 07:41:29 AM UTC 24 |
| Finished | Sep 10 07:46:30 AM UTC 24 |
| Peak memory | 596128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421435368 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device_slow_rsp.421435368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.2701060426 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 256836806 ps |
| CPU time | 24.62 seconds |
| Started | Sep 10 07:41:42 AM UTC 24 |
| Finished | Sep 10 07:42:08 AM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701060426 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_addr.2701060426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_random.1821184550 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 2421892410 ps |
| CPU time | 72.66 seconds |
| Started | Sep 10 07:41:28 AM UTC 24 |
| Finished | Sep 10 07:42:42 AM UTC 24 |
| Peak memory | 596100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821184550 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.1821184550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/98.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random.1939275991 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 581754390 ps |
| CPU time | 44.47 seconds |
| Started | Sep 10 07:41:11 AM UTC 24 |
| Finished | Sep 10 07:41:57 AM UTC 24 |
| Peak memory | 596040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939275991 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.1939275991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/98.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_large_delays.2527091319 |
| Short name | T2922 |
| Test name | |
| Test status | |
| Simulation time | 87168369017 ps |
| CPU time | 700.56 seconds |
| Started | Sep 10 07:41:24 AM UTC 24 |
| Finished | Sep 10 07:53:12 AM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527091319 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.2527091319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/98.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_slow_rsp.4117079213 |
| Short name | T2919 |
| Test name | |
| Test status | |
| Simulation time | 51518316824 ps |
| CPU time | 635.91 seconds |
| Started | Sep 10 07:41:25 AM UTC 24 |
| Finished | Sep 10 07:52:07 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117079213 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.4117079213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/98.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_zero_delays.572295687 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 244644751 ps |
| CPU time | 21.96 seconds |
| Started | Sep 10 07:41:08 AM UTC 24 |
| Finished | Sep 10 07:41:31 AM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572295687 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_delays.572295687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/98.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_same_source.3981984471 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 368713331 ps |
| CPU time | 14.88 seconds |
| Started | Sep 10 07:41:28 AM UTC 24 |
| Finished | Sep 10 07:41:44 AM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981984471 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.3981984471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/98.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke.4109148389 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 232284538 ps |
| CPU time | 13.06 seconds |
| Started | Sep 10 07:40:50 AM UTC 24 |
| Finished | Sep 10 07:41:05 AM UTC 24 |
| Peak memory | 593836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109148389 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.4109148389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/98.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_large_delays.2613925904 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 6688936931 ps |
| CPU time | 100.01 seconds |
| Started | Sep 10 07:40:53 AM UTC 24 |
| Finished | Sep 10 07:42:35 AM UTC 24 |
| Peak memory | 594092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613925904 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.2613925904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/98.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.3124480048 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 6111142021 ps |
| CPU time | 131.95 seconds |
| Started | Sep 10 07:41:04 AM UTC 24 |
| Finished | Sep 10 07:43:18 AM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124480048 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.3124480048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_zero_delays.2016361940 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 44901416 ps |
| CPU time | 8.32 seconds |
| Started | Sep 10 07:40:55 AM UTC 24 |
| Finished | Sep 10 07:41:05 AM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016361940 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delays.2016361940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/98.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all.2119711405 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 3480422814 ps |
| CPU time | 135.69 seconds |
| Started | Sep 10 07:41:43 AM UTC 24 |
| Finished | Sep 10 07:44:01 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119711405 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.2119711405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/98.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_error.2113454104 |
| Short name | T2906 |
| Test name | |
| Test status | |
| Simulation time | 10123441291 ps |
| CPU time | 286.45 seconds |
| Started | Sep 10 07:41:58 AM UTC 24 |
| Finished | Sep 10 07:46:49 AM UTC 24 |
| Peak memory | 596032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113454104 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.2113454104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/98.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.1253072600 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 3547885756 ps |
| CPU time | 173.91 seconds |
| Started | Sep 10 07:41:46 AM UTC 24 |
| Finished | Sep 10 07:44:43 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253072600 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_rand_reset.1253072600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.3775997939 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 2057541193 ps |
| CPU time | 126.49 seconds |
| Started | Sep 10 07:41:59 AM UTC 24 |
| Finished | Sep 10 07:44:08 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775997939 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_reset_error.3775997939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_unmapped_addr.3188722901 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 741881491 ps |
| CPU time | 28.93 seconds |
| Started | Sep 10 07:41:36 AM UTC 24 |
| Finished | Sep 10 07:42:06 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188722901 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.3188722901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/98.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device.2902149336 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 748364009 ps |
| CPU time | 53.39 seconds |
| Started | Sep 10 07:42:46 AM UTC 24 |
| Finished | Sep 10 07:43:41 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902149336 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device.2902149336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/99.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.3360899037 |
| Short name | T2925 |
| Test name | |
| Test status | |
| Simulation time | 103885284180 ps |
| CPU time | 1149.61 seconds |
| Started | Sep 10 07:42:49 AM UTC 24 |
| Finished | Sep 10 08:02:09 AM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360899037 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device_slow_rsp.3360899037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.882429855 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 501345721 ps |
| CPU time | 19.69 seconds |
| Started | Sep 10 07:43:06 AM UTC 24 |
| Finished | Sep 10 07:43:27 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882429855 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_addr.882429855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random.2871661793 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 313793432 ps |
| CPU time | 36.75 seconds |
| Started | Sep 10 07:42:21 AM UTC 24 |
| Finished | Sep 10 07:42:59 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871661793 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.2871661793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/99.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_large_delays.1717289738 |
| Short name | T2912 |
| Test name | |
| Test status | |
| Simulation time | 46911493209 ps |
| CPU time | 398.08 seconds |
| Started | Sep 10 07:42:34 AM UTC 24 |
| Finished | Sep 10 07:49:17 AM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717289738 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.1717289738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/99.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_slow_rsp.3459709301 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 17620248597 ps |
| CPU time | 236.34 seconds |
| Started | Sep 10 07:42:34 AM UTC 24 |
| Finished | Sep 10 07:46:34 AM UTC 24 |
| Peak memory | 596004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459709301 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.3459709301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/99.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_zero_delays.2210121323 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 386841292 ps |
| CPU time | 38.85 seconds |
| Started | Sep 10 07:42:25 AM UTC 24 |
| Finished | Sep 10 07:43:05 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210121323 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_delays.2210121323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/99.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_same_source.2112541826 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 2699457960 ps |
| CPU time | 88.13 seconds |
| Started | Sep 10 07:42:54 AM UTC 24 |
| Finished | Sep 10 07:44:24 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112541826 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.2112541826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/99.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke.3272775462 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 238730525 ps |
| CPU time | 12.36 seconds |
| Started | Sep 10 07:42:08 AM UTC 24 |
| Finished | Sep 10 07:42:22 AM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272775462 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.3272775462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/99.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_large_delays.1859916458 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 10203751438 ps |
| CPU time | 98.42 seconds |
| Started | Sep 10 07:42:17 AM UTC 24 |
| Finished | Sep 10 07:43:57 AM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859916458 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.1859916458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/99.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.2894973285 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 5217512629 ps |
| CPU time | 98.76 seconds |
| Started | Sep 10 07:42:19 AM UTC 24 |
| Finished | Sep 10 07:44:00 AM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894973285 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.2894973285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_zero_delays.1006695795 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 58792916 ps |
| CPU time | 7.21 seconds |
| Started | Sep 10 07:42:10 AM UTC 24 |
| Finished | Sep 10 07:42:18 AM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006695795 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delays.1006695795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/99.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all.221502925 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 6237703007 ps |
| CPU time | 188 seconds |
| Started | Sep 10 07:43:10 AM UTC 24 |
| Finished | Sep 10 07:46:21 AM UTC 24 |
| Peak memory | 596032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221502925 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.221502925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/99.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_error.3648947295 |
| Short name | T2905 |
| Test name | |
| Test status | |
| Simulation time | 7179127546 ps |
| CPU time | 197.58 seconds |
| Started | Sep 10 07:43:27 AM UTC 24 |
| Finished | Sep 10 07:46:47 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648947295 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.3648947295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/99.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.1284510474 |
| Short name | T2907 |
| Test name | |
| Test status | |
| Simulation time | 3464348577 ps |
| CPU time | 213.54 seconds |
| Started | Sep 10 07:43:21 AM UTC 24 |
| Finished | Sep 10 07:46:58 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284510474 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_rand_reset.1284510474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.2875877915 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 1866452682 ps |
| CPU time | 116.73 seconds |
| Started | Sep 10 07:43:27 AM UTC 24 |
| Finished | Sep 10 07:45:26 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875877915 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_reset_error.2875877915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_unmapped_addr.1240046142 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 246589831 ps |
| CPU time | 12.69 seconds |
| Started | Sep 10 07:43:04 AM UTC 24 |
| Finished | Sep 10 07:43:18 AM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240046142 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.1240046142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/99.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.3190051820 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 13765845495 ps |
| CPU time | 1529.22 seconds |
| Started | Sep 09 11:21:35 PM UTC 24 |
| Finished | Sep 09 11:47:25 PM UTC 24 |
| Peak memory | 623272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190051820 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.3190051820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_jtag_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sival_flash_info_access.2937855451 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 2885819782 ps |
| CPU time | 244.36 seconds |
| Started | Sep 09 10:43:09 PM UTC 24 |
| Finished | Sep 09 10:47:18 PM UTC 24 |
| Peak memory | 625524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim _dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937855451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.2937855451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sival_flash_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc.320345534 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 2263102360 ps |
| CPU time | 228.39 seconds |
| Started | Sep 09 10:57:08 PM UTC 24 |
| Finished | Sep 09 11:01:01 PM UTC 24 |
| Peak memory | 623704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_i mages=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=320345534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.320345534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en.1281166257 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 3085749723 ps |
| CPU time | 240.59 seconds |
| Started | Sep 09 10:57:09 PM UTC 24 |
| Finished | Sep 09 11:01:14 PM UTC 24 |
| Peak memory | 623532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281166257 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.1281166257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.936361420 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 2674842281 ps |
| CPU time | 254.96 seconds |
| Started | Sep 09 11:29:55 PM UTC 24 |
| Finished | Sep 09 11:34:15 PM UTC 24 |
| Peak memory | 623532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936361420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.936361420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_entropy.990105573 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 3199702188 ps |
| CPU time | 266.59 seconds |
| Started | Sep 09 11:03:46 PM UTC 24 |
| Finished | Sep 09 11:08:17 PM UTC 24 |
| Peak memory | 625720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990105573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_aes_entropy.990105573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_idle.2486724488 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 3013248650 ps |
| CPU time | 279.01 seconds |
| Started | Sep 09 10:59:05 PM UTC 24 |
| Finished | Sep 09 11:03:48 PM UTC 24 |
| Peak memory | 625764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486724488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.2486724488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_smoketest.1689840204 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 2570211600 ps |
| CPU time | 316.14 seconds |
| Started | Sep 10 12:26:20 AM UTC 24 |
| Finished | Sep 10 12:31:41 AM UTC 24 |
| Peak memory | 623716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1689840204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_a es_smoketest.1689840204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.1250674215 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 3314817245 ps |
| CPU time | 283.44 seconds |
| Started | Sep 09 11:03:48 PM UTC 24 |
| Finished | Sep 09 11:08:37 PM UTC 24 |
| Peak memory | 623652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250674215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.1250674215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_escalation.2251790656 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 5534008688 ps |
| CPU time | 456.93 seconds |
| Started | Sep 09 10:59:39 PM UTC 24 |
| Finished | Sep 09 11:07:22 PM UTC 24 |
| Peak memory | 635968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251790656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_ earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.2251790656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3239867578 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 5373132414 ps |
| CPU time | 991.21 seconds |
| Started | Sep 09 11:02:51 PM UTC 24 |
| Finished | Sep 09 11:19:35 PM UTC 24 |
| Peak memory | 625724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239867578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_ea rlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.3239867578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2275152754 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 8626132590 ps |
| CPU time | 1877.57 seconds |
| Started | Sep 09 11:03:36 PM UTC 24 |
| Finished | Sep 09 11:35:19 PM UTC 24 |
| Peak memory | 625728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275152754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_toggle.2275152754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_timeout.2944143942 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 5616915708 ps |
| CPU time | 590.04 seconds |
| Started | Sep 09 11:00:17 PM UTC 24 |
| Finished | Sep 09 11:10:15 PM UTC 24 |
| Peak memory | 625820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944143942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.2944143942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_irq.3526063946 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 4453360742 ps |
| CPU time | 425.64 seconds |
| Started | Sep 09 10:54:10 PM UTC 24 |
| Finished | Sep 09 11:01:21 PM UTC 24 |
| Peak memory | 625580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526063946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.3526063946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.294223880 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 6273195372 ps |
| CPU time | 424.38 seconds |
| Started | Sep 09 10:55:26 PM UTC 24 |
| Finished | Sep 09 11:02:37 PM UTC 24 |
| Peak memory | 625828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294223880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.294223880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_smoketest.255215179 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 3823636776 ps |
| CPU time | 463.98 seconds |
| Started | Sep 10 12:26:22 AM UTC 24 |
| Finished | Sep 10 12:34:13 AM UTC 24 |
| Peak memory | 625712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255215179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_aon_timer_smoketest.255215179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2782542376 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 11268348254 ps |
| CPU time | 895.97 seconds |
| Started | Sep 09 10:55:25 PM UTC 24 |
| Finished | Sep 09 11:10:33 PM UTC 24 |
| Peak memory | 625840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782542376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.2782542376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2468366717 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 6072331212 ps |
| CPU time | 681.83 seconds |
| Started | Sep 09 10:55:05 PM UTC 24 |
| Finished | Sep 09 11:06:36 PM UTC 24 |
| Peak memory | 623780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468366717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.2468366717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_outputs.3711952062 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 8102760860 ps |
| CPU time | 796.32 seconds |
| Started | Sep 09 11:23:55 PM UTC 24 |
| Finished | Sep 09 11:37:22 PM UTC 24 |
| Peak memory | 632044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_ clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h w/dv/tools/sim.tcl +ntb_random_seed=3711952062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.3711952062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2505071185 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 10768002196 ps |
| CPU time | 989.09 seconds |
| Started | Sep 09 11:15:53 PM UTC 24 |
| Finished | Sep 09 11:32:36 PM UTC 24 |
| Peak memory | 637968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_de vice=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505071185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.2505071185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2762702278 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 4218261658 ps |
| CPU time | 539.81 seconds |
| Started | Sep 09 11:18:01 PM UTC 24 |
| Finished | Sep 09 11:27:08 PM UTC 24 |
| Peak memory | 625608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762702278 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_rma.2762702278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3881524410 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 4541487640 ps |
| CPU time | 627.98 seconds |
| Started | Sep 09 11:15:57 PM UTC 24 |
| Finished | Sep 09 11:26:34 PM UTC 24 |
| Peak memory | 625808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388 1524410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_exter nal_clk_src_for_sw_fast_test_unlocked0.3881524410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.779773861 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 4854268246 ps |
| CPU time | 626.31 seconds |
| Started | Sep 09 11:17:33 PM UTC 24 |
| Finished | Sep 09 11:28:08 PM UTC 24 |
| Peak memory | 625896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779773861 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src _for_sw_slow_dev.779773861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1967632225 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 4159502530 ps |
| CPU time | 674.22 seconds |
| Started | Sep 09 11:18:31 PM UTC 24 |
| Finished | Sep 09 11:29:55 PM UTC 24 |
| Peak memory | 625756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967632225 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_rma.1967632225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3347029032 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 4448473750 ps |
| CPU time | 574.9 seconds |
| Started | Sep 09 11:16:18 PM UTC 24 |
| Finished | Sep 09 11:26:01 PM UTC 24 |
| Peak memory | 625744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334 7029032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_exter nal_clk_src_for_sw_slow_test_unlocked0.3347029032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter.2785742433 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 2381735739 ps |
| CPU time | 201.61 seconds |
| Started | Sep 09 11:20:20 PM UTC 24 |
| Finished | Sep 09 11:23:45 PM UTC 24 |
| Peak memory | 625524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2785742433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_clkmgr_jitter.2785742433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1347445960 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 2826324310 ps |
| CPU time | 402.32 seconds |
| Started | Sep 09 11:20:20 PM UTC 24 |
| Finished | Sep 09 11:27:08 PM UTC 24 |
| Peak memory | 623604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=1347445960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_clkmgr_jitter_frequency.1347445960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2080902541 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 2723495288 ps |
| CPU time | 195.77 seconds |
| Started | Sep 09 11:28:32 PM UTC 24 |
| Finished | Sep 09 11:31:51 PM UTC 24 |
| Peak memory | 623620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkm gr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2080902541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.2080902541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.875591268 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 5276955772 ps |
| CPU time | 478.78 seconds |
| Started | Sep 09 11:14:17 PM UTC 24 |
| Finished | Sep 09 11:22:22 PM UTC 24 |
| Peak memory | 623704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=875591268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.875591268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.649228526 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 4609524980 ps |
| CPU time | 457.16 seconds |
| Started | Sep 09 11:14:20 PM UTC 24 |
| Finished | Sep 09 11:22:03 PM UTC 24 |
| Peak memory | 625772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=649228526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.649228526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.954123750 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 5379575488 ps |
| CPU time | 434.56 seconds |
| Started | Sep 09 11:15:53 PM UTC 24 |
| Finished | Sep 09 11:23:13 PM UTC 24 |
| Peak memory | 623540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=954123750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.954123750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.332356569 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 5447616170 ps |
| CPU time | 369.9 seconds |
| Started | Sep 09 11:15:51 PM UTC 24 |
| Finished | Sep 09 11:22:07 PM UTC 24 |
| Peak memory | 625780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=332356569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.332356569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_peri.3401501040 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 11387186646 ps |
| CPU time | 1367.82 seconds |
| Started | Sep 09 11:14:20 PM UTC 24 |
| Finished | Sep 09 11:37:26 PM UTC 24 |
| Peak memory | 625584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_i mages=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401501040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.3401501040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_reset_frequency.3995581215 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 4251262204 ps |
| CPU time | 489.47 seconds |
| Started | Sep 09 11:18:50 PM UTC 24 |
| Finished | Sep 09 11:27:07 PM UTC 24 |
| Peak memory | 623544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995581215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.3995581215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1614457088 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 4708001750 ps |
| CPU time | 609.45 seconds |
| Started | Sep 09 11:21:29 PM UTC 24 |
| Finished | Sep 09 11:31:47 PM UTC 24 |
| Peak memory | 625656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614457088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.1614457088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_smoketest.1414939822 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 2881219200 ps |
| CPU time | 326.33 seconds |
| Started | Sep 10 12:26:22 AM UTC 24 |
| Finished | Sep 10 12:31:53 AM UTC 24 |
| Peak memory | 625776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1414939822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_clkmgr_smoketest.1414939822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.3368106815 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 15276692832 ps |
| CPU time | 3514.22 seconds |
| Started | Sep 09 11:03:52 PM UTC 24 |
| Finished | Sep 10 12:03:09 AM UTC 24 |
| Peak memory | 626728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurren cy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3368106815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_csrng_edn_concurrency.3368106815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.951875268 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 115121136340 ps |
| CPU time | 24082.8 seconds |
| Started | Sep 09 11:31:23 PM UTC 24 |
| Finished | Sep 10 06:17:41 AM UTC 24 |
| Peak memory | 628956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim _dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951875268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.951875268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3473587213 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 4816372088 ps |
| CPU time | 453.83 seconds |
| Started | Sep 09 11:04:40 PM UTC 24 |
| Finished | Sep 09 11:12:20 PM UTC 24 |
| Peak memory | 625760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473587213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src _fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.3473587213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_kat_test.2449916971 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 3049637430 ps |
| CPU time | 309.27 seconds |
| Started | Sep 09 11:03:55 PM UTC 24 |
| Finished | Sep 09 11:09:09 PM UTC 24 |
| Peak memory | 623676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449916971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_csrng_kat_test.2449916971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_smoketest.3390691264 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 2803890028 ps |
| CPU time | 280.06 seconds |
| Started | Sep 10 12:30:06 AM UTC 24 |
| Finished | Sep 10 12:34:50 AM UTC 24 |
| Peak memory | 623464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3390691264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _csrng_smoketest.3390691264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.1632378369 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 4540938910 ps |
| CPU time | 1020.72 seconds |
| Started | Sep 09 11:03:47 PM UTC 24 |
| Finished | Sep 09 11:21:01 PM UTC 24 |
| Peak memory | 625872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerat e_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632378369 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_auto_mode.1632378369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.2677098029 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 6285039064 ps |
| CPU time | 1007.91 seconds |
| Started | Sep 09 11:06:04 PM UTC 24 |
| Finished | Sep 09 11:23:05 PM UTC 24 |
| Peak memory | 626140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677098029 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.2677098029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_kat.1226933643 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 3218047412 ps |
| CPU time | 563.02 seconds |
| Started | Sep 09 11:03:53 PM UTC 24 |
| Finished | Sep 09 11:13:24 PM UTC 24 |
| Peak memory | 629768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_a ssert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_k at:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=1226933643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_edn_kat.1226933643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_kat/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_sw_mode.2366791570 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 9129640968 ps |
| CPU time | 1793.37 seconds |
| Started | Sep 09 11:02:52 PM UTC 24 |
| Finished | Sep 09 11:33:07 PM UTC 24 |
| Peak memory | 623732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2366791570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_edn_sw_mode.2366791570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_ast_rng_req.264629794 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 2977206296 ps |
| CPU time | 292.67 seconds |
| Started | Sep 09 11:04:10 PM UTC 24 |
| Finished | Sep 09 11:09:07 PM UTC 24 |
| Peak memory | 623616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264629794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.264629794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_kat_test.700878423 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 2942118420 ps |
| CPU time | 258.62 seconds |
| Started | Sep 09 11:03:13 PM UTC 24 |
| Finished | Sep 09 11:07:35 PM UTC 24 |
| Peak memory | 623540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700878423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.700878423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_smoketest.1906220796 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 3917008566 ps |
| CPU time | 467.53 seconds |
| Started | Sep 10 12:30:50 AM UTC 24 |
| Finished | Sep 10 12:38:45 AM UTC 24 |
| Peak memory | 625780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_de vice=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906220796 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.1906220796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.1600953000 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 2237699638 ps |
| CPU time | 163.89 seconds |
| Started | Sep 09 10:41:29 PM UTC 24 |
| Finished | Sep 09 10:44:16 PM UTC 24 |
| Peak memory | 625516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1600953000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_concurrency.1600953000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_flash.4209816887 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 2711353020 ps |
| CPU time | 221.55 seconds |
| Started | Sep 09 10:41:30 PM UTC 24 |
| Finished | Sep 09 10:45:15 PM UTC 24 |
| Peak memory | 623532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=4209816887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_example_flash.4209816887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_manufacturer.1241410096 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 2484903688 ps |
| CPU time | 192.08 seconds |
| Started | Sep 09 10:41:09 PM UTC 24 |
| Finished | Sep 09 10:44:24 PM UTC 24 |
| Peak memory | 623596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1241410096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ex ample_manufacturer.1241410096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_manufacturer/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_rom.2317201809 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 2133096216 ps |
| CPU time | 95.55 seconds |
| Started | Sep 09 10:41:32 PM UTC 24 |
| Finished | Sep 09 10:43:09 PM UTC 24 |
| Peak memory | 625376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:t est_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2317201809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_example_rom.2317201809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_crash_alert.2641393814 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 5628055474 ps |
| CPU time | 510.77 seconds |
| Started | Sep 09 11:28:31 PM UTC 24 |
| Finished | Sep 09 11:37:09 PM UTC 24 |
| Peak memory | 626056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check= 1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641393814 -assert nopostproc +UVM_TESTNAME=chip_base_test + UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.2641393814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access.2640356628 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 5764353098 ps |
| CPU time | 767.06 seconds |
| Started | Sep 09 10:41:17 PM UTC 24 |
| Finished | Sep 09 10:54:14 PM UTC 24 |
| Peak memory | 625576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2640356628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _flash_ctrl_access.2640356628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2090013078 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 6059332202 ps |
| CPU time | 968.31 seconds |
| Started | Sep 09 10:43:51 PM UTC 24 |
| Finished | Sep 09 11:00:12 PM UTC 24 |
| Peak memory | 625960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=2090013078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_flash_ctrl_access_jitter_en.2090013078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3165966197 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 8299509079 ps |
| CPU time | 1093 seconds |
| Started | Sep 09 11:28:31 PM UTC 24 |
| Finished | Sep 09 11:46:59 PM UTC 24 |
| Peak memory | 623688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165966197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3165966197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3907265363 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 5749510631 ps |
| CPU time | 863.28 seconds |
| Started | Sep 09 10:43:28 PM UTC 24 |
| Finished | Sep 09 10:58:02 PM UTC 24 |
| Peak memory | 623528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=3907265363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_flash_ctrl_clock_freqs.3907265363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.477660668 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 3558365080 ps |
| CPU time | 438.51 seconds |
| Started | Sep 09 10:43:25 PM UTC 24 |
| Finished | Sep 09 10:50:50 PM UTC 24 |
| Peak memory | 623596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=477660668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 0.chip_sw_flash_ctrl_idle_low_power.477660668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_mem_protection.4031226689 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 5217943212 ps |
| CPU time | 996.37 seconds |
| Started | Sep 09 11:35:42 PM UTC 24 |
| Finished | Sep 09 11:52:32 PM UTC 24 |
| Peak memory | 623716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=4031226689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_flash_ctrl_mem_protection.4031226689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.887514692 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 4353693172 ps |
| CPU time | 588.63 seconds |
| Started | Sep 09 10:41:53 PM UTC 24 |
| Finished | Sep 09 10:51:49 PM UTC 24 |
| Peak memory | 623660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887514692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.887514692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3939378344 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 4779417531 ps |
| CPU time | 635.26 seconds |
| Started | Sep 09 10:42:00 PM UTC 24 |
| Finished | Sep 09 10:52:44 PM UTC 24 |
| Peak memory | 623540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939378344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.3939378344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_write_clear.1845872034 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 3342555492 ps |
| CPU time | 293.67 seconds |
| Started | Sep 09 11:28:32 PM UTC 24 |
| Finished | Sep 09 11:33:30 PM UTC 24 |
| Peak memory | 625516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_image s=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845872034 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.1845872034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.3853913338 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 26123997475 ps |
| CPU time | 1962.99 seconds |
| Started | Sep 09 11:30:31 PM UTC 24 |
| Finished | Sep 10 12:03:40 AM UTC 24 |
| Peak memory | 631992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_buil d_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853913338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.3853913338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_scrambling_smoketest.1053813358 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 2055072624 ps |
| CPU time | 181.6 seconds |
| Started | Sep 09 11:35:27 PM UTC 24 |
| Finished | Sep 09 11:38:32 PM UTC 24 |
| Peak memory | 623640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_ima ges=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoketest_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053813358 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chi p_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.1053813358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio_smoketest.563243726 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2681253830 ps |
| CPU time | 244.64 seconds |
| Started | Sep 10 12:32:32 AM UTC 24 |
| Finished | Sep 10 12:36:41 AM UTC 24 |
| Peak memory | 623760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=563243726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_gpio_smoketest.563243726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc.4212213576 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 2526224940 ps |
| CPU time | 283.77 seconds |
| Started | Sep 09 11:06:02 PM UTC 24 |
| Finished | Sep 09 11:10:50 PM UTC 24 |
| Peak memory | 625696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4212213576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_h mac_enc.4212213576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.1714588180 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 3675906450 ps |
| CPU time | 293.75 seconds |
| Started | Sep 09 11:05:59 PM UTC 24 |
| Finished | Sep 09 11:10:58 PM UTC 24 |
| Peak memory | 623616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1714588180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_hmac_enc_idle.1714588180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2432012627 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 3222887789 ps |
| CPU time | 231.52 seconds |
| Started | Sep 09 11:29:56 PM UTC 24 |
| Finished | Sep 09 11:33:51 PM UTC 24 |
| Peak memory | 623676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432012627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.2432012627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_multistream.1604261595 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 7194163692 ps |
| CPU time | 1420.49 seconds |
| Started | Sep 09 11:06:05 PM UTC 24 |
| Finished | Sep 09 11:30:04 PM UTC 24 |
| Peak memory | 625804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1604261595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_multistream.1604261595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_multistream/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_oneshot.1688320264 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 2256572560 ps |
| CPU time | 278.52 seconds |
| Started | Sep 09 11:05:54 PM UTC 24 |
| Finished | Sep 09 11:10:37 PM UTC 24 |
| Peak memory | 623536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1688320264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_h mac_oneshot.1688320264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_smoketest.4043748905 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 3955375890 ps |
| CPU time | 426.85 seconds |
| Started | Sep 10 12:32:36 AM UTC 24 |
| Finished | Sep 10 12:39:49 AM UTC 24 |
| Peak memory | 625656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=4043748905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ hmac_smoketest.4043748905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.2601554263 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3509469288 ps |
| CPU time | 524.21 seconds |
| Started | Sep 09 10:43:48 PM UTC 24 |
| Finished | Sep 09 10:52:40 PM UTC 24 |
| Peak memory | 625836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2601554263 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.2601554263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.929650134 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 4721677256 ps |
| CPU time | 703.41 seconds |
| Started | Sep 09 10:43:29 PM UTC 24 |
| Finished | Sep 09 10:55:22 PM UTC 24 |
| Peak memory | 623820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=929650134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_i2c_host_tx_rx.929650134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation.956965357 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 11482251794 ps |
| CPU time | 2066.54 seconds |
| Started | Sep 09 11:05:58 PM UTC 24 |
| Finished | Sep 09 11:40:51 PM UTC 24 |
| Peak memory | 632068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956965357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_ derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.956965357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2429683235 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 9582419176 ps |
| CPU time | 1413.35 seconds |
| Started | Sep 09 11:05:56 PM UTC 24 |
| Finished | Sep 09 11:29:48 PM UTC 24 |
| Peak memory | 629768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429683235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.2429683235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2411896472 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 12037318669 ps |
| CPU time | 1993.26 seconds |
| Started | Sep 09 11:30:20 PM UTC 24 |
| Finished | Sep 10 12:03:59 AM UTC 24 |
| Peak memory | 634104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411896472 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2411896472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1561530077 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 11390350764 ps |
| CPU time | 1968.63 seconds |
| Started | Sep 09 11:05:59 PM UTC 24 |
| Finished | Sep 09 11:39:13 PM UTC 24 |
| Peak memory | 631968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_devic e=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561530077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.1561530077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.746173287 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 13093021804 ps |
| CPU time | 2386.57 seconds |
| Started | Sep 09 11:07:28 PM UTC 24 |
| Finished | Sep 09 11:47:46 PM UTC 24 |
| Peak memory | 625788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746173287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sidel oad_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.746173287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_app_rom.399283761 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 3207252132 ps |
| CPU time | 348.62 seconds |
| Started | Sep 09 11:08:55 PM UTC 24 |
| Finished | Sep 09 11:14:49 PM UTC 24 |
| Peak memory | 623464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=399283761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_kmac_app_rom.399283761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_entropy.72843555 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 2449233928 ps |
| CPU time | 211.35 seconds |
| Started | Sep 09 10:43:41 PM UTC 24 |
| Finished | Sep 09 10:47:15 PM UTC 24 |
| Peak memory | 623540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=72843555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _kmac_entropy.72843555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_idle.2532074210 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 2516674732 ps |
| CPU time | 233.11 seconds |
| Started | Sep 09 11:09:18 PM UTC 24 |
| Finished | Sep 09 11:13:15 PM UTC 24 |
| Peak memory | 623688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2532074210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ kmac_idle.2532074210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_cshake.2666845221 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 3167589200 ps |
| CPU time | 208.96 seconds |
| Started | Sep 09 11:08:23 PM UTC 24 |
| Finished | Sep 09 11:11:56 PM UTC 24 |
| Peak memory | 623712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2666845221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_sw_kmac_mode_cshake.2666845221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac.2182214977 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 2401918974 ps |
| CPU time | 290.04 seconds |
| Started | Sep 09 11:08:34 PM UTC 24 |
| Finished | Sep 09 11:13:29 PM UTC 24 |
| Peak memory | 625796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182214977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_kmac_mode_kmac.2182214977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1604200923 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 3364894111 ps |
| CPU time | 389.71 seconds |
| Started | Sep 09 11:08:38 PM UTC 24 |
| Finished | Sep 09 11:15:14 PM UTC 24 |
| Peak memory | 625584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_km ac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1604200923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.1604200923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2287187359 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 3851825231 ps |
| CPU time | 265.73 seconds |
| Started | Sep 09 11:31:09 PM UTC 24 |
| Finished | Sep 09 11:35:40 PM UTC 24 |
| Peak memory | 623696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287187359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2287187359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_smoketest.2330886354 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 3032812368 ps |
| CPU time | 301.21 seconds |
| Started | Sep 10 12:33:09 AM UTC 24 |
| Finished | Sep 10 12:38:15 AM UTC 24 |
| Peak memory | 623616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2330886354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ kmac_smoketest.2330886354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.160418533 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 2826076344 ps |
| CPU time | 325.64 seconds |
| Started | Sep 09 10:43:49 PM UTC 24 |
| Finished | Sep 09 10:49:20 PM UTC 24 |
| Peak memory | 623612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=160418533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_lc_ctrl_otp_hw_cfg0.160418533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2846273073 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 3800530144 ps |
| CPU time | 314.85 seconds |
| Started | Sep 09 10:47:09 PM UTC 24 |
| Finished | Sep 09 10:52:28 PM UTC 24 |
| Peak memory | 635892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846273073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.2846273073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1661041090 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3588425856 ps |
| CPU time | 142.58 seconds |
| Started | Sep 09 10:47:08 PM UTC 24 |
| Finished | Sep 09 10:49:33 PM UTC 24 |
| Peak memory | 635220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661041090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.1661041090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2418334480 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 2894508694 ps |
| CPU time | 154.33 seconds |
| Started | Sep 09 10:47:07 PM UTC 24 |
| Finished | Sep 09 10:49:44 PM UTC 24 |
| Peak memory | 637420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTes tLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418334480 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chi p_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.2418334480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.1101921976 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 7121959424 ps |
| CPU time | 519.93 seconds |
| Started | Sep 09 10:45:55 PM UTC 24 |
| Finished | Sep 09 10:54:42 PM UTC 24 |
| Peak memory | 635908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1101921976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_lc_ctrl_transition.1101921976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3599218274 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 2861915152 ps |
| CPU time | 135.79 seconds |
| Started | Sep 09 10:48:46 PM UTC 24 |
| Finished | Sep 09 10:51:05 PM UTC 24 |
| Peak memory | 633328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599218274 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.3599218274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2085591501 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2645532775 ps |
| CPU time | 115.31 seconds |
| Started | Sep 09 10:48:58 PM UTC 24 |
| Finished | Sep 09 10:50:56 PM UTC 24 |
| Peak memory | 633340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSo urceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20855915 01 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc _ctrl_volatile_raw_unlock_ext_clk_48mhz.2085591501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_rma.2563182869 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 47406273366 ps |
| CPU time | 5701.56 seconds |
| Started | Sep 09 10:49:05 PM UTC 24 |
| Finished | Sep 10 12:25:15 AM UTC 24 |
| Peak memory | 643436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +fl ash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563182869 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_rma.2563182869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1869381351 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 24979595192 ps |
| CPU time | 2090.26 seconds |
| Started | Sep 09 10:49:06 PM UTC 24 |
| Finished | Sep 09 11:24:22 PM UTC 24 |
| Peak memory | 640172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnl ock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869381351 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testunlocks.1869381351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3947214919 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 19371938490 ps |
| CPU time | 4094.38 seconds |
| Started | Sep 09 10:55:36 PM UTC 24 |
| Finished | Sep 10 12:04:41 AM UTC 24 |
| Peak memory | 628928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947214919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3947214919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1077406498 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 25332394405 ps |
| CPU time | 4562.43 seconds |
| Started | Sep 09 11:28:47 PM UTC 24 |
| Finished | Sep 10 12:45:46 AM UTC 24 |
| Peak memory | 628780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077406498 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1077406498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_randomness.4068956323 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 5244043580 ps |
| CPU time | 859.25 seconds |
| Started | Sep 09 10:55:25 PM UTC 24 |
| Finished | Sep 09 11:09:56 PM UTC 24 |
| Peak memory | 625860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068956323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.4068956323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_randomness/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_smoketest.3633566346 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 9954969830 ps |
| CPU time | 2310.49 seconds |
| Started | Sep 10 12:35:39 AM UTC 24 |
| Finished | Sep 10 01:14:39 AM UTC 24 |
| Peak memory | 625988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3633566346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ otbn_smoketest.3633566346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1788997611 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 26808961910 ps |
| CPU time | 5942.91 seconds |
| Started | Sep 09 10:45:10 PM UTC 24 |
| Finished | Sep 10 12:25:25 AM UTC 24 |
| Peak memory | 626528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_i mages=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788997611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.1788997611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1557562514 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 2858247288 ps |
| CPU time | 295.28 seconds |
| Started | Sep 09 10:45:29 PM UTC 24 |
| Finished | Sep 09 10:50:29 PM UTC 24 |
| Peak memory | 623536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_ error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1557562514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.1557562514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1644048736 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 7969744786 ps |
| CPU time | 1061.53 seconds |
| Started | Sep 09 10:43:52 PM UTC 24 |
| Finished | Sep 09 11:01:48 PM UTC 24 |
| Peak memory | 625588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644048736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.1644048736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1436635817 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 6851050704 ps |
| CPU time | 1173.27 seconds |
| Started | Sep 09 10:43:55 PM UTC 24 |
| Finished | Sep 09 11:03:43 PM UTC 24 |
| Peak memory | 625592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_buil d_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436635817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.1436635817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2060789510 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 7727283148 ps |
| CPU time | 1027.82 seconds |
| Started | Sep 09 10:44:32 PM UTC 24 |
| Finished | Sep 09 11:01:53 PM UTC 24 |
| Peak memory | 625952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060789510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.2060789510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.631936214 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 5317785164 ps |
| CPU time | 581.67 seconds |
| Started | Sep 09 10:43:53 PM UTC 24 |
| Finished | Sep 09 10:53:42 PM UTC 24 |
| Peak memory | 623864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631936214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.631936214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_smoketest.3082590922 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 3406864768 ps |
| CPU time | 321.54 seconds |
| Started | Sep 10 12:35:35 AM UTC 24 |
| Finished | Sep 10 12:41:01 AM UTC 24 |
| Peak memory | 623604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3082590922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_otp_ctrl_smoketest.3082590922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.2951998220 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 2261661610 ps |
| CPU time | 194.7 seconds |
| Started | Sep 09 10:41:32 PM UTC 24 |
| Finished | Sep 09 10:44:50 PM UTC 24 |
| Peak memory | 623720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_im ages=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951998220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.2951998220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pattgen_ios/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.89217200 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 4392778706 ps |
| CPU time | 530.9 seconds |
| Started | Sep 09 11:31:11 PM UTC 24 |
| Finished | Sep 09 11:40:09 PM UTC 24 |
| Peak memory | 625812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89217200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 0.chip_sw_power_idle_load.89217200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_sleep_load.1336661186 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 4216464846 ps |
| CPU time | 325.06 seconds |
| Started | Sep 09 11:34:20 PM UTC 24 |
| Finished | Sep 09 11:39:50 PM UTC 24 |
| Peak memory | 625588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1336661186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.1336661186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1135476312 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 11496041378 ps |
| CPU time | 1339.27 seconds |
| Started | Sep 09 10:54:45 PM UTC 24 |
| Finished | Sep 09 11:17:22 PM UTC 24 |
| Peak memory | 626016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135476312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep _all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.1135476312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4130643959 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 27260117800 ps |
| CPU time | 1527.67 seconds |
| Started | Sep 09 11:23:27 PM UTC 24 |
| Finished | Sep 09 11:49:14 PM UTC 24 |
| Peak memory | 625900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130643959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr _deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4130643959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1645040214 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 7201630208 ps |
| CPU time | 457.09 seconds |
| Started | Sep 09 10:52:43 PM UTC 24 |
| Finished | Sep 09 11:00:27 PM UTC 24 |
| Peak memory | 623604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_res et_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1645040214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.1645040214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.483954049 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 4412398658 ps |
| CPU time | 319.73 seconds |
| Started | Sep 09 10:52:43 PM UTC 24 |
| Finished | Sep 09 10:58:07 PM UTC 24 |
| Peak memory | 632012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483954049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main _power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.483954049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3174678527 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 13225071313 ps |
| CPU time | 1359.16 seconds |
| Started | Sep 09 10:53:51 PM UTC 24 |
| Finished | Sep 09 11:16:47 PM UTC 24 |
| Peak memory | 625856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_r eset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3174678527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3174678527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.518859312 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 5353576972 ps |
| CPU time | 605.99 seconds |
| Started | Sep 09 10:54:02 PM UTC 24 |
| Finished | Sep 09 11:04:17 PM UTC 24 |
| Peak memory | 625884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_r eset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=518859312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.518859312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4127308517 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 25020240849 ps |
| CPU time | 2153.73 seconds |
| Started | Sep 09 10:52:51 PM UTC 24 |
| Finished | Sep 09 11:29:12 PM UTC 24 |
| Peak memory | 625872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127308517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4127308517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3703308820 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 25933979240 ps |
| CPU time | 2009.64 seconds |
| Started | Sep 09 11:24:54 PM UTC 24 |
| Finished | Sep 09 11:58:50 PM UTC 24 |
| Peak memory | 625728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703308820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3703308820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2214133217 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 3265941800 ps |
| CPU time | 340.1 seconds |
| Started | Sep 09 10:55:03 PM UTC 24 |
| Finished | Sep 09 11:00:48 PM UTC 24 |
| Peak memory | 623624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2214133217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.chip_sw_pwrmgr_sleep_disabled.2214133217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.4153440088 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 5855922656 ps |
| CPU time | 491.8 seconds |
| Started | Sep 09 11:25:06 PM UTC 24 |
| Finished | Sep 09 11:33:25 PM UTC 24 |
| Peak memory | 625896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153440088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.4153440088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_smoketest.845204765 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 5164753400 ps |
| CPU time | 447.97 seconds |
| Started | Sep 10 12:35:38 AM UTC 24 |
| Finished | Sep 10 12:43:12 AM UTC 24 |
| Peak memory | 623828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_ima ges=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=845204765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.845204765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2683478510 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 7457120842 ps |
| CPU time | 1052.83 seconds |
| Started | Sep 09 10:52:42 PM UTC 24 |
| Finished | Sep 09 11:10:30 PM UTC 24 |
| Peak memory | 625656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2683478510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.2683478510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.515126291 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 5339243338 ps |
| CPU time | 586.92 seconds |
| Started | Sep 09 10:54:20 PM UTC 24 |
| Finished | Sep 09 11:04:15 PM UTC 24 |
| Peak memory | 623600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_w hen_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=515126291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.515126291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.265141475 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 6701001000 ps |
| CPU time | 512.24 seconds |
| Started | Sep 10 12:35:34 AM UTC 24 |
| Finished | Sep 10 12:44:14 AM UTC 24 |
| Peak memory | 625752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=265141475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_pwrmgr_usbdev_smoketest.265141475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_wdog_reset.4053477299 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 4229890290 ps |
| CPU time | 421.9 seconds |
| Started | Sep 09 10:54:47 PM UTC 24 |
| Finished | Sep 09 11:01:55 PM UTC 24 |
| Peak memory | 625524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053477299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.4053477299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rom_ctrl_integrity_check.897075938 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 8888857710 ps |
| CPU time | 661.56 seconds |
| Started | Sep 09 11:09:58 PM UTC 24 |
| Finished | Sep 09 11:21:09 PM UTC 24 |
| Peak memory | 640052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=897075938 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.897075938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3902812946 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 5488865374 ps |
| CPU time | 601.08 seconds |
| Started | Sep 09 10:42:19 PM UTC 24 |
| Finished | Sep 09 10:52:28 PM UTC 24 |
| Peak memory | 670204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902812946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr _cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.3902812946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_smoketest.1594477745 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 2463040500 ps |
| CPU time | 261.82 seconds |
| Started | Sep 10 12:37:24 AM UTC 24 |
| Finished | Sep 10 12:41:51 AM UTC 24 |
| Peak memory | 625512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1594477745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_rstmgr_smoketest.1594477745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_req.2144609438 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 4427001204 ps |
| CPU time | 462.57 seconds |
| Started | Sep 09 10:54:19 PM UTC 24 |
| Finished | Sep 09 11:02:08 PM UTC 24 |
| Peak memory | 623788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2144609438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_rstmgr_sw_req.2144609438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2588726994 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 3069547671 ps |
| CPU time | 279.65 seconds |
| Started | Sep 09 11:27:16 PM UTC 24 |
| Finished | Sep 09 11:32:01 PM UTC 24 |
| Peak memory | 625572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_inval idate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2588726994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.2588726994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_rnd.2711228006 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 5553288820 ps |
| CPU time | 982.22 seconds |
| Started | Sep 09 10:55:37 PM UTC 24 |
| Finished | Sep 09 11:12:13 PM UTC 24 |
| Peak memory | 625580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_b uild_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711228006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.2711228006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.3071546281 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 5339002736 ps |
| CPU time | 397.17 seconds |
| Started | Sep 09 11:25:06 PM UTC 24 |
| Finished | Sep 09 11:31:49 PM UTC 24 |
| Peak memory | 636080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_acc ess_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071546281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wak eup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.3071546281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.684295099 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 5245204072 ps |
| CPU time | 539.23 seconds |
| Started | Sep 09 11:25:02 PM UTC 24 |
| Finished | Sep 09 11:34:09 PM UTC 24 |
| Peak memory | 638092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm _reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684295099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_res et_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.684295099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_plic_smoketest.2266056951 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2482850904 ps |
| CPU time | 249.15 seconds |
| Started | Sep 10 12:35:40 AM UTC 24 |
| Finished | Sep 10 12:39:53 AM UTC 24 |
| Peak memory | 623720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=2266056951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_rv_plic_smoketest.2266056951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_irq.363221612 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 3142378322 ps |
| CPU time | 205.25 seconds |
| Started | Sep 09 10:52:52 PM UTC 24 |
| Finished | Sep 09 10:56:21 PM UTC 24 |
| Peak memory | 623756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=363221612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_rv_timer_irq.363221612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_smoketest.3876369031 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 2536371836 ps |
| CPU time | 255.03 seconds |
| Started | Sep 10 12:35:39 AM UTC 24 |
| Finished | Sep 10 12:39:58 AM UTC 24 |
| Peak memory | 625652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3876369031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_rv_timer_smoketest.3876369031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.2936585673 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 2352948075 ps |
| CPU time | 259.33 seconds |
| Started | Sep 09 11:12:20 PM UTC 24 |
| Finished | Sep 09 11:16:43 PM UTC 24 |
| Peak memory | 623800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936585673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_s tatus_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.2936585673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pwm_pulses.3639330600 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8984133980 ps |
| CPU time | 1134.87 seconds |
| Started | Sep 09 10:43:30 PM UTC 24 |
| Finished | Sep 09 11:02:39 PM UTC 24 |
| Peak memory | 625760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3639330600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_sleep_pwm_pulses.3639330600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3283527737 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 8641819608 ps |
| CPU time | 856.13 seconds |
| Started | Sep 09 11:11:57 PM UTC 24 |
| Finished | Sep 09 11:26:25 PM UTC 24 |
| Peak memory | 625712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283527737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_sram_ret_contents _no_scramble.3283527737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.924492441 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 6817336468 ps |
| CPU time | 568.95 seconds |
| Started | Sep 09 11:12:22 PM UTC 24 |
| Finished | Sep 09 11:21:58 PM UTC 24 |
| Peak memory | 625852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924492441 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_sram_ret_contents_scramble.924492441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through.3121563180 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6802173500 ps |
| CPU time | 608.29 seconds |
| Started | Sep 09 10:43:39 PM UTC 24 |
| Finished | Sep 09 10:53:56 PM UTC 24 |
| Peak memory | 640192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121563180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_spi_device_pass_through.3121563180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.914312629 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4327994754 ps |
| CPU time | 460.5 seconds |
| Started | Sep 09 10:43:29 PM UTC 24 |
| Finished | Sep 09 10:51:17 PM UTC 24 |
| Peak memory | 640400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914312629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_spi_device_pass_through_collision.914312629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.488391186 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3609259045 ps |
| CPU time | 368.53 seconds |
| Started | Sep 09 10:41:46 PM UTC 24 |
| Finished | Sep 09 10:48:00 PM UTC 24 |
| Peak memory | 636160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=488391186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.488391186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.2935641620 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 9167493737 ps |
| CPU time | 1045.09 seconds |
| Started | Sep 09 11:12:09 PM UTC 24 |
| Finished | Sep 09 11:29:47 PM UTC 24 |
| Peak memory | 625872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2935641620 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.2935641620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.428972094 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 5467326561 ps |
| CPU time | 666.28 seconds |
| Started | Sep 09 11:12:22 PM UTC 24 |
| Finished | Sep 09 11:23:38 PM UTC 24 |
| Peak memory | 625848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_ch eck=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428972094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctr l_scrambled_access_jitter_en.428972094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3012151301 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 6378826250 ps |
| CPU time | 536.24 seconds |
| Started | Sep 09 11:32:06 PM UTC 24 |
| Finished | Sep 09 11:41:10 PM UTC 24 |
| Peak memory | 625680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_r eady_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012151301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3012151301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_smoketest.3916260888 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 2830249724 ps |
| CPU time | 282.65 seconds |
| Started | Sep 10 12:37:25 AM UTC 24 |
| Finished | Sep 10 12:42:12 AM UTC 24 |
| Peak memory | 625584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916260888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_sram_ctrl_smoketest.3916260888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.663191475 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 20479656333 ps |
| CPU time | 3026.04 seconds |
| Started | Sep 09 10:54:51 PM UTC 24 |
| Finished | Sep 09 11:45:55 PM UTC 24 |
| Peak memory | 628896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=663191475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.663191475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_inputs.836694198 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3021858069 ps |
| CPU time | 318.6 seconds |
| Started | Sep 09 10:54:11 PM UTC 24 |
| Finished | Sep 09 10:59:35 PM UTC 24 |
| Peak memory | 627816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=836694198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_sysrst_ctrl_inputs.836694198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.502826799 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4159750156 ps |
| CPU time | 325.21 seconds |
| Started | Sep 09 10:54:50 PM UTC 24 |
| Finished | Sep 09 11:00:21 PM UTC 24 |
| Peak memory | 625772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=502826799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_sysrst_ctrl_outputs.502826799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3209132582 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5358544616 ps |
| CPU time | 332.3 seconds |
| Started | Sep 09 10:55:04 PM UTC 24 |
| Finished | Sep 09 11:00:42 PM UTC 24 |
| Peak memory | 625952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3209132582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3209132582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_smoketest.3013091588 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 3195839800 ps |
| CPU time | 300.31 seconds |
| Started | Sep 10 12:39:07 AM UTC 24 |
| Finished | Sep 10 12:44:13 AM UTC 24 |
| Peak memory | 629844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3013091588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch ip_sw_uart_smoketest.3013091588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1568913955 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 13357987367 ps |
| CPU time | 1611.99 seconds |
| Started | Sep 09 10:40:07 PM UTC 24 |
| Finished | Sep 09 11:07:19 PM UTC 24 |
| Peak memory | 636984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568913955 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1568913955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3739188206 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 81367882370 ps |
| CPU time | 17883 seconds |
| Started | Sep 09 10:43:24 PM UTC 24 |
| Finished | Sep 10 03:45:05 AM UTC 24 |
| Peak memory | 655476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout _ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739188206 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.3739188206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.3457491275 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 4065912024 ps |
| CPU time | 520.42 seconds |
| Started | Sep 09 10:43:47 PM UTC 24 |
| Finished | Sep 09 10:52:35 PM UTC 24 |
| Peak memory | 639868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457491275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.3457491275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.3904529379 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4765319810 ps |
| CPU time | 569.29 seconds |
| Started | Sep 09 10:43:10 PM UTC 24 |
| Finished | Sep 09 10:52:47 PM UTC 24 |
| Peak memory | 640072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904529379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.3904529379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usb_ast_clk_calib.2432968117 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2856743274 ps |
| CPU time | 339.24 seconds |
| Started | Sep 09 11:27:17 PM UTC 24 |
| Finished | Sep 09 11:33:01 PM UTC 24 |
| Peak memory | 625736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw _images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432968117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.2432968117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_dpi.647434992 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 11982280328 ps |
| CPU time | 2595.46 seconds |
| Started | Sep 09 10:41:27 PM UTC 24 |
| Finished | Sep 09 11:25:15 PM UTC 24 |
| Peak memory | 626528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_ 000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647434992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.647434992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pincfg.4137639657 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 31879382814 ps |
| CPU time | 8669.35 seconds |
| Started | Sep 09 10:43:10 PM UTC 24 |
| Finished | Sep 10 01:09:26 AM UTC 24 |
| Peak memory | 626744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000 _000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137639657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlg rey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.4137639657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.4182953009 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3029332970 ps |
| CPU time | 217.86 seconds |
| Started | Sep 09 10:41:59 PM UTC 24 |
| Finished | Sep 09 10:45:41 PM UTC 24 |
| Peak memory | 625520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182953009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.4182953009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.4232971452 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3309586040 ps |
| CPU time | 465.97 seconds |
| Started | Sep 09 10:42:49 PM UTC 24 |
| Finished | Sep 09 10:50:42 PM UTC 24 |
| Peak memory | 623724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232971452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.4232971452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_stream.3554549052 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 18943957992 ps |
| CPU time | 4692.86 seconds |
| Started | Sep 09 10:42:59 PM UTC 24 |
| Finished | Sep 10 12:02:10 AM UTC 24 |
| Peak memory | 628588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_ 000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554549052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_ear lgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.3554549052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_stream/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_vbus.2545438082 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 2545844370 ps |
| CPU time | 322.37 seconds |
| Started | Sep 09 10:43:41 PM UTC 24 |
| Finished | Sep 09 10:49:09 PM UTC 24 |
| Peak memory | 623464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545438082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.2545438082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_prod.1915358009 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 12489195688 ps |
| CPU time | 1098.09 seconds |
| Started | Sep 09 11:25:52 PM UTC 24 |
| Finished | Sep 09 11:44:24 PM UTC 24 |
| Peak memory | 642428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915358009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.1915358009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.4272521011 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 2577191287 ps |
| CPU time | 134.94 seconds |
| Started | Sep 09 11:24:59 PM UTC 24 |
| Finished | Sep 09 11:27:16 PM UTC 24 |
| Peak memory | 637876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272521011 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.4272521011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_dev.3003413878 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 15108596811 ps |
| CPU time | 4541.57 seconds |
| Started | Sep 09 11:48:35 PM UTC 24 |
| Finished | Sep 10 01:05:13 AM UTC 24 |
| Peak memory | 625968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003413878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.3003413878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod.723132028 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 15304150705 ps |
| CPU time | 4388.46 seconds |
| Started | Sep 09 11:48:40 PM UTC 24 |
| Finished | Sep 10 01:02:45 AM UTC 24 |
| Peak memory | 624000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723132028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.723132028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod_end.3125062173 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 16279800030 ps |
| CPU time | 4101 seconds |
| Started | Sep 09 11:50:04 PM UTC 24 |
| Finished | Sep 10 12:59:14 AM UTC 24 |
| Peak memory | 624104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312506 2173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_in it_prod_end.3125062173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_rma.1238754515 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 15525309273 ps |
| CPU time | 4057.46 seconds |
| Started | Sep 09 11:52:23 PM UTC 24 |
| Finished | Sep 10 01:00:50 AM UTC 24 |
| Peak memory | 625892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238754515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.1238754515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_test_unlocked0.461708686 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 11068581441 ps |
| CPU time | 3014.17 seconds |
| Started | Sep 09 11:48:06 PM UTC 24 |
| Finished | Sep 10 12:38:57 AM UTC 24 |
| Peak memory | 623848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=461708686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2 e_asm_init_test_unlocked0.461708686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.211573527 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 24591613244 ps |
| CPU time | 7273.79 seconds |
| Started | Sep 09 11:40:23 PM UTC 24 |
| Finished | Sep 10 01:43:09 AM UTC 24 |
| Peak memory | 626968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211573527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.211573527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.941595344 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 24718166242 ps |
| CPU time | 7459.05 seconds |
| Started | Sep 09 11:39:40 PM UTC 24 |
| Finished | Sep 10 01:45:32 AM UTC 24 |
| Peak memory | 626880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941595344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.941595344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1030111346 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 24267392496 ps |
| CPU time | 6803.27 seconds |
| Started | Sep 09 11:40:13 PM UTC 24 |
| Finished | Sep 10 01:34:59 AM UTC 24 |
| Peak memory | 626724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030111346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1030111346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1435489208 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 18252237352 ps |
| CPU time | 5633.63 seconds |
| Started | Sep 09 11:40:21 PM UTC 24 |
| Finished | Sep 10 01:15:24 AM UTC 24 |
| Peak memory | 626924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435489208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1435489208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.4172530925 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 15305178696 ps |
| CPU time | 4650.72 seconds |
| Started | Sep 09 11:40:40 PM UTC 24 |
| Finished | Sep 10 12:59:10 AM UTC 24 |
| Peak memory | 623728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172530925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.4172530925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.4251209721 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 15390409416 ps |
| CPU time | 4481.11 seconds |
| Started | Sep 09 11:38:59 PM UTC 24 |
| Finished | Sep 10 12:54:35 AM UTC 24 |
| Peak memory | 626960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251209721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.4251209721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3532559014 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 15683793372 ps |
| CPU time | 4721.51 seconds |
| Started | Sep 09 11:40:08 PM UTC 24 |
| Finished | Sep 10 12:59:50 AM UTC 24 |
| Peak memory | 626808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532559014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3532559014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.225060834 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 14882128534 ps |
| CPU time | 3721.03 seconds |
| Started | Sep 09 11:41:01 PM UTC 24 |
| Finished | Sep 10 12:43:47 AM UTC 24 |
| Peak memory | 623724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225060834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_b ase_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.225060834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1562478206 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 11216824076 ps |
| CPU time | 3197.11 seconds |
| Started | Sep 09 11:40:23 PM UTC 24 |
| Finished | Sep 10 12:34:22 AM UTC 24 |
| Peak memory | 623816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562478206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1562478206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1045357801 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 15271624304 ps |
| CPU time | 4325.61 seconds |
| Started | Sep 09 11:38:00 PM UTC 24 |
| Finished | Sep 10 12:50:58 AM UTC 24 |
| Peak memory | 626896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045357801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1045357801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.4129308425 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 15095439680 ps |
| CPU time | 4052.53 seconds |
| Started | Sep 09 11:35:55 PM UTC 24 |
| Finished | Sep 10 12:44:19 AM UTC 24 |
| Peak memory | 628776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129308425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.4129308425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.661550414 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 15675014596 ps |
| CPU time | 4203.38 seconds |
| Started | Sep 09 11:38:46 PM UTC 24 |
| Finished | Sep 10 12:49:41 AM UTC 24 |
| Peak memory | 628844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661550414 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.661550414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1350303989 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 15689539312 ps |
| CPU time | 4305.94 seconds |
| Started | Sep 09 11:37:19 PM UTC 24 |
| Finished | Sep 10 12:50:00 AM UTC 24 |
| Peak memory | 628992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350303989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1350303989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.261139965 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 11941412168 ps |
| CPU time | 2897.72 seconds |
| Started | Sep 09 11:36:24 PM UTC 24 |
| Finished | Sep 10 12:25:18 AM UTC 24 |
| Peak memory | 626004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261139965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.261139965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_rma.1796954401 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 10837873525 ps |
| CPU time | 2155.3 seconds |
| Started | Sep 09 11:58:16 PM UTC 24 |
| Finished | Sep 10 12:34:41 AM UTC 24 |
| Peak memory | 636196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_devic e=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796954401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jta g_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.1796954401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.4160071920 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 11669848609 ps |
| CPU time | 2324.91 seconds |
| Started | Sep 09 11:53:11 PM UTC 24 |
| Finished | Sep 10 12:32:28 AM UTC 24 |
| Peak memory | 640416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_devic e=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160071920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.4160071920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_dev.1051670404 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 34985505311 ps |
| CPU time | 4134.17 seconds |
| Started | Sep 10 12:02:41 AM UTC 24 |
| Finished | Sep 10 01:12:28 AM UTC 24 |
| Peak memory | 635652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_imag e=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051670404 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.1051670404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_rma.770087660 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 32408753973 ps |
| CPU time | 2983.76 seconds |
| Started | Sep 10 12:03:51 AM UTC 24 |
| Finished | Sep 10 12:54:12 AM UTC 24 |
| Peak memory | 635512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_imag e=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770087660 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.770087660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.3757069039 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 41109190043 ps |
| CPU time | 3719.24 seconds |
| Started | Sep 09 11:59:32 PM UTC 24 |
| Finished | Sep 10 01:02:17 AM UTC 24 |
| Peak memory | 635644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_imag e=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757069039 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_test_unlocked0.3757069039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.41502625 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 14630110386 ps |
| CPU time | 4079.91 seconds |
| Started | Sep 10 12:08:30 AM UTC 24 |
| Finished | Sep 10 01:17:20 AM UTC 24 |
| Peak memory | 624008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41502625 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_invalid_meas.41502625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.610444415 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 15163270070 ps |
| CPU time | 4436.09 seconds |
| Started | Sep 10 12:04:49 AM UTC 24 |
| Finished | Sep 10 01:19:40 AM UTC 24 |
| Peak memory | 625776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610444415 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.610444415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2683167566 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 15816474900 ps |
| CPU time | 4360.48 seconds |
| Started | Sep 10 12:05:30 AM UTC 24 |
| Finished | Sep 10 01:19:08 AM UTC 24 |
| Peak memory | 623720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683167566 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_no_meas.2683167566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_self_hash.1750917296 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 26924178072 ps |
| CPU time | 7886.5 seconds |
| Started | Sep 10 12:14:34 AM UTC 24 |
| Finished | Sep 10 02:27:39 AM UTC 24 |
| Peak memory | 628764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_rules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750917296 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.1750917296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_exception_c.1997402744 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 14315213562 ps |
| CPU time | 3857.18 seconds |
| Started | Sep 09 11:34:56 PM UTC 24 |
| Finished | Sep 10 12:40:00 AM UTC 24 |
| Peak memory | 628968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997402744 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_exception_c.1997402744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1387984574 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 23723062298 ps |
| CPU time | 6592.2 seconds |
| Started | Sep 09 11:42:40 PM UTC 24 |
| Finished | Sep 10 01:33:53 AM UTC 24 |
| Peak memory | 626980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_fla sh_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387984574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1387984574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3020254067 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 24000387060 ps |
| CPU time | 6641.1 seconds |
| Started | Sep 09 11:43:08 PM UTC 24 |
| Finished | Sep 10 01:35:11 AM UTC 24 |
| Peak memory | 629064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_fl ash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020254067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3020254067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3461010034 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 23366484486 ps |
| CPU time | 7305.83 seconds |
| Started | Sep 09 11:41:14 PM UTC 24 |
| Finished | Sep 10 01:44:31 AM UTC 24 |
| Peak memory | 626776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_fl ash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461010034 -assert nopostproc +UVM_TESTNAME=chip_base_test + UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3461010034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1918462587 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 22516119662 ps |
| CPU time | 6493.19 seconds |
| Started | Sep 09 11:43:10 PM UTC 24 |
| Finished | Sep 10 01:32:45 AM UTC 24 |
| Peak memory | 626788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_fl ash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918462587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1918462587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2878592840 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 17687837416 ps |
| CPU time | 5359.89 seconds |
| Started | Sep 09 11:42:28 PM UTC 24 |
| Finished | Sep 10 01:12:53 AM UTC 24 |
| Peak memory | 628740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_fl ash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878592840 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2878592840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.155163747 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 14982703365 ps |
| CPU time | 4152.64 seconds |
| Started | Sep 09 11:42:42 PM UTC 24 |
| Finished | Sep 10 12:52:46 AM UTC 24 |
| Peak memory | 623828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mas k_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=155163747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.155163747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1180334306 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 14992290390 ps |
| CPU time | 3911.37 seconds |
| Started | Sep 09 11:42:07 PM UTC 24 |
| Finished | Sep 10 12:48:11 AM UTC 24 |
| Peak memory | 623784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4 ,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1180334306 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1180334306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.146191445 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 13872126232 ps |
| CPU time | 4047.51 seconds |
| Started | Sep 09 11:43:00 PM UTC 24 |
| Finished | Sep 10 12:51:20 AM UTC 24 |
| Peak memory | 624000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=146191445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.146191445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1383818823 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 11654140162 ps |
| CPU time | 2854.54 seconds |
| Started | Sep 09 11:41:19 PM UTC 24 |
| Finished | Sep 10 12:29:28 AM UTC 24 |
| Peak memory | 624024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_ test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1383818823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1383818823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3437853688 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 14960109080 ps |
| CPU time | 4084.57 seconds |
| Started | Sep 09 11:43:25 PM UTC 24 |
| Finished | Sep 10 12:52:20 AM UTC 24 |
| Peak memory | 625836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3437853688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3437853688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2532636471 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 14624621455 ps |
| CPU time | 3920.7 seconds |
| Started | Sep 09 11:45:12 PM UTC 24 |
| Finished | Sep 10 12:51:22 AM UTC 24 |
| Peak memory | 623792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mas k_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2532636471 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2532636471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2070364975 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 13856407422 ps |
| CPU time | 4036.68 seconds |
| Started | Sep 09 11:46:41 PM UTC 24 |
| Finished | Sep 10 12:54:48 AM UTC 24 |
| Peak memory | 623784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4 ,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2070364975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2070364975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2173003534 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 15030140356 ps |
| CPU time | 3661.45 seconds |
| Started | Sep 09 11:47:53 PM UTC 24 |
| Finished | Sep 10 12:49:39 AM UTC 24 |
| Peak memory | 623964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2173003534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2173003534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1282518075 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 11174870330 ps |
| CPU time | 3268.9 seconds |
| Started | Sep 09 11:43:15 PM UTC 24 |
| Finished | Sep 10 12:38:24 AM UTC 24 |
| Peak memory | 623904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unloc ked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282518075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1282518075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_smoke.3665850665 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 14924142260 ps |
| CPU time | 3969.1 seconds |
| Started | Sep 09 11:36:29 PM UTC 24 |
| Finished | Sep 10 12:43:26 AM UTC 24 |
| Peak memory | 629024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665850665 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.3665850665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.3959728170 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 17505699438 ps |
| CPU time | 4420.78 seconds |
| Started | Sep 10 12:04:38 AM UTC 24 |
| Finished | Sep 10 01:19:12 AM UTC 24 |
| Peak memory | 626016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959728170 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.3959728170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_keymgr_functest.337793568 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 4698105098 ps |
| CPU time | 734.74 seconds |
| Started | Sep 10 12:21:38 AM UTC 24 |
| Finished | Sep 10 12:34:02 AM UTC 24 |
| Peak memory | 625584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337793568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.rom_keymgr_functest.337793568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_keymgr_functest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_raw_unlock.4152611233 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 5930042935 ps |
| CPU time | 416.62 seconds |
| Started | Sep 10 12:13:53 AM UTC 24 |
| Finished | Sep 10 12:20:56 AM UTC 24 |
| Peak memory | 637484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images =empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152611233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.4152611233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_volatile_raw_unlock.662574988 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 2661582032 ps |
| CPU time | 103.7 seconds |
| Started | Sep 10 12:11:57 AM UTC 24 |
| Finished | Sep 10 12:13:43 AM UTC 24 |
| Peak memory | 633256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRa w +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot _flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=662574988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.662574988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.3339515722 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 10121430435 ps |
| CPU time | 976.32 seconds |
| Started | Sep 10 01:39:51 AM UTC 24 |
| Finished | Sep 10 01:56:20 AM UTC 24 |
| Peak memory | 622792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333951 5722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_csr_rw.3339515722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.2846959509 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 13410706592 ps |
| CPU time | 1264.24 seconds |
| Started | Sep 10 01:39:56 AM UTC 24 |
| Finished | Sep 10 02:01:17 AM UTC 24 |
| Peak memory | 623016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846959509 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.2846959509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_jtag_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.524238691 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 4535968946 ps |
| CPU time | 397.09 seconds |
| Started | Sep 10 01:43:49 AM UTC 24 |
| Finished | Sep 10 01:50:32 AM UTC 24 |
| Peak memory | 635824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524238691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.524238691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sival_flash_info_access.3249642649 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 3372272640 ps |
| CPU time | 337.94 seconds |
| Started | Sep 10 12:41:09 AM UTC 24 |
| Finished | Sep 10 12:46:53 AM UTC 24 |
| Peak memory | 623468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim _dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249642649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.3249642649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sival_flash_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.612706440 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 19341968642 ps |
| CPU time | 670.31 seconds |
| Started | Sep 10 01:12:56 AM UTC 24 |
| Finished | Sep 10 01:24:16 AM UTC 24 |
| Peak memory | 636084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612706440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.612706440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.43859533 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 2928462470 ps |
| CPU time | 245.2 seconds |
| Started | Sep 10 01:13:30 AM UTC 24 |
| Finished | Sep 10 01:17:40 AM UTC 24 |
| Peak memory | 623596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_i mages=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=43859533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_aes_enc.43859533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.3479363210 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 2369957430 ps |
| CPU time | 273.44 seconds |
| Started | Sep 10 01:13:35 AM UTC 24 |
| Finished | Sep 10 01:18:13 AM UTC 24 |
| Peak memory | 623756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479363210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.3479363210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.250078366 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 3371310635 ps |
| CPU time | 240.1 seconds |
| Started | Sep 10 01:49:55 AM UTC 24 |
| Finished | Sep 10 01:53:59 AM UTC 24 |
| Peak memory | 625728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250078366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.250078366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.3074871411 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 3340417988 ps |
| CPU time | 322.42 seconds |
| Started | Sep 10 01:19:04 AM UTC 24 |
| Finished | Sep 10 01:24:31 AM UTC 24 |
| Peak memory | 623696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074871411 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_aes_entropy.3074871411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.1916336613 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 2688017036 ps |
| CPU time | 217.64 seconds |
| Started | Sep 10 01:15:07 AM UTC 24 |
| Finished | Sep 10 01:18:48 AM UTC 24 |
| Peak memory | 625768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916336613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.1916336613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.1686067296 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 3708720545 ps |
| CPU time | 353.96 seconds |
| Started | Sep 10 01:15:22 AM UTC 24 |
| Finished | Sep 10 01:21:22 AM UTC 24 |
| Peak memory | 623532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686067296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_aes_masking_off.1686067296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_masking_off/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.118826211 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 2940565400 ps |
| CPU time | 313.03 seconds |
| Started | Sep 10 01:55:13 AM UTC 24 |
| Finished | Sep 10 02:00:31 AM UTC 24 |
| Peak memory | 623716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=118826211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ae s_smoketest.118826211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.4160042644 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 3303471383 ps |
| CPU time | 400.41 seconds |
| Started | Sep 10 01:18:31 AM UTC 24 |
| Finished | Sep 10 01:25:18 AM UTC 24 |
| Peak memory | 625584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160042644 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.4160042644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.1581875976 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 5198607000 ps |
| CPU time | 549.2 seconds |
| Started | Sep 10 01:16:18 AM UTC 24 |
| Finished | Sep 10 01:25:35 AM UTC 24 |
| Peak memory | 636016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581875976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_ earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.1581875976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.4289235572 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 6414000012 ps |
| CPU time | 1282.91 seconds |
| Started | Sep 10 01:18:01 AM UTC 24 |
| Finished | Sep 10 01:39:41 AM UTC 24 |
| Peak memory | 625592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289235572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_ea rlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.4289235572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3511184427 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 6126264760 ps |
| CPU time | 1244.68 seconds |
| Started | Sep 10 01:18:30 AM UTC 24 |
| Finished | Sep 10 01:39:32 AM UTC 24 |
| Peak memory | 625580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511184427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_toggle.3511184427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3815877182 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 11065833538 ps |
| CPU time | 1106.44 seconds |
| Started | Sep 10 01:17:24 AM UTC 24 |
| Finished | Sep 10 01:36:05 AM UTC 24 |
| Peak memory | 625916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815877182 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_hand ler_lpg_sleep_mode_pings.3815877182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.796624658 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 7578987440 ps |
| CPU time | 1199.49 seconds |
| Started | Sep 10 01:17:22 AM UTC 24 |
| Finished | Sep 10 01:37:37 AM UTC 24 |
| Peak memory | 623716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796624658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_bas e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.796624658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_timeout.1056802305 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 4736102030 ps |
| CPU time | 517.08 seconds |
| Started | Sep 10 01:16:21 AM UTC 24 |
| Finished | Sep 10 01:25:05 AM UTC 24 |
| Peak memory | 625572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056802305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.1056802305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.2640072432 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 2956188884 ps |
| CPU time | 407.36 seconds |
| Started | Sep 10 01:16:17 AM UTC 24 |
| Finished | Sep 10 01:23:11 AM UTC 24 |
| Peak memory | 623712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand om_seed=2640072432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aler t_test.2640072432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.1200048084 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 4310319378 ps |
| CPU time | 445.84 seconds |
| Started | Sep 10 01:10:12 AM UTC 24 |
| Finished | Sep 10 01:17:45 AM UTC 24 |
| Peak memory | 625760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200048084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.1200048084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1005022944 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 6821516608 ps |
| CPU time | 481.7 seconds |
| Started | Sep 10 01:10:13 AM UTC 24 |
| Finished | Sep 10 01:18:21 AM UTC 24 |
| Peak memory | 625652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005022944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1005022944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.1973075711 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 2812746440 ps |
| CPU time | 261.76 seconds |
| Started | Sep 10 01:55:20 AM UTC 24 |
| Finished | Sep 10 01:59:46 AM UTC 24 |
| Peak memory | 623524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973075711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_aon_timer_smoketest.1973075711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1846760633 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 7145312068 ps |
| CPU time | 581.13 seconds |
| Started | Sep 10 01:11:35 AM UTC 24 |
| Finished | Sep 10 01:21:24 AM UTC 24 |
| Peak memory | 625776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846760633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.1846760633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1961758583 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 5867484760 ps |
| CPU time | 547.47 seconds |
| Started | Sep 10 01:12:08 AM UTC 24 |
| Finished | Sep 10 01:21:23 AM UTC 24 |
| Peak memory | 625720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961758583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.1961758583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.3102520681 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 7978870600 ps |
| CPU time | 810.9 seconds |
| Started | Sep 10 01:40:32 AM UTC 24 |
| Finished | Sep 10 01:54:14 AM UTC 24 |
| Peak memory | 631800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_ clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h w/dv/tools/sim.tcl +ntb_random_seed=3102520681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.3102520681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1118521730 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 13448419664 ps |
| CPU time | 946.77 seconds |
| Started | Sep 10 01:35:52 AM UTC 24 |
| Finished | Sep 10 01:51:52 AM UTC 24 |
| Peak memory | 637964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_de vice=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118521730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.1118521730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.32193808 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 3908320888 ps |
| CPU time | 551.54 seconds |
| Started | Sep 10 01:38:19 AM UTC 24 |
| Finished | Sep 10 01:47:38 AM UTC 24 |
| Peak memory | 625816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32193808 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_ for_sw_fast_dev.32193808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2746121630 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 4436080168 ps |
| CPU time | 613.4 seconds |
| Started | Sep 10 01:38:27 AM UTC 24 |
| Finished | Sep 10 01:48:49 AM UTC 24 |
| Peak memory | 625732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746121630 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_rma.2746121630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2242403359 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 3969309490 ps |
| CPU time | 507.74 seconds |
| Started | Sep 10 01:36:48 AM UTC 24 |
| Finished | Sep 10 01:45:23 AM UTC 24 |
| Peak memory | 625540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224 2403359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_exter nal_clk_src_for_sw_fast_test_unlocked0.2242403359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.986928097 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 5123399556 ps |
| CPU time | 562.7 seconds |
| Started | Sep 10 01:38:17 AM UTC 24 |
| Finished | Sep 10 01:47:47 AM UTC 24 |
| Peak memory | 625624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986928097 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src _for_sw_slow_dev.986928097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3637791877 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 5332447796 ps |
| CPU time | 659.62 seconds |
| Started | Sep 10 01:38:27 AM UTC 24 |
| Finished | Sep 10 01:49:36 AM UTC 24 |
| Peak memory | 625824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637791877 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_rma.3637791877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.132610242 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 4780862056 ps |
| CPU time | 654.22 seconds |
| Started | Sep 10 01:36:49 AM UTC 24 |
| Finished | Sep 10 01:47:52 AM UTC 24 |
| Peak memory | 625796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132 610242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_extern al_clk_src_for_sw_slow_test_unlocked0.132610242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.558814942 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 2679693468 ps |
| CPU time | 244.03 seconds |
| Started | Sep 10 01:39:51 AM UTC 24 |
| Finished | Sep 10 01:43:59 AM UTC 24 |
| Peak memory | 623192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=558814942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_clkmgr_jitter.558814942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.803711128 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 3166911624 ps |
| CPU time | 446.3 seconds |
| Started | Sep 10 01:39:06 AM UTC 24 |
| Finished | Sep 10 01:46:39 AM UTC 24 |
| Peak memory | 625764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=803711128 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_clkmgr_jitter_frequency.803711128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3560235339 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 2337808533 ps |
| CPU time | 209.42 seconds |
| Started | Sep 10 01:47:43 AM UTC 24 |
| Finished | Sep 10 01:51:16 AM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkm gr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3560235339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.3560235339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3417138950 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 4904894810 ps |
| CPU time | 564.92 seconds |
| Started | Sep 10 01:35:18 AM UTC 24 |
| Finished | Sep 10 01:44:51 AM UTC 24 |
| Peak memory | 623732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3417138950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.3417138950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1042133270 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 5366139000 ps |
| CPU time | 492.88 seconds |
| Started | Sep 10 01:35:14 AM UTC 24 |
| Finished | Sep 10 01:43:34 AM UTC 24 |
| Peak memory | 623536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1042133270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_clkmgr_off_hmac_trans.1042133270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3774836244 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 4263082756 ps |
| CPU time | 590.57 seconds |
| Started | Sep 10 01:35:19 AM UTC 24 |
| Finished | Sep 10 01:45:18 AM UTC 24 |
| Peak memory | 625604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3774836244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_clkmgr_off_kmac_trans.3774836244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3973443865 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 6165156628 ps |
| CPU time | 665.02 seconds |
| Started | Sep 10 01:35:48 AM UTC 24 |
| Finished | Sep 10 01:47:02 AM UTC 24 |
| Peak memory | 625588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3973443865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_clkmgr_off_otbn_trans.3973443865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.40570615 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 12436790320 ps |
| CPU time | 1419.29 seconds |
| Started | Sep 10 01:35:20 AM UTC 24 |
| Finished | Sep 10 01:59:18 AM UTC 24 |
| Peak memory | 625580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_i mages=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40570615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.40570615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_reset_frequency.1488111132 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 3550288632 ps |
| CPU time | 383.25 seconds |
| Started | Sep 10 01:38:26 AM UTC 24 |
| Finished | Sep 10 01:44:55 AM UTC 24 |
| Peak memory | 625768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488111132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.1488111132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1106437951 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 4717780180 ps |
| CPU time | 543.32 seconds |
| Started | Sep 10 01:39:51 AM UTC 24 |
| Finished | Sep 10 01:49:02 AM UTC 24 |
| Peak memory | 623604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106437951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.1106437951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.3471338672 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 2539243568 ps |
| CPU time | 258.49 seconds |
| Started | Sep 10 01:55:33 AM UTC 24 |
| Finished | Sep 10 01:59:56 AM UTC 24 |
| Peak memory | 623672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3471338672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_clkmgr_smoketest.3471338672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency.2246296697 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 18033001732 ps |
| CPU time | 5155.04 seconds |
| Started | Sep 10 01:20:47 AM UTC 24 |
| Finished | Sep 10 02:47:49 AM UTC 24 |
| Peak memory | 628784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurren cy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2246296697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_csrng_edn_concurrency.2246296697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2658919332 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 3839390856 ps |
| CPU time | 453.87 seconds |
| Started | Sep 10 01:21:31 AM UTC 24 |
| Finished | Sep 10 01:29:12 AM UTC 24 |
| Peak memory | 623468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658919332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src _fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.2658919332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_kat_test.2098930788 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 2416939390 ps |
| CPU time | 348.87 seconds |
| Started | Sep 10 01:20:47 AM UTC 24 |
| Finished | Sep 10 01:26:42 AM UTC 24 |
| Peak memory | 623660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098930788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_csrng_kat_test.2098930788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.2507311467 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 5287741460 ps |
| CPU time | 616.14 seconds |
| Started | Sep 10 01:20:46 AM UTC 24 |
| Finished | Sep 10 01:31:10 AM UTC 24 |
| Peak memory | 625708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_ otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507311467 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_lc_hw_debug_en_test.2507311467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.3065100317 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 3537100412 ps |
| CPU time | 241.42 seconds |
| Started | Sep 10 01:56:12 AM UTC 24 |
| Finished | Sep 10 02:00:18 AM UTC 24 |
| Peak memory | 623696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3065100317 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _csrng_smoketest.3065100317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.2021051469 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 5616961408 ps |
| CPU time | 625.13 seconds |
| Started | Sep 10 12:41:43 AM UTC 24 |
| Finished | Sep 10 12:52:17 AM UTC 24 |
| Peak memory | 625896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021051469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.2021051469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.3262552723 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 4898245720 ps |
| CPU time | 975.47 seconds |
| Started | Sep 10 01:20:27 AM UTC 24 |
| Finished | Sep 10 01:36:56 AM UTC 24 |
| Peak memory | 625916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerat e_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262552723 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_auto_mode.3262552723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.1873800914 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 2718414860 ps |
| CPU time | 514.12 seconds |
| Started | Sep 10 01:20:12 AM UTC 24 |
| Finished | Sep 10 01:28:54 AM UTC 24 |
| Peak memory | 625924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerat e_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873800914 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_boot_mode.1873800914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs.3848369164 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 6909114840 ps |
| CPU time | 991.97 seconds |
| Started | Sep 10 01:22:42 AM UTC 24 |
| Finished | Sep 10 01:39:27 AM UTC 24 |
| Peak memory | 626072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848369164 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.3848369164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.569133935 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 6409856086 ps |
| CPU time | 1233.79 seconds |
| Started | Sep 10 01:22:42 AM UTC 24 |
| Finished | Sep 10 01:43:32 AM UTC 24 |
| Peak memory | 626068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569133935 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.569133935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.1697507003 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 3127693522 ps |
| CPU time | 556.56 seconds |
| Started | Sep 10 01:20:41 AM UTC 24 |
| Finished | Sep 10 01:30:05 AM UTC 24 |
| Peak memory | 629828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_a ssert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_k at:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=1697507003 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_edn_kat.1697507003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_kat/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.1820530616 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 8767737652 ps |
| CPU time | 1837.83 seconds |
| Started | Sep 10 01:20:26 AM UTC 24 |
| Finished | Sep 10 01:51:27 AM UTC 24 |
| Peak memory | 623740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1820530616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_edn_sw_mode.1820530616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3941115935 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 2612003968 ps |
| CPU time | 223.44 seconds |
| Started | Sep 10 01:22:41 AM UTC 24 |
| Finished | Sep 10 01:26:28 AM UTC 24 |
| Peak memory | 625656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941115935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.3941115935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.3960853404 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 5189355792 ps |
| CPU time | 969.58 seconds |
| Started | Sep 10 01:22:43 AM UTC 24 |
| Finished | Sep 10 01:39:06 AM UTC 24 |
| Peak memory | 623976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_ srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960853404 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.3960853404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.1277830478 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 2969976712 ps |
| CPU time | 306.48 seconds |
| Started | Sep 10 01:19:04 AM UTC 24 |
| Finished | Sep 10 01:24:15 AM UTC 24 |
| Peak memory | 625768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277830478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.1277830478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_smoketest.680439414 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 4013090764 ps |
| CPU time | 485.64 seconds |
| Started | Sep 10 01:56:19 AM UTC 24 |
| Finished | Sep 10 02:04:32 AM UTC 24 |
| Peak memory | 625588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_de vice=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680439414 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.680439414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_concurrency.3440121583 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 2422262544 ps |
| CPU time | 190.28 seconds |
| Started | Sep 10 12:41:11 AM UTC 24 |
| Finished | Sep 10 12:44:25 AM UTC 24 |
| Peak memory | 623780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3440121583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_concurrency.3440121583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_flash.2754894016 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 2435804836 ps |
| CPU time | 250.07 seconds |
| Started | Sep 10 12:39:09 AM UTC 24 |
| Finished | Sep 10 12:43:23 AM UTC 24 |
| Peak memory | 625584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2754894016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_example_flash.2754894016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_manufacturer.570658715 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 3026395054 ps |
| CPU time | 224.67 seconds |
| Started | Sep 10 12:39:37 AM UTC 24 |
| Finished | Sep 10 12:43:26 AM UTC 24 |
| Peak memory | 623648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=570658715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exa mple_manufacturer.570658715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_manufacturer/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_rom.3208362610 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 2482073012 ps |
| CPU time | 138.48 seconds |
| Started | Sep 10 12:39:19 AM UTC 24 |
| Finished | Sep 10 12:41:40 AM UTC 24 |
| Peak memory | 623076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:t est_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3208362610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_example_rom.3208362610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.1891558037 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 4990868144 ps |
| CPU time | 645.69 seconds |
| Started | Sep 10 01:46:23 AM UTC 24 |
| Finished | Sep 10 01:57:17 AM UTC 24 |
| Peak memory | 626000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check= 1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891558037 -assert nopostproc +UVM_TESTNAME=chip_base_test + UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.1891558037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.56491178 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 5365308750 ps |
| CPU time | 987.39 seconds |
| Started | Sep 10 12:52:25 AM UTC 24 |
| Finished | Sep 10 01:09:05 AM UTC 24 |
| Peak memory | 623528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=56491178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_f lash_ctrl_access.56491178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1276401388 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 5742579988 ps |
| CPU time | 1102.96 seconds |
| Started | Sep 10 12:52:26 AM UTC 24 |
| Finished | Sep 10 01:11:04 AM UTC 24 |
| Peak memory | 623776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=1276401388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_flash_ctrl_access_jitter_en.1276401388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3833999745 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 7387645252 ps |
| CPU time | 1102.99 seconds |
| Started | Sep 10 01:47:48 AM UTC 24 |
| Finished | Sep 10 02:06:26 AM UTC 24 |
| Peak memory | 623536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833999745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3833999745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2661235928 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 5149703229 ps |
| CPU time | 947.74 seconds |
| Started | Sep 10 12:54:54 AM UTC 24 |
| Finished | Sep 10 01:10:55 AM UTC 24 |
| Peak memory | 625660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=2661235928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_flash_ctrl_clock_freqs.2661235928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1859542279 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 3156268900 ps |
| CPU time | 364.68 seconds |
| Started | Sep 10 12:53:05 AM UTC 24 |
| Finished | Sep 10 12:59:15 AM UTC 24 |
| Peak memory | 625796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1859542279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_flash_ctrl_idle_low_power.1859542279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2233501850 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 5751287592 ps |
| CPU time | 519.79 seconds |
| Started | Sep 10 12:52:20 AM UTC 24 |
| Finished | Sep 10 01:01:07 AM UTC 24 |
| Peak memory | 625816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233501850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ct rl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.2233501850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1000390244 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 4796477596 ps |
| CPU time | 907.34 seconds |
| Started | Sep 10 01:53:13 AM UTC 24 |
| Finished | Sep 10 02:08:33 AM UTC 24 |
| Peak memory | 625716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1000390244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_flash_ctrl_mem_protection.1000390244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.524141825 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 3672749072 ps |
| CPU time | 595.2 seconds |
| Started | Sep 10 12:52:25 AM UTC 24 |
| Finished | Sep 10 01:02:29 AM UTC 24 |
| Peak memory | 623688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524141825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.524141825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1052432540 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 4434594404 ps |
| CPU time | 632.18 seconds |
| Started | Sep 10 12:52:16 AM UTC 24 |
| Finished | Sep 10 01:02:56 AM UTC 24 |
| Peak memory | 623800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052432540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.1052432540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1336194613 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 5399851004 ps |
| CPU time | 575.22 seconds |
| Started | Sep 10 01:47:48 AM UTC 24 |
| Finished | Sep 10 01:57:31 AM UTC 24 |
| Peak memory | 625588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336194613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1336194613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.829053154 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 3357888250 ps |
| CPU time | 356.25 seconds |
| Started | Sep 10 01:46:58 AM UTC 24 |
| Finished | Sep 10 01:52:59 AM UTC 24 |
| Peak memory | 623480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_image s=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829053154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.829053154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.577724811 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 20671690312 ps |
| CPU time | 2066.44 seconds |
| Started | Sep 10 12:53:02 AM UTC 24 |
| Finished | Sep 10 01:27:57 AM UTC 24 |
| Peak memory | 627892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577724811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.577724811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_init/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init_reduced_freq.1507377546 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 24079374672 ps |
| CPU time | 2174.26 seconds |
| Started | Sep 10 01:49:55 AM UTC 24 |
| Finished | Sep 10 02:26:37 AM UTC 24 |
| Peak memory | 630892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_buil d_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507377546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.1507377546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.3218357234 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 2606102430 ps |
| CPU time | 178.2 seconds |
| Started | Sep 10 01:55:31 AM UTC 24 |
| Finished | Sep 10 01:58:32 AM UTC 24 |
| Peak memory | 623560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_ima ges=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoketest_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218357234 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chi p_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.3218357234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.4162210614 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 2865966525 ps |
| CPU time | 302.39 seconds |
| Started | Sep 10 01:56:42 AM UTC 24 |
| Finished | Sep 10 02:01:49 AM UTC 24 |
| Peak memory | 623712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=4162210614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_sw_gpio_smoketest.4162210614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.340470800 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 2616946780 ps |
| CPU time | 296.49 seconds |
| Started | Sep 10 01:23:05 AM UTC 24 |
| Finished | Sep 10 01:28:07 AM UTC 24 |
| Peak memory | 623732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=340470800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hm ac_enc.340470800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.1917621495 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 2873586432 ps |
| CPU time | 277.65 seconds |
| Started | Sep 10 01:25:29 AM UTC 24 |
| Finished | Sep 10 01:30:11 AM UTC 24 |
| Peak memory | 623592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1917621495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_hmac_enc_idle.1917621495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en.3518883487 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 3146154719 ps |
| CPU time | 198.61 seconds |
| Started | Sep 10 01:23:52 AM UTC 24 |
| Finished | Sep 10 01:27:14 AM UTC 24 |
| Peak memory | 623468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3518883487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_hmac_enc_jitter_en.3518883487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1797721400 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 3340993095 ps |
| CPU time | 279.27 seconds |
| Started | Sep 10 01:49:00 AM UTC 24 |
| Finished | Sep 10 01:53:44 AM UTC 24 |
| Peak memory | 623616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797721400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.1797721400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.3236767660 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 6565165768 ps |
| CPU time | 1347.02 seconds |
| Started | Sep 10 01:25:58 AM UTC 24 |
| Finished | Sep 10 01:48:43 AM UTC 24 |
| Peak memory | 623696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3236767660 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_multistream.3236767660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_multistream/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.11257772 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 2688823648 ps |
| CPU time | 312.73 seconds |
| Started | Sep 10 01:25:45 AM UTC 24 |
| Finished | Sep 10 01:31:03 AM UTC 24 |
| Peak memory | 625512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=11257772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hma c_oneshot.11257772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.3920246174 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 2970022134 ps |
| CPU time | 431.24 seconds |
| Started | Sep 10 01:57:01 AM UTC 24 |
| Finished | Sep 10 02:04:19 AM UTC 24 |
| Peak memory | 623616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3920246174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ hmac_smoketest.3920246174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.2543863479 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3647282060 ps |
| CPU time | 544.69 seconds |
| Started | Sep 10 12:48:54 AM UTC 24 |
| Finished | Sep 10 12:58:07 AM UTC 24 |
| Peak memory | 625656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2543863479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.2543863479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.1841301893 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 4862203448 ps |
| CPU time | 710.02 seconds |
| Started | Sep 10 12:47:56 AM UTC 24 |
| Finished | Sep 10 12:59:56 AM UTC 24 |
| Peak memory | 623596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1841301893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_i2c_host_tx_rx.1841301893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.4169138073 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 4074314950 ps |
| CPU time | 707.34 seconds |
| Started | Sep 10 12:47:58 AM UTC 24 |
| Finished | Sep 10 12:59:56 AM UTC 24 |
| Peak memory | 625900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=4169138073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.4169138073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.633309501 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 4236809876 ps |
| CPU time | 796.66 seconds |
| Started | Sep 10 12:48:01 AM UTC 24 |
| Finished | Sep 10 01:01:29 AM UTC 24 |
| Peak memory | 623832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=633309501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.633309501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_inject_scramble_seed.2009717271 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 66804309834 ps |
| CPU time | 15644.9 seconds |
| Started | Sep 10 12:45:57 AM UTC 24 |
| Finished | Sep 10 05:09:55 AM UTC 24 |
| Peak memory | 643348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=1 50_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009717271 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.2009717271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation.579526713 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 11274516016 ps |
| CPU time | 2240.76 seconds |
| Started | Sep 10 01:25:59 AM UTC 24 |
| Finished | Sep 10 02:03:48 AM UTC 24 |
| Peak memory | 631956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579526713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_ derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.579526713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3348588821 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 10318908160 ps |
| CPU time | 1888.21 seconds |
| Started | Sep 10 01:26:14 AM UTC 24 |
| Finished | Sep 10 01:58:06 AM UTC 24 |
| Peak memory | 632080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348588821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.3348588821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1594525197 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 8605745310 ps |
| CPU time | 1084 seconds |
| Started | Sep 10 01:49:30 AM UTC 24 |
| Finished | Sep 10 02:07:49 AM UTC 24 |
| Peak memory | 631996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594525197 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1594525197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3452115276 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 6231081494 ps |
| CPU time | 1216.26 seconds |
| Started | Sep 10 01:26:17 AM UTC 24 |
| Finished | Sep 10 01:46:50 AM UTC 24 |
| Peak memory | 631828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_devic e=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452115276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.3452115276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_aes.2572957696 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 8944762512 ps |
| CPU time | 1400.46 seconds |
| Started | Sep 10 01:27:32 AM UTC 24 |
| Finished | Sep 10 01:51:12 AM UTC 24 |
| Peak memory | 625740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572957696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sidel oad_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.2572957696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.1970107011 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 9164788748 ps |
| CPU time | 1708.18 seconds |
| Started | Sep 10 01:26:18 AM UTC 24 |
| Finished | Sep 10 01:55:10 AM UTC 24 |
| Peak memory | 625720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970107011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_side load_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.1970107011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_otbn.2759817301 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 18742866514 ps |
| CPU time | 4970.19 seconds |
| Started | Sep 10 01:27:36 AM UTC 24 |
| Finished | Sep 10 02:51:27 AM UTC 24 |
| Peak memory | 628904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759817301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.2759817301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_app_rom.2504714730 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 2744982472 ps |
| CPU time | 244.71 seconds |
| Started | Sep 10 01:28:16 AM UTC 24 |
| Finished | Sep 10 01:32:24 AM UTC 24 |
| Peak memory | 623684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=2504714730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_kmac_app_rom.2504714730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.2384584622 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 2754970680 ps |
| CPU time | 263.55 seconds |
| Started | Sep 10 12:55:53 AM UTC 24 |
| Finished | Sep 10 01:00:21 AM UTC 24 |
| Peak memory | 623600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=2384584622 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_kmac_entropy.2384584622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.1524200547 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 3106905244 ps |
| CPU time | 336.39 seconds |
| Started | Sep 10 01:28:45 AM UTC 24 |
| Finished | Sep 10 01:34:27 AM UTC 24 |
| Peak memory | 625500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=1524200547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ kmac_idle.1524200547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.3278462531 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 2582307526 ps |
| CPU time | 264.09 seconds |
| Started | Sep 10 01:27:37 AM UTC 24 |
| Finished | Sep 10 01:32:05 AM UTC 24 |
| Peak memory | 625648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3278462531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_sw_kmac_mode_cshake.3278462531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.196492506 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 2616825440 ps |
| CPU time | 344.47 seconds |
| Started | Sep 10 01:28:16 AM UTC 24 |
| Finished | Sep 10 01:34:06 AM UTC 24 |
| Peak memory | 625736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196492506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_kmac_mode_kmac.196492506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3295396339 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 2572116493 ps |
| CPU time | 329.9 seconds |
| Started | Sep 10 01:28:19 AM UTC 24 |
| Finished | Sep 10 01:33:54 AM UTC 24 |
| Peak memory | 623688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_km ac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3295396339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.3295396339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1041656031 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 2721115795 ps |
| CPU time | 236.21 seconds |
| Started | Sep 10 01:49:22 AM UTC 24 |
| Finished | Sep 10 01:53:22 AM UTC 24 |
| Peak memory | 625520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041656031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1041656031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.3872649223 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 3103984060 ps |
| CPU time | 388.87 seconds |
| Started | Sep 10 01:57:55 AM UTC 24 |
| Finished | Sep 10 02:04:31 AM UTC 24 |
| Peak memory | 625528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3872649223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ kmac_smoketest.3872649223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.266135223 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 3192064520 ps |
| CPU time | 295.2 seconds |
| Started | Sep 10 12:55:52 AM UTC 24 |
| Finished | Sep 10 01:00:52 AM UTC 24 |
| Peak memory | 623472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=266135223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_lc_ctrl_otp_hw_cfg0.266135223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_program_error.2246327346 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 6136152116 ps |
| CPU time | 574.72 seconds |
| Started | Sep 10 01:40:39 AM UTC 24 |
| Finished | Sep 10 01:50:22 AM UTC 24 |
| Peak memory | 625888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246327346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_l c_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.2246327346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.118798633 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 2988120361 ps |
| CPU time | 278.57 seconds |
| Started | Sep 10 12:58:48 AM UTC 24 |
| Finished | Sep 10 01:03:31 AM UTC 24 |
| Peak memory | 635824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118798633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.118798633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.4272325042 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 4932433530 ps |
| CPU time | 446.57 seconds |
| Started | Sep 10 12:58:04 AM UTC 24 |
| Finished | Sep 10 01:05:37 AM UTC 24 |
| Peak memory | 635908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=4272325042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_lc_ctrl_transition.4272325042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1931823746 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 2359987471 ps |
| CPU time | 105.61 seconds |
| Started | Sep 10 01:02:35 AM UTC 24 |
| Finished | Sep 10 01:04:23 AM UTC 24 |
| Peak memory | 635236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931823746 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.1931823746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1133078292 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 1711172418 ps |
| CPU time | 134.42 seconds |
| Started | Sep 10 01:02:42 AM UTC 24 |
| Finished | Sep 10 01:04:59 AM UTC 24 |
| Peak memory | 633136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSo urceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11330782 92 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc _ctrl_volatile_raw_unlock_ext_clk_48mhz.1133078292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_dev.3958987076 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 50247145808 ps |
| CPU time | 6643.69 seconds |
| Started | Sep 10 01:02:51 AM UTC 24 |
| Finished | Sep 10 02:54:57 AM UTC 24 |
| Peak memory | 643436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958987076 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_dev.3958987076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prod.2217289512 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 49836903336 ps |
| CPU time | 6605.25 seconds |
| Started | Sep 10 01:00:52 AM UTC 24 |
| Finished | Sep 10 02:52:20 AM UTC 24 |
| Peak memory | 643368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217289512 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prod.2217289512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.984483250 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 10448446182 ps |
| CPU time | 1032.54 seconds |
| Started | Sep 10 01:02:19 AM UTC 24 |
| Finished | Sep 10 01:19:46 AM UTC 24 |
| Peak memory | 640252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984483250 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.984483250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_rma.3321393456 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 48412222595 ps |
| CPU time | 5751.24 seconds |
| Started | Sep 10 01:01:07 AM UTC 24 |
| Finished | Sep 10 02:38:09 AM UTC 24 |
| Peak memory | 643488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +fl ash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321393456 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_rma.3321393456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3248099894 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 34754229008 ps |
| CPU time | 2462.92 seconds |
| Started | Sep 10 01:02:48 AM UTC 24 |
| Finished | Sep 10 01:44:24 AM UTC 24 |
| Peak memory | 640168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnl ock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248099894 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testunlocks.3248099894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2681468789 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 17243708532 ps |
| CPU time | 4086.64 seconds |
| Started | Sep 10 01:12:55 AM UTC 24 |
| Finished | Sep 10 02:21:54 AM UTC 24 |
| Peak memory | 628932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681468789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.2681468789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3275844698 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 18128271317 ps |
| CPU time | 4175.56 seconds |
| Started | Sep 10 01:12:55 AM UTC 24 |
| Finished | Sep 10 02:23:24 AM UTC 24 |
| Peak memory | 628916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275844698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3275844698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3542383442 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 24402351135 ps |
| CPU time | 4325.42 seconds |
| Started | Sep 10 01:48:06 AM UTC 24 |
| Finished | Sep 10 03:01:07 AM UTC 24 |
| Peak memory | 628872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542383442 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3542383442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_mem_scramble.4199441353 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 3444228060 ps |
| CPU time | 508.66 seconds |
| Started | Sep 10 01:13:17 AM UTC 24 |
| Finished | Sep 10 01:21:53 AM UTC 24 |
| Peak memory | 625660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199441353 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.4199441353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_randomness.3954135114 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 5956263342 ps |
| CPU time | 856.63 seconds |
| Started | Sep 10 01:12:50 AM UTC 24 |
| Finished | Sep 10 01:27:19 AM UTC 24 |
| Peak memory | 625792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954135114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.3954135114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_randomness/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_smoketest.20310842 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 9875932128 ps |
| CPU time | 2439.15 seconds |
| Started | Sep 10 01:58:08 AM UTC 24 |
| Finished | Sep 10 02:39:19 AM UTC 24 |
| Peak memory | 623904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=20310842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ot bn_smoketest.20310842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.3539237291 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 3348507703 ps |
| CPU time | 256.39 seconds |
| Started | Sep 10 12:57:24 AM UTC 24 |
| Finished | Sep 10 01:01:44 AM UTC 24 |
| Peak memory | 623536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_ error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3539237291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.3539237291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1280609023 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 9949671976 ps |
| CPU time | 1382.54 seconds |
| Started | Sep 10 12:55:56 AM UTC 24 |
| Finished | Sep 10 01:19:17 AM UTC 24 |
| Peak memory | 623764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280609023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.1280609023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.426490185 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 9319529592 ps |
| CPU time | 1173.27 seconds |
| Started | Sep 10 12:56:40 AM UTC 24 |
| Finished | Sep 10 01:16:30 AM UTC 24 |
| Peak memory | 625668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_buil d_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426490185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.426490185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1355456166 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 9010265132 ps |
| CPU time | 1166.58 seconds |
| Started | Sep 10 12:56:43 AM UTC 24 |
| Finished | Sep 10 01:16:25 AM UTC 24 |
| Peak memory | 625816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355456166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.1355456166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1237402567 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 4544604420 ps |
| CPU time | 546.21 seconds |
| Started | Sep 10 12:55:52 AM UTC 24 |
| Finished | Sep 10 01:05:06 AM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237402567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_ asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1237402567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.3127536305 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 3571573370 ps |
| CPU time | 274.44 seconds |
| Started | Sep 10 01:58:13 AM UTC 24 |
| Finished | Sep 10 02:02:51 AM UTC 24 |
| Peak memory | 623468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3127536305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_otp_ctrl_smoketest.3127536305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.3883365003 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 3092605542 ps |
| CPU time | 215.06 seconds |
| Started | Sep 10 01:35:20 AM UTC 24 |
| Finished | Sep 10 01:38:58 AM UTC 24 |
| Peak memory | 623712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3883365003 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_plic_sw_irq.3883365003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.4139327737 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 3894102054 ps |
| CPU time | 475.22 seconds |
| Started | Sep 10 01:50:23 AM UTC 24 |
| Finished | Sep 10 01:58:25 AM UTC 24 |
| Peak memory | 625756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139327737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_power_idle_load.4139327737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_idle_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.19722140 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 3827050872 ps |
| CPU time | 312 seconds |
| Started | Sep 10 01:50:46 AM UTC 24 |
| Finished | Sep 10 01:56:03 AM UTC 24 |
| Peak memory | 625696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=19722140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_power_sleep_load.19722140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_sleep_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_virus.1489639097 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 5894712676 ps |
| CPU time | 1312.54 seconds |
| Started | Sep 10 01:55:29 AM UTC 24 |
| Finished | Sep 10 02:17:38 AM UTC 24 |
| Peak memory | 640400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_tim eout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv + sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489639097 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_virus.1489639097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3948381217 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 10660273564 ps |
| CPU time | 1826.78 seconds |
| Started | Sep 10 01:02:58 AM UTC 24 |
| Finished | Sep 10 01:33:48 AM UTC 24 |
| Peak memory | 625800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948381217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep _all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.3948381217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3564238707 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 27962975042 ps |
| CPU time | 2230.09 seconds |
| Started | Sep 10 01:32:48 AM UTC 24 |
| Finished | Sep 10 02:10:27 AM UTC 24 |
| Peak memory | 625720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564238707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_re set_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.3564238707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1743600912 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 12948910539 ps |
| CPU time | 1725.74 seconds |
| Started | Sep 10 01:03:59 AM UTC 24 |
| Finished | Sep 10 01:33:07 AM UTC 24 |
| Peak memory | 625984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743600912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1743600912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3524291333 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 26734014720 ps |
| CPU time | 1906.62 seconds |
| Started | Sep 10 01:42:45 AM UTC 24 |
| Finished | Sep 10 02:14:55 AM UTC 24 |
| Peak memory | 625832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524291333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr _deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3524291333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3478013499 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 7843751500 ps |
| CPU time | 722.72 seconds |
| Started | Sep 10 01:03:58 AM UTC 24 |
| Finished | Sep 10 01:16:11 AM UTC 24 |
| Peak memory | 625776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_res et_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3478013499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.3478013499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2046298036 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 4979331460 ps |
| CPU time | 375.31 seconds |
| Started | Sep 10 01:04:14 AM UTC 24 |
| Finished | Sep 10 01:10:35 AM UTC 24 |
| Peak memory | 631952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046298036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2046298036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1681642085 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 8996683640 ps |
| CPU time | 499.79 seconds |
| Started | Sep 10 01:02:50 AM UTC 24 |
| Finished | Sep 10 01:11:17 AM UTC 24 |
| Peak memory | 625648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1681642085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_pwrmgr_full_aon_reset.1681642085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.160534255 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 4661972386 ps |
| CPU time | 327.92 seconds |
| Started | Sep 10 01:02:57 AM UTC 24 |
| Finished | Sep 10 01:08:30 AM UTC 24 |
| Peak memory | 631756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160534255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main _power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.160534255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1806786903 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 13399533135 ps |
| CPU time | 1462.58 seconds |
| Started | Sep 10 01:04:14 AM UTC 24 |
| Finished | Sep 10 01:28:55 AM UTC 24 |
| Peak memory | 625920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_r eset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1806786903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1806786903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1312482318 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 6886216434 ps |
| CPU time | 462.42 seconds |
| Started | Sep 10 01:40:39 AM UTC 24 |
| Finished | Sep 10 01:48:28 AM UTC 24 |
| Peak memory | 625648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_w ake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1312482318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1312482318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.999397669 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 6635785385 ps |
| CPU time | 442.86 seconds |
| Started | Sep 10 01:04:09 AM UTC 24 |
| Finished | Sep 10 01:11:38 AM UTC 24 |
| Peak memory | 625876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_r eset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=999397669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.999397669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3162269303 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 22074622734 ps |
| CPU time | 2101.84 seconds |
| Started | Sep 10 01:02:54 AM UTC 24 |
| Finished | Sep 10 01:38:24 AM UTC 24 |
| Peak memory | 625872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162269303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3162269303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.319633357 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 21408079118 ps |
| CPU time | 1531.87 seconds |
| Started | Sep 10 01:42:42 AM UTC 24 |
| Finished | Sep 10 02:08:34 AM UTC 24 |
| Peak memory | 625740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319633357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.319633357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3828082354 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 5429639880 ps |
| CPU time | 465.53 seconds |
| Started | Sep 10 01:42:48 AM UTC 24 |
| Finished | Sep 10 01:50:40 AM UTC 24 |
| Peak memory | 625720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828082354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3828082354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1874028606 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 3504754600 ps |
| CPU time | 338.14 seconds |
| Started | Sep 10 01:05:04 AM UTC 24 |
| Finished | Sep 10 01:10:48 AM UTC 24 |
| Peak memory | 625580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1874028606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_pwrmgr_sleep_disabled.1874028606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3693599423 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 5363509704 ps |
| CPU time | 466.84 seconds |
| Started | Sep 10 01:31:56 AM UTC 24 |
| Finished | Sep 10 01:39:49 AM UTC 24 |
| Peak memory | 623604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_im ages=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693599423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3693599423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2546252234 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 6937312530 ps |
| CPU time | 621.99 seconds |
| Started | Sep 10 01:42:43 AM UTC 24 |
| Finished | Sep 10 01:53:13 AM UTC 24 |
| Peak memory | 625828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546252234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.2546252234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.1494404944 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 5528213652 ps |
| CPU time | 367.12 seconds |
| Started | Sep 10 01:58:47 AM UTC 24 |
| Finished | Sep 10 02:04:59 AM UTC 24 |
| Peak memory | 623600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_ima ges=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494404944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.1494404944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2871952146 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 7566411120 ps |
| CPU time | 1169.72 seconds |
| Started | Sep 10 01:02:40 AM UTC 24 |
| Finished | Sep 10 01:22:25 AM UTC 24 |
| Peak memory | 625892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2871952146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.2871952146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1878525408 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 3942050690 ps |
| CPU time | 598.93 seconds |
| Started | Sep 10 01:05:59 AM UTC 24 |
| Finished | Sep 10 01:16:07 AM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_w hen_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=1878525408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1878525408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2178455888 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 5378497938 ps |
| CPU time | 335.96 seconds |
| Started | Sep 10 01:59:15 AM UTC 24 |
| Finished | Sep 10 02:04:56 AM UTC 24 |
| Peak memory | 623848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2178455888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_pwrmgr_usbdev_smoketest.2178455888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1335605169 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 4012800008 ps |
| CPU time | 477.05 seconds |
| Started | Sep 10 01:12:46 AM UTC 24 |
| Finished | Sep 10 01:20:49 AM UTC 24 |
| Peak memory | 625692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335605169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.1335605169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2865150296 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 10298309489 ps |
| CPU time | 508.42 seconds |
| Started | Sep 10 01:28:48 AM UTC 24 |
| Finished | Sep 10 01:37:24 AM UTC 24 |
| Peak memory | 640040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2865150296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.2865150296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.1207471922 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 5746880490 ps |
| CPU time | 736.97 seconds |
| Started | Sep 10 01:02:45 AM UTC 24 |
| Finished | Sep 10 01:15:12 AM UTC 24 |
| Peak memory | 625664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207471922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_sw_rstmgr_cpu_info.1207471922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3131881964 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 4903093430 ps |
| CPU time | 514.08 seconds |
| Started | Sep 10 12:41:05 AM UTC 24 |
| Finished | Sep 10 12:49:47 AM UTC 24 |
| Peak memory | 669948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131881964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr _cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.3131881964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.923765107 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 3020153296 ps |
| CPU time | 211.03 seconds |
| Started | Sep 10 02:00:11 AM UTC 24 |
| Finished | Sep 10 02:03:46 AM UTC 24 |
| Peak memory | 623588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=923765107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _rstmgr_smoketest.923765107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.621439884 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 3952120106 ps |
| CPU time | 282.9 seconds |
| Started | Sep 10 01:02:44 AM UTC 24 |
| Finished | Sep 10 01:07:31 AM UTC 24 |
| Peak memory | 625520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=621439884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_rstmgr_sw_req.621439884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.3895475843 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 2992463750 ps |
| CPU time | 205.72 seconds |
| Started | Sep 10 01:02:54 AM UTC 24 |
| Finished | Sep 10 01:06:23 AM UTC 24 |
| Peak memory | 623684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3895475843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_rstmgr_sw_rst.3895475843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.999140502 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3245339164 ps |
| CPU time | 323.2 seconds |
| Started | Sep 10 01:45:39 AM UTC 24 |
| Finished | Sep 10 01:51:07 AM UTC 24 |
| Peak memory | 623684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_im ages=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999140502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_b ase_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.999140502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.4244604345 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2902410840 ps |
| CPU time | 262.13 seconds |
| Started | Sep 10 01:46:22 AM UTC 24 |
| Finished | Sep 10 01:50:48 AM UTC 24 |
| Peak memory | 623656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_inval idate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=4244604345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.4244604345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.4185033932 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 5449838376 ps |
| CPU time | 769.38 seconds |
| Started | Sep 10 01:13:35 AM UTC 24 |
| Finished | Sep 10 01:26:34 AM UTC 24 |
| Peak memory | 623528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185033932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.4185033932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.3805039015 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 5568321288 ps |
| CPU time | 941.84 seconds |
| Started | Sep 10 01:12:50 AM UTC 24 |
| Finished | Sep 10 01:28:44 AM UTC 24 |
| Peak memory | 623532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_b uild_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805039015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.3805039015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3448557828 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 5808266444 ps |
| CPU time | 633.79 seconds |
| Started | Sep 10 01:44:39 AM UTC 24 |
| Finished | Sep 10 01:55:22 AM UTC 24 |
| Peak memory | 637872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_han dler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448557828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_esc alation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.3448557828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.832521238 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 5740308824 ps |
| CPU time | 456.9 seconds |
| Started | Sep 10 01:44:34 AM UTC 24 |
| Finished | Sep 10 01:52:18 AM UTC 24 |
| Peak memory | 635896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_acc ess_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=832521238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wake up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.832521238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1154181327 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 3539843900 ps |
| CPU time | 362.96 seconds |
| Started | Sep 10 01:44:25 AM UTC 24 |
| Finished | Sep 10 01:50:33 AM UTC 24 |
| Peak memory | 638180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm _reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154181327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_re set_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asi c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1154181327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_plic_smoketest.3934381518 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 2811232418 ps |
| CPU time | 231.78 seconds |
| Started | Sep 10 01:59:16 AM UTC 24 |
| Finished | Sep 10 02:03:11 AM UTC 24 |
| Peak memory | 625764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=3934381518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_rv_plic_smoketest.3934381518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.438183545 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 2973996136 ps |
| CPU time | 298.43 seconds |
| Started | Sep 10 01:06:02 AM UTC 24 |
| Finished | Sep 10 01:11:05 AM UTC 24 |
| Peak memory | 625744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=438183545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_rv_timer_irq.438183545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.3856669410 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 3507145004 ps |
| CPU time | 330.55 seconds |
| Started | Sep 10 02:00:10 AM UTC 24 |
| Finished | Sep 10 02:05:46 AM UTC 24 |
| Peak memory | 625660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3856669410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_rv_timer_smoketest.3856669410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.2373538613 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 2758955086 ps |
| CPU time | 235.86 seconds |
| Started | Sep 10 01:31:55 AM UTC 24 |
| Finished | Sep 10 01:35:55 AM UTC 24 |
| Peak memory | 625988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373538613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_s tatus_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.2373538613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.1000175868 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 2989515700 ps |
| CPU time | 241.37 seconds |
| Started | Sep 10 12:42:52 AM UTC 24 |
| Finished | Sep 10 12:46:58 AM UTC 24 |
| Peak memory | 625564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1000175868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_sleep_pin_retention.1000175868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.1879937505 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 5745829106 ps |
| CPU time | 481.31 seconds |
| Started | Sep 10 12:42:36 AM UTC 24 |
| Finished | Sep 10 12:50:44 AM UTC 24 |
| Peak memory | 625716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879937505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.1879937505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.3903023544 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 8361041684 ps |
| CPU time | 1219.09 seconds |
| Started | Sep 10 12:45:50 AM UTC 24 |
| Finished | Sep 10 01:06:25 AM UTC 24 |
| Peak memory | 625960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3903023544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_sleep_pwm_pulses.3903023544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2467334985 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 8351317400 ps |
| CPU time | 958.66 seconds |
| Started | Sep 10 01:30:04 AM UTC 24 |
| Finished | Sep 10 01:46:16 AM UTC 24 |
| Peak memory | 625648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467334985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_sram_ret_contents _no_scramble.2467334985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.37867302 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 7364125812 ps |
| CPU time | 619.93 seconds |
| Started | Sep 10 01:30:58 AM UTC 24 |
| Finished | Sep 10 01:41:27 AM UTC 24 |
| Peak memory | 625828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37867302 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_sram_ret_contents_scramble.37867302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.78862120 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 6604522189 ps |
| CPU time | 744.96 seconds |
| Started | Sep 10 12:51:05 AM UTC 24 |
| Finished | Sep 10 01:03:40 AM UTC 24 |
| Peak memory | 640484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78862120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 1.chip_sw_spi_device_pass_through.78862120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through_collision.826579495 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 4225285989 ps |
| CPU time | 494.5 seconds |
| Started | Sep 10 12:51:04 AM UTC 24 |
| Finished | Sep 10 12:59:25 AM UTC 24 |
| Peak memory | 640192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826579495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_spi_device_pass_through_collision.826579495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_tpm.322734757 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3492150895 ps |
| CPU time | 330.97 seconds |
| Started | Sep 10 12:51:08 AM UTC 24 |
| Finished | Sep 10 12:56:44 AM UTC 24 |
| Peak memory | 636080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=322734757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.322734757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.3809173009 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 6695414499 ps |
| CPU time | 561.22 seconds |
| Started | Sep 10 01:30:03 AM UTC 24 |
| Finished | Sep 10 01:39:32 AM UTC 24 |
| Peak memory | 625580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3809173009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.3809173009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3819147197 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 5426247272 ps |
| CPU time | 619.12 seconds |
| Started | Sep 10 01:29:58 AM UTC 24 |
| Finished | Sep 10 01:40:26 AM UTC 24 |
| Peak memory | 625684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819147197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_ access.3819147197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2640825427 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 5247876651 ps |
| CPU time | 670.62 seconds |
| Started | Sep 10 01:30:05 AM UTC 24 |
| Finished | Sep 10 01:41:25 AM UTC 24 |
| Peak memory | 625740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_ch eck=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640825427 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ct rl_scrambled_access_jitter_en.2640825427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2737063011 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 4737842459 ps |
| CPU time | 560.64 seconds |
| Started | Sep 10 01:50:25 AM UTC 24 |
| Finished | Sep 10 01:59:54 AM UTC 24 |
| Peak memory | 625800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_r eady_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737063011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2737063011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.4119591463 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 2846572728 ps |
| CPU time | 277.95 seconds |
| Started | Sep 10 02:00:53 AM UTC 24 |
| Finished | Sep 10 02:05:37 AM UTC 24 |
| Peak memory | 625684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119591463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_sram_ctrl_smoketest.4119591463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2911281623 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 21242211027 ps |
| CPU time | 3280.47 seconds |
| Started | Sep 10 01:09:47 AM UTC 24 |
| Finished | Sep 10 02:05:10 AM UTC 24 |
| Peak memory | 628896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2911281623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.2911281623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2388042042 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 5445194734 ps |
| CPU time | 690.39 seconds |
| Started | Sep 10 01:07:16 AM UTC 24 |
| Finished | Sep 10 01:18:57 AM UTC 24 |
| Peak memory | 628060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2388042042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_sysrst_ctrl_in_irq.2388042042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.440364074 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 3069638481 ps |
| CPU time | 303.86 seconds |
| Started | Sep 10 01:06:18 AM UTC 24 |
| Finished | Sep 10 01:11:28 AM UTC 24 |
| Peak memory | 627820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=440364074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_sysrst_ctrl_inputs.440364074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_outputs.2622882200 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 3149994560 ps |
| CPU time | 307.5 seconds |
| Started | Sep 10 01:09:12 AM UTC 24 |
| Finished | Sep 10 01:14:25 AM UTC 24 |
| Peak memory | 623788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2622882200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_sysrst_ctrl_outputs.2622882200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.802596665 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 23373371902 ps |
| CPU time | 1709.94 seconds |
| Started | Sep 10 01:08:12 AM UTC 24 |
| Finished | Sep 10 01:37:03 AM UTC 24 |
| Peak memory | 627892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_i mages=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802596665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.802596665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3164334275 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 6140519984 ps |
| CPU time | 487.41 seconds |
| Started | Sep 10 01:07:16 AM UTC 24 |
| Finished | Sep 10 01:15:31 AM UTC 24 |
| Peak memory | 623920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3164334275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3164334275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.2110823483 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 8720961000 ps |
| CPU time | 1475.68 seconds |
| Started | Sep 10 12:46:24 AM UTC 24 |
| Finished | Sep 10 01:11:19 AM UTC 24 |
| Peak memory | 636132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110823483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.2110823483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_smoketest.693629761 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 2933610320 ps |
| CPU time | 323.25 seconds |
| Started | Sep 10 02:00:51 AM UTC 24 |
| Finished | Sep 10 02:06:20 AM UTC 24 |
| Peak memory | 629772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=693629761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_uart_smoketest.693629761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx.1177297320 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 3721973388 ps |
| CPU time | 567.96 seconds |
| Started | Sep 10 12:46:04 AM UTC 24 |
| Finished | Sep 10 12:55:40 AM UTC 24 |
| Peak memory | 640112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177297320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.1177297320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.287208364 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 9440202251 ps |
| CPU time | 1573.03 seconds |
| Started | Sep 10 12:46:05 AM UTC 24 |
| Finished | Sep 10 01:12:39 AM UTC 24 |
| Peak memory | 636052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287208364 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_alt_clk_freq.287208364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1396053489 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 8929543279 ps |
| CPU time | 969.61 seconds |
| Started | Sep 10 12:46:27 AM UTC 24 |
| Finished | Sep 10 01:02:49 AM UTC 24 |
| Peak memory | 635960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396053489 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1396053489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.780410460 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 82001879084 ps |
| CPU time | 18602.5 seconds |
| Started | Sep 10 12:46:03 AM UTC 24 |
| Finished | Sep 10 05:59:55 AM UTC 24 |
| Peak memory | 655404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout _ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780410460 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chi p_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.780410460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx1.2738824151 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 4746259178 ps |
| CPU time | 663.91 seconds |
| Started | Sep 10 12:46:09 AM UTC 24 |
| Finished | Sep 10 12:57:23 AM UTC 24 |
| Peak memory | 639996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738824151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.2738824151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx2.1917098043 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 4362937646 ps |
| CPU time | 505.1 seconds |
| Started | Sep 10 12:46:08 AM UTC 24 |
| Finished | Sep 10 12:54:41 AM UTC 24 |
| Peak memory | 640016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917098043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.1917098043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx3.900308331 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 3793416696 ps |
| CPU time | 529.18 seconds |
| Started | Sep 10 12:46:02 AM UTC 24 |
| Finished | Sep 10 12:54:59 AM UTC 24 |
| Peak memory | 639868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900308331 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.900308331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.4028700447 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 2666542970 ps |
| CPU time | 152.34 seconds |
| Started | Sep 10 01:44:48 AM UTC 24 |
| Finished | Sep 10 01:47:23 AM UTC 24 |
| Peak memory | 639924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028700447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.4028700447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.1980637833 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 2732939809 ps |
| CPU time | 123.72 seconds |
| Started | Sep 10 01:45:34 AM UTC 24 |
| Finished | Sep 10 01:47:40 AM UTC 24 |
| Peak memory | 639556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980637833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.1980637833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.3424322588 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 6427739066 ps |
| CPU time | 481.01 seconds |
| Started | Sep 10 01:45:04 AM UTC 24 |
| Finished | Sep 10 01:53:12 AM UTC 24 |
| Peak memory | 652744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424322588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_tap_straps_rma.3424322588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.4030003157 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 4833604712 ps |
| CPU time | 392.73 seconds |
| Started | Sep 10 01:44:56 AM UTC 24 |
| Finished | Sep 10 01:51:35 AM UTC 24 |
| Peak memory | 640384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030003157 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.4030003157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_dev.548677282 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 15523528225 ps |
| CPU time | 4110.73 seconds |
| Started | Sep 10 01:55:04 AM UTC 24 |
| Finished | Sep 10 03:04:25 AM UTC 24 |
| Peak memory | 627036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548677282 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.548677282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod.1266057638 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 15750775608 ps |
| CPU time | 3863.92 seconds |
| Started | Sep 10 01:56:07 AM UTC 24 |
| Finished | Sep 10 03:01:20 AM UTC 24 |
| Peak memory | 623852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266057638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.1266057638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod_end.2781591364 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 15300529054 ps |
| CPU time | 4171.29 seconds |
| Started | Sep 10 01:55:15 AM UTC 24 |
| Finished | Sep 10 03:05:39 AM UTC 24 |
| Peak memory | 626848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278159 1364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_in it_prod_end.2781591364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_rma.2788894538 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 14757780201 ps |
| CPU time | 3952.94 seconds |
| Started | Sep 10 01:55:44 AM UTC 24 |
| Finished | Sep 10 03:02:28 AM UTC 24 |
| Peak memory | 628896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788894538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.2788894538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1945274845 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 11763746670 ps |
| CPU time | 3191.24 seconds |
| Started | Sep 10 01:56:10 AM UTC 24 |
| Finished | Sep 10 02:50:01 AM UTC 24 |
| Peak memory | 626112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1945274845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e 2e_asm_init_test_unlocked0.1945274845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3482439423 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 14895984392 ps |
| CPU time | 4214.28 seconds |
| Started | Sep 10 01:55:48 AM UTC 24 |
| Finished | Sep 10 03:06:54 AM UTC 24 |
| Peak memory | 626976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482439423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3482439423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.4173696131 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 15480779280 ps |
| CPU time | 4085.73 seconds |
| Started | Sep 10 01:56:05 AM UTC 24 |
| Finished | Sep 10 03:05:01 AM UTC 24 |
| Peak memory | 624588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173696131 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.4173696131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1807517182 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 14641102774 ps |
| CPU time | 4083.45 seconds |
| Started | Sep 10 01:55:51 AM UTC 24 |
| Finished | Sep 10 03:04:45 AM UTC 24 |
| Peak memory | 626992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807517182 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_no_meas.1807517182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_self_hash.2403393845 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 27297655520 ps |
| CPU time | 7687.49 seconds |
| Started | Sep 10 01:56:04 AM UTC 24 |
| Finished | Sep 10 04:05:48 AM UTC 24 |
| Peak memory | 626800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_rules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403393845 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.2403393845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_exception_c.4276501242 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 14701395539 ps |
| CPU time | 3930.83 seconds |
| Started | Sep 10 01:55:19 AM UTC 24 |
| Finished | Sep 10 03:01:39 AM UTC 24 |
| Peak memory | 628996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276501242 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_exception_c.4276501242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_output.2066343069 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 29513883631 ps |
| CPU time | 4473.92 seconds |
| Started | Sep 10 01:55:50 AM UTC 24 |
| Finished | Sep 10 03:11:22 AM UTC 24 |
| Peak memory | 628704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_flash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066343069 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.2066343069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_smoke.2334819671 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 14492658776 ps |
| CPU time | 4135.98 seconds |
| Started | Sep 10 01:54:58 AM UTC 24 |
| Finished | Sep 10 03:04:45 AM UTC 24 |
| Peak memory | 629036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334819671 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.2334819671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.rom_e2e_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_static_critical.1068611116 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 17349020488 ps |
| CPU time | 5044.03 seconds |
| Started | Sep 10 01:56:16 AM UTC 24 |
| Finished | Sep 10 03:21:22 AM UTC 24 |
| Peak memory | 626876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068611116 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.1068611116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.618245012 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 4114537110 ps |
| CPU time | 589.42 seconds |
| Started | Sep 10 01:56:20 AM UTC 24 |
| Finished | Sep 10 02:06:17 AM UTC 24 |
| Peak memory | 623680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618245012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.rom_keymgr_functest.618245012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.rom_keymgr_functest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_raw_unlock.225656220 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 5714143820 ps |
| CPU time | 254.27 seconds |
| Started | Sep 10 01:55:07 AM UTC 24 |
| Finished | Sep 10 01:59:25 AM UTC 24 |
| Peak memory | 637560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images =empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225656220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.225656220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_volatile_raw_unlock.3214470686 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 2700377256 ps |
| CPU time | 105.92 seconds |
| Started | Sep 10 01:55:16 AM UTC 24 |
| Finished | Sep 10 01:57:04 AM UTC 24 |
| Peak memory | 633200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRa w +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot _flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3214470686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.3214470686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.rom_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.2402577496 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 6826554617 ps |
| CPU time | 435.2 seconds |
| Started | Sep 10 04:08:20 AM UTC 24 |
| Finished | Sep 10 04:15:41 AM UTC 24 |
| Peak memory | 638120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2402577496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 10.chip_sw_lc_ctrl_transition.2402577496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.3535093982 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 3628968810 ps |
| CPU time | 561.44 seconds |
| Started | Sep 10 04:08:15 AM UTC 24 |
| Finished | Sep 10 04:17:45 AM UTC 24 |
| Peak memory | 635980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535093982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.3535093982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_lc_ctrl_transition.3708393332 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 5992369378 ps |
| CPU time | 544.54 seconds |
| Started | Sep 10 04:08:01 AM UTC 24 |
| Finished | Sep 10 04:17:14 AM UTC 24 |
| Peak memory | 638008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3708393332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 11.chip_sw_lc_ctrl_transition.3708393332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.740169662 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 4174322856 ps |
| CPU time | 617.27 seconds |
| Started | Sep 10 04:08:29 AM UTC 24 |
| Finished | Sep 10 04:18:55 AM UTC 24 |
| Peak memory | 636116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740169662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.740169662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.3158919680 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 7310030745 ps |
| CPU time | 646.09 seconds |
| Started | Sep 10 04:08:29 AM UTC 24 |
| Finished | Sep 10 04:19:24 AM UTC 24 |
| Peak memory | 635900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3158919680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 12.chip_sw_lc_ctrl_transition.3158919680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.1230239680 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 3541097660 ps |
| CPU time | 568.38 seconds |
| Started | Sep 10 04:08:17 AM UTC 24 |
| Finished | Sep 10 04:17:54 AM UTC 24 |
| Peak memory | 636152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230239680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.1230239680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.950781007 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 5996233421 ps |
| CPU time | 534.8 seconds |
| Started | Sep 10 04:12:20 AM UTC 24 |
| Finished | Sep 10 04:21:23 AM UTC 24 |
| Peak memory | 635900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=950781007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 13.chip_sw_lc_ctrl_transition.950781007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.4269085826 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 4235823536 ps |
| CPU time | 580.12 seconds |
| Started | Sep 10 04:12:05 AM UTC 24 |
| Finished | Sep 10 04:21:53 AM UTC 24 |
| Peak memory | 635900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269085826 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.4269085826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.1700719178 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 5882391056 ps |
| CPU time | 755.83 seconds |
| Started | Sep 10 04:12:24 AM UTC 24 |
| Finished | Sep 10 04:25:11 AM UTC 24 |
| Peak memory | 674288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700719178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.1700719178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.1402996054 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 9835682160 ps |
| CPU time | 654.96 seconds |
| Started | Sep 10 04:12:40 AM UTC 24 |
| Finished | Sep 10 04:23:44 AM UTC 24 |
| Peak memory | 637948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1402996054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 14.chip_sw_lc_ctrl_transition.1402996054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.2210730206 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 4101518360 ps |
| CPU time | 594.53 seconds |
| Started | Sep 10 04:12:37 AM UTC 24 |
| Finished | Sep 10 04:22:40 AM UTC 24 |
| Peak memory | 636044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210730206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.2210730206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.3548044011 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 5312123300 ps |
| CPU time | 634.54 seconds |
| Started | Sep 10 04:14:15 AM UTC 24 |
| Finished | Sep 10 04:24:59 AM UTC 24 |
| Peak memory | 674456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548044011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.3548044011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.1455116046 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 7931728996 ps |
| CPU time | 1553.76 seconds |
| Started | Sep 10 04:15:59 AM UTC 24 |
| Finished | Sep 10 04:42:15 AM UTC 24 |
| Peak memory | 635964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455116046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.1455116046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.941829845 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 8135211088 ps |
| CPU time | 1463.88 seconds |
| Started | Sep 10 04:19:16 AM UTC 24 |
| Finished | Sep 10 04:43:59 AM UTC 24 |
| Peak memory | 636060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941829845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.941829845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.4011558363 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 3591065108 ps |
| CPU time | 367.69 seconds |
| Started | Sep 10 04:19:17 AM UTC 24 |
| Finished | Sep 10 04:25:30 AM UTC 24 |
| Peak memory | 672500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011558363 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_alert_handler_lpg_ sleep_mode_alerts.4011558363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.2259848956 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 5331323752 ps |
| CPU time | 698.75 seconds |
| Started | Sep 10 04:19:33 AM UTC 24 |
| Finished | Sep 10 04:31:21 AM UTC 24 |
| Peak memory | 674456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259848956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.2259848956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.2484588678 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 12982626372 ps |
| CPU time | 2484.45 seconds |
| Started | Sep 10 04:18:40 AM UTC 24 |
| Finished | Sep 10 05:00:36 AM UTC 24 |
| Peak memory | 636784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484588678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.2484588678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.263913435 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 4399039298 ps |
| CPU time | 520.99 seconds |
| Started | Sep 10 04:18:41 AM UTC 24 |
| Finished | Sep 10 04:27:29 AM UTC 24 |
| Peak memory | 635904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263913435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.263913435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.1947439211 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 7867617654 ps |
| CPU time | 1530.22 seconds |
| Started | Sep 10 04:20:04 AM UTC 24 |
| Finished | Sep 10 04:45:54 AM UTC 24 |
| Peak memory | 636044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947439211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.1947439211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_mem_access.3752779887 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 13574486800 ps |
| CPU time | 1333.15 seconds |
| Started | Sep 10 03:14:35 AM UTC 24 |
| Finished | Sep 10 03:37:06 AM UTC 24 |
| Peak memory | 623080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752779887 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.3752779887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_jtag_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_rv_dm_ndm_reset_req.2411462007 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 3862084148 ps |
| CPU time | 385.39 seconds |
| Started | Sep 10 03:18:10 AM UTC 24 |
| Finished | Sep 10 03:24:41 AM UTC 24 |
| Peak memory | 635904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411462007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_ reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.2411462007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.994728088 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 3586055918 ps |
| CPU time | 332.66 seconds |
| Started | Sep 10 02:02:32 AM UTC 24 |
| Finished | Sep 10 02:08:10 AM UTC 24 |
| Peak memory | 625652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim _dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994728088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_bas e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.994728088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sival_flash_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1394348924 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 18508924490 ps |
| CPU time | 454.07 seconds |
| Started | Sep 10 02:40:03 AM UTC 24 |
| Finished | Sep 10 02:47:44 AM UTC 24 |
| Peak memory | 636028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394348924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/c hip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1394348924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc.3042789010 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 3489311656 ps |
| CPU time | 341.61 seconds |
| Started | Sep 10 02:44:13 AM UTC 24 |
| Finished | Sep 10 02:50:00 AM UTC 24 |
| Peak memory | 623700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_i mages=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042789010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.3042789010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en.4280108294 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 3213087601 ps |
| CPU time | 266.08 seconds |
| Started | Sep 10 02:46:16 AM UTC 24 |
| Finished | Sep 10 02:50:47 AM UTC 24 |
| Peak memory | 623688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280108294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.4280108294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.323607531 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 2797696290 ps |
| CPU time | 204.7 seconds |
| Started | Sep 10 03:21:49 AM UTC 24 |
| Finished | Sep 10 03:25:17 AM UTC 24 |
| Peak memory | 623712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323607531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.323607531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_entropy.1395331565 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 2912683988 ps |
| CPU time | 296.44 seconds |
| Started | Sep 10 02:51:28 AM UTC 24 |
| Finished | Sep 10 02:56:29 AM UTC 24 |
| Peak memory | 623528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395331565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_aes_entropy.1395331565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_idle.2384745418 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 3048077000 ps |
| CPU time | 283.46 seconds |
| Started | Sep 10 02:46:17 AM UTC 24 |
| Finished | Sep 10 02:51:05 AM UTC 24 |
| Peak memory | 625516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384745418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.2384745418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_masking_off.2506718923 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 3548381504 ps |
| CPU time | 362.88 seconds |
| Started | Sep 10 02:46:38 AM UTC 24 |
| Finished | Sep 10 02:52:46 AM UTC 24 |
| Peak memory | 623584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506718923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_aes_masking_off.2506718923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_masking_off/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_smoketest.3208654861 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 2745353100 ps |
| CPU time | 238.82 seconds |
| Started | Sep 10 03:29:12 AM UTC 24 |
| Finished | Sep 10 03:33:15 AM UTC 24 |
| Peak memory | 623464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3208654861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_a es_smoketest.3208654861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_entropy.1779221544 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 3653818100 ps |
| CPU time | 400.9 seconds |
| Started | Sep 10 02:50:53 AM UTC 24 |
| Finished | Sep 10 02:57:40 AM UTC 24 |
| Peak memory | 623472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779221544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.1779221544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_escalation.982978214 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 4855938328 ps |
| CPU time | 654.69 seconds |
| Started | Sep 10 02:49:19 AM UTC 24 |
| Finished | Sep 10 03:00:23 AM UTC 24 |
| Peak memory | 636080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982978214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_e arlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.982978214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2307539039 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 6189804320 ps |
| CPU time | 1179.45 seconds |
| Started | Sep 10 02:49:41 AM UTC 24 |
| Finished | Sep 10 03:09:36 AM UTC 24 |
| Peak memory | 625592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307539039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_ea rlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.2307539039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.4189778439 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 7246528012 ps |
| CPU time | 1518.98 seconds |
| Started | Sep 10 02:50:52 AM UTC 24 |
| Finished | Sep 10 03:16:32 AM UTC 24 |
| Peak memory | 625648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189778439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_toggle.4189778439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3042462246 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 11244951756 ps |
| CPU time | 1360.18 seconds |
| Started | Sep 10 02:49:37 AM UTC 24 |
| Finished | Sep 10 03:12:34 AM UTC 24 |
| Peak memory | 625652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042462246 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_hand ler_lpg_sleep_mode_pings.3042462246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_ok.1781135035 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 7659073000 ps |
| CPU time | 1281.72 seconds |
| Started | Sep 10 02:49:20 AM UTC 24 |
| Finished | Sep 10 03:10:59 AM UTC 24 |
| Peak memory | 625580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781135035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.1781135035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_timeout.2474132362 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 3474311594 ps |
| CPU time | 434.76 seconds |
| Started | Sep 10 02:49:21 AM UTC 24 |
| Finished | Sep 10 02:56:42 AM UTC 24 |
| Peak memory | 623640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474132362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.2474132362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_test.2113444339 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 3246072374 ps |
| CPU time | 285.83 seconds |
| Started | Sep 10 02:47:22 AM UTC 24 |
| Finished | Sep 10 02:52:13 AM UTC 24 |
| Peak memory | 625524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand om_seed=2113444339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aler t_test.2113444339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.1091831623 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 3985523690 ps |
| CPU time | 386.11 seconds |
| Started | Sep 10 02:39:28 AM UTC 24 |
| Finished | Sep 10 02:46:00 AM UTC 24 |
| Peak memory | 625504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091831623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.1091831623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3288212122 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 6496337944 ps |
| CPU time | 481.69 seconds |
| Started | Sep 10 02:39:28 AM UTC 24 |
| Finished | Sep 10 02:47:37 AM UTC 24 |
| Peak memory | 623728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288212122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3288212122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_smoketest.2215572083 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 3117745896 ps |
| CPU time | 245.82 seconds |
| Started | Sep 10 03:30:12 AM UTC 24 |
| Finished | Sep 10 03:34:21 AM UTC 24 |
| Peak memory | 625720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215572083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_aon_timer_smoketest.2215572083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3382663928 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 10484333400 ps |
| CPU time | 896.09 seconds |
| Started | Sep 10 02:39:42 AM UTC 24 |
| Finished | Sep 10 02:54:49 AM UTC 24 |
| Peak memory | 625648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382663928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.3382663928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3774638775 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 5048611760 ps |
| CPU time | 531.61 seconds |
| Started | Sep 10 02:40:00 AM UTC 24 |
| Finished | Sep 10 02:48:59 AM UTC 24 |
| Peak memory | 625744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774638775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.3774638775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_outputs.158307501 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 7967176224 ps |
| CPU time | 918.24 seconds |
| Started | Sep 10 03:15:09 AM UTC 24 |
| Finished | Sep 10 03:30:41 AM UTC 24 |
| Peak memory | 631800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_ clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h w/dv/tools/sim.tcl +ntb_random_seed=158307501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.158307501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_rst_inputs.2129123181 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 22506120856 ps |
| CPU time | 3732.88 seconds |
| Started | Sep 10 03:23:54 AM UTC 24 |
| Finished | Sep 10 04:26:54 AM UTC 24 |
| Peak memory | 628796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_ images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129123181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_input s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.2129123181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2041207311 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 4912659919 ps |
| CPU time | 462.56 seconds |
| Started | Sep 10 03:08:08 AM UTC 24 |
| Finished | Sep 10 03:15:57 AM UTC 24 |
| Peak memory | 636096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_de vice=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041207311 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.2041207311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2577481918 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 3963426698 ps |
| CPU time | 606.94 seconds |
| Started | Sep 10 03:09:27 AM UTC 24 |
| Finished | Sep 10 03:19:43 AM UTC 24 |
| Peak memory | 625704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577481918 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_dev.2577481918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3206003705 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 4047237064 ps |
| CPU time | 592.97 seconds |
| Started | Sep 10 03:10:43 AM UTC 24 |
| Finished | Sep 10 03:20:45 AM UTC 24 |
| Peak memory | 625564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206003705 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_rma.3206003705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.499594627 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 3859628444 ps |
| CPU time | 464.51 seconds |
| Started | Sep 10 03:08:25 AM UTC 24 |
| Finished | Sep 10 03:16:16 AM UTC 24 |
| Peak memory | 625804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499 594627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_extern al_clk_src_for_sw_fast_test_unlocked0.499594627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.835664114 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 4843245064 ps |
| CPU time | 610.15 seconds |
| Started | Sep 10 03:10:18 AM UTC 24 |
| Finished | Sep 10 03:20:36 AM UTC 24 |
| Peak memory | 625896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835664114 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src _for_sw_slow_dev.835664114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.699274516 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 4518651720 ps |
| CPU time | 558.7 seconds |
| Started | Sep 10 03:11:39 AM UTC 24 |
| Finished | Sep 10 03:21:06 AM UTC 24 |
| Peak memory | 625656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699274516 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src _for_sw_slow_rma.699274516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3074379700 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 4761742096 ps |
| CPU time | 639.1 seconds |
| Started | Sep 10 03:08:29 AM UTC 24 |
| Finished | Sep 10 03:19:17 AM UTC 24 |
| Peak memory | 625796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307 4379700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_exter nal_clk_src_for_sw_slow_test_unlocked0.3074379700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter.732817030 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 2789932322 ps |
| CPU time | 274.73 seconds |
| Started | Sep 10 03:13:16 AM UTC 24 |
| Finished | Sep 10 03:17:55 AM UTC 24 |
| Peak memory | 623636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=732817030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_clkmgr_jitter.732817030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2466770030 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 3934582384 ps |
| CPU time | 489.38 seconds |
| Started | Sep 10 03:12:03 AM UTC 24 |
| Finished | Sep 10 03:20:20 AM UTC 24 |
| Peak memory | 623616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=2466770030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_clkmgr_jitter_frequency.2466770030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3990785211 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 3108845311 ps |
| CPU time | 179.28 seconds |
| Started | Sep 10 03:19:58 AM UTC 24 |
| Finished | Sep 10 03:23:01 AM UTC 24 |
| Peak memory | 623472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkm gr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3990785211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.3990785211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3953236965 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 5605980520 ps |
| CPU time | 506.36 seconds |
| Started | Sep 10 03:06:49 AM UTC 24 |
| Finished | Sep 10 03:15:23 AM UTC 24 |
| Peak memory | 625816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3953236965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.3953236965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1802524988 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 4980090256 ps |
| CPU time | 522.74 seconds |
| Started | Sep 10 03:08:26 AM UTC 24 |
| Finished | Sep 10 03:17:16 AM UTC 24 |
| Peak memory | 623604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1802524988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_clkmgr_off_hmac_trans.1802524988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.405232905 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 5094414808 ps |
| CPU time | 518.48 seconds |
| Started | Sep 10 03:08:07 AM UTC 24 |
| Finished | Sep 10 03:16:53 AM UTC 24 |
| Peak memory | 625660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=405232905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.405232905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1432399417 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 5233559270 ps |
| CPU time | 535.13 seconds |
| Started | Sep 10 03:08:24 AM UTC 24 |
| Finished | Sep 10 03:17:27 AM UTC 24 |
| Peak memory | 625840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1432399417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_clkmgr_off_otbn_trans.1432399417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_peri.2550861376 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 9581170068 ps |
| CPU time | 935.11 seconds |
| Started | Sep 10 03:06:57 AM UTC 24 |
| Finished | Sep 10 03:22:45 AM UTC 24 |
| Peak memory | 625924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_i mages=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550861376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.2550861376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_reset_frequency.2369957722 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 3544662335 ps |
| CPU time | 372.3 seconds |
| Started | Sep 10 03:11:42 AM UTC 24 |
| Finished | Sep 10 03:17:59 AM UTC 24 |
| Peak memory | 625776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369957722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.2369957722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3869312326 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 4177216342 ps |
| CPU time | 593.6 seconds |
| Started | Sep 10 03:13:31 AM UTC 24 |
| Finished | Sep 10 03:23:33 AM UTC 24 |
| Peak memory | 625736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869312326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.3869312326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_smoketest.2139488122 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 3184964380 ps |
| CPU time | 276.79 seconds |
| Started | Sep 10 03:30:13 AM UTC 24 |
| Finished | Sep 10 03:34:54 AM UTC 24 |
| Peak memory | 625656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2139488122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_clkmgr_smoketest.2139488122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency.776621546 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 15696925866 ps |
| CPU time | 3836.21 seconds |
| Started | Sep 10 02:53:25 AM UTC 24 |
| Finished | Sep 10 03:58:08 AM UTC 24 |
| Peak memory | 628780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurren cy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=776621546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_csrng_edn_concurrency.776621546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.4257875864 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 22252328807 ps |
| CPU time | 4741.04 seconds |
| Started | Sep 10 03:22:35 AM UTC 24 |
| Finished | Sep 10 04:42:36 AM UTC 24 |
| Peak memory | 628784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim _dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257875864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_b ase_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.4257875864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.913107202 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 3749425680 ps |
| CPU time | 550.83 seconds |
| Started | Sep 10 02:54:39 AM UTC 24 |
| Finished | Sep 10 03:03:58 AM UTC 24 |
| Peak memory | 625524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913107202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_ fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.913107202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_kat_test.433815082 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 2848727976 ps |
| CPU time | 251.84 seconds |
| Started | Sep 10 02:54:38 AM UTC 24 |
| Finished | Sep 10 02:58:55 AM UTC 24 |
| Peak memory | 625816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=433815082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.433815082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.4016175872 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 6079020843 ps |
| CPU time | 720.45 seconds |
| Started | Sep 10 02:53:03 AM UTC 24 |
| Finished | Sep 10 03:05:13 AM UTC 24 |
| Peak memory | 625928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_ otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016175872 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_lc_hw_debug_en_test.4016175872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_smoketest.3543082521 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 2960473288 ps |
| CPU time | 298.49 seconds |
| Started | Sep 10 03:30:34 AM UTC 24 |
| Finished | Sep 10 03:35:37 AM UTC 24 |
| Peak memory | 623472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3543082521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _csrng_smoketest.3543082521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.2419408 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 4842689304 ps |
| CPU time | 707.07 seconds |
| Started | Sep 10 02:04:00 AM UTC 24 |
| Finished | Sep 10 02:15:57 AM UTC 24 |
| Peak memory | 625784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.2419408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_auto_mode.1725391240 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 5015848712 ps |
| CPU time | 1207.55 seconds |
| Started | Sep 10 02:52:25 AM UTC 24 |
| Finished | Sep 10 03:12:49 AM UTC 24 |
| Peak memory | 625776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerat e_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725391240 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_auto_mode.1725391240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_boot_mode.1008120515 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 3529108912 ps |
| CPU time | 506.48 seconds |
| Started | Sep 10 02:52:23 AM UTC 24 |
| Finished | Sep 10 03:00:58 AM UTC 24 |
| Peak memory | 623884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerat e_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008120515 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_boot_mode.1008120515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs.1323518236 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 7535691240 ps |
| CPU time | 1087.42 seconds |
| Started | Sep 10 02:57:30 AM UTC 24 |
| Finished | Sep 10 03:15:52 AM UTC 24 |
| Peak memory | 626004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323518236 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.1323518236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2501455316 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 7591001397 ps |
| CPU time | 993.04 seconds |
| Started | Sep 10 02:57:29 AM UTC 24 |
| Finished | Sep 10 03:14:16 AM UTC 24 |
| Peak memory | 625864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501455316 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.2501455316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_kat.4041808467 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 3849232146 ps |
| CPU time | 645.87 seconds |
| Started | Sep 10 02:52:24 AM UTC 24 |
| Finished | Sep 10 03:03:20 AM UTC 24 |
| Peak memory | 629800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_a ssert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_k at:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=4041808467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_edn_kat.4041808467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_kat/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_sw_mode.121622182 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 8371266120 ps |
| CPU time | 1910.24 seconds |
| Started | Sep 10 02:53:02 AM UTC 24 |
| Finished | Sep 10 03:25:17 AM UTC 24 |
| Peak memory | 623760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=121622182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_edn_sw_mode.121622182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_ast_rng_req.799474341 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 3529043034 ps |
| CPU time | 361.01 seconds |
| Started | Sep 10 02:55:43 AM UTC 24 |
| Finished | Sep 10 03:01:49 AM UTC 24 |
| Peak memory | 625508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799474341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.799474341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_csrng.4265693904 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 7506125740 ps |
| CPU time | 1475.95 seconds |
| Started | Sep 10 02:55:43 AM UTC 24 |
| Finished | Sep 10 03:20:38 AM UTC 24 |
| Peak memory | 623724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_ srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265693904 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.4265693904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_kat_test.3196837708 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 3046670604 ps |
| CPU time | 363.39 seconds |
| Started | Sep 10 02:51:43 AM UTC 24 |
| Finished | Sep 10 02:57:52 AM UTC 24 |
| Peak memory | 623472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196837708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.3196837708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_smoketest.2216544398 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 3972380928 ps |
| CPU time | 631.17 seconds |
| Started | Sep 10 03:31:22 AM UTC 24 |
| Finished | Sep 10 03:42:02 AM UTC 24 |
| Peak memory | 623612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_de vice=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216544398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.2216544398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.3945285352 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 2864342840 ps |
| CPU time | 293.55 seconds |
| Started | Sep 10 02:01:58 AM UTC 24 |
| Finished | Sep 10 02:06:56 AM UTC 24 |
| Peak memory | 623712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3945285352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_concurrency.3945285352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_example_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.3372976415 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 3172549880 ps |
| CPU time | 274.52 seconds |
| Started | Sep 10 02:00:52 AM UTC 24 |
| Finished | Sep 10 02:05:31 AM UTC 24 |
| Peak memory | 623648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3372976415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_example_flash.3372976415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_example_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.1462939252 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 2414063980 ps |
| CPU time | 281.47 seconds |
| Started | Sep 10 02:01:11 AM UTC 24 |
| Finished | Sep 10 02:05:57 AM UTC 24 |
| Peak memory | 623688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1462939252 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ex ample_manufacturer.1462939252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_example_manufacturer/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.3393573303 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 2299309920 ps |
| CPU time | 125.78 seconds |
| Started | Sep 10 02:00:54 AM UTC 24 |
| Finished | Sep 10 02:03:03 AM UTC 24 |
| Peak memory | 625380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:t est_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3393573303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2. chip_sw_example_rom.3393573303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_example_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_crash_alert.3301115580 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 5473839780 ps |
| CPU time | 636.26 seconds |
| Started | Sep 10 03:19:10 AM UTC 24 |
| Finished | Sep 10 03:29:56 AM UTC 24 |
| Peak memory | 626128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check= 1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301115580 -assert nopostproc +UVM_TESTNAME=chip_base_test + UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.3301115580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access.3479612364 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 5761882500 ps |
| CPU time | 896.83 seconds |
| Started | Sep 10 02:16:51 AM UTC 24 |
| Finished | Sep 10 02:31:59 AM UTC 24 |
| Peak memory | 623536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3479612364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _flash_ctrl_access.3479612364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3249767996 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 5929789290 ps |
| CPU time | 1139.86 seconds |
| Started | Sep 10 02:16:51 AM UTC 24 |
| Finished | Sep 10 02:36:07 AM UTC 24 |
| Peak memory | 623584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=3249767996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_flash_ctrl_access_jitter_en.3249767996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.995325650 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 7571912217 ps |
| CPU time | 1190.62 seconds |
| Started | Sep 10 03:21:47 AM UTC 24 |
| Finished | Sep 10 03:41:53 AM UTC 24 |
| Peak memory | 623540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995325650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.995325650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2889074212 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 6016483923 ps |
| CPU time | 936.22 seconds |
| Started | Sep 10 02:17:32 AM UTC 24 |
| Finished | Sep 10 02:33:21 AM UTC 24 |
| Peak memory | 623596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=2889074212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_flash_ctrl_clock_freqs.2889074212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1082516345 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 3019759426 ps |
| CPU time | 371.09 seconds |
| Started | Sep 10 02:17:32 AM UTC 24 |
| Finished | Sep 10 02:23:49 AM UTC 24 |
| Peak memory | 625580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1082516345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_flash_ctrl_idle_low_power.1082516345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2375034923 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 5677766615 ps |
| CPU time | 687.58 seconds |
| Started | Sep 10 02:15:49 AM UTC 24 |
| Finished | Sep 10 02:27:26 AM UTC 24 |
| Peak memory | 625720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375034923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ct rl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.2375034923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2290548409 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 5704489436 ps |
| CPU time | 1031.49 seconds |
| Started | Sep 10 03:26:23 AM UTC 24 |
| Finished | Sep 10 03:43:49 AM UTC 24 |
| Peak memory | 623668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2290548409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_flash_ctrl_mem_protection.2290548409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops.4073652452 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 3976036956 ps |
| CPU time | 708.98 seconds |
| Started | Sep 10 02:15:17 AM UTC 24 |
| Finished | Sep 10 02:27:16 AM UTC 24 |
| Peak memory | 623460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073652452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.4073652452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1357806698 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 5021837355 ps |
| CPU time | 519.75 seconds |
| Started | Sep 10 03:20:21 AM UTC 24 |
| Finished | Sep 10 03:29:08 AM UTC 24 |
| Peak memory | 625660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357806698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1357806698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_write_clear.2460174384 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 3538901328 ps |
| CPU time | 377.26 seconds |
| Started | Sep 10 03:19:25 AM UTC 24 |
| Finished | Sep 10 03:25:48 AM UTC 24 |
| Peak memory | 625520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_image s=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460174384 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.2460174384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init.3242132215 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 26072075404 ps |
| CPU time | 2019.01 seconds |
| Started | Sep 10 02:17:25 AM UTC 24 |
| Finished | Sep 10 02:51:29 AM UTC 24 |
| Peak memory | 629944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242132215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_flash_init.3242132215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_init/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.1866735370 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 25305437235 ps |
| CPU time | 1888.47 seconds |
| Started | Sep 10 03:22:11 AM UTC 24 |
| Finished | Sep 10 03:54:03 AM UTC 24 |
| Peak memory | 629928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_buil d_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866735370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.1866735370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_scrambling_smoketest.2811481683 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 3092708392 ps |
| CPU time | 309.45 seconds |
| Started | Sep 10 03:28:24 AM UTC 24 |
| Finished | Sep 10 03:33:38 AM UTC 24 |
| Peak memory | 623612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_ima ges=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoketest_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811481683 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chi p_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.2811481683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.1506519882 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 4072741750 ps |
| CPU time | 524.93 seconds |
| Started | Sep 10 02:11:32 AM UTC 24 |
| Finished | Sep 10 02:20:25 AM UTC 24 |
| Peak memory | 623680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1506519882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_gpio.1506519882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_gpio/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio_smoketest.3364604552 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 2491662254 ps |
| CPU time | 303.39 seconds |
| Started | Sep 10 03:31:57 AM UTC 24 |
| Finished | Sep 10 03:37:06 AM UTC 24 |
| Peak memory | 623596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3364604552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_sw_gpio_smoketest.3364604552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc.819854157 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 2954802716 ps |
| CPU time | 331.95 seconds |
| Started | Sep 10 02:57:29 AM UTC 24 |
| Finished | Sep 10 03:03:07 AM UTC 24 |
| Peak memory | 625592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=819854157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hm ac_enc.819854157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_idle.1346490134 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 2756356200 ps |
| CPU time | 282.87 seconds |
| Started | Sep 10 02:59:19 AM UTC 24 |
| Finished | Sep 10 03:04:07 AM UTC 24 |
| Peak memory | 623472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1346490134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_hmac_enc_idle.1346490134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en.1057534607 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 3131548225 ps |
| CPU time | 328.92 seconds |
| Started | Sep 10 02:57:47 AM UTC 24 |
| Finished | Sep 10 03:03:21 AM UTC 24 |
| Peak memory | 625724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1057534607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_hmac_enc_jitter_en.1057534607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3995355220 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 3268833336 ps |
| CPU time | 296 seconds |
| Started | Sep 10 03:22:17 AM UTC 24 |
| Finished | Sep 10 03:27:18 AM UTC 24 |
| Peak memory | 623468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995355220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.3995355220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_multistream.4212859901 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 7104766440 ps |
| CPU time | 1444.59 seconds |
| Started | Sep 10 02:59:16 AM UTC 24 |
| Finished | Sep 10 03:23:39 AM UTC 24 |
| Peak memory | 623688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4212859901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_multistream.4212859901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_multistream/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_oneshot.3137280150 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 3036548856 ps |
| CPU time | 359.49 seconds |
| Started | Sep 10 02:59:20 AM UTC 24 |
| Finished | Sep 10 03:05:25 AM UTC 24 |
| Peak memory | 625772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3137280150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_h mac_oneshot.3137280150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_smoketest.3318688931 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 2912444860 ps |
| CPU time | 341.93 seconds |
| Started | Sep 10 03:32:19 AM UTC 24 |
| Finished | Sep 10 03:38:06 AM UTC 24 |
| Peak memory | 625820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3318688931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ hmac_smoketest.3318688931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.2900648009 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 3925464108 ps |
| CPU time | 606.04 seconds |
| Started | Sep 10 02:09:27 AM UTC 24 |
| Finished | Sep 10 02:19:42 AM UTC 24 |
| Peak memory | 625656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2900648009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.2900648009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx.3467135233 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 5120265400 ps |
| CPU time | 777.86 seconds |
| Started | Sep 10 02:07:57 AM UTC 24 |
| Finished | Sep 10 02:21:06 AM UTC 24 |
| Peak memory | 623736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3467135233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_i2c_host_tx_rx.3467135233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.237590268 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 4789819240 ps |
| CPU time | 734.74 seconds |
| Started | Sep 10 02:08:30 AM UTC 24 |
| Finished | Sep 10 02:20:55 AM UTC 24 |
| Peak memory | 625656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=237590268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.237590268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3856586274 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 5335316660 ps |
| CPU time | 830.79 seconds |
| Started | Sep 10 02:08:51 AM UTC 24 |
| Finished | Sep 10 02:22:53 AM UTC 24 |
| Peak memory | 623596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3856586274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.3856586274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.1126930649 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 67905097024 ps |
| CPU time | 16123.9 seconds |
| Started | Sep 10 02:07:15 AM UTC 24 |
| Finished | Sep 10 06:39:12 AM UTC 24 |
| Peak memory | 643356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=1 50_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126930649 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.1126930649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation.1077803720 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 11522238390 ps |
| CPU time | 2403.49 seconds |
| Started | Sep 10 02:59:11 AM UTC 24 |
| Finished | Sep 10 03:39:45 AM UTC 24 |
| Peak memory | 631820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077803720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key _derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.1077803720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1430103827 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 8231630365 ps |
| CPU time | 1466.13 seconds |
| Started | Sep 10 02:59:16 AM UTC 24 |
| Finished | Sep 10 03:24:01 AM UTC 24 |
| Peak memory | 631896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430103827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.1430103827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.12944215 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 9009232067 ps |
| CPU time | 1315.51 seconds |
| Started | Sep 10 03:22:00 AM UTC 24 |
| Finished | Sep 10 03:44:13 AM UTC 24 |
| Peak memory | 631964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12944215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.12944215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3214567164 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 6300493960 ps |
| CPU time | 1157.02 seconds |
| Started | Sep 10 02:59:11 AM UTC 24 |
| Finished | Sep 10 03:18:43 AM UTC 24 |
| Peak memory | 632036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_devic e=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214567164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.3214567164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_aes.1549862012 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 13173699110 ps |
| CPU time | 2588.18 seconds |
| Started | Sep 10 02:59:50 AM UTC 24 |
| Finished | Sep 10 03:43:31 AM UTC 24 |
| Peak memory | 625804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549862012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sidel oad_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.1549862012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_kmac.1892538258 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 6892248116 ps |
| CPU time | 994.69 seconds |
| Started | Sep 10 02:59:49 AM UTC 24 |
| Finished | Sep 10 03:16:38 AM UTC 24 |
| Peak memory | 625728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892538258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_side load_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.1892538258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.1613873075 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 13941358076 ps |
| CPU time | 3873.23 seconds |
| Started | Sep 10 03:01:07 AM UTC 24 |
| Finished | Sep 10 04:06:30 AM UTC 24 |
| Peak memory | 628772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613873075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.1613873075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_app_rom.2495419505 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 2532431662 ps |
| CPU time | 276.72 seconds |
| Started | Sep 10 03:02:05 AM UTC 24 |
| Finished | Sep 10 03:06:46 AM UTC 24 |
| Peak memory | 623468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=2495419505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_kmac_app_rom.2495419505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_entropy.2299660040 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 3128478840 ps |
| CPU time | 319.73 seconds |
| Started | Sep 10 02:18:35 AM UTC 24 |
| Finished | Sep 10 02:24:00 AM UTC 24 |
| Peak memory | 623680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=2299660040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_kmac_entropy.2299660040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_idle.4284783444 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 2748857816 ps |
| CPU time | 282.34 seconds |
| Started | Sep 10 03:02:30 AM UTC 24 |
| Finished | Sep 10 03:07:17 AM UTC 24 |
| Peak memory | 623724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=4284783444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ kmac_idle.4284783444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_cshake.1430643520 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 3298210984 ps |
| CPU time | 259.98 seconds |
| Started | Sep 10 03:01:08 AM UTC 24 |
| Finished | Sep 10 03:05:32 AM UTC 24 |
| Peak memory | 623468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1430643520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_sw_kmac_mode_cshake.1430643520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac.3365786659 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 3348625304 ps |
| CPU time | 331.46 seconds |
| Started | Sep 10 03:02:00 AM UTC 24 |
| Finished | Sep 10 03:07:36 AM UTC 24 |
| Peak memory | 623656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365786659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_kmac_mode_kmac.3365786659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2934576901 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 2841842010 ps |
| CPU time | 285.27 seconds |
| Started | Sep 10 03:02:02 AM UTC 24 |
| Finished | Sep 10 03:06:52 AM UTC 24 |
| Peak memory | 623532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_km ac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2934576901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.2934576901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3288253592 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 2966941368 ps |
| CPU time | 330.8 seconds |
| Started | Sep 10 03:22:11 AM UTC 24 |
| Finished | Sep 10 03:27:47 AM UTC 24 |
| Peak memory | 623476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288253592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3288253592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_smoketest.3470738556 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 3045443820 ps |
| CPU time | 266.88 seconds |
| Started | Sep 10 03:32:57 AM UTC 24 |
| Finished | Sep 10 03:37:28 AM UTC 24 |
| Peak memory | 623468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3470738556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ kmac_smoketest.3470738556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.176043039 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 2909947524 ps |
| CPU time | 287.63 seconds |
| Started | Sep 10 02:18:35 AM UTC 24 |
| Finished | Sep 10 02:23:28 AM UTC 24 |
| Peak memory | 625588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=176043039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_lc_ctrl_otp_hw_cfg0.176043039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_program_error.1334749274 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 4754281190 ps |
| CPU time | 462.74 seconds |
| Started | Sep 10 03:15:10 AM UTC 24 |
| Finished | Sep 10 03:23:00 AM UTC 24 |
| Peak memory | 625596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334749274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_l c_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.1334749274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3591147131 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 2947837781 ps |
| CPU time | 266.27 seconds |
| Started | Sep 10 02:21:55 AM UTC 24 |
| Finished | Sep 10 02:26:26 AM UTC 24 |
| Peak memory | 635744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591147131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.3591147131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_transition.3173675196 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 11171399711 ps |
| CPU time | 909.46 seconds |
| Started | Sep 10 02:21:58 AM UTC 24 |
| Finished | Sep 10 02:37:20 AM UTC 24 |
| Peak memory | 636040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3173675196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_lc_ctrl_transition.3173675196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.139565559 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 2819537422 ps |
| CPU time | 165.92 seconds |
| Started | Sep 10 02:24:15 AM UTC 24 |
| Finished | Sep 10 02:27:04 AM UTC 24 |
| Peak memory | 633184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139565559 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.139565559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.737175522 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 2895590743 ps |
| CPU time | 179.82 seconds |
| Started | Sep 10 02:24:15 AM UTC 24 |
| Finished | Sep 10 02:27:18 AM UTC 24 |
| Peak memory | 633252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSo urceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73717552 2 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ ctrl_volatile_raw_unlock_ext_clk_48mhz.737175522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.2821731865 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 49835580640 ps |
| CPU time | 6437.09 seconds |
| Started | Sep 10 02:21:59 AM UTC 24 |
| Finished | Sep 10 04:10:38 AM UTC 24 |
| Peak memory | 643180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821731865 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_dev.2821731865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.165552428 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 49410916600 ps |
| CPU time | 6772.16 seconds |
| Started | Sep 10 02:22:36 AM UTC 24 |
| Finished | Sep 10 04:16:52 AM UTC 24 |
| Peak memory | 643304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165552428 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prod.165552428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prodend.2369774729 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 11261150302 ps |
| CPU time | 950.35 seconds |
| Started | Sep 10 02:23:34 AM UTC 24 |
| Finished | Sep 10 02:39:38 AM UTC 24 |
| Peak memory | 640052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369774729 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.2369774729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.2693240814 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 48916204606 ps |
| CPU time | 6634.35 seconds |
| Started | Sep 10 02:24:51 AM UTC 24 |
| Finished | Sep 10 04:16:51 AM UTC 24 |
| Peak memory | 643184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +fl ash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693240814 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_rma.2693240814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.970111721 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 26233240180 ps |
| CPU time | 1962.48 seconds |
| Started | Sep 10 02:24:52 AM UTC 24 |
| Finished | Sep 10 02:58:01 AM UTC 24 |
| Peak memory | 640132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnl ock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970111721 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testunlocks.970111721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3512046119 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 17292409426 ps |
| CPU time | 4293.49 seconds |
| Started | Sep 10 02:40:29 AM UTC 24 |
| Finished | Sep 10 03:53:00 AM UTC 24 |
| Peak memory | 628972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512046119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.3512046119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3048262786 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 19226537682 ps |
| CPU time | 4791.56 seconds |
| Started | Sep 10 02:41:02 AM UTC 24 |
| Finished | Sep 10 04:01:54 AM UTC 24 |
| Peak memory | 626732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048262786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3048262786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3620313335 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 24274681406 ps |
| CPU time | 4215.7 seconds |
| Started | Sep 10 03:22:14 AM UTC 24 |
| Finished | Sep 10 04:33:23 AM UTC 24 |
| Peak memory | 628780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620313335 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3620313335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_mem_scramble.2032347097 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 3082922304 ps |
| CPU time | 433.11 seconds |
| Started | Sep 10 02:41:06 AM UTC 24 |
| Finished | Sep 10 02:48:25 AM UTC 24 |
| Peak memory | 625824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032347097 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.2032347097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_randomness.3106858737 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 5996379446 ps |
| CPU time | 1011.71 seconds |
| Started | Sep 10 02:40:29 AM UTC 24 |
| Finished | Sep 10 02:57:35 AM UTC 24 |
| Peak memory | 625792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106858737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.3106858737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_randomness/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_smoketest.2638339131 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 6868318640 ps |
| CPU time | 1207.37 seconds |
| Started | Sep 10 03:33:25 AM UTC 24 |
| Finished | Sep 10 03:53:48 AM UTC 24 |
| Peak memory | 623868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2638339131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ otbn_smoketest.2638339131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2766835874 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 3048394460 ps |
| CPU time | 297.25 seconds |
| Started | Sep 10 02:21:06 AM UTC 24 |
| Finished | Sep 10 02:26:08 AM UTC 24 |
| Peak memory | 623672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_ error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2766835874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.2766835874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.4104194993 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 6825692304 ps |
| CPU time | 1274.25 seconds |
| Started | Sep 10 02:18:41 AM UTC 24 |
| Finished | Sep 10 02:40:11 AM UTC 24 |
| Peak memory | 625592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104194993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.4104194993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3943062124 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 7079717094 ps |
| CPU time | 945.87 seconds |
| Started | Sep 10 02:18:59 AM UTC 24 |
| Finished | Sep 10 02:34:57 AM UTC 24 |
| Peak memory | 625592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_buil d_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943062124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.3943062124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.723691919 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 7580487360 ps |
| CPU time | 1234.64 seconds |
| Started | Sep 10 02:19:35 AM UTC 24 |
| Finished | Sep 10 02:40:26 AM UTC 24 |
| Peak memory | 625584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723691919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.723691919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2868676197 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 4497386952 ps |
| CPU time | 689.26 seconds |
| Started | Sep 10 02:18:40 AM UTC 24 |
| Finished | Sep 10 02:30:19 AM UTC 24 |
| Peak memory | 625652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868676197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_ asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2868676197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_smoketest.1604586510 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 3210946900 ps |
| CPU time | 284.3 seconds |
| Started | Sep 10 03:34:02 AM UTC 24 |
| Finished | Sep 10 03:38:51 AM UTC 24 |
| Peak memory | 625504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1604586510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_otp_ctrl_smoketest.1604586510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.3133112320 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 3073059944 ps |
| CPU time | 266.45 seconds |
| Started | Sep 10 02:05:47 AM UTC 24 |
| Finished | Sep 10 02:10:18 AM UTC 24 |
| Peak memory | 625580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_im ages=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133112320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.3133112320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pattgen_ios/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_plic_sw_irq.225197775 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 2471384964 ps |
| CPU time | 243.79 seconds |
| Started | Sep 10 03:06:40 AM UTC 24 |
| Finished | Sep 10 03:10:48 AM UTC 24 |
| Peak memory | 623612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=225197775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _plic_sw_irq.225197775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_idle_load.828002670 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 3983464104 ps |
| CPU time | 548.03 seconds |
| Started | Sep 10 03:23:26 AM UTC 24 |
| Finished | Sep 10 03:32:42 AM UTC 24 |
| Peak memory | 625756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828002670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_power_idle_load.828002670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_idle_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_sleep_load.2651857965 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 5024126508 ps |
| CPU time | 330.83 seconds |
| Started | Sep 10 03:23:54 AM UTC 24 |
| Finished | Sep 10 03:29:30 AM UTC 24 |
| Peak memory | 625796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2651857965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.2651857965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_sleep_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_virus.1091410497 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 5323997120 ps |
| CPU time | 1387.35 seconds |
| Started | Sep 10 03:26:43 AM UTC 24 |
| Finished | Sep 10 03:50:08 AM UTC 24 |
| Peak memory | 640472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_tim eout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv + sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091410497 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_virus.1091410497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.752525265 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 11666538268 ps |
| CPU time | 1807.96 seconds |
| Started | Sep 10 02:28:29 AM UTC 24 |
| Finished | Sep 10 02:59:00 AM UTC 24 |
| Peak memory | 625892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752525265 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_ all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.752525265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.75813730 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 18265580320 ps |
| CPU time | 1835.81 seconds |
| Started | Sep 10 03:06:57 AM UTC 24 |
| Finished | Sep 10 03:37:56 AM UTC 24 |
| Peak memory | 625652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75813730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_rese t_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.75813730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4119892126 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 16509983714 ps |
| CPU time | 1492.8 seconds |
| Started | Sep 10 02:28:37 AM UTC 24 |
| Finished | Sep 10 02:53:48 AM UTC 24 |
| Peak memory | 625796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119892126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4119892126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4177481937 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 23131224240 ps |
| CPU time | 1488.59 seconds |
| Started | Sep 10 03:17:42 AM UTC 24 |
| Finished | Sep 10 03:42:51 AM UTC 24 |
| Peak memory | 625796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177481937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr _deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4177481937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2333514813 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 9020413672 ps |
| CPU time | 521.78 seconds |
| Started | Sep 10 02:28:38 AM UTC 24 |
| Finished | Sep 10 02:37:26 AM UTC 24 |
| Peak memory | 625928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_res et_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2333514813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.2333514813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1361949516 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 7645966704 ps |
| CPU time | 697.27 seconds |
| Started | Sep 10 02:31:44 AM UTC 24 |
| Finished | Sep 10 02:43:32 AM UTC 24 |
| Peak memory | 631956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361949516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1361949516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.254169705 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 8834430798 ps |
| CPU time | 634.8 seconds |
| Started | Sep 10 02:27:29 AM UTC 24 |
| Finished | Sep 10 02:38:12 AM UTC 24 |
| Peak memory | 625848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=254169705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.254169705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1124328117 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 3683633116 ps |
| CPU time | 384.42 seconds |
| Started | Sep 10 03:17:04 AM UTC 24 |
| Finished | Sep 10 03:23:34 AM UTC 24 |
| Peak memory | 623704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=1124328117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_pwrmgr_lowpower_cancel.1124328117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.247140275 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 3858820230 ps |
| CPU time | 373.09 seconds |
| Started | Sep 10 02:27:28 AM UTC 24 |
| Finished | Sep 10 02:33:47 AM UTC 24 |
| Peak memory | 631872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247140275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main _power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.247140275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3429585111 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 12254031092 ps |
| CPU time | 1493.92 seconds |
| Started | Sep 10 02:28:33 AM UTC 24 |
| Finished | Sep 10 02:53:47 AM UTC 24 |
| Peak memory | 625860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_r eset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3429585111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3429585111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1935014640 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 7263275388 ps |
| CPU time | 589.23 seconds |
| Started | Sep 10 03:15:34 AM UTC 24 |
| Finished | Sep 10 03:25:31 AM UTC 24 |
| Peak memory | 625716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_w ake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1935014640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1935014640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3887600543 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 4811129759 ps |
| CPU time | 422.52 seconds |
| Started | Sep 10 02:31:00 AM UTC 24 |
| Finished | Sep 10 02:38:09 AM UTC 24 |
| Peak memory | 625652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_r eset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3887600543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.3887600543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3231444658 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 24975646570 ps |
| CPU time | 2775.94 seconds |
| Started | Sep 10 02:28:38 AM UTC 24 |
| Finished | Sep 10 03:15:29 AM UTC 24 |
| Peak memory | 625728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231444658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3231444658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1323509956 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 21974274384 ps |
| CPU time | 1064.32 seconds |
| Started | Sep 10 03:16:59 AM UTC 24 |
| Finished | Sep 10 03:34:58 AM UTC 24 |
| Peak memory | 626024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323509956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1323509956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3001001118 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 6779837268 ps |
| CPU time | 499.48 seconds |
| Started | Sep 10 03:17:47 AM UTC 24 |
| Finished | Sep 10 03:26:13 AM UTC 24 |
| Peak memory | 625856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001001118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3001001118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3097414139 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 3193769524 ps |
| CPU time | 329.92 seconds |
| Started | Sep 10 02:32:55 AM UTC 24 |
| Finished | Sep 10 02:38:30 AM UTC 24 |
| Peak memory | 623468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3097414139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_pwrmgr_sleep_disabled.3097414139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.601779076 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 5907860952 ps |
| CPU time | 447.25 seconds |
| Started | Sep 10 03:06:44 AM UTC 24 |
| Finished | Sep 10 03:14:17 AM UTC 24 |
| Peak memory | 625648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_im ages=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601779076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.601779076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1424513708 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 6564813780 ps |
| CPU time | 362.7 seconds |
| Started | Sep 10 03:17:46 AM UTC 24 |
| Finished | Sep 10 03:23:55 AM UTC 24 |
| Peak memory | 625816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424513708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.1424513708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_smoketest.3104062968 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 5832384416 ps |
| CPU time | 481.49 seconds |
| Started | Sep 10 03:34:02 AM UTC 24 |
| Finished | Sep 10 03:42:11 AM UTC 24 |
| Peak memory | 625872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_ima ges=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104062968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.3104062968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1840338335 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 6319216222 ps |
| CPU time | 932.59 seconds |
| Started | Sep 10 02:27:27 AM UTC 24 |
| Finished | Sep 10 02:43:13 AM UTC 24 |
| Peak memory | 625844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1840338335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.1840338335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1073962735 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 5678218056 ps |
| CPU time | 679.31 seconds |
| Started | Sep 10 02:34:02 AM UTC 24 |
| Finished | Sep 10 02:45:31 AM UTC 24 |
| Peak memory | 625708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_w hen_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=1073962735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1073962735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2985104223 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 5257808550 ps |
| CPU time | 370.23 seconds |
| Started | Sep 10 03:34:17 AM UTC 24 |
| Finished | Sep 10 03:40:33 AM UTC 24 |
| Peak memory | 623848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2985104223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_pwrmgr_usbdev_smoketest.2985104223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1969131833 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 4512089652 ps |
| CPU time | 479.17 seconds |
| Started | Sep 10 02:39:47 AM UTC 24 |
| Finished | Sep 10 02:47:53 AM UTC 24 |
| Peak memory | 623720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969131833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.1969131833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3017215783 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 9372792896 ps |
| CPU time | 443.89 seconds |
| Started | Sep 10 03:02:32 AM UTC 24 |
| Finished | Sep 10 03:10:02 AM UTC 24 |
| Peak memory | 625712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3017215783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.3017215783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.1542961319 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 12029233044 ps |
| CPU time | 1476.66 seconds |
| Started | Sep 10 02:26:23 AM UTC 24 |
| Finished | Sep 10 02:51:19 AM UTC 24 |
| Peak memory | 625584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_buil d_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542961319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.1542961319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_cpu_info.3528837413 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 5659379388 ps |
| CPU time | 672.26 seconds |
| Started | Sep 10 02:26:46 AM UTC 24 |
| Finished | Sep 10 02:38:07 AM UTC 24 |
| Peak memory | 623552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528837413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_sw_rstmgr_cpu_info.3528837413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1943736779 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 5930876400 ps |
| CPU time | 717.9 seconds |
| Started | Sep 10 02:03:59 AM UTC 24 |
| Finished | Sep 10 02:16:07 AM UTC 24 |
| Peak memory | 670136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943736779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr _cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.1943736779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_smoketest.2256313506 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 2610550680 ps |
| CPU time | 246.69 seconds |
| Started | Sep 10 03:35:42 AM UTC 24 |
| Finished | Sep 10 03:39:53 AM UTC 24 |
| Peak memory | 623540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2256313506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_rstmgr_smoketest.2256313506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_req.9749519 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 4253888560 ps |
| CPU time | 339.08 seconds |
| Started | Sep 10 02:24:53 AM UTC 24 |
| Finished | Sep 10 02:30:37 AM UTC 24 |
| Peak memory | 623540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=9749519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _rstmgr_sw_req.9749519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_rst.3648834284 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 3306225296 ps |
| CPU time | 294.33 seconds |
| Started | Sep 10 02:26:03 AM UTC 24 |
| Finished | Sep 10 02:31:02 AM UTC 24 |
| Peak memory | 625660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3648834284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_rstmgr_sw_rst.3648834284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1532571020 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 3676081776 ps |
| CPU time | 330.66 seconds |
| Started | Sep 10 03:19:07 AM UTC 24 |
| Finished | Sep 10 03:24:43 AM UTC 24 |
| Peak memory | 623752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_im ages=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532571020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.1532571020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1433376490 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 2959455428 ps |
| CPU time | 259.74 seconds |
| Started | Sep 10 03:19:10 AM UTC 24 |
| Finished | Sep 10 03:23:34 AM UTC 24 |
| Peak memory | 623672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_inval idate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1433376490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.1433376490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3201694179 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 5122520904 ps |
| CPU time | 824.25 seconds |
| Started | Sep 10 02:43:54 AM UTC 24 |
| Finished | Sep 10 02:57:50 AM UTC 24 |
| Peak memory | 625580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201694179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.3201694179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_rnd.1759546092 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 5481320008 ps |
| CPU time | 853.58 seconds |
| Started | Sep 10 02:42:42 AM UTC 24 |
| Finished | Sep 10 02:57:06 AM UTC 24 |
| Peak memory | 623536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_b uild_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759546092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.1759546092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2215186576 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 5275768547 ps |
| CPU time | 467.9 seconds |
| Started | Sep 10 03:18:11 AM UTC 24 |
| Finished | Sep 10 03:26:06 AM UTC 24 |
| Peak memory | 639920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_han dler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215186576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_esc alation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.2215186576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2592868829 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 6262167600 ps |
| CPU time | 544.62 seconds |
| Started | Sep 10 03:17:54 AM UTC 24 |
| Finished | Sep 10 03:27:06 AM UTC 24 |
| Peak memory | 635828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_acc ess_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592868829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wak eup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.2592868829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1570910242 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 3894293982 ps |
| CPU time | 513.63 seconds |
| Started | Sep 10 03:18:01 AM UTC 24 |
| Finished | Sep 10 03:26:42 AM UTC 24 |
| Peak memory | 636028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm _reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570910242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_re set_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asi c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1570910242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_plic_smoketest.2563609113 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 2860952712 ps |
| CPU time | 282.47 seconds |
| Started | Sep 10 03:35:01 AM UTC 24 |
| Finished | Sep 10 03:39:48 AM UTC 24 |
| Peak memory | 625556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=2563609113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_rv_plic_smoketest.2563609113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_irq.3475319147 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 3358304396 ps |
| CPU time | 299.32 seconds |
| Started | Sep 10 02:34:37 AM UTC 24 |
| Finished | Sep 10 02:39:41 AM UTC 24 |
| Peak memory | 625692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3475319147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_rv_timer_irq.3475319147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_smoketest.2585027934 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 3522227904 ps |
| CPU time | 289.8 seconds |
| Started | Sep 10 03:35:04 AM UTC 24 |
| Finished | Sep 10 03:39:59 AM UTC 24 |
| Peak memory | 623460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2585027934 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_rv_timer_smoketest.2585027934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.36189094 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 7301797844 ps |
| CPU time | 737.39 seconds |
| Started | Sep 10 03:04:53 AM UTC 24 |
| Finished | Sep 10 03:17:21 AM UTC 24 |
| Peak memory | 625724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36189094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.36189094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_status.187121490 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 2832001593 ps |
| CPU time | 214.34 seconds |
| Started | Sep 10 03:05:07 AM UTC 24 |
| Finished | Sep 10 03:08:45 AM UTC 24 |
| Peak memory | 623932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187121490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_st atus_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.187121490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.1375902614 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 3286000714 ps |
| CPU time | 313.82 seconds |
| Started | Sep 10 02:05:22 AM UTC 24 |
| Finished | Sep 10 02:10:40 AM UTC 24 |
| Peak memory | 623736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1375902614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_sleep_pin_retention.1375902614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pwm_pulses.3499912908 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 9388119236 ps |
| CPU time | 1163.88 seconds |
| Started | Sep 10 02:06:45 AM UTC 24 |
| Finished | Sep 10 02:26:25 AM UTC 24 |
| Peak memory | 625716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3499912908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_sleep_pwm_pulses.3499912908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.47514579 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 6435664408 ps |
| CPU time | 544.61 seconds |
| Started | Sep 10 03:04:14 AM UTC 24 |
| Finished | Sep 10 03:13:26 AM UTC 24 |
| Peak memory | 625720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47514579 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_sram_ret_contents_n o_scramble.47514579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.584001119 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 7442787496 ps |
| CPU time | 780.36 seconds |
| Started | Sep 10 03:04:52 AM UTC 24 |
| Finished | Sep 10 03:18:03 AM UTC 24 |
| Peak memory | 625876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584001119 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_sram_ret_contents_scramble.584001119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through.626413832 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 6991738037 ps |
| CPU time | 832.93 seconds |
| Started | Sep 10 02:11:36 AM UTC 24 |
| Finished | Sep 10 02:25:40 AM UTC 24 |
| Peak memory | 640256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626413832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_spi_device_pass_through.626413832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through_collision.3216703901 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 3479195851 ps |
| CPU time | 558.08 seconds |
| Started | Sep 10 02:11:35 AM UTC 24 |
| Finished | Sep 10 02:21:01 AM UTC 24 |
| Peak memory | 640400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216703901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.3216703901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.627594914 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 3841272888 ps |
| CPU time | 398.45 seconds |
| Started | Sep 10 02:11:32 AM UTC 24 |
| Finished | Sep 10 02:18:16 AM UTC 24 |
| Peak memory | 636248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=627594914 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_spi_device_pinmux_sleep_retention.627594914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_tpm.965484254 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 2830275084 ps |
| CPU time | 421.59 seconds |
| Started | Sep 10 02:09:26 AM UTC 24 |
| Finished | Sep 10 02:16:34 AM UTC 24 |
| Peak memory | 636088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=965484254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.965484254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.1524088356 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3427912376 ps |
| CPU time | 363.3 seconds |
| Started | Sep 10 02:10:30 AM UTC 24 |
| Finished | Sep 10 02:16:39 AM UTC 24 |
| Peak memory | 623596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524088356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 2.chip_sw_spi_host_tx_rx.1524088356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_execution_main.3714987798 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 8134857395 ps |
| CPU time | 661.61 seconds |
| Started | Sep 10 03:04:14 AM UTC 24 |
| Finished | Sep 10 03:15:25 AM UTC 24 |
| Peak memory | 625580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3714987798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.3714987798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1605018438 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 5682767350 ps |
| CPU time | 746.91 seconds |
| Started | Sep 10 03:03:10 AM UTC 24 |
| Finished | Sep 10 03:15:47 AM UTC 24 |
| Peak memory | 625844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605018438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_ access.1605018438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.524897858 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 5204540550 ps |
| CPU time | 617.38 seconds |
| Started | Sep 10 03:03:43 AM UTC 24 |
| Finished | Sep 10 03:14:09 AM UTC 24 |
| Peak memory | 625856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_ch eck=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524897858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctr l_scrambled_access_jitter_en.524897858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.585649631 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 5296679639 ps |
| CPU time | 590.06 seconds |
| Started | Sep 10 03:22:18 AM UTC 24 |
| Finished | Sep 10 03:32:16 AM UTC 24 |
| Peak memory | 625860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_r eady_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585649631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.585649631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_smoketest.1715718413 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 2451929860 ps |
| CPU time | 214.64 seconds |
| Started | Sep 10 03:35:43 AM UTC 24 |
| Finished | Sep 10 03:39:21 AM UTC 24 |
| Peak memory | 623468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715718413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_sram_ctrl_smoketest.1715718413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1463745340 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 21095224054 ps |
| CPU time | 3521.41 seconds |
| Started | Sep 10 02:39:42 AM UTC 24 |
| Finished | Sep 10 03:39:10 AM UTC 24 |
| Peak memory | 626960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1463745340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.1463745340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.4197695862 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 5115534965 ps |
| CPU time | 733.55 seconds |
| Started | Sep 10 02:35:52 AM UTC 24 |
| Finished | Sep 10 02:48:18 AM UTC 24 |
| Peak memory | 628144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=4197695862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_sysrst_ctrl_in_irq.4197695862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1233190269 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 3027543715 ps |
| CPU time | 361.62 seconds |
| Started | Sep 10 02:35:52 AM UTC 24 |
| Finished | Sep 10 02:42:00 AM UTC 24 |
| Peak memory | 627980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1233190269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_sysrst_ctrl_inputs.1233190269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3593392204 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 3563074324 ps |
| CPU time | 420.44 seconds |
| Started | Sep 10 02:38:16 AM UTC 24 |
| Finished | Sep 10 02:45:24 AM UTC 24 |
| Peak memory | 625932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3593392204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_sysrst_ctrl_outputs.3593392204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_reset.4212963754 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 24051884020 ps |
| CPU time | 1704.53 seconds |
| Started | Sep 10 02:38:15 AM UTC 24 |
| Finished | Sep 10 03:07:03 AM UTC 24 |
| Peak memory | 630084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_i mages=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212963754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.4212963754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2803089924 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 5765532780 ps |
| CPU time | 583.63 seconds |
| Started | Sep 10 02:36:47 AM UTC 24 |
| Finished | Sep 10 02:46:39 AM UTC 24 |
| Peak memory | 625972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2803089924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2803089924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_rand_baudrate.4173902007 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 8526459320 ps |
| CPU time | 1434.07 seconds |
| Started | Sep 10 02:07:58 AM UTC 24 |
| Finished | Sep 10 02:32:10 AM UTC 24 |
| Peak memory | 635960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173902007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.4173902007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_smoketest.4026581383 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 2851395992 ps |
| CPU time | 317.4 seconds |
| Started | Sep 10 03:36:18 AM UTC 24 |
| Finished | Sep 10 03:41:41 AM UTC 24 |
| Peak memory | 629880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=4026581383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_sw_uart_smoketest.4026581383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx.3786266827 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 3658151570 ps |
| CPU time | 521.56 seconds |
| Started | Sep 10 02:07:50 AM UTC 24 |
| Finished | Sep 10 02:16:38 AM UTC 24 |
| Peak memory | 640040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786266827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.3786266827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.4218502740 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 4936911196 ps |
| CPU time | 566.99 seconds |
| Started | Sep 10 02:07:54 AM UTC 24 |
| Finished | Sep 10 02:17:29 AM UTC 24 |
| Peak memory | 636104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218502740 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_alt_clk_freq.4218502740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.149446239 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 3984883459 ps |
| CPU time | 436.35 seconds |
| Started | Sep 10 02:07:38 AM UTC 24 |
| Finished | Sep 10 02:15:01 AM UTC 24 |
| Peak memory | 636104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149446239 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.149446239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2478633841 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 81566068209 ps |
| CPU time | 19041.1 seconds |
| Started | Sep 10 02:07:19 AM UTC 24 |
| Finished | Sep 10 07:28:28 AM UTC 24 |
| Peak memory | 655552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout _ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478633841 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.2478633841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx1.751376027 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 4550870850 ps |
| CPU time | 718.19 seconds |
| Started | Sep 10 02:06:44 AM UTC 24 |
| Finished | Sep 10 02:18:52 AM UTC 24 |
| Peak memory | 639992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751376027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.751376027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx2.3518075757 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 4565458452 ps |
| CPU time | 604.08 seconds |
| Started | Sep 10 02:07:36 AM UTC 24 |
| Finished | Sep 10 02:17:49 AM UTC 24 |
| Peak memory | 640200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518075757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.3518075757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx3.3710756901 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 4532942920 ps |
| CPU time | 590.14 seconds |
| Started | Sep 10 02:07:24 AM UTC 24 |
| Finished | Sep 10 02:17:22 AM UTC 24 |
| Peak memory | 640124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710756901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.3710756901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_dev.637744651 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 10892946229 ps |
| CPU time | 974.77 seconds |
| Started | Sep 10 03:17:43 AM UTC 24 |
| Finished | Sep 10 03:34:10 AM UTC 24 |
| Peak memory | 640508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637744651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.637744651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_prod.506937006 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 8765603400 ps |
| CPU time | 777.74 seconds |
| Started | Sep 10 03:18:08 AM UTC 24 |
| Finished | Sep 10 03:31:16 AM UTC 24 |
| Peak memory | 642504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506937006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.506937006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_rma.2787840054 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 7470048287 ps |
| CPU time | 578.73 seconds |
| Started | Sep 10 03:18:08 AM UTC 24 |
| Finished | Sep 10 03:27:55 AM UTC 24 |
| Peak memory | 640524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787840054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_tap_straps_rma.2787840054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_testunlock0.3299533160 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 2320637727 ps |
| CPU time | 179.49 seconds |
| Started | Sep 10 03:18:10 AM UTC 24 |
| Finished | Sep 10 03:21:12 AM UTC 24 |
| Peak memory | 640388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299533160 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.3299533160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_dev.2346175402 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 16363879716 ps |
| CPU time | 4422.94 seconds |
| Started | Sep 10 03:28:46 AM UTC 24 |
| Finished | Sep 10 04:43:25 AM UTC 24 |
| Peak memory | 628892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346175402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.2346175402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod.3786282304 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 15728687280 ps |
| CPU time | 4385.11 seconds |
| Started | Sep 10 03:28:56 AM UTC 24 |
| Finished | Sep 10 04:42:55 AM UTC 24 |
| Peak memory | 626984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786282304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.3786282304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod_end.1235682587 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 16341588695 ps |
| CPU time | 4238.23 seconds |
| Started | Sep 10 03:30:07 AM UTC 24 |
| Finished | Sep 10 04:41:38 AM UTC 24 |
| Peak memory | 624168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123568 2587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_in it_prod_end.1235682587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_rma.2436408663 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 14762743600 ps |
| CPU time | 4383.73 seconds |
| Started | Sep 10 03:29:53 AM UTC 24 |
| Finished | Sep 10 04:43:51 AM UTC 24 |
| Peak memory | 626976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436408663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.2436408663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1774080533 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 11118300298 ps |
| CPU time | 3049.48 seconds |
| Started | Sep 10 03:29:00 AM UTC 24 |
| Finished | Sep 10 04:20:27 AM UTC 24 |
| Peak memory | 623988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1774080533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e 2e_asm_init_test_unlocked0.1774080533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2551728287 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 14936949368 ps |
| CPU time | 4323.8 seconds |
| Started | Sep 10 03:29:40 AM UTC 24 |
| Finished | Sep 10 04:42:38 AM UTC 24 |
| Peak memory | 626976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551728287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2551728287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2180262017 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 15435090966 ps |
| CPU time | 4102.07 seconds |
| Started | Sep 10 03:29:14 AM UTC 24 |
| Finished | Sep 10 04:38:29 AM UTC 24 |
| Peak memory | 626972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180262017 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.2180262017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.296533492 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 15148278800 ps |
| CPU time | 3922.28 seconds |
| Started | Sep 10 03:29:40 AM UTC 24 |
| Finished | Sep 10 04:35:53 AM UTC 24 |
| Peak memory | 626032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296533492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_no_meas.296533492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.2882198407 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 26841582248 ps |
| CPU time | 8047.24 seconds |
| Started | Sep 10 03:29:14 AM UTC 24 |
| Finished | Sep 10 05:45:00 AM UTC 24 |
| Peak memory | 626960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_rules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882198407 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.2882198407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.rom_e2e_self_hash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.3869328289 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 14788545801 ps |
| CPU time | 4165.52 seconds |
| Started | Sep 10 03:27:03 AM UTC 24 |
| Finished | Sep 10 04:37:20 AM UTC 24 |
| Peak memory | 629048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869328289 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_exception_c.3869328289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.1324924706 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 27617181880 ps |
| CPU time | 4113.38 seconds |
| Started | Sep 10 03:28:59 AM UTC 24 |
| Finished | Sep 10 04:38:23 AM UTC 24 |
| Peak memory | 628860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_flash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324924706 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.1324924706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.rom_e2e_shutdown_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.1452432110 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 14894307336 ps |
| CPU time | 3978.55 seconds |
| Started | Sep 10 03:29:02 AM UTC 24 |
| Finished | Sep 10 04:36:10 AM UTC 24 |
| Peak memory | 628976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452432110 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.1452432110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.rom_e2e_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.1902017156 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 17047703074 ps |
| CPU time | 4279.33 seconds |
| Started | Sep 10 03:29:25 AM UTC 24 |
| Finished | Sep 10 04:41:38 AM UTC 24 |
| Peak memory | 628772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902017156 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.1902017156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.rom_e2e_static_critical/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_keymgr_functest.1673875400 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 3885037532 ps |
| CPU time | 525.52 seconds |
| Started | Sep 10 03:28:48 AM UTC 24 |
| Finished | Sep 10 03:37:41 AM UTC 24 |
| Peak memory | 625724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673875400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 2.rom_keymgr_functest.1673875400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.rom_keymgr_functest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_raw_unlock.4093057237 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 4539086536 ps |
| CPU time | 246.26 seconds |
| Started | Sep 10 03:28:59 AM UTC 24 |
| Finished | Sep 10 03:33:09 AM UTC 24 |
| Peak memory | 637484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images =empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093057237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.4093057237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.rom_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_volatile_raw_unlock.2941452705 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 2027092694 ps |
| CPU time | 126.98 seconds |
| Started | Sep 10 03:29:28 AM UTC 24 |
| Finished | Sep 10 03:31:37 AM UTC 24 |
| Peak memory | 633372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRa w +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot _flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2941452705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.2941452705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.rom_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.1932438110 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 5167477520 ps |
| CPU time | 617.95 seconds |
| Started | Sep 10 04:21:18 AM UTC 24 |
| Finished | Sep 10 04:31:44 AM UTC 24 |
| Peak memory | 636288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932438110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.1932438110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.904423224 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 5176822878 ps |
| CPU time | 627.99 seconds |
| Started | Sep 10 04:21:57 AM UTC 24 |
| Finished | Sep 10 04:32:34 AM UTC 24 |
| Peak memory | 674220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904423224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.904423224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2870303429 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 3985933180 ps |
| CPU time | 450.7 seconds |
| Started | Sep 10 04:22:02 AM UTC 24 |
| Finished | Sep 10 04:29:39 AM UTC 24 |
| Peak memory | 672484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870303429 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2870303429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.2969745573 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 6284318216 ps |
| CPU time | 763.25 seconds |
| Started | Sep 10 04:22:49 AM UTC 24 |
| Finished | Sep 10 04:35:43 AM UTC 24 |
| Peak memory | 674224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969745573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.2969745573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.408669931 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 3451870168 ps |
| CPU time | 373.06 seconds |
| Started | Sep 10 04:25:09 AM UTC 24 |
| Finished | Sep 10 04:31:28 AM UTC 24 |
| Peak memory | 672408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408669931 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_alert_handler_lpg_s leep_mode_alerts.408669931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.1173939815 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 5096506772 ps |
| CPU time | 613.93 seconds |
| Started | Sep 10 04:24:47 AM UTC 24 |
| Finished | Sep 10 04:35:10 AM UTC 24 |
| Peak memory | 674236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173939815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.1173939815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2258530089 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 3336635132 ps |
| CPU time | 305.72 seconds |
| Started | Sep 10 04:26:48 AM UTC 24 |
| Finished | Sep 10 04:31:59 AM UTC 24 |
| Peak memory | 672248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258530089 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2258530089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.4051822310 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 3954762170 ps |
| CPU time | 600.68 seconds |
| Started | Sep 10 04:26:42 AM UTC 24 |
| Finished | Sep 10 04:36:51 AM UTC 24 |
| Peak memory | 674416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051822310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.4051822310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1078440404 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 3685434344 ps |
| CPU time | 471.76 seconds |
| Started | Sep 10 03:41:00 AM UTC 24 |
| Finished | Sep 10 03:48:59 AM UTC 24 |
| Peak memory | 672180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078440404 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_alert_handler_lpg_s leep_mode_alerts.1078440404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_all_escalation_resets.2064113091 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 4827022194 ps |
| CPU time | 775.29 seconds |
| Started | Sep 10 03:38:49 AM UTC 24 |
| Finished | Sep 10 03:51:55 AM UTC 24 |
| Peak memory | 674524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064113091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.2064113091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2880349626 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 7023136338 ps |
| CPU time | 513.43 seconds |
| Started | Sep 10 03:41:17 AM UTC 24 |
| Finished | Sep 10 03:49:57 AM UTC 24 |
| Peak memory | 625796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880349626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2880349626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.2183904956 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 23060669964 ps |
| CPU time | 6279.62 seconds |
| Started | Sep 10 03:41:17 AM UTC 24 |
| Finished | Sep 10 05:27:15 AM UTC 24 |
| Peak memory | 629032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurren cy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2183904956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 3.chip_sw_csrng_edn_concurrency.2183904956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_data_integrity_escalation.3353446396 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 5574761816 ps |
| CPU time | 778.9 seconds |
| Started | Sep 10 03:38:56 AM UTC 24 |
| Finished | Sep 10 03:52:06 AM UTC 24 |
| Peak memory | 625884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353446396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.3353446396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_lc_ctrl_transition.3422218319 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 11130432018 ps |
| CPU time | 1106.31 seconds |
| Started | Sep 10 03:41:13 AM UTC 24 |
| Finished | Sep 10 03:59:54 AM UTC 24 |
| Peak memory | 636148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3422218319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 3.chip_sw_lc_ctrl_transition.3422218319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.1635962237 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 13418845060 ps |
| CPU time | 2457.63 seconds |
| Started | Sep 10 03:39:34 AM UTC 24 |
| Finished | Sep 10 04:21:02 AM UTC 24 |
| Peak memory | 635896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635962237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.1635962237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx.3800112940 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 4109907708 ps |
| CPU time | 729.69 seconds |
| Started | Sep 10 03:38:57 AM UTC 24 |
| Finished | Sep 10 03:51:17 AM UTC 24 |
| Peak memory | 640124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800112940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.3800112940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3088549318 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 3920469896 ps |
| CPU time | 706.84 seconds |
| Started | Sep 10 03:40:03 AM UTC 24 |
| Finished | Sep 10 03:52:00 AM UTC 24 |
| Peak memory | 636044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088549318 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_alt_clk_freq.3088549318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3140208027 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 14368806908 ps |
| CPU time | 1886.94 seconds |
| Started | Sep 10 03:40:04 AM UTC 24 |
| Finished | Sep 10 04:11:57 AM UTC 24 |
| Peak memory | 636256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140208027 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3140208027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx1.995103309 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 4733046392 ps |
| CPU time | 617.33 seconds |
| Started | Sep 10 03:39:00 AM UTC 24 |
| Finished | Sep 10 03:49:26 AM UTC 24 |
| Peak memory | 639932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995103309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.995103309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx2.2760260341 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 4599799788 ps |
| CPU time | 598.51 seconds |
| Started | Sep 10 03:38:57 AM UTC 24 |
| Finished | Sep 10 03:49:04 AM UTC 24 |
| Peak memory | 640116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760260341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.2760260341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx3.299077081 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 3779810480 ps |
| CPU time | 684.71 seconds |
| Started | Sep 10 03:38:55 AM UTC 24 |
| Finished | Sep 10 03:50:29 AM UTC 24 |
| Peak memory | 640092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299077081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.299077081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.1949799202 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 2389734701 ps |
| CPU time | 160.57 seconds |
| Started | Sep 10 03:42:14 AM UTC 24 |
| Finished | Sep 10 03:44:58 AM UTC 24 |
| Peak memory | 639852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949799202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.1949799202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_prod.1033466419 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 11646861047 ps |
| CPU time | 1407.71 seconds |
| Started | Sep 10 03:42:45 AM UTC 24 |
| Finished | Sep 10 04:06:31 AM UTC 24 |
| Peak memory | 640632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033466419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.1033466419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_rma.3217819781 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 3180434880 ps |
| CPU time | 197.28 seconds |
| Started | Sep 10 03:42:37 AM UTC 24 |
| Finished | Sep 10 03:45:57 AM UTC 24 |
| Peak memory | 650864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217819781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 3.chip_tap_straps_rma.3217819781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_testunlock0.1706690631 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 7726113162 ps |
| CPU time | 799.08 seconds |
| Started | Sep 10 03:42:28 AM UTC 24 |
| Finished | Sep 10 03:55:58 AM UTC 24 |
| Peak memory | 642424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706690631 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.1706690631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1757439900 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 4066571592 ps |
| CPU time | 414.53 seconds |
| Started | Sep 10 04:28:12 AM UTC 24 |
| Finished | Sep 10 04:35:13 AM UTC 24 |
| Peak memory | 672396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757439900 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1757439900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.290365968 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 4289056808 ps |
| CPU time | 413 seconds |
| Started | Sep 10 04:30:58 AM UTC 24 |
| Finished | Sep 10 04:37:57 AM UTC 24 |
| Peak memory | 672372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290365968 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_alert_handler_lpg_s leep_mode_alerts.290365968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.116585639 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 4023169960 ps |
| CPU time | 437.25 seconds |
| Started | Sep 10 04:31:02 AM UTC 24 |
| Finished | Sep 10 04:38:27 AM UTC 24 |
| Peak memory | 672340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116585639 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_alert_handler_lpg_s leep_mode_alerts.116585639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1218242198 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 3970929548 ps |
| CPU time | 386.65 seconds |
| Started | Sep 10 04:32:25 AM UTC 24 |
| Finished | Sep 10 04:38:58 AM UTC 24 |
| Peak memory | 672276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218242198 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1218242198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.79201427 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 5346562680 ps |
| CPU time | 512.41 seconds |
| Started | Sep 10 04:31:38 AM UTC 24 |
| Finished | Sep 10 04:40:17 AM UTC 24 |
| Peak memory | 636472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79201427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esca lation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.79201427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2489855683 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 3888023544 ps |
| CPU time | 433.12 seconds |
| Started | Sep 10 04:33:49 AM UTC 24 |
| Finished | Sep 10 04:41:08 AM UTC 24 |
| Peak memory | 672352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489855683 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2489855683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.1372310889 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 5209901800 ps |
| CPU time | 502.47 seconds |
| Started | Sep 10 04:33:46 AM UTC 24 |
| Finished | Sep 10 04:42:16 AM UTC 24 |
| Peak memory | 674224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372310889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.1372310889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1662322456 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 3767208972 ps |
| CPU time | 356.63 seconds |
| Started | Sep 10 03:50:07 AM UTC 24 |
| Finished | Sep 10 03:56:09 AM UTC 24 |
| Peak memory | 672176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662322456 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_alert_handler_lpg_s leep_mode_alerts.1662322456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.3724860682 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 6278932714 ps |
| CPU time | 753.26 seconds |
| Started | Sep 10 03:43:06 AM UTC 24 |
| Finished | Sep 10 03:55:49 AM UTC 24 |
| Peak memory | 674364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724860682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.3724860682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1742646705 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 6948866108 ps |
| CPU time | 379.74 seconds |
| Started | Sep 10 03:49:52 AM UTC 24 |
| Finished | Sep 10 03:56:18 AM UTC 24 |
| Peak memory | 625860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742646705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1742646705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.73568750 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 21043673162 ps |
| CPU time | 5685.87 seconds |
| Started | Sep 10 03:50:50 AM UTC 24 |
| Finished | Sep 10 05:26:49 AM UTC 24 |
| Peak memory | 626728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurren cy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=73568750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 4.chip_sw_csrng_edn_concurrency.73568750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.222306604 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 5688102726 ps |
| CPU time | 774.75 seconds |
| Started | Sep 10 03:43:33 AM UTC 24 |
| Finished | Sep 10 03:56:38 AM UTC 24 |
| Peak memory | 625652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222306604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.222306604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.274697299 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 5370066158 ps |
| CPU time | 618.71 seconds |
| Started | Sep 10 03:49:52 AM UTC 24 |
| Finished | Sep 10 04:00:19 AM UTC 24 |
| Peak memory | 636136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=274697299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 4.chip_sw_lc_ctrl_transition.274697299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.2303381816 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 12574398736 ps |
| CPU time | 2657.5 seconds |
| Started | Sep 10 03:45:53 AM UTC 24 |
| Finished | Sep 10 04:30:44 AM UTC 24 |
| Peak memory | 635896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303381816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.2303381816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx.1898496262 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 4554503688 ps |
| CPU time | 596.3 seconds |
| Started | Sep 10 03:44:14 AM UTC 24 |
| Finished | Sep 10 03:54:19 AM UTC 24 |
| Peak memory | 640056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898496262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.1898496262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1792565464 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 3149357765 ps |
| CPU time | 544.52 seconds |
| Started | Sep 10 03:46:41 AM UTC 24 |
| Finished | Sep 10 03:55:53 AM UTC 24 |
| Peak memory | 635960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792565464 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_alt_clk_freq.1792565464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.195482227 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 8720100183 ps |
| CPU time | 1153.66 seconds |
| Started | Sep 10 03:47:11 AM UTC 24 |
| Finished | Sep 10 04:06:41 AM UTC 24 |
| Peak memory | 636196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195482227 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.195482227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx1.242008142 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 4973272180 ps |
| CPU time | 649.33 seconds |
| Started | Sep 10 03:44:28 AM UTC 24 |
| Finished | Sep 10 03:55:26 AM UTC 24 |
| Peak memory | 639924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242008142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.242008142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx2.1078819142 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 4101581072 ps |
| CPU time | 593.59 seconds |
| Started | Sep 10 03:44:56 AM UTC 24 |
| Finished | Sep 10 03:54:58 AM UTC 24 |
| Peak memory | 639936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078819142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.1078819142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx3.1682861112 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 4172308802 ps |
| CPU time | 662.58 seconds |
| Started | Sep 10 03:45:53 AM UTC 24 |
| Finished | Sep 10 03:57:04 AM UTC 24 |
| Peak memory | 640016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682861112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.1682861112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.334706292 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 6722664929 ps |
| CPU time | 611.84 seconds |
| Started | Sep 10 03:51:03 AM UTC 24 |
| Finished | Sep 10 04:01:23 AM UTC 24 |
| Peak memory | 642484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334706292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.334706292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.1852684228 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 6979142677 ps |
| CPU time | 650.1 seconds |
| Started | Sep 10 03:52:41 AM UTC 24 |
| Finished | Sep 10 04:03:40 AM UTC 24 |
| Peak memory | 650616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852684228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.1852684228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_rma.257343370 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 5193483765 ps |
| CPU time | 411.99 seconds |
| Started | Sep 10 03:51:58 AM UTC 24 |
| Finished | Sep 10 03:58:55 AM UTC 24 |
| Peak memory | 642428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257343370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 4.chip_tap_straps_rma.257343370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_testunlock0.2184876501 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 9899896529 ps |
| CPU time | 956.31 seconds |
| Started | Sep 10 03:51:57 AM UTC 24 |
| Finished | Sep 10 04:08:06 AM UTC 24 |
| Peak memory | 652736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184876501 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.2184876501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3792169453 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 4506482120 ps |
| CPU time | 434.1 seconds |
| Started | Sep 10 04:34:35 AM UTC 24 |
| Finished | Sep 10 04:41:56 AM UTC 24 |
| Peak memory | 672452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792169453 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3792169453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.881870674 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 3971262376 ps |
| CPU time | 334.98 seconds |
| Started | Sep 10 04:34:40 AM UTC 24 |
| Finished | Sep 10 04:40:20 AM UTC 24 |
| Peak memory | 672340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881870674 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_alert_handler_lpg_s leep_mode_alerts.881870674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.652513184 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 5313866084 ps |
| CPU time | 530.24 seconds |
| Started | Sep 10 04:34:40 AM UTC 24 |
| Finished | Sep 10 04:43:37 AM UTC 24 |
| Peak memory | 674420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652513184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.652513184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.4105621232 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 4001214620 ps |
| CPU time | 383.01 seconds |
| Started | Sep 10 04:38:20 AM UTC 24 |
| Finished | Sep 10 04:44:49 AM UTC 24 |
| Peak memory | 672424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105621232 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_alert_handler_lpg_ sleep_mode_alerts.4105621232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.2145819107 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 5275039956 ps |
| CPU time | 555.47 seconds |
| Started | Sep 10 04:34:41 AM UTC 24 |
| Finished | Sep 10 04:44:04 AM UTC 24 |
| Peak memory | 674472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145819107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.2145819107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.2704405522 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 4623241376 ps |
| CPU time | 529.76 seconds |
| Started | Sep 10 04:38:20 AM UTC 24 |
| Finished | Sep 10 04:47:17 AM UTC 24 |
| Peak memory | 674452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704405522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.2704405522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.68375515 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 3427525216 ps |
| CPU time | 331.23 seconds |
| Started | Sep 10 04:37:39 AM UTC 24 |
| Finished | Sep 10 04:43:16 AM UTC 24 |
| Peak memory | 672436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68375515 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_alert_handler_lpg_sl eep_mode_alerts.68375515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2509566923 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 3722102424 ps |
| CPU time | 344.2 seconds |
| Started | Sep 10 04:37:50 AM UTC 24 |
| Finished | Sep 10 04:43:39 AM UTC 24 |
| Peak memory | 636356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509566923 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2509566923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3924157103 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 4205723502 ps |
| CPU time | 365.39 seconds |
| Started | Sep 10 04:37:45 AM UTC 24 |
| Finished | Sep 10 04:43:57 AM UTC 24 |
| Peak memory | 672256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924157103 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3924157103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.166094482 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 5524236512 ps |
| CPU time | 461.28 seconds |
| Started | Sep 10 04:38:20 AM UTC 24 |
| Finished | Sep 10 04:46:08 AM UTC 24 |
| Peak memory | 636408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166094482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.166094482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.154156874 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 3558266010 ps |
| CPU time | 400.16 seconds |
| Started | Sep 10 04:42:02 AM UTC 24 |
| Finished | Sep 10 04:48:48 AM UTC 24 |
| Peak memory | 672360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154156874 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_alert_handler_lpg_s leep_mode_alerts.154156874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.2323931294 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 6307772100 ps |
| CPU time | 477.93 seconds |
| Started | Sep 10 04:38:23 AM UTC 24 |
| Finished | Sep 10 04:46:28 AM UTC 24 |
| Peak memory | 674456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323931294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.2323931294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2697813023 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 3585711278 ps |
| CPU time | 454.71 seconds |
| Started | Sep 10 03:54:45 AM UTC 24 |
| Finished | Sep 10 04:02:26 AM UTC 24 |
| Peak memory | 672172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697813023 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_alert_handler_lpg_s leep_mode_alerts.2697813023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.2779752553 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 22107270356 ps |
| CPU time | 5503.45 seconds |
| Started | Sep 10 03:55:01 AM UTC 24 |
| Finished | Sep 10 05:27:51 AM UTC 24 |
| Peak memory | 628780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurren cy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2779752553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 5.chip_sw_csrng_edn_concurrency.2779752553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.3335658134 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 5791524310 ps |
| CPU time | 699.63 seconds |
| Started | Sep 10 03:52:58 AM UTC 24 |
| Finished | Sep 10 04:04:48 AM UTC 24 |
| Peak memory | 625948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335658134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.3335658134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_lc_ctrl_transition.412662625 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 12366972005 ps |
| CPU time | 971.77 seconds |
| Started | Sep 10 03:54:29 AM UTC 24 |
| Finished | Sep 10 04:10:55 AM UTC 24 |
| Peak memory | 638188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=412662625 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.chip_sw_lc_ctrl_transition.412662625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.1343974441 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 7920926890 ps |
| CPU time | 1371.57 seconds |
| Started | Sep 10 03:53:42 AM UTC 24 |
| Finished | Sep 10 04:16:51 AM UTC 24 |
| Peak memory | 635960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343974441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.1343974441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.289575984 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 3635550000 ps |
| CPU time | 379.93 seconds |
| Started | Sep 10 04:41:34 AM UTC 24 |
| Finished | Sep 10 04:47:59 AM UTC 24 |
| Peak memory | 672372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289575984 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_alert_handler_lpg_s leep_mode_alerts.289575984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.798430061 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 5073254510 ps |
| CPU time | 473.61 seconds |
| Started | Sep 10 04:41:32 AM UTC 24 |
| Finished | Sep 10 04:49:32 AM UTC 24 |
| Peak memory | 674360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798430061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.798430061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2557353061 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 3793631138 ps |
| CPU time | 347.27 seconds |
| Started | Sep 10 04:42:05 AM UTC 24 |
| Finished | Sep 10 04:47:58 AM UTC 24 |
| Peak memory | 672408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557353061 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2557353061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.1954156302 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 6520053912 ps |
| CPU time | 606.67 seconds |
| Started | Sep 10 04:41:32 AM UTC 24 |
| Finished | Sep 10 04:51:47 AM UTC 24 |
| Peak memory | 674312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954156302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.1954156302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2754442697 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 3704745272 ps |
| CPU time | 296.48 seconds |
| Started | Sep 10 04:42:00 AM UTC 24 |
| Finished | Sep 10 04:47:01 AM UTC 24 |
| Peak memory | 672260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754442697 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2754442697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.2976614894 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 4780557490 ps |
| CPU time | 448.57 seconds |
| Started | Sep 10 04:40:59 AM UTC 24 |
| Finished | Sep 10 04:48:34 AM UTC 24 |
| Peak memory | 674476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976614894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.2976614894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1625814646 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 3591492010 ps |
| CPU time | 302.23 seconds |
| Started | Sep 10 04:42:01 AM UTC 24 |
| Finished | Sep 10 04:47:07 AM UTC 24 |
| Peak memory | 672184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625814646 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1625814646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1567008479 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 4057891128 ps |
| CPU time | 326.85 seconds |
| Started | Sep 10 04:42:27 AM UTC 24 |
| Finished | Sep 10 04:47:59 AM UTC 24 |
| Peak memory | 672412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567008479 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1567008479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_all_escalation_resets.2546948912 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 4874862228 ps |
| CPU time | 407.39 seconds |
| Started | Sep 10 04:41:22 AM UTC 24 |
| Finished | Sep 10 04:48:15 AM UTC 24 |
| Peak memory | 636224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546948912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.2546948912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.319864650 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 3556674368 ps |
| CPU time | 276.2 seconds |
| Started | Sep 10 04:43:42 AM UTC 24 |
| Finished | Sep 10 04:48:22 AM UTC 24 |
| Peak memory | 672412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319864650 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_alert_handler_lpg_s leep_mode_alerts.319864650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2240217239 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 3497057038 ps |
| CPU time | 265.79 seconds |
| Started | Sep 10 04:43:31 AM UTC 24 |
| Finished | Sep 10 04:48:01 AM UTC 24 |
| Peak memory | 672408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240217239 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2240217239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.4224343995 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 5965576588 ps |
| CPU time | 568.09 seconds |
| Started | Sep 10 04:44:55 AM UTC 24 |
| Finished | Sep 10 04:54:31 AM UTC 24 |
| Peak memory | 674472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224343995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.4224343995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2231694823 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 3723571836 ps |
| CPU time | 313.96 seconds |
| Started | Sep 10 04:46:09 AM UTC 24 |
| Finished | Sep 10 04:51:28 AM UTC 24 |
| Peak memory | 672260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231694823 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2231694823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.3602949699 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 12613212356 ps |
| CPU time | 3136.51 seconds |
| Started | Sep 10 03:57:34 AM UTC 24 |
| Finished | Sep 10 04:50:31 AM UTC 24 |
| Peak memory | 625784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurren cy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3602949699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 6.chip_sw_csrng_edn_concurrency.3602949699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.1123906747 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 11520933661 ps |
| CPU time | 1178.37 seconds |
| Started | Sep 10 03:57:34 AM UTC 24 |
| Finished | Sep 10 04:17:27 AM UTC 24 |
| Peak memory | 636148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1123906747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 6.chip_sw_lc_ctrl_transition.1123906747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.771811419 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 7782338328 ps |
| CPU time | 1524.5 seconds |
| Started | Sep 10 03:56:09 AM UTC 24 |
| Finished | Sep 10 04:21:53 AM UTC 24 |
| Peak memory | 635900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771811419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.771811419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2937107168 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 3408247914 ps |
| CPU time | 255.83 seconds |
| Started | Sep 10 04:47:39 AM UTC 24 |
| Finished | Sep 10 04:51:59 AM UTC 24 |
| Peak memory | 672344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937107168 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2937107168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.3780779488 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 4420502892 ps |
| CPU time | 516.21 seconds |
| Started | Sep 10 04:47:36 AM UTC 24 |
| Finished | Sep 10 04:56:20 AM UTC 24 |
| Peak memory | 674372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780779488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.3780779488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1645653213 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 3076205474 ps |
| CPU time | 305.11 seconds |
| Started | Sep 10 04:46:49 AM UTC 24 |
| Finished | Sep 10 04:51:59 AM UTC 24 |
| Peak memory | 672472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645653213 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1645653213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_all_escalation_resets.1312984399 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 6389823052 ps |
| CPU time | 596.58 seconds |
| Started | Sep 10 04:45:49 AM UTC 24 |
| Finished | Sep 10 04:55:53 AM UTC 24 |
| Peak memory | 674460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312984399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.1312984399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.56738722 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 3589468600 ps |
| CPU time | 361.73 seconds |
| Started | Sep 10 04:47:16 AM UTC 24 |
| Finished | Sep 10 04:53:24 AM UTC 24 |
| Peak memory | 672368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56738722 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_alert_handler_lpg_sl eep_mode_alerts.56738722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_all_escalation_resets.4135131117 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 5189942332 ps |
| CPU time | 460.36 seconds |
| Started | Sep 10 04:50:30 AM UTC 24 |
| Finished | Sep 10 04:58:17 AM UTC 24 |
| Peak memory | 674228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135131117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.4135131117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1064311043 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 3665700288 ps |
| CPU time | 417.92 seconds |
| Started | Sep 10 04:47:07 AM UTC 24 |
| Finished | Sep 10 04:54:11 AM UTC 24 |
| Peak memory | 672184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064311043 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1064311043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.4271329800 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 5378872564 ps |
| CPU time | 613.48 seconds |
| Started | Sep 10 04:47:34 AM UTC 24 |
| Finished | Sep 10 04:57:57 AM UTC 24 |
| Peak memory | 674448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271329800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.4271329800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3505091048 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 3758376792 ps |
| CPU time | 393.92 seconds |
| Started | Sep 10 04:47:35 AM UTC 24 |
| Finished | Sep 10 04:54:15 AM UTC 24 |
| Peak memory | 672428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505091048 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3505091048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1060765591 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 3577681834 ps |
| CPU time | 309.68 seconds |
| Started | Sep 10 04:46:07 AM UTC 24 |
| Finished | Sep 10 04:51:21 AM UTC 24 |
| Peak memory | 672380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060765591 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1060765591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.3337889583 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 5913952080 ps |
| CPU time | 583.96 seconds |
| Started | Sep 10 04:47:23 AM UTC 24 |
| Finished | Sep 10 04:57:15 AM UTC 24 |
| Peak memory | 674344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337889583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.3337889583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.2656901130 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 5033173880 ps |
| CPU time | 481.66 seconds |
| Started | Sep 10 04:47:04 AM UTC 24 |
| Finished | Sep 10 04:55:13 AM UTC 24 |
| Peak memory | 674428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656901130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.2656901130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3531946950 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 3264030720 ps |
| CPU time | 342.82 seconds |
| Started | Sep 10 04:46:58 AM UTC 24 |
| Finished | Sep 10 04:52:46 AM UTC 24 |
| Peak memory | 672252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531946950 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3531946950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.1050056570 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 6393511688 ps |
| CPU time | 573.92 seconds |
| Started | Sep 10 04:47:17 AM UTC 24 |
| Finished | Sep 10 04:56:59 AM UTC 24 |
| Peak memory | 674228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050056570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.1050056570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1138957307 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 4213356896 ps |
| CPU time | 469.77 seconds |
| Started | Sep 10 03:57:53 AM UTC 24 |
| Finished | Sep 10 04:05:49 AM UTC 24 |
| Peak memory | 672192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138957307 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_alert_handler_lpg_s leep_mode_alerts.1138957307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.929805759 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 4654570474 ps |
| CPU time | 559.73 seconds |
| Started | Sep 10 03:57:48 AM UTC 24 |
| Finished | Sep 10 04:07:16 AM UTC 24 |
| Peak memory | 674396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929805759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.929805759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.3558892750 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 8971046064 ps |
| CPU time | 2202.65 seconds |
| Started | Sep 10 03:58:41 AM UTC 24 |
| Finished | Sep 10 04:35:51 AM UTC 24 |
| Peak memory | 625784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurren cy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3558892750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 7.chip_sw_csrng_edn_concurrency.3558892750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_lc_ctrl_transition.4217090474 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 4420621746 ps |
| CPU time | 471.57 seconds |
| Started | Sep 10 03:57:50 AM UTC 24 |
| Finished | Sep 10 04:05:48 AM UTC 24 |
| Peak memory | 636044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=4217090474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 7.chip_sw_lc_ctrl_transition.4217090474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.3249952600 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 7946685960 ps |
| CPU time | 1528.14 seconds |
| Started | Sep 10 03:57:29 AM UTC 24 |
| Finished | Sep 10 04:23:18 AM UTC 24 |
| Peak memory | 635896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249952600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.3249952600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2151273785 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 3872361000 ps |
| CPU time | 341.54 seconds |
| Started | Sep 10 04:48:53 AM UTC 24 |
| Finished | Sep 10 04:54:40 AM UTC 24 |
| Peak memory | 672412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151273785 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2151273785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.757004471 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 3369884738 ps |
| CPU time | 367.78 seconds |
| Started | Sep 10 04:49:44 AM UTC 24 |
| Finished | Sep 10 04:55:58 AM UTC 24 |
| Peak memory | 672424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757004471 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_alert_handler_lpg_s leep_mode_alerts.757004471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.4192057064 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 5489371662 ps |
| CPU time | 540.52 seconds |
| Started | Sep 10 04:48:08 AM UTC 24 |
| Finished | Sep 10 04:57:15 AM UTC 24 |
| Peak memory | 674380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192057064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.4192057064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1013850682 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 3774959568 ps |
| CPU time | 336.63 seconds |
| Started | Sep 10 04:51:08 AM UTC 24 |
| Finished | Sep 10 04:56:49 AM UTC 24 |
| Peak memory | 672260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013850682 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1013850682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.1010350628 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 4559728314 ps |
| CPU time | 612.95 seconds |
| Started | Sep 10 04:51:22 AM UTC 24 |
| Finished | Sep 10 05:01:43 AM UTC 24 |
| Peak memory | 674300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010350628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.1010350628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.765556015 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 4257598140 ps |
| CPU time | 424.03 seconds |
| Started | Sep 10 04:50:19 AM UTC 24 |
| Finished | Sep 10 04:57:29 AM UTC 24 |
| Peak memory | 672420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765556015 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_alert_handler_lpg_s leep_mode_alerts.765556015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.1739193014 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 5986930868 ps |
| CPU time | 557.03 seconds |
| Started | Sep 10 04:51:07 AM UTC 24 |
| Finished | Sep 10 05:00:32 AM UTC 24 |
| Peak memory | 674240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739193014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.1739193014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.567333370 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 4145479016 ps |
| CPU time | 400.76 seconds |
| Started | Sep 10 04:50:48 AM UTC 24 |
| Finished | Sep 10 04:57:35 AM UTC 24 |
| Peak memory | 672184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567333370 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_alert_handler_lpg_s leep_mode_alerts.567333370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.110025080 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 5809889816 ps |
| CPU time | 636.76 seconds |
| Started | Sep 10 04:52:00 AM UTC 24 |
| Finished | Sep 10 05:02:46 AM UTC 24 |
| Peak memory | 674852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110025080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.110025080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.3048899070 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 5458388200 ps |
| CPU time | 563.18 seconds |
| Started | Sep 10 04:52:00 AM UTC 24 |
| Finished | Sep 10 05:01:31 AM UTC 24 |
| Peak memory | 674408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048899070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.3048899070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3477699619 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 3658897348 ps |
| CPU time | 333.87 seconds |
| Started | Sep 10 04:50:32 AM UTC 24 |
| Finished | Sep 10 04:56:11 AM UTC 24 |
| Peak memory | 672332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477699619 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3477699619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.1280081971 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 5787517106 ps |
| CPU time | 530.67 seconds |
| Started | Sep 10 04:50:51 AM UTC 24 |
| Finished | Sep 10 04:59:49 AM UTC 24 |
| Peak memory | 674300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280081971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.1280081971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2583119080 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 4232051360 ps |
| CPU time | 367.58 seconds |
| Started | Sep 10 04:50:35 AM UTC 24 |
| Finished | Sep 10 04:56:48 AM UTC 24 |
| Peak memory | 672324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583119080 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2583119080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3532478056 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 4063395910 ps |
| CPU time | 390.57 seconds |
| Started | Sep 10 04:50:36 AM UTC 24 |
| Finished | Sep 10 04:57:12 AM UTC 24 |
| Peak memory | 672488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532478056 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3532478056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.720028434 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 3849424660 ps |
| CPU time | 297.82 seconds |
| Started | Sep 10 04:01:12 AM UTC 24 |
| Finished | Sep 10 04:06:15 AM UTC 24 |
| Peak memory | 672324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720028434 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_alert_handler_lpg_sl eep_mode_alerts.720028434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.3046641527 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 5137552558 ps |
| CPU time | 669.52 seconds |
| Started | Sep 10 03:59:40 AM UTC 24 |
| Finished | Sep 10 04:10:58 AM UTC 24 |
| Peak memory | 674292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046641527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.3046641527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.1029982545 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 22288719712 ps |
| CPU time | 6159.77 seconds |
| Started | Sep 10 04:01:13 AM UTC 24 |
| Finished | Sep 10 05:45:08 AM UTC 24 |
| Peak memory | 628920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurren cy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1029982545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 8.chip_sw_csrng_edn_concurrency.1029982545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.499030964 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 13080954606 ps |
| CPU time | 1205.23 seconds |
| Started | Sep 10 04:00:35 AM UTC 24 |
| Finished | Sep 10 04:20:57 AM UTC 24 |
| Peak memory | 636148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=499030964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 8.chip_sw_lc_ctrl_transition.499030964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.807503050 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 8275613364 ps |
| CPU time | 1378.27 seconds |
| Started | Sep 10 04:00:13 AM UTC 24 |
| Finished | Sep 10 04:23:29 AM UTC 24 |
| Peak memory | 636212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807503050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.807503050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.4033460403 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 4146038968 ps |
| CPU time | 410.9 seconds |
| Started | Sep 10 04:51:08 AM UTC 24 |
| Finished | Sep 10 04:58:05 AM UTC 24 |
| Peak memory | 672336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033460403 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_alert_handler_lpg_ sleep_mode_alerts.4033460403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_all_escalation_resets.3012594122 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 5055904870 ps |
| CPU time | 449.54 seconds |
| Started | Sep 10 04:52:02 AM UTC 24 |
| Finished | Sep 10 04:59:37 AM UTC 24 |
| Peak memory | 674360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012594122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.3012594122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2365269894 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 4072023044 ps |
| CPU time | 441.27 seconds |
| Started | Sep 10 04:52:07 AM UTC 24 |
| Finished | Sep 10 04:59:35 AM UTC 24 |
| Peak memory | 672292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365269894 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2365269894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.1260286631 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 4809873600 ps |
| CPU time | 668.9 seconds |
| Started | Sep 10 04:52:01 AM UTC 24 |
| Finished | Sep 10 05:03:20 AM UTC 24 |
| Peak memory | 675148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260286631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.1260286631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2092256232 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 3806645920 ps |
| CPU time | 351.98 seconds |
| Started | Sep 10 04:52:19 AM UTC 24 |
| Finished | Sep 10 04:58:16 AM UTC 24 |
| Peak memory | 672396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092256232 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2092256232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.2604866908 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 5392806620 ps |
| CPU time | 546.93 seconds |
| Started | Sep 10 04:52:32 AM UTC 24 |
| Finished | Sep 10 05:01:47 AM UTC 24 |
| Peak memory | 672320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604866908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.2604866908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3046906574 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 4154231348 ps |
| CPU time | 385.82 seconds |
| Started | Sep 10 04:53:03 AM UTC 24 |
| Finished | Sep 10 04:59:35 AM UTC 24 |
| Peak memory | 672416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046906574 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3046906574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.1407571519 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 5669838980 ps |
| CPU time | 501.32 seconds |
| Started | Sep 10 04:53:07 AM UTC 24 |
| Finished | Sep 10 05:01:35 AM UTC 24 |
| Peak memory | 674224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407571519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.1407571519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3133358783 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 3799824704 ps |
| CPU time | 380.85 seconds |
| Started | Sep 10 04:53:04 AM UTC 24 |
| Finished | Sep 10 04:59:30 AM UTC 24 |
| Peak memory | 672432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133358783 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3133358783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.2973071743 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 5815456040 ps |
| CPU time | 626.17 seconds |
| Started | Sep 10 04:53:09 AM UTC 24 |
| Finished | Sep 10 05:03:43 AM UTC 24 |
| Peak memory | 674424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973071743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.2973071743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2381114443 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 3348772218 ps |
| CPU time | 404.61 seconds |
| Started | Sep 10 04:53:27 AM UTC 24 |
| Finished | Sep 10 05:00:18 AM UTC 24 |
| Peak memory | 672364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381114443 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2381114443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.935606853 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 4265168200 ps |
| CPU time | 450.12 seconds |
| Started | Sep 10 04:54:48 AM UTC 24 |
| Finished | Sep 10 05:02:25 AM UTC 24 |
| Peak memory | 672256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935606853 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_alert_handler_lpg_s leep_mode_alerts.935606853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.9600031 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 5028487264 ps |
| CPU time | 697.25 seconds |
| Started | Sep 10 04:54:08 AM UTC 24 |
| Finished | Sep 10 05:05:55 AM UTC 24 |
| Peak memory | 675084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9600031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escal ation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.9600031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3588819841 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 3027444168 ps |
| CPU time | 352.27 seconds |
| Started | Sep 10 04:56:05 AM UTC 24 |
| Finished | Sep 10 05:02:03 AM UTC 24 |
| Peak memory | 672484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588819841 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3588819841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.978948414 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 5930862548 ps |
| CPU time | 487.22 seconds |
| Started | Sep 10 04:55:38 AM UTC 24 |
| Finished | Sep 10 05:03:51 AM UTC 24 |
| Peak memory | 674480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978948414 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.978948414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1052985040 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 3801409690 ps |
| CPU time | 400.16 seconds |
| Started | Sep 10 04:56:02 AM UTC 24 |
| Finished | Sep 10 05:02:48 AM UTC 24 |
| Peak memory | 672380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052985040 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1052985040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3249462512 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 3726176120 ps |
| CPU time | 386.62 seconds |
| Started | Sep 10 04:58:03 AM UTC 24 |
| Finished | Sep 10 05:04:35 AM UTC 24 |
| Peak memory | 672256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249462512 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3249462512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_all_escalation_resets.3503521428 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 4906952074 ps |
| CPU time | 634.7 seconds |
| Started | Sep 10 04:57:39 AM UTC 24 |
| Finished | Sep 10 05:08:23 AM UTC 24 |
| Peak memory | 674228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503521428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.3503521428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4021740196 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 3890851488 ps |
| CPU time | 379.13 seconds |
| Started | Sep 10 04:04:22 AM UTC 24 |
| Finished | Sep 10 04:10:48 AM UTC 24 |
| Peak memory | 672268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021740196 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_alert_handler_lpg_s leep_mode_alerts.4021740196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.3433862898 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4326293026 ps |
| CPU time | 558.26 seconds |
| Started | Sep 10 04:02:06 AM UTC 24 |
| Finished | Sep 10 04:11:32 AM UTC 24 |
| Peak memory | 674300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433862898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.3433862898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.3671959885 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 17934802410 ps |
| CPU time | 4718.49 seconds |
| Started | Sep 10 04:04:57 AM UTC 24 |
| Finished | Sep 10 05:24:34 AM UTC 24 |
| Peak memory | 628784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurren cy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3671959885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 9.chip_sw_csrng_edn_concurrency.3671959885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_lc_ctrl_transition.3882219042 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 5939880472 ps |
| CPU time | 618.07 seconds |
| Started | Sep 10 04:03:05 AM UTC 24 |
| Finished | Sep 10 04:13:32 AM UTC 24 |
| Peak memory | 638196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3882219042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 9.chip_sw_lc_ctrl_transition.3882219042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.1324796524 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 13072864174 ps |
| CPU time | 2649.97 seconds |
| Started | Sep 10 04:02:37 AM UTC 24 |
| Finished | Sep 10 04:47:21 AM UTC 24 |
| Peak memory | 635896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324796524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.1324796524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.921965345 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 4902666548 ps |
| CPU time | 672.86 seconds |
| Started | Sep 10 04:57:39 AM UTC 24 |
| Finished | Sep 10 05:09:02 AM UTC 24 |
| Peak memory | 636788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921965345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.921965345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/91.chip_sw_all_escalation_resets.229265396 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 5303370134 ps |
| CPU time | 779.2 seconds |
| Started | Sep 10 04:58:01 AM UTC 24 |
| Finished | Sep 10 05:11:11 AM UTC 24 |
| Peak memory | 674932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229265396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.229265396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.3849172788 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 6092315512 ps |
| CPU time | 702.81 seconds |
| Started | Sep 10 04:58:06 AM UTC 24 |
| Finished | Sep 10 05:09:58 AM UTC 24 |
| Peak memory | 674476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849172788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.3849172788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.291837231 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 4701390232 ps |
| CPU time | 700.07 seconds |
| Started | Sep 10 04:58:06 AM UTC 24 |
| Finished | Sep 10 05:09:56 AM UTC 24 |
| Peak memory | 674472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291837231 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.291837231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.4011841931 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 4384856480 ps |
| CPU time | 647.24 seconds |
| Started | Sep 10 04:57:57 AM UTC 24 |
| Finished | Sep 10 05:08:54 AM UTC 24 |
| Peak memory | 674396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011841931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.4011841931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.2837070167 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 6161553556 ps |
| CPU time | 803.61 seconds |
| Started | Sep 10 04:58:04 AM UTC 24 |
| Finished | Sep 10 05:11:40 AM UTC 24 |
| Peak memory | 674936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837070167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.2837070167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.4095427504 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 4264833428 ps |
| CPU time | 420.6 seconds |
| Started | Sep 10 04:57:54 AM UTC 24 |
| Finished | Sep 10 05:05:01 AM UTC 24 |
| Peak memory | 672188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095427504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.4095427504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.3281063875 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 5201405760 ps |
| CPU time | 612.76 seconds |
| Started | Sep 10 04:58:09 AM UTC 24 |
| Finished | Sep 10 05:08:30 AM UTC 24 |
| Peak memory | 674224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281063875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.3281063875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.951343477 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 6717525512 ps |
| CPU time | 781.46 seconds |
| Started | Sep 10 04:57:54 AM UTC 24 |
| Finished | Sep 10 05:11:08 AM UTC 24 |
| Peak memory | 675156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951343477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.951343477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.3463429375 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 5040759524 ps |
| CPU time | 524.58 seconds |
| Started | Sep 10 04:58:01 AM UTC 24 |
| Finished | Sep 10 05:06:53 AM UTC 24 |
| Peak memory | 674404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463429375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.3463429375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1261812808 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 5436225298 ps |
| CPU time | 302.17 seconds |
| Started | Sep 10 04:57:23 AM UTC 24 |
| Finished | Sep 10 05:02:29 AM UTC 24 |
| Peak memory | 666224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261812 808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 1.chip_ padctrl_attributes.1261812808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3761447309 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 4150944288 ps |
| CPU time | 297.2 seconds |
| Started | Sep 10 04:57:31 AM UTC 24 |
| Finished | Sep 10 05:02:32 AM UTC 24 |
| Peak memory | 672516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761447 309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 2.chip_ padctrl_attributes.3761447309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3144087861 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 6286045685 ps |
| CPU time | 356.92 seconds |
| Started | Sep 10 04:57:36 AM UTC 24 |
| Finished | Sep 10 05:03:39 AM UTC 24 |
| Peak memory | 672380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144087 861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 4.chip_ padctrl_attributes.3144087861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/4.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.4144977578 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 5822172632 ps |
| CPU time | 288.37 seconds |
| Started | Sep 10 04:57:38 AM UTC 24 |
| Finished | Sep 10 05:02:31 AM UTC 24 |
| Peak memory | 666288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144977 578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 5.chip_ padctrl_attributes.4144977578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/5.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1154731506 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3965641920 ps |
| CPU time | 281.28 seconds |
| Started | Sep 10 04:57:46 AM UTC 24 |
| Finished | Sep 10 05:02:31 AM UTC 24 |
| Peak memory | 656128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154731 506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 6.chip_ padctrl_attributes.1154731506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/6.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.30774363 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 5560367908 ps |
| CPU time | 336.79 seconds |
| Started | Sep 10 04:57:50 AM UTC 24 |
| Finished | Sep 10 05:03:32 AM UTC 24 |
| Peak memory | 672512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077436 3 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 7.chip_pa dctrl_attributes.30774363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/7.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.222195295 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 3717351035 ps |
| CPU time | 318.88 seconds |
| Started | Sep 10 04:57:57 AM UTC 24 |
| Finished | Sep 10 05:03:22 AM UTC 24 |
| Peak memory | 666292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221952 95 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 8.chip_p adctrl_attributes.222195295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/8.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1405085081 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 5447514506 ps |
| CPU time | 345.79 seconds |
| Started | Sep 10 04:58:23 AM UTC 24 |
| Finished | Sep 10 05:04:15 AM UTC 24 |
| Peak memory | 655984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405085 081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 9.chip_ padctrl_attributes.1405085081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/9.chip_padctrl_attributes/latest |
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