Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.17 95.52 94.02 95.39 94.99 97.53 99.59


Total test records in report: 2926
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html | tests61.html

T431 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.3601949317 Sep 10 02:03:57 AM UTC 24 Sep 10 02:14:34 AM UTC 24 5668829208 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3524291333 Sep 10 01:42:45 AM UTC 24 Sep 10 02:14:55 AM UTC 24 26734014720 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.149446239 Sep 10 02:07:38 AM UTC 24 Sep 10 02:15:01 AM UTC 24 3984883459 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.2419408 Sep 10 02:04:00 AM UTC 24 Sep 10 02:15:57 AM UTC 24 4842689304 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1943736779 Sep 10 02:03:59 AM UTC 24 Sep 10 02:16:07 AM UTC 24 5930876400 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_tpm.965484254 Sep 10 02:09:26 AM UTC 24 Sep 10 02:16:34 AM UTC 24 2830275084 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx.3786266827 Sep 10 02:07:50 AM UTC 24 Sep 10 02:16:38 AM UTC 24 3658151570 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.1524088356 Sep 10 02:10:30 AM UTC 24 Sep 10 02:16:39 AM UTC 24 3427912376 ps
T1073 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx3.3710756901 Sep 10 02:07:24 AM UTC 24 Sep 10 02:17:22 AM UTC 24 4532942920 ps
T1074 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.4218502740 Sep 10 02:07:54 AM UTC 24 Sep 10 02:17:29 AM UTC 24 4936911196 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_virus.1489639097 Sep 10 01:55:29 AM UTC 24 Sep 10 02:17:38 AM UTC 24 5894712676 ps
T1075 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx2.3518075757 Sep 10 02:07:36 AM UTC 24 Sep 10 02:17:49 AM UTC 24 4565458452 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.627594914 Sep 10 02:11:32 AM UTC 24 Sep 10 02:18:16 AM UTC 24 3841272888 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx1.751376027 Sep 10 02:06:44 AM UTC 24 Sep 10 02:18:52 AM UTC 24 4550870850 ps
T1076 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.2900648009 Sep 10 02:09:27 AM UTC 24 Sep 10 02:19:42 AM UTC 24 3925464108 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.1506519882 Sep 10 02:11:32 AM UTC 24 Sep 10 02:20:25 AM UTC 24 4072741750 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.237590268 Sep 10 02:08:30 AM UTC 24 Sep 10 02:20:55 AM UTC 24 4789819240 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through_collision.3216703901 Sep 10 02:11:35 AM UTC 24 Sep 10 02:21:01 AM UTC 24 3479195851 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx.3467135233 Sep 10 02:07:57 AM UTC 24 Sep 10 02:21:06 AM UTC 24 5120265400 ps
T1077 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2681468789 Sep 10 01:12:55 AM UTC 24 Sep 10 02:21:54 AM UTC 24 17243708532 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3856586274 Sep 10 02:08:51 AM UTC 24 Sep 10 02:22:53 AM UTC 24 5335316660 ps
T1078 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3275844698 Sep 10 01:12:55 AM UTC 24 Sep 10 02:23:24 AM UTC 24 18128271317 ps
T1079 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.176043039 Sep 10 02:18:35 AM UTC 24 Sep 10 02:23:28 AM UTC 24 2909947524 ps
T1080 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1082516345 Sep 10 02:17:32 AM UTC 24 Sep 10 02:23:49 AM UTC 24 3019759426 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.4214807360 Sep 10 02:20:22 AM UTC 24 Sep 10 02:23:53 AM UTC 24 2093324473 ps
T1081 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_entropy.2299660040 Sep 10 02:18:35 AM UTC 24 Sep 10 02:24:00 AM UTC 24 3128478840 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1363461173 Sep 10 02:15:49 AM UTC 24 Sep 10 02:25:22 AM UTC 24 3922642118 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through.626413832 Sep 10 02:11:36 AM UTC 24 Sep 10 02:25:40 AM UTC 24 6991738037 ps
T1082 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2766835874 Sep 10 02:21:06 AM UTC 24 Sep 10 02:26:08 AM UTC 24 3048394460 ps
T1083 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pwm_pulses.3499912908 Sep 10 02:06:45 AM UTC 24 Sep 10 02:26:25 AM UTC 24 9388119236 ps
T1084 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3591147131 Sep 10 02:21:55 AM UTC 24 Sep 10 02:26:26 AM UTC 24 2947837781 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init_reduced_freq.1507377546 Sep 10 01:49:55 AM UTC 24 Sep 10 02:26:37 AM UTC 24 24079374672 ps
T1085 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.139565559 Sep 10 02:24:15 AM UTC 24 Sep 10 02:27:04 AM UTC 24 2819537422 ps
T1086 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops.4073652452 Sep 10 02:15:17 AM UTC 24 Sep 10 02:27:16 AM UTC 24 3976036956 ps
T1087 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.737175522 Sep 10 02:24:15 AM UTC 24 Sep 10 02:27:18 AM UTC 24 2895590743 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2375034923 Sep 10 02:15:49 AM UTC 24 Sep 10 02:27:26 AM UTC 24 5677766615 ps
T1088 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_self_hash.1750917296 Sep 10 12:14:34 AM UTC 24 Sep 10 02:27:39 AM UTC 24 26924178072 ps
T1089 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2868676197 Sep 10 02:18:40 AM UTC 24 Sep 10 02:30:19 AM UTC 24 4497386952 ps
T1090 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_req.9749519 Sep 10 02:24:53 AM UTC 24 Sep 10 02:30:37 AM UTC 24 4253888560 ps
T1091 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_rst.3648834284 Sep 10 02:26:03 AM UTC 24 Sep 10 02:31:02 AM UTC 24 3306225296 ps
T1092 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access.3479612364 Sep 10 02:16:51 AM UTC 24 Sep 10 02:31:59 AM UTC 24 5761882500 ps
T1093 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_rand_baudrate.4173902007 Sep 10 02:07:58 AM UTC 24 Sep 10 02:32:10 AM UTC 24 8526459320 ps
T1094 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2889074212 Sep 10 02:17:32 AM UTC 24 Sep 10 02:33:21 AM UTC 24 6016483923 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.687131276 Sep 10 12:53:20 AM UTC 24 Sep 10 02:33:45 AM UTC 24 44015571200 ps
T1095 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.247140275 Sep 10 02:27:28 AM UTC 24 Sep 10 02:33:47 AM UTC 24 3858820230 ps
T1096 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3943062124 Sep 10 02:18:59 AM UTC 24 Sep 10 02:34:57 AM UTC 24 7079717094 ps
T1097 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3249767996 Sep 10 02:16:51 AM UTC 24 Sep 10 02:36:07 AM UTC 24 5929789290 ps
T1098 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_transition.3173675196 Sep 10 02:21:58 AM UTC 24 Sep 10 02:37:20 AM UTC 24 11171399711 ps
T1099 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2333514813 Sep 10 02:28:38 AM UTC 24 Sep 10 02:37:26 AM UTC 24 9020413672 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_cpu_info.3528837413 Sep 10 02:26:46 AM UTC 24 Sep 10 02:38:07 AM UTC 24 5659379388 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_rma.3321393456 Sep 10 01:01:07 AM UTC 24 Sep 10 02:38:09 AM UTC 24 48412222595 ps
T1100 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3887600543 Sep 10 02:31:00 AM UTC 24 Sep 10 02:38:09 AM UTC 24 4811129759 ps
T1101 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.254169705 Sep 10 02:27:29 AM UTC 24 Sep 10 02:38:12 AM UTC 24 8834430798 ps
T640 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3097414139 Sep 10 02:32:55 AM UTC 24 Sep 10 02:38:30 AM UTC 24 3193769524 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_rst_inputs.57785765 Sep 10 01:50:02 AM UTC 24 Sep 10 02:39:00 AM UTC 24 19767238657 ps
T1102 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_smoketest.20310842 Sep 10 01:58:08 AM UTC 24 Sep 10 02:39:19 AM UTC 24 9875932128 ps
T1103 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prodend.2369774729 Sep 10 02:23:34 AM UTC 24 Sep 10 02:39:38 AM UTC 24 11261150302 ps
T1104 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_irq.3475319147 Sep 10 02:34:37 AM UTC 24 Sep 10 02:39:41 AM UTC 24 3358304396 ps
T1105 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.4104194993 Sep 10 02:18:41 AM UTC 24 Sep 10 02:40:11 AM UTC 24 6825692304 ps
T1106 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.723691919 Sep 10 02:19:35 AM UTC 24 Sep 10 02:40:26 AM UTC 24 7580487360 ps
T1107 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1233190269 Sep 10 02:35:52 AM UTC 24 Sep 10 02:42:00 AM UTC 24 3027543715 ps
T1108 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1840338335 Sep 10 02:27:27 AM UTC 24 Sep 10 02:43:13 AM UTC 24 6319216222 ps
T1109 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1361949516 Sep 10 02:31:44 AM UTC 24 Sep 10 02:43:32 AM UTC 24 7645966704 ps
T1110 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3593392204 Sep 10 02:38:16 AM UTC 24 Sep 10 02:45:24 AM UTC 24 3563074324 ps
T1111 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1073962735 Sep 10 02:34:02 AM UTC 24 Sep 10 02:45:31 AM UTC 24 5678218056 ps
T1112 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.1091831623 Sep 10 02:39:28 AM UTC 24 Sep 10 02:46:00 AM UTC 24 3985523690 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2803089924 Sep 10 02:36:47 AM UTC 24 Sep 10 02:46:39 AM UTC 24 5765532780 ps
T1113 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3288212122 Sep 10 02:39:28 AM UTC 24 Sep 10 02:47:37 AM UTC 24 6496337944 ps
T1114 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1394348924 Sep 10 02:40:03 AM UTC 24 Sep 10 02:47:44 AM UTC 24 18508924490 ps
T1115 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency.2246296697 Sep 10 01:20:47 AM UTC 24 Sep 10 02:47:49 AM UTC 24 18033001732 ps
T1116 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1969131833 Sep 10 02:39:47 AM UTC 24 Sep 10 02:47:53 AM UTC 24 4512089652 ps
T1117 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.4197695862 Sep 10 02:35:52 AM UTC 24 Sep 10 02:48:18 AM UTC 24 5115534965 ps
T1118 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_mem_scramble.2032347097 Sep 10 02:41:06 AM UTC 24 Sep 10 02:48:25 AM UTC 24 3082922304 ps
T1119 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3774638775 Sep 10 02:40:00 AM UTC 24 Sep 10 02:48:59 AM UTC 24 5048611760 ps
T1120 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc.3042789010 Sep 10 02:44:13 AM UTC 24 Sep 10 02:50:00 AM UTC 24 3489311656 ps
T1121 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1945274845 Sep 10 01:56:10 AM UTC 24 Sep 10 02:50:01 AM UTC 24 11763746670 ps
T1122 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en.4280108294 Sep 10 02:46:16 AM UTC 24 Sep 10 02:50:47 AM UTC 24 3213087601 ps
T1123 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_idle.2384745418 Sep 10 02:46:17 AM UTC 24 Sep 10 02:51:05 AM UTC 24 3048077000 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.1542961319 Sep 10 02:26:23 AM UTC 24 Sep 10 02:51:19 AM UTC 24 12029233044 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_otbn.2759817301 Sep 10 01:27:36 AM UTC 24 Sep 10 02:51:27 AM UTC 24 18742866514 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init.3242132215 Sep 10 02:17:25 AM UTC 24 Sep 10 02:51:29 AM UTC 24 26072075404 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_test.2113444339 Sep 10 02:47:22 AM UTC 24 Sep 10 02:52:13 AM UTC 24 3246072374 ps
T1124 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prod.2217289512 Sep 10 01:00:52 AM UTC 24 Sep 10 02:52:20 AM UTC 24 49836903336 ps
T1125 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_masking_off.2506718923 Sep 10 02:46:38 AM UTC 24 Sep 10 02:52:46 AM UTC 24 3548381504 ps
T1126 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3429585111 Sep 10 02:28:33 AM UTC 24 Sep 10 02:53:47 AM UTC 24 12254031092 ps
T1127 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4119892126 Sep 10 02:28:37 AM UTC 24 Sep 10 02:53:48 AM UTC 24 16509983714 ps
T1128 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3382663928 Sep 10 02:39:42 AM UTC 24 Sep 10 02:54:49 AM UTC 24 10484333400 ps
T1129 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_dev.3958987076 Sep 10 01:02:51 AM UTC 24 Sep 10 02:54:57 AM UTC 24 50247145808 ps
T666 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1406256318 Sep 10 02:49:39 AM UTC 24 Sep 10 02:56:21 AM UTC 24 3873364968 ps
T1130 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_entropy.1395331565 Sep 10 02:51:28 AM UTC 24 Sep 10 02:56:29 AM UTC 24 2912683988 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_timeout.2474132362 Sep 10 02:49:21 AM UTC 24 Sep 10 02:56:42 AM UTC 24 3474311594 ps
T1131 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_rnd.1759546092 Sep 10 02:42:42 AM UTC 24 Sep 10 02:57:06 AM UTC 24 5481320008 ps
T1132 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_randomness.3106858737 Sep 10 02:40:29 AM UTC 24 Sep 10 02:57:35 AM UTC 24 5996379446 ps
T1133 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_entropy.1779221544 Sep 10 02:50:53 AM UTC 24 Sep 10 02:57:40 AM UTC 24 3653818100 ps
T654 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3201694179 Sep 10 02:43:54 AM UTC 24 Sep 10 02:57:50 AM UTC 24 5122520904 ps
T1134 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_kat_test.3196837708 Sep 10 02:51:43 AM UTC 24 Sep 10 02:57:52 AM UTC 24 3046670604 ps
T1135 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.970111721 Sep 10 02:24:52 AM UTC 24 Sep 10 02:58:01 AM UTC 24 26233240180 ps
T1136 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_kat_test.433815082 Sep 10 02:54:38 AM UTC 24 Sep 10 02:58:55 AM UTC 24 2848727976 ps
T1137 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.752525265 Sep 10 02:28:29 AM UTC 24 Sep 10 02:59:00 AM UTC 24 11666538268 ps
T1138 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_escalation.982978214 Sep 10 02:49:19 AM UTC 24 Sep 10 03:00:23 AM UTC 24 4855938328 ps
T617 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_boot_mode.1008120515 Sep 10 02:52:23 AM UTC 24 Sep 10 03:00:58 AM UTC 24 3529108912 ps
T620 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3542383442 Sep 10 01:48:06 AM UTC 24 Sep 10 03:01:07 AM UTC 24 24402351135 ps
T1139 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod.1266057638 Sep 10 01:56:07 AM UTC 24 Sep 10 03:01:20 AM UTC 24 15750775608 ps
T1140 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_exception_c.4276501242 Sep 10 01:55:19 AM UTC 24 Sep 10 03:01:39 AM UTC 24 14701395539 ps
T1141 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_ast_rng_req.799474341 Sep 10 02:55:43 AM UTC 24 Sep 10 03:01:49 AM UTC 24 3529043034 ps
T1142 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_rma.2788894538 Sep 10 01:55:44 AM UTC 24 Sep 10 03:02:28 AM UTC 24 14757780201 ps
T1143 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc.819854157 Sep 10 02:57:29 AM UTC 24 Sep 10 03:03:07 AM UTC 24 2954802716 ps
T1144 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_kat.4041808467 Sep 10 02:52:24 AM UTC 24 Sep 10 03:03:20 AM UTC 24 3849232146 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en.1057534607 Sep 10 02:57:47 AM UTC 24 Sep 10 03:03:21 AM UTC 24 3131548225 ps
T1145 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.913107202 Sep 10 02:54:39 AM UTC 24 Sep 10 03:03:58 AM UTC 24 3749425680 ps
T1146 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_idle.1346490134 Sep 10 02:59:19 AM UTC 24 Sep 10 03:04:07 AM UTC 24 2756356200 ps
T1147 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_dev.548677282 Sep 10 01:55:04 AM UTC 24 Sep 10 03:04:25 AM UTC 24 15523528225 ps
T1148 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_smoke.2334819671 Sep 10 01:54:58 AM UTC 24 Sep 10 03:04:45 AM UTC 24 14492658776 ps
T1149 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1807517182 Sep 10 01:55:51 AM UTC 24 Sep 10 03:04:45 AM UTC 24 14641102774 ps
T1150 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.4173696131 Sep 10 01:56:05 AM UTC 24 Sep 10 03:05:01 AM UTC 24 15480779280 ps
T1151 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.4016175872 Sep 10 02:53:03 AM UTC 24 Sep 10 03:05:13 AM UTC 24 6079020843 ps
T1152 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_oneshot.3137280150 Sep 10 02:59:20 AM UTC 24 Sep 10 03:05:25 AM UTC 24 3036548856 ps
T1153 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_cshake.1430643520 Sep 10 03:01:08 AM UTC 24 Sep 10 03:05:32 AM UTC 24 3298210984 ps
T1154 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod_end.2781591364 Sep 10 01:55:15 AM UTC 24 Sep 10 03:05:39 AM UTC 24 15300529054 ps
T1155 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_app_rom.2495419505 Sep 10 03:02:05 AM UTC 24 Sep 10 03:06:46 AM UTC 24 2532431662 ps
T1156 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2934576901 Sep 10 03:02:02 AM UTC 24 Sep 10 03:06:52 AM UTC 24 2841842010 ps
T1157 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3482439423 Sep 10 01:55:48 AM UTC 24 Sep 10 03:06:54 AM UTC 24 14895984392 ps
T1158 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_reset.4212963754 Sep 10 02:38:15 AM UTC 24 Sep 10 03:07:03 AM UTC 24 24051884020 ps
T1159 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_idle.4284783444 Sep 10 03:02:30 AM UTC 24 Sep 10 03:07:17 AM UTC 24 2748857816 ps
T1160 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac.3365786659 Sep 10 03:02:00 AM UTC 24 Sep 10 03:07:36 AM UTC 24 3348625304 ps
T1161 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_status.187121490 Sep 10 03:05:07 AM UTC 24 Sep 10 03:08:45 AM UTC 24 2832001593 ps
T1162 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2307539039 Sep 10 02:49:41 AM UTC 24 Sep 10 03:09:36 AM UTC 24 6189804320 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3017215783 Sep 10 03:02:32 AM UTC 24 Sep 10 03:10:02 AM UTC 24 9372792896 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_plic_sw_irq.225197775 Sep 10 03:06:40 AM UTC 24 Sep 10 03:10:48 AM UTC 24 2471384964 ps
T1163 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_ok.1781135035 Sep 10 02:49:20 AM UTC 24 Sep 10 03:10:59 AM UTC 24 7659073000 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_output.2066343069 Sep 10 01:55:50 AM UTC 24 Sep 10 03:11:22 AM UTC 24 29513883631 ps
T676 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3042462246 Sep 10 02:49:37 AM UTC 24 Sep 10 03:12:34 AM UTC 24 11244951756 ps
T1164 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_auto_mode.1725391240 Sep 10 02:52:25 AM UTC 24 Sep 10 03:12:49 AM UTC 24 5015848712 ps
T1165 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.47514579 Sep 10 03:04:14 AM UTC 24 Sep 10 03:13:26 AM UTC 24 6435664408 ps
T1166 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.524897858 Sep 10 03:03:43 AM UTC 24 Sep 10 03:14:09 AM UTC 24 5204540550 ps
T1167 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2501455316 Sep 10 02:57:29 AM UTC 24 Sep 10 03:14:16 AM UTC 24 7591001397 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.601779076 Sep 10 03:06:44 AM UTC 24 Sep 10 03:14:17 AM UTC 24 5907860952 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.2608256693 Sep 10 03:06:44 AM UTC 24 Sep 10 03:14:51 AM UTC 24 4127992482 ps
T1168 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3953236965 Sep 10 03:06:49 AM UTC 24 Sep 10 03:15:23 AM UTC 24 5605980520 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_execution_main.3714987798 Sep 10 03:04:14 AM UTC 24 Sep 10 03:15:25 AM UTC 24 8134857395 ps
T1169 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3231444658 Sep 10 02:28:38 AM UTC 24 Sep 10 03:15:29 AM UTC 24 24975646570 ps
T1170 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1605018438 Sep 10 03:03:10 AM UTC 24 Sep 10 03:15:47 AM UTC 24 5682767350 ps
T1171 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs.1323518236 Sep 10 02:57:30 AM UTC 24 Sep 10 03:15:52 AM UTC 24 7535691240 ps
T1172 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2041207311 Sep 10 03:08:08 AM UTC 24 Sep 10 03:15:57 AM UTC 24 4912659919 ps
T1173 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.499594627 Sep 10 03:08:25 AM UTC 24 Sep 10 03:16:16 AM UTC 24 3859628444 ps
T1174 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.4189778439 Sep 10 02:50:52 AM UTC 24 Sep 10 03:16:32 AM UTC 24 7246528012 ps
T1175 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_kmac.1892538258 Sep 10 02:59:49 AM UTC 24 Sep 10 03:16:38 AM UTC 24 6892248116 ps
T1176 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.405232905 Sep 10 03:08:07 AM UTC 24 Sep 10 03:16:53 AM UTC 24 5094414808 ps
T1177 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1802524988 Sep 10 03:08:26 AM UTC 24 Sep 10 03:17:16 AM UTC 24 4980090256 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.36189094 Sep 10 03:04:53 AM UTC 24 Sep 10 03:17:21 AM UTC 24 7301797844 ps
T1178 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1432399417 Sep 10 03:08:24 AM UTC 24 Sep 10 03:17:27 AM UTC 24 5233559270 ps
T1179 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter.732817030 Sep 10 03:13:16 AM UTC 24 Sep 10 03:17:55 AM UTC 24 2789932322 ps
T1180 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_reset_frequency.2369957722 Sep 10 03:11:42 AM UTC 24 Sep 10 03:17:59 AM UTC 24 3544662335 ps
T1181 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.584001119 Sep 10 03:04:52 AM UTC 24 Sep 10 03:18:03 AM UTC 24 7442787496 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.2148836679 Sep 10 03:06:56 AM UTC 24 Sep 10 03:18:15 AM UTC 24 5207286828 ps
T1182 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3214567164 Sep 10 02:59:11 AM UTC 24 Sep 10 03:18:43 AM UTC 24 6300493960 ps
T1183 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3074379700 Sep 10 03:08:29 AM UTC 24 Sep 10 03:19:17 AM UTC 24 4761742096 ps
T1184 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2577481918 Sep 10 03:09:27 AM UTC 24 Sep 10 03:19:43 AM UTC 24 3963426698 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_inject_scramble_seed.4190887929 Sep 09 10:43:52 PM UTC 24 Sep 10 03:20:14 AM UTC 24 66557508491 ps
T1185 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2466770030 Sep 10 03:12:03 AM UTC 24 Sep 10 03:20:20 AM UTC 24 3934582384 ps
T1186 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.835664114 Sep 10 03:10:18 AM UTC 24 Sep 10 03:20:36 AM UTC 24 4843245064 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_csrng.4265693904 Sep 10 02:55:43 AM UTC 24 Sep 10 03:20:38 AM UTC 24 7506125740 ps
T1187 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3206003705 Sep 10 03:10:43 AM UTC 24 Sep 10 03:20:45 AM UTC 24 4047237064 ps
T1188 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.699274516 Sep 10 03:11:39 AM UTC 24 Sep 10 03:21:06 AM UTC 24 4518651720 ps
T1189 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_testunlock0.3299533160 Sep 10 03:18:10 AM UTC 24 Sep 10 03:21:12 AM UTC 24 2320637727 ps
T1190 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_static_critical.1068611116 Sep 10 01:56:16 AM UTC 24 Sep 10 03:21:22 AM UTC 24 17349020488 ps
T1191 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_peri.2550861376 Sep 10 03:06:57 AM UTC 24 Sep 10 03:22:45 AM UTC 24 9581170068 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_program_error.1334749274 Sep 10 03:15:10 AM UTC 24 Sep 10 03:23:00 AM UTC 24 4754281190 ps
T1192 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3990785211 Sep 10 03:19:58 AM UTC 24 Sep 10 03:23:01 AM UTC 24 3108845311 ps
T1193 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3869312326 Sep 10 03:13:31 AM UTC 24 Sep 10 03:23:33 AM UTC 24 4177216342 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1433376490 Sep 10 03:19:10 AM UTC 24 Sep 10 03:23:34 AM UTC 24 2959455428 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1124328117 Sep 10 03:17:04 AM UTC 24 Sep 10 03:23:34 AM UTC 24 3683633116 ps
T1194 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_multistream.4212859901 Sep 10 02:59:16 AM UTC 24 Sep 10 03:23:39 AM UTC 24 7104766440 ps
T1195 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1424513708 Sep 10 03:17:46 AM UTC 24 Sep 10 03:23:55 AM UTC 24 6564813780 ps
T1196 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1430103827 Sep 10 02:59:16 AM UTC 24 Sep 10 03:24:01 AM UTC 24 8231630365 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_rv_dm_ndm_reset_req.2411462007 Sep 10 03:18:10 AM UTC 24 Sep 10 03:24:41 AM UTC 24 3862084148 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1532571020 Sep 10 03:19:07 AM UTC 24 Sep 10 03:24:43 AM UTC 24 3676081776 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.1383920079 Sep 10 03:06:49 AM UTC 24 Sep 10 03:24:56 AM UTC 24 6322913656 ps
T1197 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_sw_mode.121622182 Sep 10 02:53:02 AM UTC 24 Sep 10 03:25:17 AM UTC 24 8371266120 ps
T1198 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.323607531 Sep 10 03:21:49 AM UTC 24 Sep 10 03:25:17 AM UTC 24 2797696290 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1935014640 Sep 10 03:15:34 AM UTC 24 Sep 10 03:25:31 AM UTC 24 7263275388 ps
T1199 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_write_clear.2460174384 Sep 10 03:19:25 AM UTC 24 Sep 10 03:25:48 AM UTC 24 3538901328 ps
T622 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2215186576 Sep 10 03:18:11 AM UTC 24 Sep 10 03:26:06 AM UTC 24 5275768547 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3001001118 Sep 10 03:17:47 AM UTC 24 Sep 10 03:26:13 AM UTC 24 6779837268 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1570910242 Sep 10 03:18:01 AM UTC 24 Sep 10 03:26:42 AM UTC 24 3894293982 ps
T1200 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2592868829 Sep 10 03:17:54 AM UTC 24 Sep 10 03:27:06 AM UTC 24 6262167600 ps
T1201 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3995355220 Sep 10 03:22:17 AM UTC 24 Sep 10 03:27:18 AM UTC 24 3268833336 ps
T1202 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3288253592 Sep 10 03:22:11 AM UTC 24 Sep 10 03:27:47 AM UTC 24 2966941368 ps
T1203 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_rma.2787840054 Sep 10 03:18:08 AM UTC 24 Sep 10 03:27:55 AM UTC 24 7470048287 ps
T1204 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1357806698 Sep 10 03:20:21 AM UTC 24 Sep 10 03:29:08 AM UTC 24 5021837355 ps
T646 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_sleep_load.2651857965 Sep 10 03:23:54 AM UTC 24 Sep 10 03:29:30 AM UTC 24 5024126508 ps
T1205 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_crash_alert.3301115580 Sep 10 03:19:10 AM UTC 24 Sep 10 03:29:56 AM UTC 24 5473839780 ps
T1206 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_outputs.158307501 Sep 10 03:15:09 AM UTC 24 Sep 10 03:30:41 AM UTC 24 7967176224 ps
T1207 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_prod.506937006 Sep 10 03:18:08 AM UTC 24 Sep 10 03:31:16 AM UTC 24 8765603400 ps
T1208 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_volatile_raw_unlock.2941452705 Sep 10 03:29:28 AM UTC 24 Sep 10 03:31:37 AM UTC 24 2027092694 ps
T606 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.585649631 Sep 10 03:22:18 AM UTC 24 Sep 10 03:32:16 AM UTC 24 5296679639 ps
T1209 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_idle_load.828002670 Sep 10 03:23:26 AM UTC 24 Sep 10 03:32:42 AM UTC 24 3983464104 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_raw_unlock.4093057237 Sep 10 03:28:59 AM UTC 24 Sep 10 03:33:09 AM UTC 24 4539086536 ps
T1210 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_smoketest.3208654861 Sep 10 03:29:12 AM UTC 24 Sep 10 03:33:15 AM UTC 24 2745353100 ps
T1211 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_scrambling_smoketest.2811481683 Sep 10 03:28:24 AM UTC 24 Sep 10 03:33:38 AM UTC 24 3092708392 ps
T1212 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_dev.637744651 Sep 10 03:17:43 AM UTC 24 Sep 10 03:34:10 AM UTC 24 10892946229 ps
T1213 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_smoketest.2215572083 Sep 10 03:30:12 AM UTC 24 Sep 10 03:34:21 AM UTC 24 3117745896 ps
T1214 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_smoketest.2139488122 Sep 10 03:30:13 AM UTC 24 Sep 10 03:34:54 AM UTC 24 3184964380 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1323509956 Sep 10 03:16:59 AM UTC 24 Sep 10 03:34:58 AM UTC 24 21974274384 ps
T1215 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_smoketest.3543082521 Sep 10 03:30:34 AM UTC 24 Sep 10 03:35:37 AM UTC 24 2960473288 ps
T1216 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio_smoketest.3364604552 Sep 10 03:31:57 AM UTC 24 Sep 10 03:37:06 AM UTC 24 2491662254 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_mem_access.3752779887 Sep 10 03:14:35 AM UTC 24 Sep 10 03:37:06 AM UTC 24 13574486800 ps
T1217 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_smoketest.3470738556 Sep 10 03:32:57 AM UTC 24 Sep 10 03:37:28 AM UTC 24 3045443820 ps
T1218 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_keymgr_functest.1673875400 Sep 10 03:28:48 AM UTC 24 Sep 10 03:37:41 AM UTC 24 3885037532 ps
T1219 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.75813730 Sep 10 03:06:57 AM UTC 24 Sep 10 03:37:56 AM UTC 24 18265580320 ps
T1220 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_smoketest.3318688931 Sep 10 03:32:19 AM UTC 24 Sep 10 03:38:06 AM UTC 24 2912444860 ps
T1221 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_smoketest.1604586510 Sep 10 03:34:02 AM UTC 24 Sep 10 03:38:51 AM UTC 24 3210946900 ps
T1222 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1463745340 Sep 10 02:39:42 AM UTC 24 Sep 10 03:39:10 AM UTC 24 21095224054 ps
T1223 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_smoketest.1715718413 Sep 10 03:35:43 AM UTC 24 Sep 10 03:39:21 AM UTC 24 2451929860 ps
T1224 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation.1077803720 Sep 10 02:59:11 AM UTC 24 Sep 10 03:39:45 AM UTC 24 11522238390 ps
T1225 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_plic_smoketest.2563609113 Sep 10 03:35:01 AM UTC 24 Sep 10 03:39:48 AM UTC 24 2860952712 ps
T1226 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_smoketest.2256313506 Sep 10 03:35:42 AM UTC 24 Sep 10 03:39:53 AM UTC 24 2610550680 ps
T1227 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_smoketest.2585027934 Sep 10 03:35:04 AM UTC 24 Sep 10 03:39:59 AM UTC 24 3522227904 ps
T1228 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2985104223 Sep 10 03:34:17 AM UTC 24 Sep 10 03:40:33 AM UTC 24 5257808550 ps
T1229 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_smoketest.4026581383 Sep 10 03:36:18 AM UTC 24 Sep 10 03:41:41 AM UTC 24 2851395992 ps
T1230 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.995325650 Sep 10 03:21:47 AM UTC 24 Sep 10 03:41:53 AM UTC 24 7571912217 ps
T1231 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_smoketest.2216544398 Sep 10 03:31:22 AM UTC 24 Sep 10 03:42:02 AM UTC 24 3972380928 ps
T1232 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_smoketest.3104062968 Sep 10 03:34:02 AM UTC 24 Sep 10 03:42:11 AM UTC 24 5832384416 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.6490260 Sep 10 01:50:46 AM UTC 24 Sep 10 03:42:25 AM UTC 24 33328239397 ps
T1233 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4177481937 Sep 10 03:17:42 AM UTC 24 Sep 10 03:42:51 AM UTC 24 23131224240 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_aes.1549862012 Sep 10 02:59:50 AM UTC 24 Sep 10 03:43:31 AM UTC 24 13173699110 ps
T1234 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2290548409 Sep 10 03:26:23 AM UTC 24 Sep 10 03:43:49 AM UTC 24 5704489436 ps
T1235 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.12944215 Sep 10 03:22:00 AM UTC 24 Sep 10 03:44:13 AM UTC 24 9009232067 ps
T1236 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.1949799202 Sep 10 03:42:14 AM UTC 24 Sep 10 03:44:58 AM UTC 24 2389734701 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3739188206 Sep 09 10:43:24 PM UTC 24 Sep 10 03:45:05 AM UTC 24 81367882370 ps
T1237 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_rma.3217819781 Sep 10 03:42:37 AM UTC 24 Sep 10 03:45:57 AM UTC 24 3180434880 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.3671950904 Sep 10 03:13:52 AM UTC 24 Sep 10 03:46:28 AM UTC 24 19218847556 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1078440404 Sep 10 03:41:00 AM UTC 24 Sep 10 03:48:59 AM UTC 24 3685434344 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx2.2760260341 Sep 10 03:38:57 AM UTC 24 Sep 10 03:49:04 AM UTC 24 4599799788 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx1.995103309 Sep 10 03:39:00 AM UTC 24 Sep 10 03:49:26 AM UTC 24 4733046392 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2880349626 Sep 10 03:41:17 AM UTC 24 Sep 10 03:49:57 AM UTC 24 7023136338 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_virus.1091410497 Sep 10 03:26:43 AM UTC 24 Sep 10 03:50:08 AM UTC 24 5323997120 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx3.299077081 Sep 10 03:38:55 AM UTC 24 Sep 10 03:50:29 AM UTC 24 3779810480 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.3971187156 Sep 10 03:41:20 AM UTC 24 Sep 10 03:51:16 AM UTC 24 4877999730 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx.3800112940 Sep 10 03:38:57 AM UTC 24 Sep 10 03:51:17 AM UTC 24 4109907708 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_all_escalation_resets.2064113091 Sep 10 03:38:49 AM UTC 24 Sep 10 03:51:55 AM UTC 24 4827022194 ps
T1238 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3088549318 Sep 10 03:40:03 AM UTC 24 Sep 10 03:52:00 AM UTC 24 3920469896 ps
T1239 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_data_integrity_escalation.3353446396 Sep 10 03:38:56 AM UTC 24 Sep 10 03:52:06 AM UTC 24 5574761816 ps
T1240 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3512046119 Sep 10 02:40:29 AM UTC 24 Sep 10 03:53:00 AM UTC 24 17292409426 ps
T1241 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_smoketest.2638339131 Sep 10 03:33:25 AM UTC 24 Sep 10 03:53:48 AM UTC 24 6868318640 ps
T1242 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.1866735370 Sep 10 03:22:11 AM UTC 24 Sep 10 03:54:03 AM UTC 24 25305437235 ps
T1243 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx.1898496262 Sep 10 03:44:14 AM UTC 24 Sep 10 03:54:19 AM UTC 24 4554503688 ps
T1244 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx2.1078819142 Sep 10 03:44:56 AM UTC 24 Sep 10 03:54:58 AM UTC 24 4101581072 ps
T1245 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx1.242008142 Sep 10 03:44:28 AM UTC 24 Sep 10 03:55:26 AM UTC 24 4973272180 ps
T763 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.3724860682 Sep 10 03:43:06 AM UTC 24 Sep 10 03:55:49 AM UTC 24 6278932714 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%