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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.17 95.52 94.02 95.39 94.99 97.53 99.59


Total test records in report: 2926
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T1788 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.268117454 Sep 10 06:25:27 AM UTC 24 Sep 10 06:27:36 AM UTC 24 8554927927 ps
T1789 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.3052214484 Sep 10 06:25:26 AM UTC 24 Sep 10 06:27:36 AM UTC 24 5555120642 ps
T852 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3702656479 Sep 10 06:21:55 AM UTC 24 Sep 10 06:27:42 AM UTC 24 711682910 ps
T1790 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.1478938996 Sep 10 06:27:33 AM UTC 24 Sep 10 06:27:53 AM UTC 24 452853203 ps
T1791 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.392737896 Sep 10 06:22:03 AM UTC 24 Sep 10 06:28:07 AM UTC 24 11165307157 ps
T1792 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.3449090777 Sep 10 06:12:46 AM UTC 24 Sep 10 06:28:09 AM UTC 24 53196162440 ps
T1793 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.3453381972 Sep 10 06:27:11 AM UTC 24 Sep 10 06:28:16 AM UTC 24 6415254420 ps
T1794 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.2241727486 Sep 10 06:15:52 AM UTC 24 Sep 10 06:28:20 AM UTC 24 42054913782 ps
T1795 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.990358956 Sep 10 06:27:54 AM UTC 24 Sep 10 06:28:26 AM UTC 24 872721429 ps
T1796 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.215916848 Sep 10 06:27:37 AM UTC 24 Sep 10 06:28:27 AM UTC 24 599435479 ps
T1797 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.2230207696 Sep 10 06:28:05 AM UTC 24 Sep 10 06:28:29 AM UTC 24 329165903 ps
T1798 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.3162328672 Sep 10 06:23:54 AM UTC 24 Sep 10 06:28:31 AM UTC 24 6305740562 ps
T1799 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.3159422549 Sep 10 06:28:03 AM UTC 24 Sep 10 06:28:35 AM UTC 24 828747029 ps
T1800 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.313991671 Sep 10 06:15:48 AM UTC 24 Sep 10 06:28:38 AM UTC 24 47126326314 ps
T1801 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.1409847426 Sep 10 06:28:10 AM UTC 24 Sep 10 06:28:41 AM UTC 24 322908165 ps
T1802 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.864279965 Sep 10 06:25:55 AM UTC 24 Sep 10 06:28:45 AM UTC 24 11060323006 ps
T1803 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.758160927 Sep 10 06:22:05 AM UTC 24 Sep 10 06:28:45 AM UTC 24 6499115744 ps
T1804 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.2866514436 Sep 10 06:28:48 AM UTC 24 Sep 10 06:29:01 AM UTC 24 177537062 ps
T1805 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.1342230453 Sep 10 06:24:50 AM UTC 24 Sep 10 06:29:02 AM UTC 24 7178993346 ps
T1806 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.3755535859 Sep 10 06:28:22 AM UTC 24 Sep 10 06:29:03 AM UTC 24 1006857249 ps
T1807 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.3618067062 Sep 10 06:28:53 AM UTC 24 Sep 10 06:29:04 AM UTC 24 46994843 ps
T1808 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.2467725571 Sep 10 06:22:54 AM UTC 24 Sep 10 06:29:20 AM UTC 24 11849630701 ps
T1809 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.1985974829 Sep 10 06:28:40 AM UTC 24 Sep 10 06:29:20 AM UTC 24 138336879 ps
T1810 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.349910625 Sep 10 06:29:00 AM UTC 24 Sep 10 06:29:28 AM UTC 24 242617925 ps
T1811 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.2645616018 Sep 10 06:14:00 AM UTC 24 Sep 10 06:29:29 AM UTC 24 102848654187 ps
T598 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.3027881553 Sep 10 06:23:58 AM UTC 24 Sep 10 06:29:29 AM UTC 24 4137348178 ps
T859 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.3253611933 Sep 10 06:26:37 AM UTC 24 Sep 10 06:29:29 AM UTC 24 621705937 ps
T1812 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.3343405130 Sep 10 06:23:27 AM UTC 24 Sep 10 06:29:33 AM UTC 24 20965337614 ps
T1813 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.3541248356 Sep 10 06:27:27 AM UTC 24 Sep 10 06:29:44 AM UTC 24 6869212757 ps
T1814 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.3771842660 Sep 10 06:27:51 AM UTC 24 Sep 10 06:29:47 AM UTC 24 2516024935 ps
T1815 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.4016108414 Sep 10 06:29:30 AM UTC 24 Sep 10 06:29:48 AM UTC 24 160516645 ps
T1816 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.2251629737 Sep 10 06:25:04 AM UTC 24 Sep 10 06:29:56 AM UTC 24 8017940321 ps
T1817 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.1663109456 Sep 10 06:23:02 AM UTC 24 Sep 10 06:29:59 AM UTC 24 3092532073 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.499166448 Sep 10 05:40:37 AM UTC 24 Sep 10 06:29:59 AM UTC 24 29240341234 ps
T1818 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.515641585 Sep 10 06:26:35 AM UTC 24 Sep 10 06:30:49 AM UTC 24 2651065801 ps
T1819 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.2677525165 Sep 10 06:28:55 AM UTC 24 Sep 10 06:30:00 AM UTC 24 1830046844 ps
T1820 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.2775161013 Sep 10 06:19:22 AM UTC 24 Sep 10 06:30:00 AM UTC 24 43355068712 ps
T1821 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.691177301 Sep 10 06:29:53 AM UTC 24 Sep 10 06:30:03 AM UTC 24 43790745 ps
T1822 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.1775685666 Sep 10 06:12:24 AM UTC 24 Sep 10 06:30:05 AM UTC 24 108542116635 ps
T1823 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.3335523868 Sep 10 06:29:53 AM UTC 24 Sep 10 06:30:06 AM UTC 24 192492629 ps
T1824 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.3800657796 Sep 10 06:29:26 AM UTC 24 Sep 10 06:30:11 AM UTC 24 1210520451 ps
T497 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.688241370 Sep 10 06:21:48 AM UTC 24 Sep 10 06:30:14 AM UTC 24 14800958961 ps
T1825 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.3229757906 Sep 10 06:29:30 AM UTC 24 Sep 10 06:30:14 AM UTC 24 263561136 ps
T1826 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.1376844765 Sep 10 06:28:57 AM UTC 24 Sep 10 06:30:17 AM UTC 24 5347326042 ps
T1827 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.2255564070 Sep 10 06:28:55 AM UTC 24 Sep 10 06:30:21 AM UTC 24 6803190785 ps
T1828 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.1941567833 Sep 10 06:30:11 AM UTC 24 Sep 10 06:30:23 AM UTC 24 81218875 ps
T1829 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.1359133566 Sep 10 06:29:55 AM UTC 24 Sep 10 06:30:25 AM UTC 24 389010468 ps
T1830 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.2828271252 Sep 10 06:29:27 AM UTC 24 Sep 10 06:30:41 AM UTC 24 2194066053 ps
T1831 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.552608529 Sep 10 06:30:26 AM UTC 24 Sep 10 06:30:41 AM UTC 24 99483655 ps
T1832 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.275344617 Sep 10 07:02:38 AM UTC 24 Sep 10 07:02:49 AM UTC 24 153694103 ps
T1833 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.1421654815 Sep 10 06:30:45 AM UTC 24 Sep 10 06:30:53 AM UTC 24 49858482 ps
T1834 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.3845559053 Sep 10 06:30:46 AM UTC 24 Sep 10 06:30:59 AM UTC 24 209159733 ps
T1835 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.798806002 Sep 10 06:30:27 AM UTC 24 Sep 10 06:31:07 AM UTC 24 758170464 ps
T1836 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.1266901713 Sep 10 06:29:10 AM UTC 24 Sep 10 06:31:07 AM UTC 24 2815160326 ps
T1837 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.1568365437 Sep 10 06:30:26 AM UTC 24 Sep 10 06:31:12 AM UTC 24 1121335998 ps
T1838 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.2021107112 Sep 10 06:31:05 AM UTC 24 Sep 10 06:31:16 AM UTC 24 155195841 ps
T1839 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.2136241090 Sep 10 06:30:28 AM UTC 24 Sep 10 06:31:17 AM UTC 24 997286030 ps
T1840 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.882716044 Sep 10 06:29:53 AM UTC 24 Sep 10 06:31:19 AM UTC 24 206069170 ps
T1841 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.2804781338 Sep 10 06:30:13 AM UTC 24 Sep 10 06:31:21 AM UTC 24 582158858 ps
T1842 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.2947746424 Sep 10 06:23:22 AM UTC 24 Sep 10 06:31:24 AM UTC 24 44620657121 ps
T1843 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.4251877245 Sep 10 06:29:08 AM UTC 24 Sep 10 06:31:34 AM UTC 24 9882671308 ps
T1844 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.1971658651 Sep 10 06:31:16 AM UTC 24 Sep 10 06:31:37 AM UTC 24 190858980 ps
T1845 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.3432912166 Sep 10 06:30:00 AM UTC 24 Sep 10 06:31:48 AM UTC 24 7847600653 ps
T1846 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.541312365 Sep 10 06:20:36 AM UTC 24 Sep 10 06:31:51 AM UTC 24 15736851571 ps
T1847 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.3271408680 Sep 10 06:26:44 AM UTC 24 Sep 10 06:31:52 AM UTC 24 8945468263 ps
T1848 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.2545115163 Sep 10 06:31:43 AM UTC 24 Sep 10 06:32:04 AM UTC 24 312968631 ps
T1849 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.2361178235 Sep 10 06:07:07 AM UTC 24 Sep 10 06:32:04 AM UTC 24 98544819969 ps
T1850 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.58609920 Sep 10 06:30:10 AM UTC 24 Sep 10 06:32:07 AM UTC 24 6090980823 ps
T1851 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.3146670530 Sep 10 06:31:32 AM UTC 24 Sep 10 06:32:08 AM UTC 24 710895541 ps
T1852 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.3260353428 Sep 10 06:30:49 AM UTC 24 Sep 10 06:32:14 AM UTC 24 8553499541 ps
T1853 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.1461383739 Sep 10 06:30:24 AM UTC 24 Sep 10 06:32:20 AM UTC 24 2665515965 ps
T1854 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.4045305600 Sep 10 06:31:41 AM UTC 24 Sep 10 06:32:20 AM UTC 24 400367422 ps
T1855 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.815437377 Sep 10 06:31:46 AM UTC 24 Sep 10 06:32:21 AM UTC 24 277839993 ps
T1856 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.3601663457 Sep 10 06:32:13 AM UTC 24 Sep 10 06:32:27 AM UTC 24 224499934 ps
T1857 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.1743756547 Sep 10 06:32:17 AM UTC 24 Sep 10 06:32:28 AM UTC 24 46458228 ps
T1858 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.3531705207 Sep 10 06:31:34 AM UTC 24 Sep 10 06:32:39 AM UTC 24 2061665337 ps
T1859 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.2919186815 Sep 10 06:31:04 AM UTC 24 Sep 10 06:32:40 AM UTC 24 4018939288 ps
T1860 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.4249370911 Sep 10 06:24:26 AM UTC 24 Sep 10 06:32:45 AM UTC 24 53388018350 ps
T802 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.2615527201 Sep 10 06:02:30 AM UTC 24 Sep 10 06:32:46 AM UTC 24 116588780698 ps
T1861 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.1300615580 Sep 10 06:24:52 AM UTC 24 Sep 10 06:32:49 AM UTC 24 8433264838 ps
T1862 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.897323766 Sep 10 06:32:32 AM UTC 24 Sep 10 06:33:07 AM UTC 24 389615897 ps
T1863 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.2965686097 Sep 10 06:32:48 AM UTC 24 Sep 10 06:33:20 AM UTC 24 373487020 ps
T1864 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.1133526439 Sep 10 06:33:14 AM UTC 24 Sep 10 06:33:25 AM UTC 24 38913478 ps
T1865 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.138072727 Sep 10 06:32:34 AM UTC 24 Sep 10 06:33:33 AM UTC 24 570852726 ps
T860 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.4156455510 Sep 10 06:31:50 AM UTC 24 Sep 10 06:33:35 AM UTC 24 198440077 ps
T1866 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.2772913351 Sep 10 06:32:44 AM UTC 24 Sep 10 06:33:37 AM UTC 24 1044460060 ps
T1867 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.3624035748 Sep 10 06:32:55 AM UTC 24 Sep 10 06:33:38 AM UTC 24 376948947 ps
T1868 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.907167548 Sep 10 06:31:48 AM UTC 24 Sep 10 06:33:41 AM UTC 24 2643753056 ps
T1869 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.3569005757 Sep 10 06:33:33 AM UTC 24 Sep 10 06:33:43 AM UTC 24 46503431 ps
T1870 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.3031882256 Sep 10 06:32:54 AM UTC 24 Sep 10 06:33:48 AM UTC 24 1063984675 ps
T865 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.2927521429 Sep 10 06:30:36 AM UTC 24 Sep 10 06:33:49 AM UTC 24 494418482 ps
T1871 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.3056842179 Sep 10 06:28:37 AM UTC 24 Sep 10 06:33:56 AM UTC 24 8637515544 ps
T1872 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.815700572 Sep 10 06:33:47 AM UTC 24 Sep 10 06:33:57 AM UTC 24 50068036 ps
T1873 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.2670064460 Sep 10 06:33:05 AM UTC 24 Sep 10 06:33:58 AM UTC 24 1073335507 ps
T1874 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.1492444521 Sep 10 06:29:47 AM UTC 24 Sep 10 06:34:06 AM UTC 24 6878890747 ps
T1875 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.410552861 Sep 10 06:32:19 AM UTC 24 Sep 10 06:34:21 AM UTC 24 9856554065 ps
T1876 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.2368011540 Sep 10 06:32:01 AM UTC 24 Sep 10 06:34:31 AM UTC 24 1797361885 ps
T1877 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.3842937726 Sep 10 06:34:04 AM UTC 24 Sep 10 06:34:33 AM UTC 24 306192576 ps
T1878 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.1054919622 Sep 10 06:32:31 AM UTC 24 Sep 10 06:34:36 AM UTC 24 5431752669 ps
T1879 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.4163478683 Sep 10 05:21:27 AM UTC 24 Sep 10 06:34:50 AM UTC 24 29748055093 ps
T1880 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.3942042992 Sep 10 06:34:25 AM UTC 24 Sep 10 06:34:50 AM UTC 24 489145772 ps
T1881 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.2278037966 Sep 10 06:34:11 AM UTC 24 Sep 10 06:34:55 AM UTC 24 420407545 ps
T1882 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.3187272015 Sep 10 06:34:01 AM UTC 24 Sep 10 06:34:56 AM UTC 24 1500160004 ps
T1883 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.3866585899 Sep 10 06:34:23 AM UTC 24 Sep 10 06:34:58 AM UTC 24 572500835 ps
T831 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.1953810422 Sep 10 06:30:40 AM UTC 24 Sep 10 06:35:16 AM UTC 24 7084435687 ps
T1884 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.2476424062 Sep 10 06:35:03 AM UTC 24 Sep 10 06:35:17 AM UTC 24 205295235 ps
T1885 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.2331034105 Sep 10 06:34:14 AM UTC 24 Sep 10 06:35:19 AM UTC 24 2518664050 ps
T1886 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.2562431557 Sep 10 06:24:33 AM UTC 24 Sep 10 06:35:20 AM UTC 24 39191138601 ps
T1887 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.524964377 Sep 10 06:33:59 AM UTC 24 Sep 10 06:35:20 AM UTC 24 5963424457 ps
T1888 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.262012398 Sep 10 06:35:18 AM UTC 24 Sep 10 06:35:28 AM UTC 24 44638094 ps
T1889 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.2390692307 Sep 10 06:35:26 AM UTC 24 Sep 10 06:35:36 AM UTC 24 37588626 ps
T1890 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.2156372115 Sep 10 06:33:53 AM UTC 24 Sep 10 06:35:39 AM UTC 24 9519764447 ps
T1891 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.1962366832 Sep 10 06:34:24 AM UTC 24 Sep 10 06:35:47 AM UTC 24 2108109492 ps
T832 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.678723036 Sep 10 06:11:18 AM UTC 24 Sep 10 06:35:50 AM UTC 24 98402429404 ps
T1892 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.1952441681 Sep 10 06:19:18 AM UTC 24 Sep 10 06:35:50 AM UTC 24 107392904963 ps
T1893 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.2877609778 Sep 10 06:25:47 AM UTC 24 Sep 10 06:36:11 AM UTC 24 49663459981 ps
T1894 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.3195534246 Sep 10 06:35:23 AM UTC 24 Sep 10 06:36:21 AM UTC 24 1663598191 ps
T1895 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.4008272692 Sep 10 06:31:26 AM UTC 24 Sep 10 06:36:22 AM UTC 24 18924763050 ps
T1896 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.748479086 Sep 10 06:33:07 AM UTC 24 Sep 10 06:36:24 AM UTC 24 2093500142 ps
T1897 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.1496519449 Sep 10 06:36:08 AM UTC 24 Sep 10 06:36:31 AM UTC 24 318546806 ps
T1898 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.3646229007 Sep 10 06:35:55 AM UTC 24 Sep 10 06:36:34 AM UTC 24 784768085 ps
T1899 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.1604944649 Sep 10 06:26:57 AM UTC 24 Sep 10 06:36:46 AM UTC 24 17169223230 ps
T1900 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.727719553 Sep 10 06:36:04 AM UTC 24 Sep 10 06:36:51 AM UTC 24 333398028 ps
T1901 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.2672267022 Sep 10 06:34:48 AM UTC 24 Sep 10 06:36:53 AM UTC 24 190936624 ps
T1902 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.3528366354 Sep 10 06:23:31 AM UTC 24 Sep 10 06:36:55 AM UTC 24 52786382419 ps
T1903 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.3892045298 Sep 10 06:35:49 AM UTC 24 Sep 10 06:36:56 AM UTC 24 1634404564 ps
T1904 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.3691145928 Sep 10 06:36:50 AM UTC 24 Sep 10 06:36:59 AM UTC 24 42114908 ps
T1905 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.873439134 Sep 10 06:36:50 AM UTC 24 Sep 10 06:37:01 AM UTC 24 51163487 ps
T1906 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.4085461036 Sep 10 06:35:23 AM UTC 24 Sep 10 06:37:10 AM UTC 24 5151832807 ps
T1907 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.4036068143 Sep 10 06:33:12 AM UTC 24 Sep 10 06:37:13 AM UTC 24 469119446 ps
T1908 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.3265147773 Sep 10 06:35:18 AM UTC 24 Sep 10 06:37:16 AM UTC 24 7353575289 ps
T1909 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.2362887892 Sep 10 06:28:35 AM UTC 24 Sep 10 06:37:21 AM UTC 24 6214736873 ps
T1910 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.1731112746 Sep 10 06:36:15 AM UTC 24 Sep 10 06:37:27 AM UTC 24 1213911998 ps
T1911 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.1781645037 Sep 10 06:32:02 AM UTC 24 Sep 10 06:37:34 AM UTC 24 2397438351 ps
T1912 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.1411500409 Sep 10 06:30:27 AM UTC 24 Sep 10 06:37:37 AM UTC 24 29886562704 ps
T786 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3078094684 Sep 10 06:30:39 AM UTC 24 Sep 10 06:37:43 AM UTC 24 7169278306 ps
T1913 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.1532670177 Sep 10 06:37:29 AM UTC 24 Sep 10 06:37:48 AM UTC 24 166633290 ps
T1914 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.3232564586 Sep 10 06:37:38 AM UTC 24 Sep 10 06:37:55 AM UTC 24 200861638 ps
T1915 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.743124010 Sep 10 06:35:48 AM UTC 24 Sep 10 06:38:00 AM UTC 24 3040504065 ps
T787 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.3889588988 Sep 10 06:21:38 AM UTC 24 Sep 10 06:38:06 AM UTC 24 58098358230 ps
T1916 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.498926224 Sep 10 06:37:24 AM UTC 24 Sep 10 06:38:06 AM UTC 24 438271405 ps
T1917 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.295953132 Sep 10 06:17:45 AM UTC 24 Sep 10 06:38:15 AM UTC 24 77588406669 ps
T1918 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.2002995321 Sep 10 06:37:14 AM UTC 24 Sep 10 06:38:15 AM UTC 24 518544721 ps
T1919 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.2032328570 Sep 10 06:38:03 AM UTC 24 Sep 10 06:38:16 AM UTC 24 174783713 ps
T1920 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.1461597918 Sep 10 06:34:06 AM UTC 24 Sep 10 06:38:16 AM UTC 24 18935528302 ps
T1921 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.2544357074 Sep 10 06:38:09 AM UTC 24 Sep 10 06:38:16 AM UTC 24 47173073 ps
T1922 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.1196903097 Sep 10 06:36:57 AM UTC 24 Sep 10 06:38:21 AM UTC 24 4409818126 ps
T1923 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.904333224 Sep 10 06:36:53 AM UTC 24 Sep 10 06:38:28 AM UTC 24 11312171732 ps
T1924 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.3855989144 Sep 10 06:37:00 AM UTC 24 Sep 10 06:38:31 AM UTC 24 2125242232 ps
T1925 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.584521280 Sep 10 06:38:32 AM UTC 24 Sep 10 06:38:42 AM UTC 24 35171199 ps
T1926 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.3813343705 Sep 10 06:22:40 AM UTC 24 Sep 10 06:38:45 AM UTC 24 59782416008 ps
T1927 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.2873943953 Sep 10 06:34:59 AM UTC 24 Sep 10 06:38:50 AM UTC 24 2645605050 ps
T1928 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.1677292013 Sep 10 06:37:27 AM UTC 24 Sep 10 06:38:52 AM UTC 24 2673191041 ps
T1929 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.3788276234 Sep 10 06:37:36 AM UTC 24 Sep 10 06:38:55 AM UTC 24 1378319543 ps
T1930 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.1284984262 Sep 10 06:37:20 AM UTC 24 Sep 10 06:38:59 AM UTC 24 5712810980 ps
T1931 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.2919594288 Sep 10 06:38:42 AM UTC 24 Sep 10 06:39:01 AM UTC 24 257874427 ps
T1932 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.4028396291 Sep 10 06:35:47 AM UTC 24 Sep 10 06:39:03 AM UTC 24 10674524411 ps
T1933 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.1310095638 Sep 10 06:35:42 AM UTC 24 Sep 10 06:39:06 AM UTC 24 16910024677 ps
T1934 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.2581289421 Sep 10 06:38:28 AM UTC 24 Sep 10 06:39:07 AM UTC 24 309551822 ps
T1935 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.2645975877 Sep 10 06:27:46 AM UTC 24 Sep 10 06:39:17 AM UTC 24 47138902776 ps
T1936 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.4244297924 Sep 10 06:32:48 AM UTC 24 Sep 10 06:39:20 AM UTC 24 18412419328 ps
T1937 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.3727925568 Sep 10 06:38:45 AM UTC 24 Sep 10 06:39:22 AM UTC 24 364744848 ps
T1938 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.1633876772 Sep 10 06:39:14 AM UTC 24 Sep 10 06:39:25 AM UTC 24 138570572 ps
T1939 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.4002904508 Sep 10 06:38:43 AM UTC 24 Sep 10 06:39:30 AM UTC 24 2913359704 ps
T1940 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.4114579438 Sep 10 06:39:22 AM UTC 24 Sep 10 06:39:32 AM UTC 24 46971250 ps
T1941 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.354327769 Sep 10 06:38:12 AM UTC 24 Sep 10 06:39:43 AM UTC 24 9317069209 ps
T1942 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.85017085 Sep 10 06:38:55 AM UTC 24 Sep 10 06:39:44 AM UTC 24 1402528354 ps
T1943 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.580686504 Sep 10 06:38:50 AM UTC 24 Sep 10 06:39:45 AM UTC 24 915463765 ps
T1944 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.1527073142 Sep 10 06:38:44 AM UTC 24 Sep 10 06:39:48 AM UTC 24 2290157433 ps
T1945 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.1633639292 Sep 10 06:36:18 AM UTC 24 Sep 10 06:39:54 AM UTC 24 2884553750 ps
T1946 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.604107763 Sep 10 06:37:46 AM UTC 24 Sep 10 06:40:00 AM UTC 24 1587694018 ps
T1947 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.2612429925 Sep 10 06:22:41 AM UTC 24 Sep 10 06:40:01 AM UTC 24 65590418546 ps
T788 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.2306495777 Sep 10 06:30:33 AM UTC 24 Sep 10 06:40:03 AM UTC 24 17353981943 ps
T1948 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.4159760988 Sep 10 06:39:30 AM UTC 24 Sep 10 06:40:10 AM UTC 24 351912945 ps
T1949 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.3423777085 Sep 10 06:22:35 AM UTC 24 Sep 10 06:40:11 AM UTC 24 102728391803 ps
T1950 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.776193051 Sep 10 05:36:06 AM UTC 24 Sep 10 06:40:11 AM UTC 24 31414224564 ps
T1951 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.2963520737 Sep 10 06:39:24 AM UTC 24 Sep 10 06:40:14 AM UTC 24 4501423374 ps
T1952 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.3040653729 Sep 10 06:40:19 AM UTC 24 Sep 10 06:40:28 AM UTC 24 48010526 ps
T1953 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.115409768 Sep 10 06:38:21 AM UTC 24 Sep 10 06:40:29 AM UTC 24 6002987638 ps
T1954 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.3286845559 Sep 10 06:39:51 AM UTC 24 Sep 10 06:40:33 AM UTC 24 412580726 ps
T1955 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.1141660141 Sep 10 06:39:45 AM UTC 24 Sep 10 06:40:33 AM UTC 24 464687685 ps
T1956 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.2880351958 Sep 10 06:40:25 AM UTC 24 Sep 10 06:40:34 AM UTC 24 48799435 ps
T1957 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.3132433482 Sep 10 06:39:30 AM UTC 24 Sep 10 06:40:36 AM UTC 24 593263877 ps
T1958 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.2831679704 Sep 10 06:39:48 AM UTC 24 Sep 10 06:40:36 AM UTC 24 1165170631 ps
T1959 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.2998276271 Sep 10 06:39:58 AM UTC 24 Sep 10 06:40:44 AM UTC 24 1024698265 ps
T1960 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.3801308820 Sep 10 06:40:38 AM UTC 24 Sep 10 06:40:47 AM UTC 24 36110414 ps
T1961 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.2027849224 Sep 10 06:34:33 AM UTC 24 Sep 10 06:40:54 AM UTC 24 10450480512 ps
T1962 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.41739347 Sep 10 06:39:58 AM UTC 24 Sep 10 06:40:55 AM UTC 24 1309329308 ps
T1963 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.1395579531 Sep 10 06:25:57 AM UTC 24 Sep 10 06:41:02 AM UTC 24 53213581549 ps
T1964 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1956057725 Sep 10 06:39:28 AM UTC 24 Sep 10 06:41:09 AM UTC 24 5057568092 ps
T1965 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.1477554853 Sep 10 06:40:37 AM UTC 24 Sep 10 06:41:23 AM UTC 24 457941627 ps
T1966 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.3431263212 Sep 10 06:37:17 AM UTC 24 Sep 10 06:41:29 AM UTC 24 21112671243 ps
T1967 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.1742638682 Sep 10 06:41:23 AM UTC 24 Sep 10 06:41:32 AM UTC 24 44566431 ps
T1968 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.3911464531 Sep 10 06:41:10 AM UTC 24 Sep 10 06:41:35 AM UTC 24 345966341 ps
T1969 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.188203942 Sep 10 06:41:04 AM UTC 24 Sep 10 06:41:35 AM UTC 24 244947851 ps
T1970 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3652715297 Sep 10 06:41:28 AM UTC 24 Sep 10 06:41:37 AM UTC 24 48200872 ps
T1971 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.2439995057 Sep 10 06:40:57 AM UTC 24 Sep 10 06:41:37 AM UTC 24 506389413 ps
T1972 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.3236625028 Sep 10 06:37:40 AM UTC 24 Sep 10 06:41:47 AM UTC 24 2902860026 ps
T1973 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.3418145727 Sep 10 06:39:09 AM UTC 24 Sep 10 06:41:48 AM UTC 24 316612056 ps
T1974 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.1304661032 Sep 10 06:40:27 AM UTC 24 Sep 10 06:41:55 AM UTC 24 6044316694 ps
T1975 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.1285053339 Sep 10 06:40:11 AM UTC 24 Sep 10 06:42:05 AM UTC 24 1598375852 ps
T1976 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.2642781941 Sep 10 06:41:01 AM UTC 24 Sep 10 06:42:07 AM UTC 24 1372525053 ps
T1977 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.3080163929 Sep 10 06:40:56 AM UTC 24 Sep 10 06:42:09 AM UTC 24 1494004258 ps
T1978 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.2899716329 Sep 10 06:40:12 AM UTC 24 Sep 10 06:42:10 AM UTC 24 569797214 ps
T1979 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.3615252275 Sep 10 06:41:00 AM UTC 24 Sep 10 06:42:10 AM UTC 24 2084495523 ps
T1980 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.678813671 Sep 10 06:47:33 AM UTC 24 Sep 10 06:47:43 AM UTC 24 56724160 ps
T1981 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.2060569528 Sep 10 06:40:27 AM UTC 24 Sep 10 06:42:11 AM UTC 24 9680504048 ps
T1982 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.657263038 Sep 10 06:41:57 AM UTC 24 Sep 10 06:42:14 AM UTC 24 150185411 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.3314103677 Sep 10 06:42:05 AM UTC 24 Sep 10 06:42:22 AM UTC 24 171398843 ps
T1983 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.3679991560 Sep 10 06:42:13 AM UTC 24 Sep 10 06:42:31 AM UTC 24 125114743 ps
T1984 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.3252024291 Sep 10 06:42:37 AM UTC 24 Sep 10 06:42:44 AM UTC 24 40381636 ps
T1985 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.3337475801 Sep 10 06:42:21 AM UTC 24 Sep 10 06:42:46 AM UTC 24 356793526 ps
T1986 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.2230465900 Sep 10 06:42:41 AM UTC 24 Sep 10 06:42:52 AM UTC 24 50257580 ps
T1987 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.1218878685 Sep 10 06:09:01 AM UTC 24 Sep 10 06:42:56 AM UTC 24 125227979878 ps
T1988 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.4245881846 Sep 10 06:37:53 AM UTC 24 Sep 10 06:42:58 AM UTC 24 9532148975 ps
T1989 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.2289077756 Sep 10 06:42:14 AM UTC 24 Sep 10 06:43:02 AM UTC 24 534759280 ps
T1990 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.1294585385 Sep 10 06:41:52 AM UTC 24 Sep 10 06:43:12 AM UTC 24 2293080578 ps
T1991 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.2834124643 Sep 10 06:41:38 AM UTC 24 Sep 10 06:43:16 AM UTC 24 8189547576 ps
T1992 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.3925126150 Sep 10 06:39:14 AM UTC 24 Sep 10 06:43:16 AM UTC 24 2043238764 ps
T1993 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.2369106717 Sep 10 06:38:02 AM UTC 24 Sep 10 06:43:25 AM UTC 24 1016853162 ps
T1994 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.99407830 Sep 10 06:42:33 AM UTC 24 Sep 10 06:43:32 AM UTC 24 1238645336 ps
T1995 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.1631885740 Sep 10 06:43:14 AM UTC 24 Sep 10 06:43:35 AM UTC 24 135580232 ps
T1996 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.384423639 Sep 10 06:41:49 AM UTC 24 Sep 10 06:43:39 AM UTC 24 4871551203 ps
T1997 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.1798655148 Sep 10 06:42:52 AM UTC 24 Sep 10 06:43:48 AM UTC 24 3831941853 ps
T1998 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.4040108927 Sep 10 06:29:46 AM UTC 24 Sep 10 06:43:51 AM UTC 24 7326070191 ps
T1999 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.3100124945 Sep 10 06:43:42 AM UTC 24 Sep 10 06:43:51 AM UTC 24 46550779 ps
T2000 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.3221119078 Sep 10 06:43:51 AM UTC 24 Sep 10 06:44:01 AM UTC 24 74546160 ps
T2001 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.1611099451 Sep 10 06:43:24 AM UTC 24 Sep 10 06:44:03 AM UTC 24 331970983 ps
T2002 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.2968709118 Sep 10 06:43:38 AM UTC 24 Sep 10 06:44:09 AM UTC 24 284269594 ps
T2003 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.1217330218 Sep 10 06:34:58 AM UTC 24 Sep 10 06:44:11 AM UTC 24 5827987325 ps
T2004 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.642488512 Sep 10 06:36:18 AM UTC 24 Sep 10 06:44:26 AM UTC 24 5569195653 ps
T2005 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.2760633259 Sep 10 06:41:01 AM UTC 24 Sep 10 06:44:28 AM UTC 24 5876190171 ps
T873 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.272753708 Sep 10 06:40:09 AM UTC 24 Sep 10 06:44:28 AM UTC 24 693133057 ps
T2006 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.190875080 Sep 10 06:44:20 AM UTC 24 Sep 10 06:44:30 AM UTC 24 58596069 ps
T2007 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.2828750273 Sep 10 06:44:19 AM UTC 24 Sep 10 06:44:32 AM UTC 24 194357686 ps
T2008 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.4101642553 Sep 10 06:38:57 AM UTC 24 Sep 10 06:44:34 AM UTC 24 10958441033 ps
T2009 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.205714719 Sep 10 06:42:50 AM UTC 24 Sep 10 06:44:37 AM UTC 24 8953981077 ps
T2010 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.1634358260 Sep 10 06:43:12 AM UTC 24 Sep 10 06:44:41 AM UTC 24 2475739308 ps
T2011 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.2234728606 Sep 10 06:44:16 AM UTC 24 Sep 10 06:44:51 AM UTC 24 84316318 ps
T2012 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.4200450228 Sep 10 06:44:39 AM UTC 24 Sep 10 06:44:55 AM UTC 24 107872338 ps
T2013 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.426715635 Sep 10 06:33:16 AM UTC 24 Sep 10 06:45:00 AM UTC 24 6479831343 ps
T2014 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.1745702931 Sep 10 06:43:44 AM UTC 24 Sep 10 06:45:05 AM UTC 24 2057567435 ps
T2015 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.2434283678 Sep 10 06:41:11 AM UTC 24 Sep 10 06:45:08 AM UTC 24 510815461 ps
T2016 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.791218115 Sep 10 06:42:32 AM UTC 24 Sep 10 06:45:12 AM UTC 24 1922412864 ps
T2017 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.1717231937 Sep 10 06:45:05 AM UTC 24 Sep 10 06:45:20 AM UTC 24 159972096 ps
T2018 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.2167516405 Sep 10 06:44:59 AM UTC 24 Sep 10 06:45:21 AM UTC 24 265016170 ps
T2019 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.3963890896 Sep 10 06:44:37 AM UTC 24 Sep 10 06:45:22 AM UTC 24 393340946 ps
T2020 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.4240022537 Sep 10 06:41:23 AM UTC 24 Sep 10 06:45:30 AM UTC 24 1971388625 ps
T2021 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.3512595951 Sep 10 06:45:20 AM UTC 24 Sep 10 06:45:32 AM UTC 24 7725409 ps
T2022 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.1386372791 Sep 10 06:42:00 AM UTC 24 Sep 10 06:45:35 AM UTC 24 12969283879 ps
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