| T383 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.2690281254 |
|
|
Sep 10 05:24:36 AM UTC 24 |
Sep 10 06:05:44 AM UTC 24 |
16889597446 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.863080533 |
|
|
Sep 10 06:01:16 AM UTC 24 |
Sep 10 06:05:49 AM UTC 24 |
727340410 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.4026187915 |
|
|
Sep 10 06:04:17 AM UTC 24 |
Sep 10 06:06:00 AM UTC 24 |
2168460917 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.838977324 |
|
|
Sep 10 06:05:34 AM UTC 24 |
Sep 10 06:06:02 AM UTC 24 |
498186374 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.1458632158 |
|
|
Sep 10 06:04:41 AM UTC 24 |
Sep 10 06:06:05 AM UTC 24 |
2409538847 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.2530489074 |
|
|
Sep 10 06:05:50 AM UTC 24 |
Sep 10 06:06:07 AM UTC 24 |
252053953 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.1400599646 |
|
|
Sep 10 06:04:39 AM UTC 24 |
Sep 10 06:06:08 AM UTC 24 |
1552855981 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.3446969558 |
|
|
Sep 10 06:05:31 AM UTC 24 |
Sep 10 06:06:10 AM UTC 24 |
397666245 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.3033447184 |
|
|
Sep 10 06:05:49 AM UTC 24 |
Sep 10 06:06:13 AM UTC 24 |
376030588 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.4094971182 |
|
|
Sep 10 06:06:27 AM UTC 24 |
Sep 10 06:06:37 AM UTC 24 |
47964536 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.105581539 |
|
|
Sep 10 06:01:31 AM UTC 24 |
Sep 10 06:06:37 AM UTC 24 |
3567042035 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.1111459041 |
|
|
Sep 10 06:06:29 AM UTC 24 |
Sep 10 06:06:39 AM UTC 24 |
38479413 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.4294258027 |
|
|
Sep 10 05:51:16 AM UTC 24 |
Sep 10 06:06:53 AM UTC 24 |
50485509974 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.4111870102 |
|
|
Sep 10 06:06:08 AM UTC 24 |
Sep 10 06:06:57 AM UTC 24 |
106100138 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.3128569068 |
|
|
Sep 10 06:06:36 AM UTC 24 |
Sep 10 06:07:09 AM UTC 24 |
331587185 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.1434871601 |
|
|
Sep 10 06:01:31 AM UTC 24 |
Sep 10 06:07:13 AM UTC 24 |
4358259992 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.817970645 |
|
|
Sep 10 06:00:31 AM UTC 24 |
Sep 10 06:07:21 AM UTC 24 |
27258252798 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.179376292 |
|
|
Sep 10 06:06:37 AM UTC 24 |
Sep 10 06:07:22 AM UTC 24 |
325487967 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.3531499405 |
|
|
Sep 10 06:07:05 AM UTC 24 |
Sep 10 06:07:35 AM UTC 24 |
691873054 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.4004245983 |
|
|
Sep 10 06:07:17 AM UTC 24 |
Sep 10 06:07:37 AM UTC 24 |
165567827 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.1535876149 |
|
|
Sep 10 06:06:34 AM UTC 24 |
Sep 10 06:07:49 AM UTC 24 |
4301548441 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.2204413834 |
|
|
Sep 10 05:52:11 AM UTC 24 |
Sep 10 06:07:53 AM UTC 24 |
10695399484 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.2041824366 |
|
|
Sep 10 06:06:04 AM UTC 24 |
Sep 10 06:07:57 AM UTC 24 |
3380862127 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.2955056581 |
|
|
Sep 10 06:07:24 AM UTC 24 |
Sep 10 06:08:04 AM UTC 24 |
413429820 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.3750971265 |
|
|
Sep 10 06:07:41 AM UTC 24 |
Sep 10 06:08:09 AM UTC 24 |
659416745 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.1226903737 |
|
|
Sep 10 06:03:38 AM UTC 24 |
Sep 10 06:08:10 AM UTC 24 |
3863110650 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.400287279 |
|
|
Sep 10 06:07:35 AM UTC 24 |
Sep 10 06:08:17 AM UTC 24 |
233874375 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.2936504411 |
|
|
Sep 10 06:00:11 AM UTC 24 |
Sep 10 06:08:19 AM UTC 24 |
4449206296 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.3493806719 |
|
|
Sep 10 06:02:15 AM UTC 24 |
Sep 10 06:08:29 AM UTC 24 |
30173287122 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.860728289 |
|
|
Sep 10 06:08:21 AM UTC 24 |
Sep 10 06:08:31 AM UTC 24 |
47782412 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.3085741327 |
|
|
Sep 10 05:50:11 AM UTC 24 |
Sep 10 06:08:32 AM UTC 24 |
9499074992 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.2827915447 |
|
|
Sep 10 06:08:24 AM UTC 24 |
Sep 10 06:08:34 AM UTC 24 |
46525855 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.2043150181 |
|
|
Sep 10 06:06:31 AM UTC 24 |
Sep 10 06:08:35 AM UTC 24 |
8567419089 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.778035822 |
|
|
Sep 10 06:03:41 AM UTC 24 |
Sep 10 06:08:37 AM UTC 24 |
974371620 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.340762480 |
|
|
Sep 10 06:09:00 AM UTC 24 |
Sep 10 06:09:13 AM UTC 24 |
250294171 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.2419896805 |
|
|
Sep 10 06:09:04 AM UTC 24 |
Sep 10 06:09:22 AM UTC 24 |
283608142 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.1006952134 |
|
|
Sep 10 06:08:42 AM UTC 24 |
Sep 10 06:09:29 AM UTC 24 |
368560929 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.918166379 |
|
|
Sep 10 06:08:38 AM UTC 24 |
Sep 10 06:09:41 AM UTC 24 |
1305690132 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.3849991536 |
|
|
Sep 10 05:54:49 AM UTC 24 |
Sep 10 06:09:47 AM UTC 24 |
11294316882 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.899949387 |
|
|
Sep 10 06:09:00 AM UTC 24 |
Sep 10 06:09:49 AM UTC 24 |
408752163 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.1439456388 |
|
|
Sep 10 06:09:41 AM UTC 24 |
Sep 10 06:09:56 AM UTC 24 |
256850988 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.4106145576 |
|
|
Sep 10 06:00:08 AM UTC 24 |
Sep 10 06:09:58 AM UTC 24 |
4378639806 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.3208902027 |
|
|
Sep 10 06:07:49 AM UTC 24 |
Sep 10 06:09:58 AM UTC 24 |
236210635 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.1342032475 |
|
|
Sep 10 06:08:36 AM UTC 24 |
Sep 10 06:10:02 AM UTC 24 |
4987660472 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.1934077711 |
|
|
Sep 10 06:03:32 AM UTC 24 |
Sep 10 06:10:04 AM UTC 24 |
10745004608 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.3552204403 |
|
|
Sep 10 06:08:32 AM UTC 24 |
Sep 10 06:10:22 AM UTC 24 |
9799596423 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.487804244 |
|
|
Sep 10 06:10:22 AM UTC 24 |
Sep 10 06:10:34 AM UTC 24 |
200462247 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.2766569011 |
|
|
Sep 10 06:10:26 AM UTC 24 |
Sep 10 06:10:36 AM UTC 24 |
57563521 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.1522274871 |
|
|
Sep 10 06:09:03 AM UTC 24 |
Sep 10 06:10:49 AM UTC 24 |
2417204653 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.863870718 |
|
|
Sep 10 05:58:26 AM UTC 24 |
Sep 10 06:10:51 AM UTC 24 |
81003939844 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.2057730416 |
|
|
Sep 10 06:10:16 AM UTC 24 |
Sep 10 06:10:52 AM UTC 24 |
265586260 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.2261530977 |
|
|
Sep 10 05:38:27 AM UTC 24 |
Sep 10 06:10:56 AM UTC 24 |
16019490735 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.318653278 |
|
|
Sep 10 05:02:52 AM UTC 24 |
Sep 10 06:10:58 AM UTC 24 |
29603919834 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.2491987077 |
|
|
Sep 10 06:10:49 AM UTC 24 |
Sep 10 06:11:05 AM UTC 24 |
146738307 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1402698492 |
|
|
Sep 10 06:04:40 AM UTC 24 |
Sep 10 06:11:27 AM UTC 24 |
23619330153 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.2053764435 |
|
|
Sep 10 06:11:23 AM UTC 24 |
Sep 10 06:11:33 AM UTC 24 |
38861715 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.1807956548 |
|
|
Sep 10 06:00:30 AM UTC 24 |
Sep 10 06:11:35 AM UTC 24 |
42404045583 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.2115387751 |
|
|
Sep 10 06:11:20 AM UTC 24 |
Sep 10 06:11:37 AM UTC 24 |
286116137 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.893056337 |
|
|
Sep 10 06:05:54 AM UTC 24 |
Sep 10 06:11:37 AM UTC 24 |
544180592 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.2422937596 |
|
|
Sep 10 06:11:25 AM UTC 24 |
Sep 10 06:11:41 AM UTC 24 |
74891570 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.1984663031 |
|
|
Sep 10 06:10:30 AM UTC 24 |
Sep 10 06:11:44 AM UTC 24 |
5095482189 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.1711102520 |
|
|
Sep 10 06:10:31 AM UTC 24 |
Sep 10 06:11:46 AM UTC 24 |
1517215881 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.2137578717 |
|
|
Sep 10 06:06:15 AM UTC 24 |
Sep 10 06:11:48 AM UTC 24 |
3851390127 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.3635468076 |
|
|
Sep 10 06:11:34 AM UTC 24 |
Sep 10 06:11:51 AM UTC 24 |
224498502 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.2205581389 |
|
|
Sep 10 05:47:08 AM UTC 24 |
Sep 10 06:11:52 AM UTC 24 |
16746326794 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.3534911777 |
|
|
Sep 10 05:58:28 AM UTC 24 |
Sep 10 06:11:58 AM UTC 24 |
53202623889 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.4110653915 |
|
|
Sep 10 05:49:03 AM UTC 24 |
Sep 10 06:12:16 AM UTC 24 |
95125043827 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.482582074 |
|
|
Sep 10 06:12:06 AM UTC 24 |
Sep 10 06:12:19 AM UTC 24 |
190790270 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.1034256845 |
|
|
Sep 10 06:10:26 AM UTC 24 |
Sep 10 06:12:22 AM UTC 24 |
10616430757 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.3361037426 |
|
|
Sep 10 06:12:11 AM UTC 24 |
Sep 10 06:12:22 AM UTC 24 |
53659907 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.56609879 |
|
|
Sep 10 06:10:09 AM UTC 24 |
Sep 10 06:12:24 AM UTC 24 |
3156154906 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.164236073 |
|
|
Sep 10 06:12:02 AM UTC 24 |
Sep 10 06:12:28 AM UTC 24 |
176738633 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.3159322757 |
|
|
Sep 10 06:02:26 AM UTC 24 |
Sep 10 06:12:31 AM UTC 24 |
42345217828 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.650011772 |
|
|
Sep 10 06:11:17 AM UTC 24 |
Sep 10 06:12:34 AM UTC 24 |
1292641816 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.967858529 |
|
|
Sep 10 06:08:02 AM UTC 24 |
Sep 10 06:12:41 AM UTC 24 |
2707253651 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.689129236 |
|
|
Sep 10 06:12:16 AM UTC 24 |
Sep 10 06:12:45 AM UTC 24 |
255906087 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.2172571649 |
|
|
Sep 10 06:09:56 AM UTC 24 |
Sep 10 06:12:55 AM UTC 24 |
379345170 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.997335240 |
|
|
Sep 10 05:42:25 AM UTC 24 |
Sep 10 06:12:56 AM UTC 24 |
123216214946 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.3461312276 |
|
|
Sep 10 06:12:50 AM UTC 24 |
Sep 10 06:13:03 AM UTC 24 |
141834811 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.944801791 |
|
|
Sep 10 06:12:48 AM UTC 24 |
Sep 10 06:13:22 AM UTC 24 |
978553648 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.2861726274 |
|
|
Sep 10 06:09:51 AM UTC 24 |
Sep 10 06:13:25 AM UTC 24 |
2089502282 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.1249054482 |
|
|
Sep 10 06:12:56 AM UTC 24 |
Sep 10 06:13:26 AM UTC 24 |
178124198 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.3822656241 |
|
|
Sep 10 06:12:19 AM UTC 24 |
Sep 10 06:13:28 AM UTC 24 |
585384755 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.2935371001 |
|
|
Sep 10 06:12:14 AM UTC 24 |
Sep 10 06:13:30 AM UTC 24 |
3476679338 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.3668020641 |
|
|
Sep 10 06:12:56 AM UTC 24 |
Sep 10 06:13:34 AM UTC 24 |
915898975 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.160780443 |
|
|
Sep 10 06:13:30 AM UTC 24 |
Sep 10 06:13:40 AM UTC 24 |
43972726 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.3093367546 |
|
|
Sep 10 06:12:45 AM UTC 24 |
Sep 10 06:13:43 AM UTC 24 |
973873369 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.3665636862 |
|
|
Sep 10 06:12:14 AM UTC 24 |
Sep 10 06:13:49 AM UTC 24 |
8513689649 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.2600612280 |
|
|
Sep 10 06:13:48 AM UTC 24 |
Sep 10 06:13:59 AM UTC 24 |
57321939 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.2638439648 |
|
|
Sep 10 06:08:16 AM UTC 24 |
Sep 10 06:14:09 AM UTC 24 |
4345766367 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.2953778882 |
|
|
Sep 10 05:30:13 AM UTC 24 |
Sep 10 06:14:16 AM UTC 24 |
17906947124 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.2210309700 |
|
|
Sep 10 06:13:56 AM UTC 24 |
Sep 10 06:14:32 AM UTC 24 |
259258497 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.2674514766 |
|
|
Sep 10 06:00:49 AM UTC 24 |
Sep 10 06:14:35 AM UTC 24 |
51774901942 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.2276941655 |
|
|
Sep 10 06:13:53 AM UTC 24 |
Sep 10 06:14:35 AM UTC 24 |
443002776 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.2588927935 |
|
|
Sep 10 06:14:26 AM UTC 24 |
Sep 10 06:14:41 AM UTC 24 |
206687512 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.1146966298 |
|
|
Sep 10 06:07:06 AM UTC 24 |
Sep 10 06:14:42 AM UTC 24 |
27651148249 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.1302136183 |
|
|
Sep 10 06:11:54 AM UTC 24 |
Sep 10 06:14:46 AM UTC 24 |
4956310171 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.508241819 |
|
|
Sep 10 05:43:47 AM UTC 24 |
Sep 10 06:14:47 AM UTC 24 |
15402101816 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.848126263 |
|
|
Sep 10 06:14:36 AM UTC 24 |
Sep 10 06:14:51 AM UTC 24 |
106689574 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.3997003457 |
|
|
Sep 10 06:14:44 AM UTC 24 |
Sep 10 06:14:54 AM UTC 24 |
39567528 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.2636840291 |
|
|
Sep 10 06:12:58 AM UTC 24 |
Sep 10 06:15:02 AM UTC 24 |
1455801454 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.3704947875 |
|
|
Sep 10 06:14:59 AM UTC 24 |
Sep 10 06:15:14 AM UTC 24 |
71962989 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.2936948154 |
|
|
Sep 10 06:04:24 AM UTC 24 |
Sep 10 06:15:17 AM UTC 24 |
65086436684 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.2027079818 |
|
|
Sep 10 06:15:13 AM UTC 24 |
Sep 10 06:15:21 AM UTC 24 |
45383821 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2184738733 |
|
|
Sep 10 06:15:13 AM UTC 24 |
Sep 10 06:15:23 AM UTC 24 |
38010583 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.912379756 |
|
|
Sep 10 06:06:38 AM UTC 24 |
Sep 10 06:15:24 AM UTC 24 |
38362326864 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.1280298442 |
|
|
Sep 10 06:13:51 AM UTC 24 |
Sep 10 06:15:26 AM UTC 24 |
5881686415 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.1242575411 |
|
|
Sep 10 06:13:51 AM UTC 24 |
Sep 10 06:15:34 AM UTC 24 |
5848882542 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.2595002374 |
|
|
Sep 10 06:12:05 AM UTC 24 |
Sep 10 06:15:38 AM UTC 24 |
3522498216 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.353583932 |
|
|
Sep 10 05:04:57 AM UTC 24 |
Sep 10 06:16:02 AM UTC 24 |
28500330478 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.2525218587 |
|
|
Sep 10 06:14:10 AM UTC 24 |
Sep 10 06:16:06 AM UTC 24 |
2794217358 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.2578186349 |
|
|
Sep 10 06:16:06 AM UTC 24 |
Sep 10 06:16:19 AM UTC 24 |
137385481 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.1370648513 |
|
|
Sep 10 06:15:21 AM UTC 24 |
Sep 10 06:16:32 AM UTC 24 |
5566454632 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.3847372997 |
|
|
Sep 10 06:13:11 AM UTC 24 |
Sep 10 06:16:36 AM UTC 24 |
4390633069 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.3898454292 |
|
|
Sep 10 06:15:42 AM UTC 24 |
Sep 10 06:16:42 AM UTC 24 |
650247538 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.2991005215 |
|
|
Sep 10 06:10:17 AM UTC 24 |
Sep 10 06:16:50 AM UTC 24 |
4030998300 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.1691386730 |
|
|
Sep 10 06:15:49 AM UTC 24 |
Sep 10 06:16:52 AM UTC 24 |
520661121 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.202611184 |
|
|
Sep 10 06:15:06 AM UTC 24 |
Sep 10 06:17:04 AM UTC 24 |
1341978493 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.2252058160 |
|
|
Sep 10 06:15:58 AM UTC 24 |
Sep 10 06:17:09 AM UTC 24 |
1817533776 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.2816102124 |
|
|
Sep 10 06:15:54 AM UTC 24 |
Sep 10 06:17:10 AM UTC 24 |
2542567693 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.1193598307 |
|
|
Sep 10 06:16:33 AM UTC 24 |
Sep 10 06:17:12 AM UTC 24 |
362314374 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.3189687225 |
|
|
Sep 10 06:16:29 AM UTC 24 |
Sep 10 06:17:13 AM UTC 24 |
1094765461 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.1510852942 |
|
|
Sep 10 06:17:09 AM UTC 24 |
Sep 10 06:17:19 AM UTC 24 |
201259284 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.3419423013 |
|
|
Sep 10 06:07:49 AM UTC 24 |
Sep 10 06:17:20 AM UTC 24 |
5306191593 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.1439141367 |
|
|
Sep 10 06:15:28 AM UTC 24 |
Sep 10 06:17:21 AM UTC 24 |
2373478267 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.3753224725 |
|
|
Sep 10 06:15:18 AM UTC 24 |
Sep 10 06:17:23 AM UTC 24 |
8745717075 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.290245721 |
|
|
Sep 10 06:17:17 AM UTC 24 |
Sep 10 06:17:28 AM UTC 24 |
52312036 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.3154210677 |
|
|
Sep 10 06:04:33 AM UTC 24 |
Sep 10 06:17:46 AM UTC 24 |
51990098031 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.1664439270 |
|
|
Sep 10 06:13:23 AM UTC 24 |
Sep 10 06:18:13 AM UTC 24 |
3442345565 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.1873733141 |
|
|
Sep 10 06:17:55 AM UTC 24 |
Sep 10 06:18:22 AM UTC 24 |
450149761 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.4075947869 |
|
|
Sep 10 06:17:49 AM UTC 24 |
Sep 10 06:18:22 AM UTC 24 |
613330680 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.2344014056 |
|
|
Sep 10 06:17:45 AM UTC 24 |
Sep 10 06:18:23 AM UTC 24 |
652398531 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.3397835755 |
|
|
Sep 10 06:18:07 AM UTC 24 |
Sep 10 06:18:25 AM UTC 24 |
94792043 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.1282074975 |
|
|
Sep 10 06:17:48 AM UTC 24 |
Sep 10 06:18:26 AM UTC 24 |
874565922 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.196611501 |
|
|
Sep 10 06:17:37 AM UTC 24 |
Sep 10 06:18:34 AM UTC 24 |
514397423 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.1911526587 |
|
|
Sep 10 06:13:22 AM UTC 24 |
Sep 10 06:18:48 AM UTC 24 |
7639563575 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.2441595848 |
|
|
Sep 10 06:17:31 AM UTC 24 |
Sep 10 06:18:49 AM UTC 24 |
5323886785 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.2152085794 |
|
|
Sep 10 06:14:59 AM UTC 24 |
Sep 10 06:18:52 AM UTC 24 |
1920071976 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.518977520 |
|
|
Sep 10 06:18:47 AM UTC 24 |
Sep 10 06:18:54 AM UTC 24 |
42361940 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.26166120 |
|
|
Sep 10 06:18:49 AM UTC 24 |
Sep 10 06:18:59 AM UTC 24 |
39114118 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.3648772524 |
|
|
Sep 10 06:17:02 AM UTC 24 |
Sep 10 06:19:07 AM UTC 24 |
876064233 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.1243025229 |
|
|
Sep 10 06:17:36 AM UTC 24 |
Sep 10 06:19:26 AM UTC 24 |
2193950164 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.423291156 |
|
|
Sep 10 06:17:19 AM UTC 24 |
Sep 10 06:19:33 AM UTC 24 |
8027453893 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.154443801 |
|
|
Sep 10 06:19:11 AM UTC 24 |
Sep 10 06:19:40 AM UTC 24 |
482769882 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.1020227381 |
|
|
Sep 10 06:19:15 AM UTC 24 |
Sep 10 06:19:42 AM UTC 24 |
221890245 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.1483637859 |
|
|
Sep 10 05:13:22 AM UTC 24 |
Sep 10 06:19:42 AM UTC 24 |
30070191444 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.3606615475 |
|
|
Sep 10 05:56:07 AM UTC 24 |
Sep 10 06:19:50 AM UTC 24 |
85881350954 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.3750230361 |
|
|
Sep 10 06:18:44 AM UTC 24 |
Sep 10 06:19:52 AM UTC 24 |
225355888 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.2420939998 |
|
|
Sep 10 06:19:01 AM UTC 24 |
Sep 10 06:20:10 AM UTC 24 |
4765911380 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.2082445515 |
|
|
Sep 10 06:15:41 AM UTC 24 |
Sep 10 06:20:11 AM UTC 24 |
26872602782 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.2638546432 |
|
|
Sep 10 06:19:54 AM UTC 24 |
Sep 10 06:20:21 AM UTC 24 |
337217207 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.2769426867 |
|
|
Sep 10 06:20:08 AM UTC 24 |
Sep 10 06:20:27 AM UTC 24 |
142014248 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.3670124737 |
|
|
Sep 10 06:17:00 AM UTC 24 |
Sep 10 06:20:29 AM UTC 24 |
5517515245 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.1173213479 |
|
|
Sep 10 06:20:06 AM UTC 24 |
Sep 10 06:20:34 AM UTC 24 |
169858091 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.1177404672 |
|
|
Sep 10 06:20:00 AM UTC 24 |
Sep 10 06:20:47 AM UTC 24 |
540516627 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.3012021746 |
|
|
Sep 10 06:20:39 AM UTC 24 |
Sep 10 06:20:50 AM UTC 24 |
58992463 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.2647210804 |
|
|
Sep 10 05:53:02 AM UTC 24 |
Sep 10 06:20:55 AM UTC 24 |
119915190015 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.2840162807 |
|
|
Sep 10 06:20:50 AM UTC 24 |
Sep 10 06:21:01 AM UTC 24 |
58151746 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.2942405354 |
|
|
Sep 10 06:21:01 AM UTC 24 |
Sep 10 06:21:10 AM UTC 24 |
79597009 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.3810192534 |
|
|
Sep 10 06:18:50 AM UTC 24 |
Sep 10 06:21:14 AM UTC 24 |
9337428769 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.2546475315 |
|
|
Sep 10 06:11:00 AM UTC 24 |
Sep 10 06:21:17 AM UTC 24 |
61984444282 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.3156849687 |
|
|
Sep 10 06:11:02 AM UTC 24 |
Sep 10 06:21:20 AM UTC 24 |
44630936982 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.4140450833 |
|
|
Sep 10 06:20:17 AM UTC 24 |
Sep 10 06:21:23 AM UTC 24 |
1533968931 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.4117871318 |
|
|
Sep 10 06:12:01 AM UTC 24 |
Sep 10 06:21:23 AM UTC 24 |
10977855359 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.2312239332 |
|
|
Sep 10 06:12:41 AM UTC 24 |
Sep 10 06:21:29 AM UTC 24 |
29854691775 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.1450786504 |
|
|
Sep 10 06:08:54 AM UTC 24 |
Sep 10 06:21:36 AM UTC 24 |
45386697867 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.1656720884 |
|
|
Sep 10 06:13:06 AM UTC 24 |
Sep 10 06:21:36 AM UTC 24 |
4940223085 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.3557065214 |
|
|
Sep 10 06:21:27 AM UTC 24 |
Sep 10 06:21:39 AM UTC 24 |
79908379 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.3418568905 |
|
|
Sep 10 06:19:25 AM UTC 24 |
Sep 10 06:21:46 AM UTC 24 |
2792839924 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.686828055 |
|
|
Sep 10 06:21:16 AM UTC 24 |
Sep 10 06:21:55 AM UTC 24 |
283797505 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.1569877007 |
|
|
Sep 10 06:08:03 AM UTC 24 |
Sep 10 06:22:00 AM UTC 24 |
16876429647 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.1086798087 |
|
|
Sep 10 06:14:15 AM UTC 24 |
Sep 10 06:22:01 AM UTC 24 |
32131231348 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.3145900767 |
|
|
Sep 10 06:21:52 AM UTC 24 |
Sep 10 06:22:05 AM UTC 24 |
58017682 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.941632655 |
|
|
Sep 10 06:21:22 AM UTC 24 |
Sep 10 06:22:08 AM UTC 24 |
2551610526 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.2704992297 |
|
|
Sep 10 06:20:56 AM UTC 24 |
Sep 10 06:22:13 AM UTC 24 |
3156046493 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.939049550 |
|
|
Sep 10 06:14:08 AM UTC 24 |
Sep 10 06:22:14 AM UTC 24 |
34982826433 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.1225574521 |
|
|
Sep 10 06:22:04 AM UTC 24 |
Sep 10 06:22:14 AM UTC 24 |
237577024 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.1390441811 |
|
|
Sep 10 06:16:46 AM UTC 24 |
Sep 10 06:22:16 AM UTC 24 |
3383030591 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.403588080 |
|
|
Sep 10 06:22:10 AM UTC 24 |
Sep 10 06:22:18 AM UTC 24 |
42901384 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.906524877 |
|
|
Sep 10 06:21:41 AM UTC 24 |
Sep 10 06:22:22 AM UTC 24 |
370759109 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.2771387933 |
|
|
Sep 10 06:20:54 AM UTC 24 |
Sep 10 06:22:23 AM UTC 24 |
5044405705 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.388807214 |
|
|
Sep 10 05:51:23 AM UTC 24 |
Sep 10 06:22:27 AM UTC 24 |
126343751974 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.2299723777 |
|
|
Sep 10 06:20:17 AM UTC 24 |
Sep 10 06:22:32 AM UTC 24 |
503782989 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.2661494237 |
|
|
Sep 10 06:21:44 AM UTC 24 |
Sep 10 06:22:34 AM UTC 24 |
543162962 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.4025291776 |
|
|
Sep 10 05:18:23 AM UTC 24 |
Sep 10 06:22:37 AM UTC 24 |
29452803115 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.3444433363 |
|
|
Sep 10 06:12:05 AM UTC 24 |
Sep 10 06:22:42 AM UTC 24 |
14025045773 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.793109286 |
|
|
Sep 10 06:15:08 AM UTC 24 |
Sep 10 06:22:49 AM UTC 24 |
3745632823 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.3569298792 |
|
|
Sep 10 05:58:39 AM UTC 24 |
Sep 10 06:22:49 AM UTC 24 |
94560235601 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.2454549605 |
|
|
Sep 10 06:15:03 AM UTC 24 |
Sep 10 06:22:49 AM UTC 24 |
3628667508 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.1078343842 |
|
|
Sep 10 06:18:36 AM UTC 24 |
Sep 10 06:22:53 AM UTC 24 |
445174547 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.832440893 |
|
|
Sep 10 05:16:27 AM UTC 24 |
Sep 10 06:22:54 AM UTC 24 |
27733791508 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.3158157546 |
|
|
Sep 10 06:19:36 AM UTC 24 |
Sep 10 06:22:56 AM UTC 24 |
14074069276 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.3151281287 |
|
|
Sep 10 06:22:32 AM UTC 24 |
Sep 10 06:23:00 AM UTC 24 |
295695824 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.3542850893 |
|
|
Sep 10 06:22:27 AM UTC 24 |
Sep 10 06:23:04 AM UTC 24 |
767030612 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.4063920953 |
|
|
Sep 10 06:22:42 AM UTC 24 |
Sep 10 06:23:05 AM UTC 24 |
588040952 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.3014995800 |
|
|
Sep 10 06:21:45 AM UTC 24 |
Sep 10 06:23:05 AM UTC 24 |
1337098371 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.68243530 |
|
|
Sep 10 06:22:46 AM UTC 24 |
Sep 10 06:23:07 AM UTC 24 |
105931417 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.1849193614 |
|
|
Sep 10 06:23:06 AM UTC 24 |
Sep 10 06:23:16 AM UTC 24 |
206807269 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.1791803158 |
|
|
Sep 10 06:08:47 AM UTC 24 |
Sep 10 06:23:19 AM UTC 24 |
76739304822 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.1888526938 |
|
|
Sep 10 04:58:32 AM UTC 24 |
Sep 10 06:23:24 AM UTC 24 |
49440837251 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.2864966427 |
|
|
Sep 10 06:23:17 AM UTC 24 |
Sep 10 06:23:27 AM UTC 24 |
45334463 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.3738765638 |
|
|
Sep 10 06:22:58 AM UTC 24 |
Sep 10 06:23:30 AM UTC 24 |
89407319 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.3423035364 |
|
|
Sep 10 06:22:43 AM UTC 24 |
Sep 10 06:23:33 AM UTC 24 |
512045320 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.805529386 |
|
|
Sep 10 06:18:48 AM UTC 24 |
Sep 10 06:23:38 AM UTC 24 |
4142938126 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.3874779039 |
|
|
Sep 10 06:23:19 AM UTC 24 |
Sep 10 06:23:40 AM UTC 24 |
156412018 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.3241852395 |
|
|
Sep 10 06:22:27 AM UTC 24 |
Sep 10 06:23:42 AM UTC 24 |
5244858344 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.3871772910 |
|
|
Sep 10 06:22:47 AM UTC 24 |
Sep 10 06:23:42 AM UTC 24 |
1450343416 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.486683803 |
|
|
Sep 10 06:23:30 AM UTC 24 |
Sep 10 06:23:43 AM UTC 24 |
133589110 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.1693434223 |
|
|
Sep 10 06:23:22 AM UTC 24 |
Sep 10 06:23:58 AM UTC 24 |
352672357 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.2833359315 |
|
|
Sep 10 06:23:43 AM UTC 24 |
Sep 10 06:24:00 AM UTC 24 |
85906248 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.521233483 |
|
|
Sep 10 06:23:44 AM UTC 24 |
Sep 10 06:24:07 AM UTC 24 |
131685662 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.585302631 |
|
|
Sep 10 06:22:41 AM UTC 24 |
Sep 10 06:24:09 AM UTC 24 |
2344731838 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.3685818373 |
|
|
Sep 10 06:23:32 AM UTC 24 |
Sep 10 06:24:12 AM UTC 24 |
498244998 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.1909272159 |
|
|
Sep 10 06:18:14 AM UTC 24 |
Sep 10 06:24:13 AM UTC 24 |
4093663246 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.2112880589 |
|
|
Sep 10 06:24:04 AM UTC 24 |
Sep 10 06:24:14 AM UTC 24 |
44906005 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.1789217530 |
|
|
Sep 10 06:24:08 AM UTC 24 |
Sep 10 06:24:16 AM UTC 24 |
55497292 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.527886035 |
|
|
Sep 10 06:17:41 AM UTC 24 |
Sep 10 06:24:21 AM UTC 24 |
23692954874 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.1422762398 |
|
|
Sep 10 06:22:20 AM UTC 24 |
Sep 10 06:24:22 AM UTC 24 |
8797830805 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.2282528732 |
|
|
Sep 10 06:17:37 AM UTC 24 |
Sep 10 06:24:25 AM UTC 24 |
44640361291 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.2385698812 |
|
|
Sep 10 06:24:21 AM UTC 24 |
Sep 10 06:24:35 AM UTC 24 |
80454586 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.504548142 |
|
|
Sep 10 06:24:10 AM UTC 24 |
Sep 10 06:24:41 AM UTC 24 |
561278869 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.167666658 |
|
|
Sep 10 06:23:16 AM UTC 24 |
Sep 10 06:24:50 AM UTC 24 |
5193560250 ps |
| T1763 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.1538111262 |
|
|
Sep 10 06:23:16 AM UTC 24 |
Sep 10 06:24:59 AM UTC 24 |
9115945659 ps |
| T1764 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.1193391017 |
|
|
Sep 10 06:24:43 AM UTC 24 |
Sep 10 06:24:59 AM UTC 24 |
100881806 ps |
| T1765 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.2535997165 |
|
|
Sep 10 06:24:36 AM UTC 24 |
Sep 10 06:25:00 AM UTC 24 |
400631952 ps |
| T1766 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.199263277 |
|
|
Sep 10 06:23:31 AM UTC 24 |
Sep 10 06:25:07 AM UTC 24 |
2275357408 ps |
| T1767 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.2646389581 |
|
|
Sep 10 06:24:08 AM UTC 24 |
Sep 10 06:25:18 AM UTC 24 |
5490829419 ps |
| T1768 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.1708115302 |
|
|
Sep 10 06:24:49 AM UTC 24 |
Sep 10 06:25:22 AM UTC 24 |
256105005 ps |
| T1769 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.782571652 |
|
|
Sep 10 06:25:18 AM UTC 24 |
Sep 10 06:25:28 AM UTC 24 |
50638758 ps |
| T1770 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.2576128330 |
|
|
Sep 10 06:24:08 AM UTC 24 |
Sep 10 06:25:34 AM UTC 24 |
9311370552 ps |
| T1771 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.3820649206 |
|
|
Sep 10 06:24:43 AM UTC 24 |
Sep 10 06:25:34 AM UTC 24 |
1088637045 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.184619465 |
|
|
Sep 10 06:20:08 AM UTC 24 |
Sep 10 06:25:35 AM UTC 24 |
8141826665 ps |
| T1772 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.1950407503 |
|
|
Sep 10 06:24:37 AM UTC 24 |
Sep 10 06:25:38 AM UTC 24 |
1847585274 ps |
| T1773 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.1082916102 |
|
|
Sep 10 06:25:27 AM UTC 24 |
Sep 10 06:25:38 AM UTC 24 |
56456095 ps |
| T1774 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.2972418038 |
|
|
Sep 10 06:25:34 AM UTC 24 |
Sep 10 06:26:06 AM UTC 24 |
300662124 ps |
| T1775 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.2447986245 |
|
|
Sep 10 06:23:46 AM UTC 24 |
Sep 10 06:26:08 AM UTC 24 |
4040711876 ps |
| T1776 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.3763948171 |
|
|
Sep 10 06:26:03 AM UTC 24 |
Sep 10 06:26:13 AM UTC 24 |
158711207 ps |
| T1777 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_aliasing.2021833898 |
|
|
Sep 10 05:04:53 AM UTC 24 |
Sep 10 06:26:15 AM UTC 24 |
36343249568 ps |
| T1778 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.2019499744 |
|
|
Sep 10 06:26:04 AM UTC 24 |
Sep 10 06:26:29 AM UTC 24 |
199326186 ps |
| T1779 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.171150478 |
|
|
Sep 10 06:21:18 AM UTC 24 |
Sep 10 06:26:34 AM UTC 24 |
29743212342 ps |
| T1780 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.3774613443 |
|
|
Sep 10 06:25:45 AM UTC 24 |
Sep 10 06:26:37 AM UTC 24 |
553629959 ps |
| T1781 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.4193282254 |
|
|
Sep 10 06:26:34 AM UTC 24 |
Sep 10 06:26:44 AM UTC 24 |
79704638 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1540050482 |
|
|
Sep 10 06:25:09 AM UTC 24 |
Sep 10 06:27:01 AM UTC 24 |
290535361 ps |
| T1782 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.2141289815 |
|
|
Sep 10 06:26:02 AM UTC 24 |
Sep 10 06:27:06 AM UTC 24 |
739450864 ps |
| T1783 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.750937675 |
|
|
Sep 10 06:27:02 AM UTC 24 |
Sep 10 06:27:13 AM UTC 24 |
177858089 ps |
| T1784 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.500479605 |
|
|
Sep 10 06:27:05 AM UTC 24 |
Sep 10 06:27:15 AM UTC 24 |
49460079 ps |
| T1785 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.4254344815 |
|
|
Sep 10 06:26:06 AM UTC 24 |
Sep 10 06:27:21 AM UTC 24 |
1408371487 ps |
| T1786 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.1939855644 |
|
|
Sep 10 05:33:16 AM UTC 24 |
Sep 10 06:27:24 AM UTC 24 |
26697940569 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3517943960 |
|
|
Sep 10 06:23:59 AM UTC 24 |
Sep 10 06:27:25 AM UTC 24 |
1756841362 ps |
| T1787 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.3940069605 |
|
|
Sep 10 06:23:02 AM UTC 24 |
Sep 10 06:27:26 AM UTC 24 |
6154966801 ps |