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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.17 95.52 94.02 95.39 94.99 97.53 99.59


Total test records in report: 2926
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T2270 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.4283892378 Sep 10 07:00:25 AM UTC 24 Sep 10 07:01:31 AM UTC 24 6340922033 ps
T2271 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.1305173257 Sep 10 06:55:47 AM UTC 24 Sep 10 07:01:33 AM UTC 24 10099933294 ps
T2272 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.3741759299 Sep 10 06:57:49 AM UTC 24 Sep 10 07:01:35 AM UTC 24 2430214488 ps
T2273 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.2739033422 Sep 10 07:00:48 AM UTC 24 Sep 10 07:01:46 AM UTC 24 591891730 ps
T2274 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.4206647658 Sep 10 07:01:39 AM UTC 24 Sep 10 07:01:48 AM UTC 24 35993851 ps
T2275 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.1523920154 Sep 10 07:01:38 AM UTC 24 Sep 10 07:01:50 AM UTC 24 231087127 ps
T2276 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.2295529032 Sep 10 07:00:50 AM UTC 24 Sep 10 07:01:53 AM UTC 24 1280512916 ps
T2277 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.663564377 Sep 10 06:50:30 AM UTC 24 Sep 10 07:02:01 AM UTC 24 76768872268 ps
T2278 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.3552560737 Sep 10 06:50:29 AM UTC 24 Sep 10 07:02:04 AM UTC 24 51773039247 ps
T2279 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.890979067 Sep 10 07:00:48 AM UTC 24 Sep 10 07:02:09 AM UTC 24 5228390995 ps
T2280 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.4072135378 Sep 10 07:01:51 AM UTC 24 Sep 10 07:02:09 AM UTC 24 134089814 ps
T2281 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.1243935969 Sep 10 07:00:37 AM UTC 24 Sep 10 07:02:13 AM UTC 24 6201001786 ps
T2282 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.4196933900 Sep 10 07:00:55 AM UTC 24 Sep 10 07:02:13 AM UTC 24 2554801204 ps
T2283 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.543368600 Sep 10 07:02:03 AM UTC 24 Sep 10 07:02:17 AM UTC 24 242294208 ps
T2284 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.3188748639 Sep 10 07:01:21 AM UTC 24 Sep 10 07:02:20 AM UTC 24 281934853 ps
T2285 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.2476934435 Sep 10 07:02:15 AM UTC 24 Sep 10 07:02:35 AM UTC 24 180779481 ps
T2286 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.1176582231 Sep 10 07:01:51 AM UTC 24 Sep 10 07:02:35 AM UTC 24 359244682 ps
T2287 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.247382439 Sep 10 07:02:40 AM UTC 24 Sep 10 07:02:51 AM UTC 24 51794799 ps
T2288 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.3606221072 Sep 10 06:49:42 AM UTC 24 Sep 10 07:02:52 AM UTC 24 6267200037 ps
T2289 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.1621168330 Sep 10 06:55:39 AM UTC 24 Sep 10 07:03:07 AM UTC 24 12648263168 ps
T2290 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.3280322601 Sep 10 07:02:37 AM UTC 24 Sep 10 07:03:08 AM UTC 24 53436992 ps
T2291 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.2789955967 Sep 10 07:01:12 AM UTC 24 Sep 10 07:03:11 AM UTC 24 3538848834 ps
T2292 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.4293638623 Sep 10 06:48:28 AM UTC 24 Sep 10 07:03:17 AM UTC 24 60726672307 ps
T2293 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.1133585810 Sep 10 07:01:46 AM UTC 24 Sep 10 07:03:28 AM UTC 24 9896268471 ps
T2294 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.969188728 Sep 10 07:02:16 AM UTC 24 Sep 10 07:03:29 AM UTC 24 1376761425 ps
T2295 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.3150337993 Sep 10 06:55:49 AM UTC 24 Sep 10 07:03:31 AM UTC 24 8670814628 ps
T2296 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.2994506679 Sep 10 06:56:26 AM UTC 24 Sep 10 07:03:35 AM UTC 24 1751970155 ps
T2297 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.3552530067 Sep 10 07:01:14 AM UTC 24 Sep 10 07:03:35 AM UTC 24 411978984 ps
T2298 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.1336013384 Sep 10 07:03:03 AM UTC 24 Sep 10 07:03:36 AM UTC 24 351744362 ps
T2299 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.1280490880 Sep 10 07:02:30 AM UTC 24 Sep 10 07:03:38 AM UTC 24 235759667 ps
T2300 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.3144385566 Sep 10 07:02:14 AM UTC 24 Sep 10 07:03:39 AM UTC 24 2132886988 ps
T2301 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.1765771129 Sep 10 07:02:49 AM UTC 24 Sep 10 07:03:42 AM UTC 24 1740969716 ps
T2302 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.1458345162 Sep 10 07:02:21 AM UTC 24 Sep 10 07:03:46 AM UTC 24 990016024 ps
T2303 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.1663390746 Sep 10 07:01:47 AM UTC 24 Sep 10 07:03:47 AM UTC 24 6421955560 ps
T2304 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.1049298299 Sep 10 07:03:40 AM UTC 24 Sep 10 07:03:49 AM UTC 24 25135666 ps
T2305 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.459156637 Sep 10 07:02:40 AM UTC 24 Sep 10 07:03:50 AM UTC 24 6363038896 ps
T2306 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.775496243 Sep 10 07:01:59 AM UTC 24 Sep 10 07:04:05 AM UTC 24 2125639913 ps
T2307 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.2904293058 Sep 10 07:03:36 AM UTC 24 Sep 10 07:04:05 AM UTC 24 648854852 ps
T2308 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.294909816 Sep 10 07:00:52 AM UTC 24 Sep 10 07:04:07 AM UTC 24 13560682578 ps
T2309 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.1941046657 Sep 10 07:04:00 AM UTC 24 Sep 10 07:04:07 AM UTC 24 45105305 ps
T2310 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.2553964551 Sep 10 07:04:02 AM UTC 24 Sep 10 07:04:13 AM UTC 24 42407645 ps
T2311 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.2315940322 Sep 10 07:02:45 AM UTC 24 Sep 10 07:04:17 AM UTC 24 4738266148 ps
T2312 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.4127916145 Sep 10 07:03:34 AM UTC 24 Sep 10 07:04:20 AM UTC 24 601576455 ps
T2313 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.3229221547 Sep 10 07:03:46 AM UTC 24 Sep 10 07:04:23 AM UTC 24 310392668 ps
T2314 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.457365401 Sep 10 07:04:08 AM UTC 24 Sep 10 07:04:30 AM UTC 24 490540756 ps
T2315 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.3927064959 Sep 10 07:04:39 AM UTC 24 Sep 10 07:04:49 AM UTC 24 70033827 ps
T2316 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.1167489089 Sep 10 07:04:35 AM UTC 24 Sep 10 07:04:52 AM UTC 24 171218814 ps
T2317 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.1873488382 Sep 10 07:04:27 AM UTC 24 Sep 10 07:04:55 AM UTC 24 837382152 ps
T2318 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.3107251936 Sep 10 07:04:12 AM UTC 24 Sep 10 07:04:55 AM UTC 24 440878153 ps
T2319 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.895927428 Sep 10 07:03:17 AM UTC 24 Sep 10 07:04:56 AM UTC 24 1157341444 ps
T2320 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.466893424 Sep 10 06:59:43 AM UTC 24 Sep 10 07:05:00 AM UTC 24 8608382442 ps
T2321 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.2737882789 Sep 10 07:04:11 AM UTC 24 Sep 10 07:05:12 AM UTC 24 702494878 ps
T2322 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.595243090 Sep 10 07:04:35 AM UTC 24 Sep 10 07:05:22 AM UTC 24 578366160 ps
T2323 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.398855297 Sep 10 07:05:15 AM UTC 24 Sep 10 07:05:23 AM UTC 24 50303187 ps
T2324 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.916209219 Sep 10 07:04:12 AM UTC 24 Sep 10 07:05:25 AM UTC 24 4169792676 ps
T2325 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.2313645504 Sep 10 07:05:16 AM UTC 24 Sep 10 07:05:27 AM UTC 24 187078727 ps
T2326 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.1876585764 Sep 10 06:57:01 AM UTC 24 Sep 10 07:05:28 AM UTC 24 48696094033 ps
T2327 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.3789889902 Sep 10 07:04:07 AM UTC 24 Sep 10 07:05:45 AM UTC 24 6593279799 ps
T2328 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.1105820330 Sep 10 07:04:05 AM UTC 24 Sep 10 07:05:52 AM UTC 24 7780685064 ps
T2329 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.320759692 Sep 10 06:57:05 AM UTC 24 Sep 10 07:05:55 AM UTC 24 37763288150 ps
T2330 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.1858495804 Sep 10 07:03:53 AM UTC 24 Sep 10 07:06:03 AM UTC 24 1348771468 ps
T2331 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.1108383908 Sep 10 07:05:22 AM UTC 24 Sep 10 07:06:12 AM UTC 24 572200911 ps
T2332 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.1348569070 Sep 10 07:04:45 AM UTC 24 Sep 10 07:06:17 AM UTC 24 702184085 ps
T2333 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.2992347537 Sep 10 07:00:08 AM UTC 24 Sep 10 07:06:19 AM UTC 24 10661558457 ps
T2334 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.2294987947 Sep 10 07:05:50 AM UTC 24 Sep 10 07:06:23 AM UTC 24 282977907 ps
T2335 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.2859487311 Sep 10 07:05:25 AM UTC 24 Sep 10 07:06:23 AM UTC 24 496796227 ps
T2336 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.698813448 Sep 10 07:05:56 AM UTC 24 Sep 10 07:06:33 AM UTC 24 867189968 ps
T2337 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.1224821586 Sep 10 07:05:57 AM UTC 24 Sep 10 07:06:33 AM UTC 24 430141985 ps
T2338 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.2842107477 Sep 10 07:05:17 AM UTC 24 Sep 10 07:06:35 AM UTC 24 4678894733 ps
T2339 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.3587854316 Sep 10 06:48:11 AM UTC 24 Sep 10 07:06:35 AM UTC 24 90862112697 ps
T2340 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.3446239480 Sep 10 07:06:14 AM UTC 24 Sep 10 07:06:36 AM UTC 24 119677697 ps
T2341 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.605773567 Sep 10 07:00:02 AM UTC 24 Sep 10 07:06:36 AM UTC 24 2818965034 ps
T2342 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.2777584626 Sep 10 07:04:49 AM UTC 24 Sep 10 07:06:41 AM UTC 24 278640535 ps
T2343 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.3481677002 Sep 10 07:01:17 AM UTC 24 Sep 10 07:06:43 AM UTC 24 10510874941 ps
T2344 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.1691797598 Sep 10 06:49:24 AM UTC 24 Sep 10 07:06:53 AM UTC 24 74443490808 ps
T2345 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.777697042 Sep 10 07:06:46 AM UTC 24 Sep 10 07:06:55 AM UTC 24 156976264 ps
T2346 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.1536294979 Sep 10 07:06:49 AM UTC 24 Sep 10 07:06:59 AM UTC 24 49325889 ps
T2347 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.3758720709 Sep 10 06:57:04 AM UTC 24 Sep 10 07:07:03 AM UTC 24 36859128185 ps
T2348 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.1405668439 Sep 10 06:54:10 AM UTC 24 Sep 10 07:07:07 AM UTC 24 53792889258 ps
T2349 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.1067374516 Sep 10 07:06:20 AM UTC 24 Sep 10 07:07:09 AM UTC 24 964484966 ps
T2350 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.1740687506 Sep 10 07:06:59 AM UTC 24 Sep 10 07:07:09 AM UTC 24 56624905 ps
T2351 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.3720018868 Sep 10 07:07:09 AM UTC 24 Sep 10 07:07:20 AM UTC 24 45294754 ps
T2352 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.1969947772 Sep 10 07:05:23 AM UTC 24 Sep 10 07:07:21 AM UTC 24 8176779797 ps
T2353 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.2591980438 Sep 10 07:06:23 AM UTC 24 Sep 10 07:07:28 AM UTC 24 715044942 ps
T2354 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.4244616383 Sep 10 06:52:37 AM UTC 24 Sep 10 07:07:31 AM UTC 24 80697486878 ps
T2355 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.46604054 Sep 10 07:07:01 AM UTC 24 Sep 10 07:07:42 AM UTC 24 474505258 ps
T2356 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.1247416485 Sep 10 07:07:27 AM UTC 24 Sep 10 07:07:56 AM UTC 24 451644933 ps
T2357 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.2964351158 Sep 10 07:07:49 AM UTC 24 Sep 10 07:07:59 AM UTC 24 45232655 ps
T2358 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.2539910913 Sep 10 07:07:49 AM UTC 24 Sep 10 07:08:03 AM UTC 24 228529412 ps
T2359 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.2018161768 Sep 10 06:56:14 AM UTC 24 Sep 10 07:08:03 AM UTC 24 45927273385 ps
T2360 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.3649868673 Sep 10 07:07:22 AM UTC 24 Sep 10 07:08:07 AM UTC 24 1009256154 ps
T2361 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.1014900983 Sep 10 07:07:20 AM UTC 24 Sep 10 07:08:12 AM UTC 24 1646590270 ps
T2362 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.3814287352 Sep 10 07:07:00 AM UTC 24 Sep 10 07:08:19 AM UTC 24 3434914495 ps
T2363 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.3936662777 Sep 10 07:07:02 AM UTC 24 Sep 10 07:08:24 AM UTC 24 1508730530 ps
T2364 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.1911645022 Sep 10 07:00:15 AM UTC 24 Sep 10 07:08:30 AM UTC 24 8847044434 ps
T2365 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.760431069 Sep 10 06:39:48 AM UTC 24 Sep 10 07:08:32 AM UTC 24 114108500222 ps
T853 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.3232889756 Sep 10 07:03:59 AM UTC 24 Sep 10 07:08:34 AM UTC 24 4086905554 ps
T2366 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.2261455236 Sep 10 06:43:26 AM UTC 24 Sep 10 07:08:41 AM UTC 24 98206500197 ps
T2367 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.3664730403 Sep 10 07:03:16 AM UTC 24 Sep 10 07:08:42 AM UTC 24 20491275485 ps
T2368 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.1976265120 Sep 10 07:06:39 AM UTC 24 Sep 10 07:08:45 AM UTC 24 1554305413 ps
T2369 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.129919464 Sep 10 07:06:45 AM UTC 24 Sep 10 07:08:52 AM UTC 24 354722821 ps
T2370 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.2204899367 Sep 10 07:06:50 AM UTC 24 Sep 10 07:08:53 AM UTC 24 9896538510 ps
T2371 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.705312602 Sep 10 07:04:10 AM UTC 24 Sep 10 07:08:55 AM UTC 24 26885597629 ps
T2372 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.305981593 Sep 10 07:08:35 AM UTC 24 Sep 10 07:08:55 AM UTC 24 201694243 ps
T2373 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.130063374 Sep 10 07:08:24 AM UTC 24 Sep 10 07:08:56 AM UTC 24 340507203 ps
T2374 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.151487079 Sep 10 06:55:02 AM UTC 24 Sep 10 07:09:08 AM UTC 24 82295267306 ps
T2375 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.2943568654 Sep 10 07:07:32 AM UTC 24 Sep 10 07:09:10 AM UTC 24 2542640070 ps
T2376 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.4135731119 Sep 10 07:08:56 AM UTC 24 Sep 10 07:09:13 AM UTC 24 223263848 ps
T2377 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.189641990 Sep 10 07:08:46 AM UTC 24 Sep 10 07:09:15 AM UTC 24 186386381 ps
T2378 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.3710108414 Sep 10 07:02:31 AM UTC 24 Sep 10 07:09:18 AM UTC 24 12002256236 ps
T2379 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.1132264812 Sep 10 06:58:35 AM UTC 24 Sep 10 07:09:18 AM UTC 24 61107985167 ps
T2380 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.369238355 Sep 10 07:08:48 AM UTC 24 Sep 10 07:09:23 AM UTC 24 1029350602 ps
T2381 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.1561899436 Sep 10 07:09:12 AM UTC 24 Sep 10 07:09:24 AM UTC 24 171557882 ps
T2382 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.979628178 Sep 10 07:07:34 AM UTC 24 Sep 10 07:09:24 AM UTC 24 2944896314 ps
T2383 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.3256675742 Sep 10 07:08:09 AM UTC 24 Sep 10 07:09:25 AM UTC 24 2012019262 ps
T2384 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.778981912 Sep 10 07:09:19 AM UTC 24 Sep 10 07:09:28 AM UTC 24 42466053 ps
T2385 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.4106006626 Sep 10 07:09:22 AM UTC 24 Sep 10 07:09:31 AM UTC 24 85181821 ps
T2386 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.1243035734 Sep 10 07:07:58 AM UTC 24 Sep 10 07:09:39 AM UTC 24 6176416633 ps
T2387 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.1435593628 Sep 10 07:03:58 AM UTC 24 Sep 10 07:09:42 AM UTC 24 3831989929 ps
T2388 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.867535582 Sep 10 07:07:56 AM UTC 24 Sep 10 07:09:48 AM UTC 24 6726130323 ps
T2389 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.1376616453 Sep 10 06:56:15 AM UTC 24 Sep 10 07:09:49 AM UTC 24 56772289934 ps
T2390 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.2429146561 Sep 10 06:51:31 AM UTC 24 Sep 10 07:09:52 AM UTC 24 109050819200 ps
T2391 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.694603779 Sep 10 07:09:24 AM UTC 24 Sep 10 07:09:55 AM UTC 24 284434689 ps
T2392 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.2283531104 Sep 10 07:09:51 AM UTC 24 Sep 10 07:10:03 AM UTC 24 216734307 ps
T2393 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.3300561173 Sep 10 07:09:47 AM UTC 24 Sep 10 07:10:12 AM UTC 24 420192169 ps
T2394 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.1306245182 Sep 10 07:10:02 AM UTC 24 Sep 10 07:10:13 AM UTC 24 52434433 ps
T2395 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.2583145433 Sep 10 07:08:31 AM UTC 24 Sep 10 07:10:15 AM UTC 24 2590714796 ps
T2396 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.3882126412 Sep 10 07:10:07 AM UTC 24 Sep 10 07:10:17 AM UTC 24 48467413 ps
T2397 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.367355172 Sep 10 07:09:43 AM UTC 24 Sep 10 07:10:25 AM UTC 24 913654575 ps
T2398 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.3481970014 Sep 10 07:02:01 AM UTC 24 Sep 10 07:10:30 AM UTC 24 33798390591 ps
T2399 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.1555579570 Sep 10 07:09:20 AM UTC 24 Sep 10 07:10:33 AM UTC 24 7338097038 ps
T2400 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.536760435 Sep 10 07:09:44 AM UTC 24 Sep 10 07:10:40 AM UTC 24 2236013561 ps
T2401 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.4019468202 Sep 10 07:09:35 AM UTC 24 Sep 10 07:10:48 AM UTC 24 7143186380 ps
T2402 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.3922420502 Sep 10 07:10:17 AM UTC 24 Sep 10 07:10:50 AM UTC 24 1086354291 ps
T857 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.568564822 Sep 10 06:55:48 AM UTC 24 Sep 10 07:10:55 AM UTC 24 8433144254 ps
T2403 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.4063424686 Sep 10 07:10:45 AM UTC 24 Sep 10 07:10:58 AM UTC 24 215717204 ps
T2404 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.3287795944 Sep 10 07:10:23 AM UTC 24 Sep 10 07:10:58 AM UTC 24 332174653 ps
T2405 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.2023773286 Sep 10 07:09:53 AM UTC 24 Sep 10 07:11:02 AM UTC 24 1122036994 ps
T2406 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.411547746 Sep 10 07:09:22 AM UTC 24 Sep 10 07:11:12 AM UTC 24 6464274083 ps
T2407 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.629882483 Sep 10 07:10:58 AM UTC 24 Sep 10 07:11:18 AM UTC 24 396921509 ps
T2408 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.785254533 Sep 10 07:09:39 AM UTC 24 Sep 10 07:11:22 AM UTC 24 2337141683 ps
T2409 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.618080338 Sep 10 06:59:38 AM UTC 24 Sep 10 07:11:22 AM UTC 24 47407556520 ps
T2410 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.2528383213 Sep 10 07:10:58 AM UTC 24 Sep 10 07:11:24 AM UTC 24 233720351 ps
T2411 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.3601471422 Sep 10 07:11:21 AM UTC 24 Sep 10 07:11:28 AM UTC 24 54449116 ps
T2412 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.2837206981 Sep 10 07:11:23 AM UTC 24 Sep 10 07:11:32 AM UTC 24 46335284 ps
T2413 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.1534793843 Sep 10 07:10:54 AM UTC 24 Sep 10 07:11:35 AM UTC 24 550225694 ps
T2414 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.597342367 Sep 10 07:08:59 AM UTC 24 Sep 10 07:11:36 AM UTC 24 1851130397 ps
T2415 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.2169183842 Sep 10 06:34:15 AM UTC 24 Sep 10 07:11:43 AM UTC 24 145289376535 ps
T2416 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.3439230486 Sep 10 06:54:10 AM UTC 24 Sep 10 07:11:55 AM UTC 24 91213864320 ps
T2417 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.2432932876 Sep 10 07:10:17 AM UTC 24 Sep 10 07:11:55 AM UTC 24 6491549409 ps
T2418 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.1950809160 Sep 10 07:10:16 AM UTC 24 Sep 10 07:11:59 AM UTC 24 9630274596 ps
T2419 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.2623432087 Sep 10 07:11:51 AM UTC 24 Sep 10 07:11:59 AM UTC 24 41676382 ps
T2420 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.1386524874 Sep 10 07:11:59 AM UTC 24 Sep 10 07:12:21 AM UTC 24 215863841 ps
T2421 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.48523181 Sep 10 07:12:01 AM UTC 24 Sep 10 07:12:25 AM UTC 24 539185226 ps
T2422 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.2438605225 Sep 10 07:11:42 AM UTC 24 Sep 10 07:12:27 AM UTC 24 1294947182 ps
T2423 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.3942370466 Sep 10 07:11:51 AM UTC 24 Sep 10 07:12:27 AM UTC 24 2784830700 ps
T2424 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.562111469 Sep 10 07:12:09 AM UTC 24 Sep 10 07:12:27 AM UTC 24 93708382 ps
T2425 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.1431007619 Sep 10 07:09:49 AM UTC 24 Sep 10 07:12:51 AM UTC 24 2398543222 ps
T2426 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.808133088 Sep 10 07:03:03 AM UTC 24 Sep 10 07:12:53 AM UTC 24 68494358420 ps
T2427 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.1982078576 Sep 10 07:11:55 AM UTC 24 Sep 10 07:12:53 AM UTC 24 818923353 ps
T2428 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.3589141341 Sep 10 07:11:30 AM UTC 24 Sep 10 07:12:56 AM UTC 24 8441011953 ps
T2429 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.2423293192 Sep 10 07:12:47 AM UTC 24 Sep 10 07:12:57 AM UTC 24 50359512 ps
T2430 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.415128011 Sep 10 07:12:20 AM UTC 24 Sep 10 07:13:01 AM UTC 24 828537533 ps
T2431 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.3298704293 Sep 10 06:47:06 AM UTC 24 Sep 10 07:13:03 AM UTC 24 109668464794 ps
T2432 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.2481234562 Sep 10 07:12:51 AM UTC 24 Sep 10 07:13:04 AM UTC 24 157702302 ps
T2433 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.1657087898 Sep 10 07:12:22 AM UTC 24 Sep 10 07:13:10 AM UTC 24 414201587 ps
T2434 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.954231974 Sep 10 07:00:53 AM UTC 24 Sep 10 07:13:23 AM UTC 24 48388489368 ps
T2435 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.654630527 Sep 10 07:11:40 AM UTC 24 Sep 10 07:13:25 AM UTC 24 4511812548 ps
T2436 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.1588688421 Sep 10 07:05:50 AM UTC 24 Sep 10 07:13:28 AM UTC 24 30645547200 ps
T2437 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.3545941841 Sep 10 07:10:41 AM UTC 24 Sep 10 07:13:30 AM UTC 24 4285220128 ps
T2438 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.391519324 Sep 10 07:13:32 AM UTC 24 Sep 10 07:13:44 AM UTC 24 77222839 ps
T2439 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.3176273199 Sep 10 07:13:19 AM UTC 24 Sep 10 07:13:45 AM UTC 24 203828470 ps
T2440 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.1775855509 Sep 10 07:11:16 AM UTC 24 Sep 10 07:13:47 AM UTC 24 235043435 ps
T2441 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.3873589704 Sep 10 07:13:22 AM UTC 24 Sep 10 07:13:47 AM UTC 24 211354622 ps
T2442 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.2642055305 Sep 10 07:09:00 AM UTC 24 Sep 10 07:13:51 AM UTC 24 890563578 ps
T2443 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.1360612465 Sep 10 07:12:27 AM UTC 24 Sep 10 07:13:58 AM UTC 24 1387894927 ps
T2444 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.3575195819 Sep 10 07:01:55 AM UTC 24 Sep 10 07:13:58 AM UTC 24 50918566621 ps
T2445 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.26226458 Sep 10 07:13:31 AM UTC 24 Sep 10 07:14:06 AM UTC 24 1000164023 ps
T2446 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.3435870621 Sep 10 07:13:48 AM UTC 24 Sep 10 07:14:06 AM UTC 24 237551793 ps
T2447 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.1373594051 Sep 10 07:08:25 AM UTC 24 Sep 10 07:14:08 AM UTC 24 33303995138 ps
T592 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.1359398772 Sep 10 07:09:11 AM UTC 24 Sep 10 07:14:09 AM UTC 24 2873408963 ps
T2448 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.101109983 Sep 10 07:10:32 AM UTC 24 Sep 10 07:14:20 AM UTC 24 25320705728 ps
T2449 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.946752769 Sep 10 07:14:13 AM UTC 24 Sep 10 07:14:20 AM UTC 24 63479368 ps
T2450 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.866097320 Sep 10 07:14:11 AM UTC 24 Sep 10 07:14:22 AM UTC 24 46917604 ps
T2451 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.983175810 Sep 10 07:12:54 AM UTC 24 Sep 10 07:14:24 AM UTC 24 5515483416 ps
T2452 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.1941907157 Sep 10 07:11:14 AM UTC 24 Sep 10 07:14:27 AM UTC 24 2891774191 ps
T2453 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.913462959 Sep 10 07:13:58 AM UTC 24 Sep 10 07:14:38 AM UTC 24 899103784 ps
T2454 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.3824828470 Sep 10 07:13:34 AM UTC 24 Sep 10 07:14:38 AM UTC 24 1310386980 ps
T2455 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.378160335 Sep 10 07:12:53 AM UTC 24 Sep 10 07:14:41 AM UTC 24 9827190622 ps
T2456 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.2848421771 Sep 10 06:58:34 AM UTC 24 Sep 10 07:14:49 AM UTC 24 57846249586 ps
T2457 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.286763118 Sep 10 07:07:37 AM UTC 24 Sep 10 07:14:50 AM UTC 24 7433831771 ps
T2458 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.1158654266 Sep 10 07:14:24 AM UTC 24 Sep 10 07:14:56 AM UTC 24 234930864 ps
T2459 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.1626016535 Sep 10 07:14:48 AM UTC 24 Sep 10 07:15:03 AM UTC 24 447419154 ps
T590 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.1535558579 Sep 10 07:04:50 AM UTC 24 Sep 10 07:15:05 AM UTC 24 17243577819 ps
T2460 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.571042208 Sep 10 07:14:24 AM UTC 24 Sep 10 07:15:10 AM UTC 24 1099297449 ps
T2461 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.425941631 Sep 10 07:14:08 AM UTC 24 Sep 10 07:15:12 AM UTC 24 6608898307 ps
T2462 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.2373324204 Sep 10 07:03:53 AM UTC 24 Sep 10 07:15:21 AM UTC 24 13696429708 ps
T2463 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.478922847 Sep 10 07:07:01 AM UTC 24 Sep 10 07:15:21 AM UTC 24 51063229946 ps
T634 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.2771811962 Sep 10 07:04:59 AM UTC 24 Sep 10 07:15:24 AM UTC 24 7086366782 ps
T2464 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.1318009429 Sep 10 07:14:53 AM UTC 24 Sep 10 07:15:27 AM UTC 24 604276377 ps
T2465 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.3383304334 Sep 10 07:14:35 AM UTC 24 Sep 10 07:15:27 AM UTC 24 576063758 ps
T2466 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.1993609720 Sep 10 07:15:14 AM UTC 24 Sep 10 07:15:28 AM UTC 24 209439910 ps
T2467 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.4268834314 Sep 10 07:15:19 AM UTC 24 Sep 10 07:15:28 AM UTC 24 38500997 ps
T2468 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.1129012231 Sep 10 07:14:49 AM UTC 24 Sep 10 07:15:30 AM UTC 24 262236801 ps
T2469 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.2734770134 Sep 10 07:14:20 AM UTC 24 Sep 10 07:15:37 AM UTC 24 5292572400 ps
T635 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.2282889513 Sep 10 06:58:58 AM UTC 24 Sep 10 07:15:41 AM UTC 24 11130037596 ps
T2470 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.1609331575 Sep 10 07:14:46 AM UTC 24 Sep 10 07:15:51 AM UTC 24 2286661616 ps
T2471 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.418466582 Sep 10 07:15:37 AM UTC 24 Sep 10 07:16:02 AM UTC 24 201927302 ps
T2472 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.3598750261 Sep 10 07:13:25 AM UTC 24 Sep 10 07:16:03 AM UTC 24 3513444218 ps
T2473 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.1314886889 Sep 10 07:15:54 AM UTC 24 Sep 10 07:16:20 AM UTC 24 671669419 ps
T2474 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.618646283 Sep 10 07:15:04 AM UTC 24 Sep 10 07:16:21 AM UTC 24 1588902936 ps
T2475 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.2652657350 Sep 10 07:16:04 AM UTC 24 Sep 10 07:16:22 AM UTC 24 94549466 ps
T2476 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.1466157331 Sep 10 07:11:24 AM UTC 24 Sep 10 07:16:24 AM UTC 24 2290767155 ps
T2477 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.3848589456 Sep 10 07:15:31 AM UTC 24 Sep 10 07:16:28 AM UTC 24 543645409 ps
T2478 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.3216147122 Sep 10 07:12:26 AM UTC 24 Sep 10 07:16:30 AM UTC 24 2497405470 ps
T2479 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.1682892326 Sep 10 07:09:10 AM UTC 24 Sep 10 07:16:34 AM UTC 24 15454885474 ps
T2480 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.2040027289 Sep 10 07:15:53 AM UTC 24 Sep 10 07:16:34 AM UTC 24 580289826 ps
T2481 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2807831851 Sep 10 06:44:58 AM UTC 24 Sep 10 07:16:35 AM UTC 24 134815303745 ps
T2482 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.4052332858 Sep 10 07:16:28 AM UTC 24 Sep 10 07:16:38 AM UTC 24 48366475 ps
T2483 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.954974065 Sep 10 07:16:32 AM UTC 24 Sep 10 07:16:40 AM UTC 24 38487164 ps
T2484 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.3568503248 Sep 10 07:15:56 AM UTC 24 Sep 10 07:16:44 AM UTC 24 336808240 ps
T2485 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.1780351019 Sep 10 07:15:53 AM UTC 24 Sep 10 07:16:44 AM UTC 24 1765800844 ps
T2486 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.2595628097 Sep 10 07:13:54 AM UTC 24 Sep 10 07:16:51 AM UTC 24 4497854702 ps
T2487 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.469479660 Sep 10 07:15:55 AM UTC 24 Sep 10 07:16:53 AM UTC 24 1205601359 ps
T2488 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.1364706476 Sep 10 07:15:32 AM UTC 24 Sep 10 07:16:56 AM UTC 24 5226642629 ps
T2489 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.2955919509 Sep 10 06:42:02 AM UTC 24 Sep 10 07:16:56 AM UTC 24 141041747345 ps
T2490 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.2278976995 Sep 10 07:11:08 AM UTC 24 Sep 10 07:16:58 AM UTC 24 4614169445 ps
T2491 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.2347536923 Sep 10 07:01:54 AM UTC 24 Sep 10 07:17:01 AM UTC 24 86270954031 ps
T2492 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.2361365565 Sep 10 07:15:23 AM UTC 24 Sep 10 07:17:05 AM UTC 24 7732106156 ps
T2493 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.3124459163 Sep 10 07:15:45 AM UTC 24 Sep 10 07:17:08 AM UTC 24 1715016616 ps
T2494 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.62775698 Sep 10 07:09:48 AM UTC 24 Sep 10 07:17:11 AM UTC 24 4304830803 ps
T2495 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.2088543549 Sep 10 07:16:51 AM UTC 24 Sep 10 07:17:16 AM UTC 24 296070889 ps
T2496 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.443827434 Sep 10 07:17:00 AM UTC 24 Sep 10 07:17:17 AM UTC 24 178510913 ps
T2497 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.2641458470 Sep 10 07:17:04 AM UTC 24 Sep 10 07:17:27 AM UTC 24 245834087 ps
T2498 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.2284336010 Sep 10 07:17:20 AM UTC 24 Sep 10 07:17:31 AM UTC 24 121777516 ps
T2499 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.828502419 Sep 10 07:17:24 AM UTC 24 Sep 10 07:17:31 AM UTC 24 40139561 ps
T2500 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.3416551832 Sep 10 07:06:31 AM UTC 24 Sep 10 07:17:37 AM UTC 24 12447000092 ps
T2501 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.764523082 Sep 10 07:17:05 AM UTC 24 Sep 10 07:17:39 AM UTC 24 923205794 ps
T2502 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.119981030 Sep 10 06:59:28 AM UTC 24 Sep 10 07:17:45 AM UTC 24 94867465434 ps
T2503 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.1545529339 Sep 10 07:13:53 AM UTC 24 Sep 10 07:17:45 AM UTC 24 1264581753 ps
T2504 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.3487148657 Sep 10 07:07:34 AM UTC 24 Sep 10 07:17:46 AM UTC 24 3832872420 ps
T2505 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.1718170052 Sep 10 07:17:02 AM UTC 24 Sep 10 07:17:52 AM UTC 24 611130433 ps
T2506 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.3228347183 Sep 10 07:17:10 AM UTC 24 Sep 10 07:17:56 AM UTC 24 1251211906 ps
T2507 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.1890349591 Sep 10 07:16:48 AM UTC 24 Sep 10 07:18:04 AM UTC 24 5146145840 ps
T2508 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.1236683339 Sep 10 07:15:50 AM UTC 24 Sep 10 07:18:08 AM UTC 24 10198712199 ps
T2509 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1055753499 Sep 10 07:17:21 AM UTC 24 Sep 10 07:18:16 AM UTC 24 206361537 ps
T2510 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.3164268198 Sep 10 07:16:49 AM UTC 24 Sep 10 07:18:17 AM UTC 24 1914489449 ps
T2511 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.2752129059 Sep 10 07:17:39 AM UTC 24 Sep 10 07:18:22 AM UTC 24 483700833 ps
T2512 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.470554105 Sep 10 07:16:46 AM UTC 24 Sep 10 07:18:23 AM UTC 24 9483033690 ps
T2513 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.4259899611 Sep 10 07:17:57 AM UTC 24 Sep 10 07:18:24 AM UTC 24 333458929 ps
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