| T1329 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.1029982545 |
|
|
Sep 10 04:01:13 AM UTC 24 |
Sep 10 05:45:08 AM UTC 24 |
22288719712 ps |
| T1330 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.780410460 |
|
|
Sep 10 12:46:03 AM UTC 24 |
Sep 10 05:59:55 AM UTC 24 |
82001879084 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.951875268 |
|
|
Sep 09 11:31:23 PM UTC 24 |
Sep 10 06:17:41 AM UTC 24 |
115121136340 ps |
| T1331 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.1126930649 |
|
|
Sep 10 02:07:15 AM UTC 24 |
Sep 10 06:39:12 AM UTC 24 |
67905097024 ps |
| T1332 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2478633841 |
|
|
Sep 10 02:07:19 AM UTC 24 |
Sep 10 07:28:28 AM UTC 24 |
81566068209 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3456740196 |
|
|
Sep 10 05:00:04 AM UTC 24 |
Sep 10 05:00:14 AM UTC 24 |
41252232 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.2036147031 |
|
|
Sep 10 05:00:02 AM UTC 24 |
Sep 10 05:00:18 AM UTC 24 |
166370978 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.2056391401 |
|
|
Sep 10 05:00:46 AM UTC 24 |
Sep 10 05:01:20 AM UTC 24 |
223797278 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.649745155 |
|
|
Sep 10 05:00:17 AM UTC 24 |
Sep 10 05:02:01 AM UTC 24 |
7156251699 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.3407733184 |
|
|
Sep 10 05:02:01 AM UTC 24 |
Sep 10 05:02:18 AM UTC 24 |
259097093 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.824555148 |
|
|
Sep 10 05:01:59 AM UTC 24 |
Sep 10 05:02:21 AM UTC 24 |
137393010 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1722290606 |
|
|
Sep 10 05:00:41 AM UTC 24 |
Sep 10 05:02:24 AM UTC 24 |
4348883316 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3098324512 |
|
|
Sep 10 05:02:09 AM UTC 24 |
Sep 10 05:02:31 AM UTC 24 |
342018982 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.3269762800 |
|
|
Sep 10 05:00:44 AM UTC 24 |
Sep 10 05:02:42 AM UTC 24 |
2142252039 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.2806156432 |
|
|
Sep 10 05:01:43 AM UTC 24 |
Sep 10 05:02:44 AM UTC 24 |
1070127837 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.2491811356 |
|
|
Sep 10 05:01:58 AM UTC 24 |
Sep 10 05:02:48 AM UTC 24 |
1319748491 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.3131549714 |
|
|
Sep 10 05:02:59 AM UTC 24 |
Sep 10 05:03:09 AM UTC 24 |
202425290 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.1953743654 |
|
|
Sep 10 05:02:09 AM UTC 24 |
Sep 10 05:03:15 AM UTC 24 |
474329824 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1868156948 |
|
|
Sep 10 05:03:08 AM UTC 24 |
Sep 10 05:03:19 AM UTC 24 |
55160032 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.2753112951 |
|
|
Sep 10 05:01:03 AM UTC 24 |
Sep 10 05:03:39 AM UTC 24 |
6701259403 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.1774352295 |
|
|
Sep 10 05:03:14 AM UTC 24 |
Sep 10 05:04:04 AM UTC 24 |
526152171 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.485781667 |
|
|
Sep 10 05:03:47 AM UTC 24 |
Sep 10 05:04:12 AM UTC 24 |
455674536 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.3278824742 |
|
|
Sep 10 04:59:49 AM UTC 24 |
Sep 10 05:04:13 AM UTC 24 |
3357683738 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.1636446404 |
|
|
Sep 10 04:59:57 AM UTC 24 |
Sep 10 05:04:16 AM UTC 24 |
6451609870 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.1582361342 |
|
|
Sep 10 05:04:05 AM UTC 24 |
Sep 10 05:04:16 AM UTC 24 |
154715841 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.823766534 |
|
|
Sep 10 05:04:06 AM UTC 24 |
Sep 10 05:04:30 AM UTC 24 |
152480384 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.1245896434 |
|
|
Sep 10 05:03:59 AM UTC 24 |
Sep 10 05:04:34 AM UTC 24 |
280285284 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1633038520 |
|
|
Sep 10 05:03:11 AM UTC 24 |
Sep 10 05:04:44 AM UTC 24 |
5109898473 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.3289715597 |
|
|
Sep 10 05:03:15 AM UTC 24 |
Sep 10 05:04:49 AM UTC 24 |
2192476354 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2037462880 |
|
|
Sep 10 05:02:09 AM UTC 24 |
Sep 10 05:04:56 AM UTC 24 |
507950678 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.3043781655 |
|
|
Sep 10 05:03:43 AM UTC 24 |
Sep 10 05:05:03 AM UTC 24 |
685661399 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2337573265 |
|
|
Sep 10 05:02:26 AM UTC 24 |
Sep 10 05:05:11 AM UTC 24 |
464674948 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.178278279 |
|
|
Sep 10 05:03:09 AM UTC 24 |
Sep 10 05:05:25 AM UTC 24 |
9554046143 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.2413272866 |
|
|
Sep 10 05:05:16 AM UTC 24 |
Sep 10 05:05:28 AM UTC 24 |
210166722 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.114585093 |
|
|
Sep 10 05:05:23 AM UTC 24 |
Sep 10 05:05:34 AM UTC 24 |
54494831 ps |
| T1333 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.413497816 |
|
|
Sep 10 05:02:56 AM UTC 24 |
Sep 10 05:05:44 AM UTC 24 |
3211265600 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.967885738 |
|
|
Sep 10 05:00:59 AM UTC 24 |
Sep 10 05:06:18 AM UTC 24 |
30262630228 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.617587625 |
|
|
Sep 10 05:05:52 AM UTC 24 |
Sep 10 05:06:24 AM UTC 24 |
221069797 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.2353115825 |
|
|
Sep 10 05:05:38 AM UTC 24 |
Sep 10 05:06:29 AM UTC 24 |
393703091 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.2825515544 |
|
|
Sep 10 05:02:29 AM UTC 24 |
Sep 10 05:06:33 AM UTC 24 |
4674984012 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.3336438992 |
|
|
Sep 10 05:06:10 AM UTC 24 |
Sep 10 05:06:46 AM UTC 24 |
580274692 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.967332301 |
|
|
Sep 10 05:05:28 AM UTC 24 |
Sep 10 05:06:55 AM UTC 24 |
9211833447 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.3110283239 |
|
|
Sep 10 05:04:28 AM UTC 24 |
Sep 10 05:07:04 AM UTC 24 |
4421307603 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.340115843 |
|
|
Sep 10 05:06:57 AM UTC 24 |
Sep 10 05:07:22 AM UTC 24 |
326097057 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.3384929752 |
|
|
Sep 10 05:05:30 AM UTC 24 |
Sep 10 05:07:31 AM UTC 24 |
6115111190 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.2378451370 |
|
|
Sep 10 05:07:32 AM UTC 24 |
Sep 10 05:07:40 AM UTC 24 |
6768479 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1477931222 |
|
|
Sep 10 05:04:38 AM UTC 24 |
Sep 10 05:07:41 AM UTC 24 |
729331449 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2729676015 |
|
|
Sep 10 05:04:18 AM UTC 24 |
Sep 10 05:07:42 AM UTC 24 |
625626355 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.4174305928 |
|
|
Sep 10 05:06:46 AM UTC 24 |
Sep 10 05:07:44 AM UTC 24 |
1258365992 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.3148520128 |
|
|
Sep 10 05:06:59 AM UTC 24 |
Sep 10 05:07:46 AM UTC 24 |
1076547056 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.3606696191 |
|
|
Sep 10 05:02:53 AM UTC 24 |
Sep 10 05:07:58 AM UTC 24 |
3363241203 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.3433397584 |
|
|
Sep 10 05:07:22 AM UTC 24 |
Sep 10 05:08:02 AM UTC 24 |
1158552519 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.1663190629 |
|
|
Sep 10 05:02:12 AM UTC 24 |
Sep 10 05:08:19 AM UTC 24 |
9024961576 ps |
| T1334 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.1171889782 |
|
|
Sep 10 05:08:13 AM UTC 24 |
Sep 10 05:08:29 AM UTC 24 |
221268145 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.3218687798 |
|
|
Sep 10 05:06:52 AM UTC 24 |
Sep 10 05:08:30 AM UTC 24 |
1974975032 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.278182943 |
|
|
Sep 10 05:05:01 AM UTC 24 |
Sep 10 05:08:31 AM UTC 24 |
3089856886 ps |
| T1335 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.2190546327 |
|
|
Sep 10 05:08:24 AM UTC 24 |
Sep 10 05:08:35 AM UTC 24 |
51430031 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.638018789 |
|
|
Sep 10 05:02:45 AM UTC 24 |
Sep 10 05:08:35 AM UTC 24 |
4621312552 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.432042422 |
|
|
Sep 10 05:06:01 AM UTC 24 |
Sep 10 05:08:38 AM UTC 24 |
10654454814 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_bit_bash.1145992074 |
|
|
Sep 10 05:04:39 AM UTC 24 |
Sep 10 05:09:09 AM UTC 24 |
3758102898 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.1275867462 |
|
|
Sep 10 05:08:51 AM UTC 24 |
Sep 10 05:09:11 AM UTC 24 |
111816357 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.2306812594 |
|
|
Sep 10 05:09:01 AM UTC 24 |
Sep 10 05:09:28 AM UTC 24 |
830523381 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.1593098641 |
|
|
Sep 10 05:08:49 AM UTC 24 |
Sep 10 05:09:40 AM UTC 24 |
473625060 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.2131412055 |
|
|
Sep 10 05:09:15 AM UTC 24 |
Sep 10 05:09:52 AM UTC 24 |
527553780 ps |
| T1336 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.1875457613 |
|
|
Sep 10 05:08:29 AM UTC 24 |
Sep 10 05:09:53 AM UTC 24 |
8447007723 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.939980815 |
|
|
Sep 10 05:04:38 AM UTC 24 |
Sep 10 05:09:56 AM UTC 24 |
5214583590 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.3876450136 |
|
|
Sep 10 05:07:17 AM UTC 24 |
Sep 10 05:10:11 AM UTC 24 |
542383992 ps |
| T1337 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.1983495996 |
|
|
Sep 10 05:09:28 AM UTC 24 |
Sep 10 05:10:22 AM UTC 24 |
925770997 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.2430722639 |
|
|
Sep 10 05:08:46 AM UTC 24 |
Sep 10 05:10:30 AM UTC 24 |
4412832660 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.9397698 |
|
|
Sep 10 05:09:06 AM UTC 24 |
Sep 10 05:10:39 AM UTC 24 |
2456140481 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.751262326 |
|
|
Sep 10 05:07:12 AM UTC 24 |
Sep 10 05:11:00 AM UTC 24 |
2091934113 ps |
| T1338 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.241048916 |
|
|
Sep 10 05:10:47 AM UTC 24 |
Sep 10 05:11:01 AM UTC 24 |
210634060 ps |
| T1339 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.2103597710 |
|
|
Sep 10 05:10:57 AM UTC 24 |
Sep 10 05:11:09 AM UTC 24 |
57206643 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.3749139180 |
|
|
Sep 10 05:08:57 AM UTC 24 |
Sep 10 05:11:32 AM UTC 24 |
2940495571 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.1892019963 |
|
|
Sep 10 05:09:36 AM UTC 24 |
Sep 10 05:11:32 AM UTC 24 |
1141076088 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.389599822 |
|
|
Sep 10 05:04:09 AM UTC 24 |
Sep 10 05:11:37 AM UTC 24 |
10800172134 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.735462810 |
|
|
Sep 10 05:11:35 AM UTC 24 |
Sep 10 05:12:07 AM UTC 24 |
223102792 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.2944051545 |
|
|
Sep 10 05:08:11 AM UTC 24 |
Sep 10 05:12:08 AM UTC 24 |
4040159016 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.1302401124 |
|
|
Sep 10 05:11:29 AM UTC 24 |
Sep 10 05:12:12 AM UTC 24 |
412418601 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.892558769 |
|
|
Sep 10 05:08:57 AM UTC 24 |
Sep 10 05:12:15 AM UTC 24 |
13593640356 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.1063619486 |
|
|
Sep 10 05:11:05 AM UTC 24 |
Sep 10 05:12:48 AM UTC 24 |
10393832948 ps |
| T1340 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.1167262551 |
|
|
Sep 10 05:12:07 AM UTC 24 |
Sep 10 05:12:54 AM UTC 24 |
375128081 ps |
| T1341 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.752989942 |
|
|
Sep 10 05:12:35 AM UTC 24 |
Sep 10 05:12:54 AM UTC 24 |
82092412 ps |
| T1342 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.4053555111 |
|
|
Sep 10 05:12:34 AM UTC 24 |
Sep 10 05:12:55 AM UTC 24 |
307606610 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3718553733 |
|
|
Sep 10 05:02:46 AM UTC 24 |
Sep 10 05:12:55 AM UTC 24 |
7337748100 ps |
| T1343 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.1100210386 |
|
|
Sep 10 05:11:28 AM UTC 24 |
Sep 10 05:12:58 AM UTC 24 |
5005741229 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.1407408816 |
|
|
Sep 10 05:12:03 AM UTC 24 |
Sep 10 05:12:58 AM UTC 24 |
480799918 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.4088167142 |
|
|
Sep 10 05:06:22 AM UTC 24 |
Sep 10 05:12:58 AM UTC 24 |
26028538265 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.931000804 |
|
|
Sep 10 05:09:39 AM UTC 24 |
Sep 10 05:13:05 AM UTC 24 |
234367297 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.2687218197 |
|
|
Sep 10 05:11:59 AM UTC 24 |
Sep 10 05:13:12 AM UTC 24 |
778648992 ps |
| T1344 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.4273745345 |
|
|
Sep 10 05:13:19 AM UTC 24 |
Sep 10 05:13:27 AM UTC 24 |
53481159 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.299207502 |
|
|
Sep 10 05:03:40 AM UTC 24 |
Sep 10 05:13:40 AM UTC 24 |
44755976683 ps |
| T1345 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.1164316819 |
|
|
Sep 10 05:13:31 AM UTC 24 |
Sep 10 05:13:42 AM UTC 24 |
46956498 ps |
| T1346 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.4150627855 |
|
|
Sep 10 05:00:00 AM UTC 24 |
Sep 10 05:13:52 AM UTC 24 |
15322105178 ps |
| T1347 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.3280162205 |
|
|
Sep 10 05:14:07 AM UTC 24 |
Sep 10 05:14:22 AM UTC 24 |
160239592 ps |
| T1348 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.2180071133 |
|
|
Sep 10 05:02:49 AM UTC 24 |
Sep 10 05:14:22 AM UTC 24 |
7459385556 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.3783395322 |
|
|
Sep 10 05:04:41 AM UTC 24 |
Sep 10 05:14:39 AM UTC 24 |
5975504663 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.169412470 |
|
|
Sep 10 05:10:38 AM UTC 24 |
Sep 10 05:14:57 AM UTC 24 |
3450971837 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.1325457769 |
|
|
Sep 10 05:14:05 AM UTC 24 |
Sep 10 05:15:13 AM UTC 24 |
533235920 ps |
| T1349 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.3161100271 |
|
|
Sep 10 05:05:02 AM UTC 24 |
Sep 10 05:15:15 AM UTC 24 |
10731091860 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.2820480633 |
|
|
Sep 10 05:10:06 AM UTC 24 |
Sep 10 05:15:18 AM UTC 24 |
4979750219 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.29919626 |
|
|
Sep 10 05:09:56 AM UTC 24 |
Sep 10 05:15:23 AM UTC 24 |
3922639992 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.2630365380 |
|
|
Sep 10 05:14:48 AM UTC 24 |
Sep 10 05:15:32 AM UTC 24 |
1102729824 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.748829420 |
|
|
Sep 10 05:07:49 AM UTC 24 |
Sep 10 05:15:37 AM UTC 24 |
7210556606 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.2114628533 |
|
|
Sep 10 05:13:10 AM UTC 24 |
Sep 10 05:15:39 AM UTC 24 |
4828230843 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.2513134236 |
|
|
Sep 10 05:11:59 AM UTC 24 |
Sep 10 05:15:40 AM UTC 24 |
11131884364 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.1417513305 |
|
|
Sep 10 05:13:37 AM UTC 24 |
Sep 10 05:15:43 AM UTC 24 |
7868990700 ps |
| T1350 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.454145372 |
|
|
Sep 10 05:15:42 AM UTC 24 |
Sep 10 05:16:01 AM UTC 24 |
76485082 ps |
| T1351 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.1343091511 |
|
|
Sep 10 05:15:45 AM UTC 24 |
Sep 10 05:16:05 AM UTC 24 |
336035495 ps |
| T1352 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.794635528 |
|
|
Sep 10 05:15:41 AM UTC 24 |
Sep 10 05:16:05 AM UTC 24 |
204658488 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.1272968819 |
|
|
Sep 10 05:03:36 AM UTC 24 |
Sep 10 05:16:10 AM UTC 24 |
65752523881 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.1778495371 |
|
|
Sep 10 05:15:25 AM UTC 24 |
Sep 10 05:16:12 AM UTC 24 |
1573910972 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.869756535 |
|
|
Sep 10 05:13:53 AM UTC 24 |
Sep 10 05:16:17 AM UTC 24 |
6541885477 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.2794241061 |
|
|
Sep 10 05:10:20 AM UTC 24 |
Sep 10 05:16:18 AM UTC 24 |
4197862130 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.3953448694 |
|
|
Sep 10 05:10:15 AM UTC 24 |
Sep 10 05:16:22 AM UTC 24 |
5956890920 ps |
| T1353 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.3276616728 |
|
|
Sep 10 05:05:11 AM UTC 24 |
Sep 10 05:16:25 AM UTC 24 |
13875390228 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.2265559278 |
|
|
Sep 10 05:04:41 AM UTC 24 |
Sep 10 05:16:30 AM UTC 24 |
11735879726 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.489100372 |
|
|
Sep 10 05:13:20 AM UTC 24 |
Sep 10 05:16:35 AM UTC 24 |
1403649347 ps |
| T1354 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.1116269051 |
|
|
Sep 10 05:16:31 AM UTC 24 |
Sep 10 05:16:41 AM UTC 24 |
245055314 ps |
| T1355 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.1921458406 |
|
|
Sep 10 05:10:21 AM UTC 24 |
Sep 10 05:16:41 AM UTC 24 |
5175531484 ps |
| T1356 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.4266450611 |
|
|
Sep 10 05:16:36 AM UTC 24 |
Sep 10 05:16:48 AM UTC 24 |
55278409 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.937459693 |
|
|
Sep 10 05:16:00 AM UTC 24 |
Sep 10 05:17:00 AM UTC 24 |
58429915 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.3114259680 |
|
|
Sep 10 05:15:48 AM UTC 24 |
Sep 10 05:17:03 AM UTC 24 |
1975469379 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.4073337089 |
|
|
Sep 10 05:16:45 AM UTC 24 |
Sep 10 05:17:20 AM UTC 24 |
265466325 ps |
| T1357 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3000735558 |
|
|
Sep 10 05:17:28 AM UTC 24 |
Sep 10 05:17:37 AM UTC 24 |
22972554 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.891369215 |
|
|
Sep 10 05:16:44 AM UTC 24 |
Sep 10 05:17:44 AM UTC 24 |
1776438053 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.1883056226 |
|
|
Sep 10 05:17:07 AM UTC 24 |
Sep 10 05:17:44 AM UTC 24 |
430391494 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.1755768154 |
|
|
Sep 10 05:16:57 AM UTC 24 |
Sep 10 05:17:56 AM UTC 24 |
991142029 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.3195614780 |
|
|
Sep 10 05:16:36 AM UTC 24 |
Sep 10 05:17:56 AM UTC 24 |
5162868683 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.2320290152 |
|
|
Sep 10 05:16:53 AM UTC 24 |
Sep 10 05:18:02 AM UTC 24 |
3065531124 ps |
| T1358 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.2097336907 |
|
|
Sep 10 05:17:15 AM UTC 24 |
Sep 10 05:18:05 AM UTC 24 |
873749625 ps |
| T1359 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.3121860904 |
|
|
Sep 10 05:17:06 AM UTC 24 |
Sep 10 05:18:10 AM UTC 24 |
606347471 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.425085379 |
|
|
Sep 10 05:13:18 AM UTC 24 |
Sep 10 05:18:19 AM UTC 24 |
6350816410 ps |
| T1360 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.4154965376 |
|
|
Sep 10 05:16:38 AM UTC 24 |
Sep 10 05:18:43 AM UTC 24 |
7327155146 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.3294879500 |
|
|
Sep 10 05:17:47 AM UTC 24 |
Sep 10 05:18:44 AM UTC 24 |
159962533 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.2507500970 |
|
|
Sep 10 05:18:36 AM UTC 24 |
Sep 10 05:18:46 AM UTC 24 |
42611878 ps |
| T1361 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.499661037 |
|
|
Sep 10 05:18:33 AM UTC 24 |
Sep 10 05:18:48 AM UTC 24 |
230618763 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.4045203578 |
|
|
Sep 10 05:12:37 AM UTC 24 |
Sep 10 05:19:16 AM UTC 24 |
10205944921 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.1430652079 |
|
|
Sep 10 05:08:57 AM UTC 24 |
Sep 10 05:19:26 AM UTC 24 |
53716742535 ps |
| T1362 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.593550968 |
|
|
Sep 10 05:08:09 AM UTC 24 |
Sep 10 05:19:28 AM UTC 24 |
5818415711 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.1105397642 |
|
|
Sep 10 05:13:19 AM UTC 24 |
Sep 10 05:19:40 AM UTC 24 |
3914869048 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.706866419 |
|
|
Sep 10 05:19:14 AM UTC 24 |
Sep 10 05:19:53 AM UTC 24 |
389803902 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.2204364427 |
|
|
Sep 10 05:13:23 AM UTC 24 |
Sep 10 05:19:54 AM UTC 24 |
4164236634 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.4222872647 |
|
|
Sep 10 05:12:42 AM UTC 24 |
Sep 10 05:19:54 AM UTC 24 |
2726499978 ps |
| T1363 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.554664712 |
|
|
Sep 10 05:19:11 AM UTC 24 |
Sep 10 05:20:20 AM UTC 24 |
2963223211 ps |
| T1364 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.574957073 |
|
|
Sep 10 05:20:07 AM UTC 24 |
Sep 10 05:20:25 AM UTC 24 |
131197670 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.3143532348 |
|
|
Sep 10 05:19:12 AM UTC 24 |
Sep 10 05:20:26 AM UTC 24 |
1819187735 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.3179898309 |
|
|
Sep 10 05:07:57 AM UTC 24 |
Sep 10 05:20:42 AM UTC 24 |
5633223800 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.1718222830 |
|
|
Sep 10 05:08:56 AM UTC 24 |
Sep 10 05:20:51 AM UTC 24 |
46903779251 ps |
| T1365 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.3307059043 |
|
|
Sep 10 05:20:19 AM UTC 24 |
Sep 10 05:20:56 AM UTC 24 |
724056366 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3108551978 |
|
|
Sep 10 05:18:11 AM UTC 24 |
Sep 10 05:21:00 AM UTC 24 |
351482108 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.3217633626 |
|
|
Sep 10 05:20:21 AM UTC 24 |
Sep 10 05:21:13 AM UTC 24 |
894490605 ps |
| T1366 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.241701175 |
|
|
Sep 10 05:20:21 AM UTC 24 |
Sep 10 05:21:18 AM UTC 24 |
487847366 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.2395367488 |
|
|
Sep 10 05:19:53 AM UTC 24 |
Sep 10 05:21:18 AM UTC 24 |
1492049262 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.2279502470 |
|
|
Sep 10 05:18:48 AM UTC 24 |
Sep 10 05:21:25 AM UTC 24 |
9823996178 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1253310952 |
|
|
Sep 10 05:16:06 AM UTC 24 |
Sep 10 05:21:44 AM UTC 24 |
2951447326 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.2654918008 |
|
|
Sep 10 05:08:07 AM UTC 24 |
Sep 10 05:21:54 AM UTC 24 |
10566498728 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.526966521 |
|
|
Sep 10 05:21:46 AM UTC 24 |
Sep 10 05:21:56 AM UTC 24 |
46705019 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.441260223 |
|
|
Sep 10 05:05:55 AM UTC 24 |
Sep 10 05:21:58 AM UTC 24 |
98209038399 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.1066142600 |
|
|
Sep 10 05:20:48 AM UTC 24 |
Sep 10 05:21:59 AM UTC 24 |
477815193 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.524215542 |
|
|
Sep 10 05:16:31 AM UTC 24 |
Sep 10 05:22:01 AM UTC 24 |
3203890800 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.145984576 |
|
|
Sep 10 05:21:46 AM UTC 24 |
Sep 10 05:22:02 AM UTC 24 |
230945695 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.1354950756 |
|
|
Sep 10 05:11:39 AM UTC 24 |
Sep 10 05:22:26 AM UTC 24 |
33590150666 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.3379190093 |
|
|
Sep 10 05:16:00 AM UTC 24 |
Sep 10 05:22:35 AM UTC 24 |
3966440627 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.3217931702 |
|
|
Sep 10 05:22:23 AM UTC 24 |
Sep 10 05:22:49 AM UTC 24 |
177196097 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.1056272945 |
|
|
Sep 10 05:17:29 AM UTC 24 |
Sep 10 05:23:12 AM UTC 24 |
8843084001 ps |
| T1367 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.103654090 |
|
|
Sep 10 05:23:04 AM UTC 24 |
Sep 10 05:23:20 AM UTC 24 |
100744344 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.1348227181 |
|
|
Sep 10 05:22:20 AM UTC 24 |
Sep 10 05:23:21 AM UTC 24 |
1176469309 ps |
| T1368 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.3999898787 |
|
|
Sep 10 05:21:54 AM UTC 24 |
Sep 10 05:23:34 AM UTC 24 |
6946860570 ps |
| T1369 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.2177669015 |
|
|
Sep 10 05:23:16 AM UTC 24 |
Sep 10 05:23:34 AM UTC 24 |
74036294 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.264192497 |
|
|
Sep 10 05:18:12 AM UTC 24 |
Sep 10 05:23:36 AM UTC 24 |
3735516054 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.271501304 |
|
|
Sep 10 05:20:53 AM UTC 24 |
Sep 10 05:24:09 AM UTC 24 |
5996589929 ps |
| T1370 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.2385172516 |
|
|
Sep 10 05:23:39 AM UTC 24 |
Sep 10 05:24:10 AM UTC 24 |
173642691 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.2908292655 |
|
|
Sep 10 05:22:54 AM UTC 24 |
Sep 10 05:24:10 AM UTC 24 |
2476493919 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.1128706518 |
|
|
Sep 10 05:14:18 AM UTC 24 |
Sep 10 05:24:23 AM UTC 24 |
59071615561 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3106533782 |
|
|
Sep 10 05:01:46 AM UTC 24 |
Sep 10 05:24:24 AM UTC 24 |
82048162417 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.3581499291 |
|
|
Sep 10 05:24:00 AM UTC 24 |
Sep 10 05:24:26 AM UTC 24 |
47162243 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.851712728 |
|
|
Sep 10 05:20:53 AM UTC 24 |
Sep 10 05:24:28 AM UTC 24 |
391837347 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.3931046815 |
|
|
Sep 10 05:22:25 AM UTC 24 |
Sep 10 05:24:30 AM UTC 24 |
2405608134 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.2179551321 |
|
|
Sep 10 05:22:12 AM UTC 24 |
Sep 10 05:24:35 AM UTC 24 |
5729791375 ps |
| T1371 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.146668013 |
|
|
Sep 10 05:24:48 AM UTC 24 |
Sep 10 05:24:57 AM UTC 24 |
41395993 ps |
| T1372 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.1775556655 |
|
|
Sep 10 05:24:50 AM UTC 24 |
Sep 10 05:25:00 AM UTC 24 |
45924419 ps |
| T1373 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1464731590 |
|
|
Sep 10 05:02:56 AM UTC 24 |
Sep 10 05:25:05 AM UTC 24 |
24299173497 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.1256840782 |
|
|
Sep 10 05:24:51 AM UTC 24 |
Sep 10 05:25:17 AM UTC 24 |
471205888 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.2867723173 |
|
|
Sep 10 05:25:01 AM UTC 24 |
Sep 10 05:25:36 AM UTC 24 |
269297535 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.3351283027 |
|
|
Sep 10 05:25:44 AM UTC 24 |
Sep 10 05:25:58 AM UTC 24 |
208836903 ps |
| T1374 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.3892481936 |
|
|
Sep 10 05:24:50 AM UTC 24 |
Sep 10 05:26:15 AM UTC 24 |
9099430867 ps |
| T1375 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.2533744404 |
|
|
Sep 10 05:26:03 AM UTC 24 |
Sep 10 05:26:29 AM UTC 24 |
208240987 ps |
| T1376 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.3704404593 |
|
|
Sep 10 05:24:55 AM UTC 24 |
Sep 10 05:26:42 AM UTC 24 |
5365891896 ps |
| T1377 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.2758513769 |
|
|
Sep 10 05:24:02 AM UTC 24 |
Sep 10 05:27:05 AM UTC 24 |
5237760150 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.2670813640 |
|
|
Sep 10 05:16:47 AM UTC 24 |
Sep 10 05:27:11 AM UTC 24 |
62038891322 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.1790770761 |
|
|
Sep 10 05:18:29 AM UTC 24 |
Sep 10 05:27:22 AM UTC 24 |
4708075696 ps |
| T1378 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.755585176 |
|
|
Sep 10 05:26:42 AM UTC 24 |
Sep 10 05:27:35 AM UTC 24 |
1315125752 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.1388359950 |
|
|
Sep 10 05:18:04 AM UTC 24 |
Sep 10 05:27:37 AM UTC 24 |
12029008402 ps |
| T1379 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.3206154889 |
|
|
Sep 10 05:26:25 AM UTC 24 |
Sep 10 05:27:46 AM UTC 24 |
1305202175 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.2328136154 |
|
|
Sep 10 05:25:28 AM UTC 24 |
Sep 10 05:27:47 AM UTC 24 |
2476866499 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.873632589 |
|
|
Sep 10 05:24:35 AM UTC 24 |
Sep 10 05:28:00 AM UTC 24 |
3511565776 ps |
| T1380 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.2578104864 |
|
|
Sep 10 05:27:17 AM UTC 24 |
Sep 10 05:28:04 AM UTC 24 |
449572618 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.470660711 |
|
|
Sep 10 05:13:21 AM UTC 24 |
Sep 10 05:28:08 AM UTC 24 |
7706400615 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.2114297045 |
|
|
Sep 10 05:27:10 AM UTC 24 |
Sep 10 05:28:13 AM UTC 24 |
609102469 ps |
| T1381 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.2287699662 |
|
|
Sep 10 05:28:03 AM UTC 24 |
Sep 10 05:28:13 AM UTC 24 |
222790749 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.109178818 |
|
|
Sep 10 05:11:36 AM UTC 24 |
Sep 10 05:28:17 AM UTC 24 |
102187899666 ps |
| T1382 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.295979043 |
|
|
Sep 10 05:28:13 AM UTC 24 |
Sep 10 05:28:23 AM UTC 24 |
37693462 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.3872057277 |
|
|
Sep 10 05:24:03 AM UTC 24 |
Sep 10 05:28:28 AM UTC 24 |
3869538728 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.1519618538 |
|
|
Sep 10 05:16:06 AM UTC 24 |
Sep 10 05:28:32 AM UTC 24 |
5533818600 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.716673406 |
|
|
Sep 10 05:28:30 AM UTC 24 |
Sep 10 05:29:15 AM UTC 24 |
346614071 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.2760819651 |
|
|
Sep 10 05:28:26 AM UTC 24 |
Sep 10 05:29:18 AM UTC 24 |
991128376 ps |
| T1383 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.1955004826 |
|
|
Sep 10 05:28:55 AM UTC 24 |
Sep 10 05:29:30 AM UTC 24 |
280212575 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.2138536050 |
|
|
Sep 10 05:17:03 AM UTC 24 |
Sep 10 05:29:31 AM UTC 24 |
50110228289 ps |
| T1384 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.2001855780 |
|
|
Sep 10 05:29:00 AM UTC 24 |
Sep 10 05:29:38 AM UTC 24 |
559134505 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.3722832689 |
|
|
Sep 10 05:22:25 AM UTC 24 |
Sep 10 05:29:47 AM UTC 24 |
22959198964 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.22541620 |
|
|
Sep 10 05:28:41 AM UTC 24 |
Sep 10 05:29:47 AM UTC 24 |
532476401 ps |
| T1385 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.378626494 |
|
|
Sep 10 05:28:17 AM UTC 24 |
Sep 10 05:29:48 AM UTC 24 |
3786933382 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.2488601761 |
|
|
Sep 10 05:10:23 AM UTC 24 |
Sep 10 05:29:52 AM UTC 24 |
10399164824 ps |
| T1386 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.1455090938 |
|
|
Sep 10 05:28:12 AM UTC 24 |
Sep 10 05:29:53 AM UTC 24 |
7220170849 ps |
| T1387 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.132953970 |
|
|
Sep 10 05:28:51 AM UTC 24 |
Sep 10 05:30:25 AM UTC 24 |
2224817084 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.4052162334 |
|
|
Sep 10 05:30:20 AM UTC 24 |
Sep 10 05:30:36 AM UTC 24 |
230304560 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.2425477131 |
|
|
Sep 10 05:21:41 AM UTC 24 |
Sep 10 05:30:40 AM UTC 24 |
4449575990 ps |
| T1388 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.3412722768 |
|
|
Sep 10 05:19:42 AM UTC 24 |
Sep 10 05:30:45 AM UTC 24 |
46647631153 ps |
| T1389 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2307897109 |
|
|
Sep 10 05:29:42 AM UTC 24 |
Sep 10 05:30:52 AM UTC 24 |
1376657549 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.2196095551 |
|
|
Sep 10 05:23:47 AM UTC 24 |
Sep 10 05:30:58 AM UTC 24 |
10636330878 ps |
| T1390 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.4075844731 |
|
|
Sep 10 05:30:50 AM UTC 24 |
Sep 10 05:31:00 AM UTC 24 |
45416974 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.2772825226 |
|
|
Sep 10 05:14:49 AM UTC 24 |
Sep 10 05:31:03 AM UTC 24 |
58402008249 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.3938796771 |
|
|
Sep 10 05:21:10 AM UTC 24 |
Sep 10 05:31:14 AM UTC 24 |
5720594437 ps |
| T1391 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.197696496 |
|
|
Sep 10 05:21:22 AM UTC 24 |
Sep 10 05:31:50 AM UTC 24 |
5631204216 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.2852239197 |
|
|
Sep 10 05:21:17 AM UTC 24 |
Sep 10 05:31:51 AM UTC 24 |
5890471452 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.396529989 |
|
|
Sep 10 05:31:29 AM UTC 24 |
Sep 10 05:31:57 AM UTC 24 |
349565743 ps |
| T1392 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.3364472047 |
|
|
Sep 10 05:31:02 AM UTC 24 |
Sep 10 05:32:01 AM UTC 24 |
5336774565 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.938941653 |
|
|
Sep 10 05:31:18 AM UTC 24 |
Sep 10 05:32:07 AM UTC 24 |
437579585 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.575279436 |
|
|
Sep 10 05:30:05 AM UTC 24 |
Sep 10 05:32:09 AM UTC 24 |
2166346621 ps |
| T1393 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.4179682315 |
|
|
Sep 10 05:25:01 AM UTC 24 |
Sep 10 05:32:14 AM UTC 24 |
42328221186 ps |
| T1394 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.254371845 |
|
|
Sep 10 05:28:34 AM UTC 24 |
Sep 10 05:32:30 AM UTC 24 |
23059505345 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.2669564680 |
|
|
Sep 10 05:19:56 AM UTC 24 |
Sep 10 05:32:33 AM UTC 24 |
50756585097 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.1330662900 |
|
|
Sep 10 05:31:12 AM UTC 24 |
Sep 10 05:32:34 AM UTC 24 |
1660166576 ps |
| T1395 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.4084785939 |
|
|
Sep 10 05:32:27 AM UTC 24 |
Sep 10 05:32:49 AM UTC 24 |
126276737 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.221602871 |
|
|
Sep 10 05:19:16 AM UTC 24 |
Sep 10 05:32:59 AM UTC 24 |
82096682645 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.604975400 |
|
|
Sep 10 05:10:24 AM UTC 24 |
Sep 10 05:33:09 AM UTC 24 |
15147545456 ps |
| T1396 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.511219462 |
|
|
Sep 10 05:31:07 AM UTC 24 |
Sep 10 05:33:14 AM UTC 24 |
5620828284 ps |
| T1397 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.563509791 |
|
|
Sep 10 05:32:23 AM UTC 24 |
Sep 10 05:33:21 AM UTC 24 |
1282590245 ps |
| T1398 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.1772075018 |
|
|
Sep 10 05:18:23 AM UTC 24 |
Sep 10 05:33:27 AM UTC 24 |
9477798736 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.555785308 |
|
|
Sep 10 05:29:45 AM UTC 24 |
Sep 10 05:33:33 AM UTC 24 |
2088075288 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1842759948 |
|
|
Sep 10 05:32:58 AM UTC 24 |
Sep 10 05:33:33 AM UTC 24 |
161359848 ps |
| T1399 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.4142161698 |
|
|
Sep 10 05:33:37 AM UTC 24 |
Sep 10 05:33:46 AM UTC 24 |
50735778 ps |
| T1400 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2465327829 |
|
|
Sep 10 05:33:41 AM UTC 24 |
Sep 10 05:33:50 AM UTC 24 |
49034439 ps |
| T1401 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.3170678082 |
|
|
Sep 10 05:32:18 AM UTC 24 |
Sep 10 05:34:01 AM UTC 24 |
2488823334 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.2202070248 |
|
|
Sep 10 05:32:17 AM UTC 24 |
Sep 10 05:34:14 AM UTC 24 |
2694113234 ps |
| T1402 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.2548584707 |
|
|
Sep 10 05:16:08 AM UTC 24 |
Sep 10 05:34:28 AM UTC 24 |
12141175828 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.3948764293 |
|
|
Sep 10 05:28:03 AM UTC 24 |
Sep 10 05:34:39 AM UTC 24 |
4255536820 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.1991640637 |
|
|
Sep 10 05:34:28 AM UTC 24 |
Sep 10 05:34:43 AM UTC 24 |
196233408 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.1756136400 |
|
|
Sep 10 05:34:01 AM UTC 24 |
Sep 10 05:34:49 AM UTC 24 |
357192271 ps |