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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.17 95.52 94.02 95.39 94.99 97.53 99.59


Total test records in report: 2926
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T2514 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.4034635579 Sep 10 07:18:05 AM UTC 24 Sep 10 07:18:29 AM UTC 24 426798092 ps
T2515 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.337259605 Sep 10 07:18:11 AM UTC 24 Sep 10 07:18:41 AM UTC 24 571550708 ps
T2516 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.1062991332 Sep 10 07:17:53 AM UTC 24 Sep 10 07:18:42 AM UTC 24 809165554 ps
T2517 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.1379530795 Sep 10 07:18:31 AM UTC 24 Sep 10 07:18:45 AM UTC 24 236875515 ps
T2518 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.2753201047 Sep 10 07:18:36 AM UTC 24 Sep 10 07:18:45 AM UTC 24 39515215 ps
T2519 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3916628088 Sep 10 07:12:46 AM UTC 24 Sep 10 07:18:51 AM UTC 24 7166899551 ps
T2520 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.1859520916 Sep 10 07:16:01 AM UTC 24 Sep 10 07:18:51 AM UTC 24 5326443817 ps
T2521 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.3599231793 Sep 10 07:17:35 AM UTC 24 Sep 10 07:18:55 AM UTC 24 2217778066 ps
T2522 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.3154089733 Sep 10 07:14:10 AM UTC 24 Sep 10 07:18:59 AM UTC 24 5020590490 ps
T2523 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.536790117 Sep 10 07:18:03 AM UTC 24 Sep 10 07:19:14 AM UTC 24 2216943422 ps
T2524 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.766214908 Sep 10 07:17:30 AM UTC 24 Sep 10 07:19:24 AM UTC 24 5599932697 ps
T2525 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.1347545232 Sep 10 07:17:08 AM UTC 24 Sep 10 07:19:26 AM UTC 24 4185120911 ps
T2526 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.1953052227 Sep 10 07:17:27 AM UTC 24 Sep 10 07:19:27 AM UTC 24 10809762733 ps
T2527 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.3740603765 Sep 10 07:15:09 AM UTC 24 Sep 10 07:19:28 AM UTC 24 1743063191 ps
T2528 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.882076934 Sep 10 07:19:08 AM UTC 24 Sep 10 07:19:32 AM UTC 24 355335301 ps
T2529 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.3819619154 Sep 10 07:18:50 AM UTC 24 Sep 10 07:19:35 AM UTC 24 483929052 ps
T2530 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.774221325 Sep 10 06:51:40 AM UTC 24 Sep 10 07:19:37 AM UTC 24 115698152190 ps
T2531 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.2387856591 Sep 10 07:19:20 AM UTC 24 Sep 10 07:19:39 AM UTC 24 158875549 ps
T2532 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.24906297 Sep 10 07:19:11 AM UTC 24 Sep 10 07:19:39 AM UTC 24 852675831 ps
T2533 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.1656669654 Sep 10 07:18:50 AM UTC 24 Sep 10 07:19:41 AM UTC 24 1266122855 ps
T2534 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.397121302 Sep 10 07:09:58 AM UTC 24 Sep 10 07:19:52 AM UTC 24 6864148100 ps
T2535 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.4174826663 Sep 10 07:18:45 AM UTC 24 Sep 10 07:20:04 AM UTC 24 4258486267 ps
T2536 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.3005509738 Sep 10 07:19:55 AM UTC 24 Sep 10 07:20:04 AM UTC 24 43570982 ps
T2537 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.2820885877 Sep 10 07:19:55 AM UTC 24 Sep 10 07:20:05 AM UTC 24 45894952 ps
T2538 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.1841813386 Sep 10 07:19:17 AM UTC 24 Sep 10 07:20:10 AM UTC 24 976398799 ps
T2539 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.1344224854 Sep 10 07:18:43 AM UTC 24 Sep 10 07:20:19 AM UTC 24 8601788439 ps
T2540 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.1933869801 Sep 10 07:19:10 AM UTC 24 Sep 10 07:20:25 AM UTC 24 2000336505 ps
T2541 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.2329370037 Sep 10 07:14:49 AM UTC 24 Sep 10 07:20:41 AM UTC 24 4208476986 ps
T2542 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.2019598841 Sep 10 07:20:32 AM UTC 24 Sep 10 07:20:43 AM UTC 24 52627827 ps
T2543 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.2814104440 Sep 10 07:20:04 AM UTC 24 Sep 10 07:20:44 AM UTC 24 1148678199 ps
T2544 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.3941067175 Sep 10 07:08:29 AM UTC 24 Sep 10 07:20:45 AM UTC 24 45902260257 ps
T2545 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.3126338969 Sep 10 07:20:30 AM UTC 24 Sep 10 07:20:50 AM UTC 24 423619289 ps
T2546 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.948669498 Sep 10 07:20:04 AM UTC 24 Sep 10 07:20:52 AM UTC 24 414683094 ps
T2547 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.1253952483 Sep 10 07:17:18 AM UTC 24 Sep 10 07:20:52 AM UTC 24 2596733810 ps
T2548 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.4164352657 Sep 10 07:20:38 AM UTC 24 Sep 10 07:20:53 AM UTC 24 87538195 ps
T2549 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.2110807252 Sep 10 07:16:16 AM UTC 24 Sep 10 07:20:58 AM UTC 24 5912423115 ps
T2550 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.519932380 Sep 10 07:19:24 AM UTC 24 Sep 10 07:21:01 AM UTC 24 225944748 ps
T2551 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.1868510674 Sep 10 07:20:08 AM UTC 24 Sep 10 07:21:07 AM UTC 24 446515708 ps
T2552 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.3670093952 Sep 10 07:10:36 AM UTC 24 Sep 10 07:21:16 AM UTC 24 46148505894 ps
T2553 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.3947879344 Sep 10 07:21:07 AM UTC 24 Sep 10 07:21:17 AM UTC 24 48076050 ps
T2554 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.2595169803 Sep 10 07:21:11 AM UTC 24 Sep 10 07:21:22 AM UTC 24 49853191 ps
T2555 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.4061604168 Sep 10 07:20:32 AM UTC 24 Sep 10 07:21:24 AM UTC 24 1210251040 ps
T2556 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.4173430014 Sep 10 07:19:56 AM UTC 24 Sep 10 07:21:30 AM UTC 24 9698212169 ps
T2557 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.3026492159 Sep 10 07:21:19 AM UTC 24 Sep 10 07:21:43 AM UTC 24 402368138 ps
T2558 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.2170060176 Sep 10 07:19:57 AM UTC 24 Sep 10 07:21:46 AM UTC 24 6241590555 ps
T2559 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.2346054178 Sep 10 07:13:23 AM UTC 24 Sep 10 07:21:46 AM UTC 24 37462912748 ps
T2560 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.4204702020 Sep 10 07:21:20 AM UTC 24 Sep 10 07:21:54 AM UTC 24 303397233 ps
T2561 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.713162770 Sep 10 06:52:47 AM UTC 24 Sep 10 07:21:58 AM UTC 24 116675415350 ps
T2562 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_slow_rsp.3643735011 Sep 10 07:21:28 AM UTC 24 Sep 10 07:22:06 AM UTC 24 2357831081 ps
T2563 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.1970885086 Sep 10 07:11:44 AM UTC 24 Sep 10 07:22:13 AM UTC 24 54368959704 ps
T2564 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.391076164 Sep 10 07:21:15 AM UTC 24 Sep 10 07:22:24 AM UTC 24 7655021903 ps
T2565 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.1725614394 Sep 10 07:21:57 AM UTC 24 Sep 10 07:22:28 AM UTC 24 561047369 ps
T2566 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.626456273 Sep 10 07:21:48 AM UTC 24 Sep 10 07:22:35 AM UTC 24 1229587812 ps
T2567 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.998758041 Sep 10 07:22:26 AM UTC 24 Sep 10 07:22:35 AM UTC 24 188805584 ps
T2568 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.816473569 Sep 10 07:03:19 AM UTC 24 Sep 10 07:22:39 AM UTC 24 72920408539 ps
T2569 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.1316926848 Sep 10 07:21:29 AM UTC 24 Sep 10 07:22:40 AM UTC 24 670892612 ps
T2570 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.1216167096 Sep 10 07:22:34 AM UTC 24 Sep 10 07:22:44 AM UTC 24 42083597 ps
T2571 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.369382139 Sep 10 07:22:14 AM UTC 24 Sep 10 07:22:44 AM UTC 24 310001723 ps
T2572 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.3948683106 Sep 10 07:21:18 AM UTC 24 Sep 10 07:22:55 AM UTC 24 6276115676 ps
T2573 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.1301617434 Sep 10 06:59:39 AM UTC 24 Sep 10 07:22:59 AM UTC 24 79635970017 ps
T2574 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.1875896015 Sep 10 07:17:59 AM UTC 24 Sep 10 07:23:02 AM UTC 24 17886918960 ps
T2575 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.3550087046 Sep 10 07:21:52 AM UTC 24 Sep 10 07:23:03 AM UTC 24 1296840533 ps
T2576 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.3195855464 Sep 10 07:21:40 AM UTC 24 Sep 10 07:23:04 AM UTC 24 2226476473 ps
T2577 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.2126942321 Sep 10 07:23:00 AM UTC 24 Sep 10 07:23:16 AM UTC 24 121133258 ps
T2578 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.2894292986 Sep 10 07:18:12 AM UTC 24 Sep 10 07:23:20 AM UTC 24 7705420247 ps
T2579 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.2426981337 Sep 10 07:23:08 AM UTC 24 Sep 10 07:23:27 AM UTC 24 239755335 ps
T2580 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.3866464150 Sep 10 07:20:46 AM UTC 24 Sep 10 07:23:34 AM UTC 24 5125873748 ps
T2581 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.1608643804 Sep 10 07:21:04 AM UTC 24 Sep 10 07:23:38 AM UTC 24 4529007548 ps
T2582 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.1670341373 Sep 10 07:23:22 AM UTC 24 Sep 10 07:23:43 AM UTC 24 152879467 ps
T2583 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.307173215 Sep 10 07:16:58 AM UTC 24 Sep 10 07:23:45 AM UTC 24 27249846729 ps
T2584 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.3299040392 Sep 10 07:19:21 AM UTC 24 Sep 10 07:23:49 AM UTC 24 2981939033 ps
T2585 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.970851223 Sep 10 07:23:29 AM UTC 24 Sep 10 07:23:51 AM UTC 24 360946365 ps
T2586 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.1784777450 Sep 10 07:22:40 AM UTC 24 Sep 10 07:23:51 AM UTC 24 6723144856 ps
T2587 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.740333214 Sep 10 07:05:40 AM UTC 24 Sep 10 07:23:55 AM UTC 24 107392905647 ps
T2588 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.3965184389 Sep 10 07:23:27 AM UTC 24 Sep 10 07:23:59 AM UTC 24 523803341 ps
T2589 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.3215709813 Sep 10 07:23:54 AM UTC 24 Sep 10 07:24:08 AM UTC 24 217755964 ps
T2590 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.1725347348 Sep 10 07:24:02 AM UTC 24 Sep 10 07:24:12 AM UTC 24 48560935 ps
T2591 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.1933158203 Sep 10 07:22:57 AM UTC 24 Sep 10 07:24:18 AM UTC 24 2158242214 ps
T2592 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.3964668351 Sep 10 07:14:34 AM UTC 24 Sep 10 07:24:21 AM UTC 24 51082827843 ps
T2593 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.808146221 Sep 10 07:24:13 AM UTC 24 Sep 10 07:24:26 AM UTC 24 170379146 ps
T2594 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.3108095872 Sep 10 07:22:51 AM UTC 24 Sep 10 07:24:32 AM UTC 24 4679483446 ps
T2595 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.2700142934 Sep 10 07:23:06 AM UTC 24 Sep 10 07:24:33 AM UTC 24 1136191788 ps
T2596 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.1412262855 Sep 10 07:18:18 AM UTC 24 Sep 10 07:24:34 AM UTC 24 13041028305 ps
T2597 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.3052034282 Sep 10 07:24:16 AM UTC 24 Sep 10 07:24:46 AM UTC 24 229862897 ps
T2598 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.1250733619 Sep 10 07:14:33 AM UTC 24 Sep 10 07:24:50 AM UTC 24 39626542289 ps
T2599 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.1646377544 Sep 10 07:24:45 AM UTC 24 Sep 10 07:24:54 AM UTC 24 51657775 ps
T2600 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.3839084807 Sep 10 07:21:09 AM UTC 24 Sep 10 07:24:55 AM UTC 24 626606936 ps
T2601 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.3880519757 Sep 10 07:24:40 AM UTC 24 Sep 10 07:24:58 AM UTC 24 134016753 ps
T2602 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.2226186848 Sep 10 07:07:02 AM UTC 24 Sep 10 07:24:59 AM UTC 24 66098681377 ps
T2603 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1214279487 Sep 10 07:18:10 AM UTC 24 Sep 10 07:25:03 AM UTC 24 6335925015 ps
T2604 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_large_delays.3947729552 Sep 10 07:17:45 AM UTC 24 Sep 10 07:25:06 AM UTC 24 48639028243 ps
T2605 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.3174169044 Sep 10 07:24:48 AM UTC 24 Sep 10 07:25:12 AM UTC 24 200448885 ps
T2606 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.2430800978 Sep 10 07:25:14 AM UTC 24 Sep 10 07:25:24 AM UTC 24 43011520 ps
T2607 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.3171685018 Sep 10 07:24:36 AM UTC 24 Sep 10 07:25:25 AM UTC 24 1256502117 ps
T2608 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.960836791 Sep 10 07:25:18 AM UTC 24 Sep 10 07:25:26 AM UTC 24 36464064 ps
T2609 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.188765030 Sep 10 07:25:22 AM UTC 24 Sep 10 07:25:35 AM UTC 24 135827936 ps
T2610 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.635216161 Sep 10 07:15:05 AM UTC 24 Sep 10 07:25:36 AM UTC 24 12791626122 ps
T2611 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.4020856166 Sep 10 07:22:10 AM UTC 24 Sep 10 07:25:52 AM UTC 24 6013311801 ps
T2612 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.1520285314 Sep 10 07:20:53 AM UTC 24 Sep 10 07:25:55 AM UTC 24 2800755712 ps
T2613 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.738509568 Sep 10 07:24:11 AM UTC 24 Sep 10 07:25:55 AM UTC 24 6848620500 ps
T2614 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.1331863786 Sep 10 07:17:01 AM UTC 24 Sep 10 07:25:56 AM UTC 24 37250841204 ps
T2615 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.2791314478 Sep 10 06:58:35 AM UTC 24 Sep 10 07:25:56 AM UTC 24 117001756728 ps
T2616 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.1003650867 Sep 10 07:24:06 AM UTC 24 Sep 10 07:26:02 AM UTC 24 11069873686 ps
T2617 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.3551694982 Sep 10 07:25:53 AM UTC 24 Sep 10 07:26:06 AM UTC 24 78224889 ps
T2618 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.2396240036 Sep 10 07:18:21 AM UTC 24 Sep 10 07:26:08 AM UTC 24 4203784984 ps
T2619 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.1539878589 Sep 10 07:24:22 AM UTC 24 Sep 10 07:26:13 AM UTC 24 1204149581 ps
T2620 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.1333371567 Sep 10 07:25:26 AM UTC 24 Sep 10 07:26:17 AM UTC 24 525900821 ps
T2621 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.2555969355 Sep 10 07:26:04 AM UTC 24 Sep 10 07:26:18 AM UTC 24 273582292 ps
T2622 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.1578911397 Sep 10 07:19:42 AM UTC 24 Sep 10 07:26:28 AM UTC 24 13122356165 ps
T2623 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.1421647909 Sep 10 07:25:52 AM UTC 24 Sep 10 07:26:30 AM UTC 24 994230379 ps
T2624 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.162652053 Sep 10 07:26:22 AM UTC 24 Sep 10 07:26:36 AM UTC 24 220728345 ps
T2625 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.3714146000 Sep 10 07:26:27 AM UTC 24 Sep 10 07:26:37 AM UTC 24 52386427 ps
T2626 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.1044092132 Sep 10 07:24:54 AM UTC 24 Sep 10 07:26:44 AM UTC 24 3211457569 ps
T2627 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.3604041149 Sep 10 07:26:04 AM UTC 24 Sep 10 07:26:48 AM UTC 24 282528287 ps
T2628 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.1647327860 Sep 10 07:25:39 AM UTC 24 Sep 10 07:26:51 AM UTC 24 1483182433 ps
T2629 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.1393733628 Sep 10 07:25:21 AM UTC 24 Sep 10 07:27:01 AM UTC 24 9424689165 ps
T2630 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.901036772 Sep 10 07:11:56 AM UTC 24 Sep 10 07:27:11 AM UTC 24 64664316957 ps
T2631 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.3256956347 Sep 10 07:27:03 AM UTC 24 Sep 10 07:27:15 AM UTC 24 72397817 ps
T2632 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.429970871 Sep 10 07:25:00 AM UTC 24 Sep 10 07:27:21 AM UTC 24 3389544922 ps
T2633 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.1562323698 Sep 10 07:21:40 AM UTC 24 Sep 10 07:27:23 AM UTC 24 23656628429 ps
T2634 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.337582307 Sep 10 07:25:22 AM UTC 24 Sep 10 07:27:33 AM UTC 24 5854460902 ps
T2635 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.4129597411 Sep 10 07:26:46 AM UTC 24 Sep 10 07:27:34 AM UTC 24 434426293 ps
T2636 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.1228905578 Sep 10 07:27:18 AM UTC 24 Sep 10 07:27:35 AM UTC 24 124213510 ps
T2637 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_large_delays.3734332504 Sep 10 07:26:46 AM UTC 24 Sep 10 07:27:37 AM UTC 24 3923708185 ps
T2638 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.2704960973 Sep 10 07:27:11 AM UTC 24 Sep 10 07:27:41 AM UTC 24 781112849 ps
T2639 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.2920398557 Sep 10 07:19:52 AM UTC 24 Sep 10 07:27:43 AM UTC 24 3548166773 ps
T2640 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.2084684362 Sep 10 07:27:15 AM UTC 24 Sep 10 07:27:51 AM UTC 24 213762690 ps
T2641 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.1577427991 Sep 10 07:26:42 AM UTC 24 Sep 10 07:27:53 AM UTC 24 1897461891 ps
T2642 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_slow_rsp.3588268151 Sep 10 07:17:43 AM UTC 24 Sep 10 07:27:57 AM UTC 24 36391844117 ps
T2643 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.1202576830 Sep 10 07:27:48 AM UTC 24 Sep 10 07:27:58 AM UTC 24 48385080 ps
T2644 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.4177957544 Sep 10 07:26:35 AM UTC 24 Sep 10 07:28:01 AM UTC 24 8513661962 ps
T2645 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.3046707618 Sep 10 07:27:59 AM UTC 24 Sep 10 07:28:10 AM UTC 24 55009383 ps
T2646 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_slow_rsp.1297387593 Sep 10 07:18:57 AM UTC 24 Sep 10 07:28:12 AM UTC 24 39679944866 ps
T2647 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.3743253202 Sep 10 07:26:58 AM UTC 24 Sep 10 07:28:14 AM UTC 24 965064660 ps
T2648 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.2879066691 Sep 10 07:26:37 AM UTC 24 Sep 10 07:28:19 AM UTC 24 4845202245 ps
T2649 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.3113414437 Sep 10 07:23:32 AM UTC 24 Sep 10 07:28:20 AM UTC 24 3523992139 ps
T2650 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.396295122 Sep 10 07:17:16 AM UTC 24 Sep 10 07:28:32 AM UTC 24 5029992726 ps
T2651 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.2320045796 Sep 10 07:28:20 AM UTC 24 Sep 10 07:28:38 AM UTC 24 262246280 ps
T2652 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.2425058642 Sep 10 07:15:36 AM UTC 24 Sep 10 07:28:38 AM UTC 24 77549305805 ps
T2653 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.1522235746 Sep 10 07:27:59 AM UTC 24 Sep 10 07:28:42 AM UTC 24 4450071808 ps
T2654 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.408977461 Sep 10 07:28:36 AM UTC 24 Sep 10 07:28:47 AM UTC 24 38020580 ps
T2655 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.4204161733 Sep 10 07:28:09 AM UTC 24 Sep 10 07:28:50 AM UTC 24 339645289 ps
T2656 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_large_delays.2012492350 Sep 10 07:25:30 AM UTC 24 Sep 10 07:28:56 AM UTC 24 18337351703 ps
T2657 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.3175668731 Sep 10 07:28:05 AM UTC 24 Sep 10 07:29:01 AM UTC 24 592527489 ps
T2658 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.4251463304 Sep 10 07:28:59 AM UTC 24 Sep 10 07:29:11 AM UTC 24 166536416 ps
T2659 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.3194599880 Sep 10 07:29:04 AM UTC 24 Sep 10 07:29:15 AM UTC 24 44476601 ps
T2660 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.4023611208 Sep 10 07:28:04 AM UTC 24 Sep 10 07:29:16 AM UTC 24 4580503963 ps
T2661 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.2833705349 Sep 10 07:28:25 AM UTC 24 Sep 10 07:29:24 AM UTC 24 2310296456 ps
T2662 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.1939659711 Sep 10 07:28:39 AM UTC 24 Sep 10 07:29:24 AM UTC 24 1266225741 ps
T2663 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_large_delays.2681631074 Sep 10 07:20:06 AM UTC 24 Sep 10 07:29:29 AM UTC 24 64727335042 ps
T2664 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.882974516 Sep 10 07:28:26 AM UTC 24 Sep 10 07:29:31 AM UTC 24 2045153474 ps
T2665 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.2099224508 Sep 10 07:29:16 AM UTC 24 Sep 10 07:29:34 AM UTC 24 111720148 ps
T2666 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.1863638772 Sep 10 07:29:40 AM UTC 24 Sep 10 07:29:54 AM UTC 24 103257448 ps
T2667 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3769269025 Sep 10 07:23:33 AM UTC 24 Sep 10 07:30:01 AM UTC 24 2276342715 ps
T2668 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.373076253 Sep 10 07:29:55 AM UTC 24 Sep 10 07:30:06 AM UTC 24 68902222 ps
T2669 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_error.2594197527 Sep 10 07:26:24 AM UTC 24 Sep 10 07:30:11 AM UTC 24 5888405900 ps
T2670 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.1121605460 Sep 10 07:15:42 AM UTC 24 Sep 10 07:30:14 AM UTC 24 56781131648 ps
T2671 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.619643767 Sep 10 07:09:37 AM UTC 24 Sep 10 07:30:21 AM UTC 24 71357975782 ps
T2672 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_slow_rsp.141798183 Sep 10 07:29:29 AM UTC 24 Sep 10 07:30:23 AM UTC 24 2598425625 ps
T2673 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.903389874 Sep 10 07:29:01 AM UTC 24 Sep 10 07:30:24 AM UTC 24 6333997102 ps
T2674 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.4044658270 Sep 10 07:29:51 AM UTC 24 Sep 10 07:30:27 AM UTC 24 242736352 ps
T2675 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_slow_rsp.1055418370 Sep 10 07:23:07 AM UTC 24 Sep 10 07:30:28 AM UTC 24 29356852569 ps
T2676 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all.872607570 Sep 10 07:26:19 AM UTC 24 Sep 10 07:30:28 AM UTC 24 3062401795 ps
T2677 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.2956831690 Sep 10 07:29:14 AM UTC 24 Sep 10 07:30:32 AM UTC 24 2116966021 ps
T2678 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all.2462923838 Sep 10 07:28:41 AM UTC 24 Sep 10 07:30:38 AM UTC 24 1483396276 ps
T2679 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.1419311800 Sep 10 07:29:52 AM UTC 24 Sep 10 07:30:41 AM UTC 24 1480487557 ps
T2680 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.3910750125 Sep 10 07:29:08 AM UTC 24 Sep 10 07:30:45 AM UTC 24 4647451900 ps
T2681 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.4137272917 Sep 10 07:30:34 AM UTC 24 Sep 10 07:30:47 AM UTC 24 192305037 ps
T2682 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_slow_rsp.3474310770 Sep 10 07:26:53 AM UTC 24 Sep 10 07:30:47 AM UTC 24 16444588132 ps
T2683 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.1352794930 Sep 10 07:30:40 AM UTC 24 Sep 10 07:30:50 AM UTC 24 54409654 ps
T2684 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.1794854146 Sep 10 07:27:48 AM UTC 24 Sep 10 07:30:51 AM UTC 24 1590629260 ps
T2685 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.1264182459 Sep 10 07:27:26 AM UTC 24 Sep 10 07:30:53 AM UTC 24 6796322908 ps
T2686 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.863364818 Sep 10 07:29:44 AM UTC 24 Sep 10 07:31:02 AM UTC 24 2016608141 ps
T2687 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3095319029 Sep 10 07:23:48 AM UTC 24 Sep 10 07:31:03 AM UTC 24 8039780331 ps
T2688 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.1185929961 Sep 10 07:30:51 AM UTC 24 Sep 10 07:31:04 AM UTC 24 118401691 ps
T2689 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_error.2806544982 Sep 10 07:28:45 AM UTC 24 Sep 10 07:31:13 AM UTC 24 2068551734 ps
T2690 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.3491570163 Sep 10 07:13:21 AM UTC 24 Sep 10 07:31:15 AM UTC 24 89711064480 ps
T2691 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.2842873201 Sep 10 07:31:07 AM UTC 24 Sep 10 07:31:16 AM UTC 24 65316407 ps
T2692 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_large_delays.2033329777 Sep 10 07:23:02 AM UTC 24 Sep 10 07:31:16 AM UTC 24 40804196238 ps
T2693 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.869430522 Sep 10 07:30:50 AM UTC 24 Sep 10 07:31:16 AM UTC 24 235832647 ps
T2694 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.388681217 Sep 10 07:22:20 AM UTC 24 Sep 10 07:31:16 AM UTC 24 6935784815 ps
T2695 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.117398273 Sep 10 07:30:02 AM UTC 24 Sep 10 07:31:29 AM UTC 24 93560773 ps
T2696 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.3446402162 Sep 10 07:30:29 AM UTC 24 Sep 10 07:31:32 AM UTC 24 150899533 ps
T2697 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.2883847880 Sep 10 07:31:29 AM UTC 24 Sep 10 07:31:36 AM UTC 24 43029145 ps
T2698 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.984215627 Sep 10 07:31:29 AM UTC 24 Sep 10 07:31:38 AM UTC 24 43173232 ps
T2699 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.3846683257 Sep 10 07:31:10 AM UTC 24 Sep 10 07:31:40 AM UTC 24 254331206 ps
T2700 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.705111330 Sep 10 07:26:24 AM UTC 24 Sep 10 07:31:44 AM UTC 24 6166327042 ps
T2701 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.3568609861 Sep 10 07:31:20 AM UTC 24 Sep 10 07:31:47 AM UTC 24 16576626 ps
T2702 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_large_delays.1943393823 Sep 10 07:21:25 AM UTC 24 Sep 10 07:31:49 AM UTC 24 66517880811 ps
T2703 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.97919167 Sep 10 07:31:14 AM UTC 24 Sep 10 07:31:50 AM UTC 24 261569489 ps
T2704 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_large_delays.1344356310 Sep 10 07:18:52 AM UTC 24 Sep 10 07:31:51 AM UTC 24 78143588270 ps
T2705 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.3408084047 Sep 10 07:30:48 AM UTC 24 Sep 10 07:31:56 AM UTC 24 4534231041 ps
T2706 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.3605651260 Sep 10 07:23:44 AM UTC 24 Sep 10 07:32:09 AM UTC 24 14731189252 ps
T2707 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.2838640504 Sep 10 07:31:40 AM UTC 24 Sep 10 07:32:09 AM UTC 24 292917562 ps
T2708 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.166436624 Sep 10 07:31:14 AM UTC 24 Sep 10 07:32:09 AM UTC 24 89420006 ps
T2709 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.408694649 Sep 10 07:30:42 AM UTC 24 Sep 10 07:32:10 AM UTC 24 8131936676 ps
T2710 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.280191565 Sep 10 07:31:58 AM UTC 24 Sep 10 07:32:11 AM UTC 24 72780849 ps
T2711 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.898821623 Sep 10 07:32:05 AM UTC 24 Sep 10 07:32:14 AM UTC 24 69306683 ps
T2712 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.2856187638 Sep 10 07:31:43 AM UTC 24 Sep 10 07:32:16 AM UTC 24 266537003 ps
T2713 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_error.1415275648 Sep 10 07:27:43 AM UTC 24 Sep 10 07:32:20 AM UTC 24 7434051631 ps
T2714 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.2650158715 Sep 10 07:31:10 AM UTC 24 Sep 10 07:32:23 AM UTC 24 2263267800 ps
T2715 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.2007271210 Sep 10 07:32:13 AM UTC 24 Sep 10 07:32:23 AM UTC 24 48998784 ps
T2716 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.690786542 Sep 10 07:32:19 AM UTC 24 Sep 10 07:32:30 AM UTC 24 58241869 ps
T2717 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.3670601123 Sep 10 07:26:22 AM UTC 24 Sep 10 07:32:34 AM UTC 24 5228392113 ps
T2718 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.1467457777 Sep 10 07:31:39 AM UTC 24 Sep 10 07:32:36 AM UTC 24 1870127828 ps
T2719 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.2847390372 Sep 10 07:32:06 AM UTC 24 Sep 10 07:32:36 AM UTC 24 220063776 ps
T2720 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.427153935 Sep 10 07:32:02 AM UTC 24 Sep 10 07:32:48 AM UTC 24 587507106 ps
T2721 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_slow_rsp.1037468542 Sep 10 07:20:07 AM UTC 24 Sep 10 07:32:49 AM UTC 24 48003164377 ps
T2722 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.3416837091 Sep 10 07:31:31 AM UTC 24 Sep 10 07:32:54 AM UTC 24 5690625269 ps
T2723 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.1664617380 Sep 10 07:24:57 AM UTC 24 Sep 10 07:33:01 AM UTC 24 6174726803 ps
T2724 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.2639032813 Sep 10 07:30:57 AM UTC 24 Sep 10 07:33:07 AM UTC 24 2777900754 ps
T2725 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.2945313244 Sep 10 07:31:36 AM UTC 24 Sep 10 07:33:07 AM UTC 24 6649314593 ps
T2726 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.1603376800 Sep 10 07:32:56 AM UTC 24 Sep 10 07:33:24 AM UTC 24 452083480 ps
T2727 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.513902863 Sep 10 07:32:49 AM UTC 24 Sep 10 07:33:32 AM UTC 24 400770482 ps
T2728 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.1255825821 Sep 10 07:32:50 AM UTC 24 Sep 10 07:33:33 AM UTC 24 1015419923 ps
T2729 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.460531631 Sep 10 07:32:57 AM UTC 24 Sep 10 07:33:34 AM UTC 24 707636927 ps
T2730 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_slow_rsp.194834394 Sep 10 07:32:40 AM UTC 24 Sep 10 07:33:34 AM UTC 24 2383132741 ps
T2731 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.2789849679 Sep 10 07:32:39 AM UTC 24 Sep 10 07:33:34 AM UTC 24 562352688 ps
T2732 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.2565969758 Sep 10 07:32:35 AM UTC 24 Sep 10 07:33:34 AM UTC 24 569711081 ps
T2733 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.3385268571 Sep 10 07:33:22 AM UTC 24 Sep 10 07:33:36 AM UTC 24 210931309 ps
T2734 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.3430141546 Sep 10 07:33:29 AM UTC 24 Sep 10 07:33:39 AM UTC 24 50714491 ps
T2735 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.2496815159 Sep 10 07:32:43 AM UTC 24 Sep 10 07:33:43 AM UTC 24 1781898271 ps
T2736 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_slow_rsp.2464228936 Sep 10 07:25:31 AM UTC 24 Sep 10 07:33:44 AM UTC 24 27769286541 ps
T2737 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.4035728883 Sep 10 07:32:37 AM UTC 24 Sep 10 07:33:46 AM UTC 24 4707495847 ps
T2738 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.4250558694 Sep 10 07:33:15 AM UTC 24 Sep 10 07:33:47 AM UTC 24 104709912 ps
T2739 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_large_delays.2839318702 Sep 10 07:32:40 AM UTC 24 Sep 10 07:33:47 AM UTC 24 6935027200 ps
T2740 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.3145356068 Sep 10 07:32:14 AM UTC 24 Sep 10 07:34:02 AM UTC 24 102091073 ps
T2741 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_large_delays.2669536362 Sep 10 07:29:24 AM UTC 24 Sep 10 07:34:03 AM UTC 24 24920502350 ps
T2742 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_zero_delays.2750890471 Sep 10 07:33:57 AM UTC 24 Sep 10 07:34:07 AM UTC 24 40995065 ps
T2743 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_large_delays.681073594 Sep 10 07:24:17 AM UTC 24 Sep 10 07:34:14 AM UTC 24 49662874268 ps
T2744 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device.1402551949 Sep 10 07:33:58 AM UTC 24 Sep 10 07:34:17 AM UTC 24 358379044 ps
T2745 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random.190599891 Sep 10 07:33:52 AM UTC 24 Sep 10 07:34:18 AM UTC 24 689726902 ps
T2746 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3449911068 Sep 10 07:04:30 AM UTC 24 Sep 10 07:34:27 AM UTC 24 117590176940 ps
T2747 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.2570297707 Sep 10 07:34:07 AM UTC 24 Sep 10 07:34:29 AM UTC 24 354663116 ps
T2748 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_zero_delays.433699743 Sep 10 07:34:28 AM UTC 24 Sep 10 07:34:35 AM UTC 24 44073762 ps
T2749 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_error.3682113123 Sep 10 07:34:12 AM UTC 24 Sep 10 07:34:38 AM UTC 24 243039096 ps
T2750 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.1158236279 Sep 10 07:34:30 AM UTC 24 Sep 10 07:34:42 AM UTC 24 55271254 ps
T2751 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_large_delays.2775850027 Sep 10 07:33:32 AM UTC 24 Sep 10 07:34:50 AM UTC 24 6128138602 ps
T2752 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.3100595967 Sep 10 07:32:37 AM UTC 24 Sep 10 07:34:50 AM UTC 24 9311178382 ps
T2753 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.2042411831 Sep 10 07:19:11 AM UTC 24 Sep 10 07:34:51 AM UTC 24 63453870725 ps
T2754 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_slow_rsp.3727722212 Sep 10 07:24:19 AM UTC 24 Sep 10 07:34:53 AM UTC 24 45003882502 ps
T2755 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_large_delays.3776253438 Sep 10 07:16:56 AM UTC 24 Sep 10 07:34:54 AM UTC 24 93655217496 ps
T2756 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_unmapped_addr.1628710067 Sep 10 07:34:03 AM UTC 24 Sep 10 07:35:03 AM UTC 24 1045656775 ps
T2757 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_error.1345963543 Sep 10 07:32:16 AM UTC 24 Sep 10 07:35:06 AM UTC 24 2419207762 ps
T2758 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_zero_delays.1274131820 Sep 10 07:34:43 AM UTC 24 Sep 10 07:35:11 AM UTC 24 264176438 ps
T2759 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all.261149308 Sep 10 07:33:05 AM UTC 24 Sep 10 07:35:12 AM UTC 24 4129313500 ps
T2760 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_same_source.804262847 Sep 10 07:33:59 AM UTC 24 Sep 10 07:35:15 AM UTC 24 2225494484 ps
T2761 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.3612281499 Sep 10 07:33:32 AM UTC 24 Sep 10 07:35:17 AM UTC 24 5909558473 ps
T599 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.3835893109 Sep 10 07:34:04 AM UTC 24 Sep 10 07:35:18 AM UTC 24 1731732288 ps
T2762 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all.3166452672 Sep 10 07:34:06 AM UTC 24 Sep 10 07:35:22 AM UTC 24 2047522459 ps
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