| T1246 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1792565464 |
|
|
Sep 10 03:46:41 AM UTC 24 |
Sep 10 03:55:53 AM UTC 24 |
3149357765 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_testunlock0.1706690631 |
|
|
Sep 10 03:42:28 AM UTC 24 |
Sep 10 03:55:58 AM UTC 24 |
7726113162 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1662322456 |
|
|
Sep 10 03:50:07 AM UTC 24 |
Sep 10 03:56:09 AM UTC 24 |
3767208972 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1742646705 |
|
|
Sep 10 03:49:52 AM UTC 24 |
Sep 10 03:56:18 AM UTC 24 |
6948866108 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.222306604 |
|
|
Sep 10 03:43:33 AM UTC 24 |
Sep 10 03:56:38 AM UTC 24 |
5688102726 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx3.1682861112 |
|
|
Sep 10 03:45:53 AM UTC 24 |
Sep 10 03:57:04 AM UTC 24 |
4172308802 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency.776621546 |
|
|
Sep 10 02:53:25 AM UTC 24 |
Sep 10 03:58:08 AM UTC 24 |
15696925866 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_rma.257343370 |
|
|
Sep 10 03:51:58 AM UTC 24 |
Sep 10 03:58:55 AM UTC 24 |
5193483765 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.741852192 |
|
|
Sep 10 03:50:51 AM UTC 24 |
Sep 10 03:59:31 AM UTC 24 |
4557403924 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_lc_ctrl_transition.3422218319 |
|
|
Sep 10 03:41:13 AM UTC 24 |
Sep 10 03:59:54 AM UTC 24 |
11130432018 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.274697299 |
|
|
Sep 10 03:49:52 AM UTC 24 |
Sep 10 04:00:19 AM UTC 24 |
5370066158 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.735859552 |
|
|
Sep 10 03:52:55 AM UTC 24 |
Sep 10 04:00:21 AM UTC 24 |
4351975892 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.334706292 |
|
|
Sep 10 03:51:03 AM UTC 24 |
Sep 10 04:01:23 AM UTC 24 |
6722664929 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3048262786 |
|
|
Sep 10 02:41:02 AM UTC 24 |
Sep 10 04:01:54 AM UTC 24 |
19226537682 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2697813023 |
|
|
Sep 10 03:54:45 AM UTC 24 |
Sep 10 04:02:26 AM UTC 24 |
3585711278 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.1852684228 |
|
|
Sep 10 03:52:41 AM UTC 24 |
Sep 10 04:03:40 AM UTC 24 |
6979142677 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.2749928064 |
|
|
Sep 10 02:17:25 AM UTC 24 |
Sep 10 04:04:15 AM UTC 24 |
44826503592 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.3335658134 |
|
|
Sep 10 03:52:58 AM UTC 24 |
Sep 10 04:04:48 AM UTC 24 |
5791524310 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_self_hash.2403393845 |
|
|
Sep 10 01:56:04 AM UTC 24 |
Sep 10 04:05:48 AM UTC 24 |
27297655520 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_lc_ctrl_transition.4217090474 |
|
|
Sep 10 03:57:50 AM UTC 24 |
Sep 10 04:05:48 AM UTC 24 |
4420621746 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1138957307 |
|
|
Sep 10 03:57:53 AM UTC 24 |
Sep 10 04:05:49 AM UTC 24 |
4213356896 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.4004725850 |
|
|
Sep 10 03:55:41 AM UTC 24 |
Sep 10 04:05:56 AM UTC 24 |
5297588324 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1649543906 |
|
|
Sep 10 03:57:33 AM UTC 24 |
Sep 10 04:06:10 AM UTC 24 |
4356603570 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.720028434 |
|
|
Sep 10 04:01:12 AM UTC 24 |
Sep 10 04:06:15 AM UTC 24 |
3849424660 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.1613873075 |
|
|
Sep 10 03:01:07 AM UTC 24 |
Sep 10 04:06:30 AM UTC 24 |
13941358076 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_prod.1033466419 |
|
|
Sep 10 03:42:45 AM UTC 24 |
Sep 10 04:06:31 AM UTC 24 |
11646861047 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.195482227 |
|
|
Sep 10 03:47:11 AM UTC 24 |
Sep 10 04:06:41 AM UTC 24 |
8720100183 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.929805759 |
|
|
Sep 10 03:57:48 AM UTC 24 |
Sep 10 04:07:16 AM UTC 24 |
4654570474 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_testunlock0.2184876501 |
|
|
Sep 10 03:51:57 AM UTC 24 |
Sep 10 04:08:06 AM UTC 24 |
9899896529 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.2821731865 |
|
|
Sep 10 02:21:59 AM UTC 24 |
Sep 10 04:10:38 AM UTC 24 |
49835580640 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4021740196 |
|
|
Sep 10 04:04:22 AM UTC 24 |
Sep 10 04:10:48 AM UTC 24 |
3890851488 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_lc_ctrl_transition.412662625 |
|
|
Sep 10 03:54:29 AM UTC 24 |
Sep 10 04:10:55 AM UTC 24 |
12366972005 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.3046641527 |
|
|
Sep 10 03:59:40 AM UTC 24 |
Sep 10 04:10:58 AM UTC 24 |
5137552558 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.3433862898 |
|
|
Sep 10 04:02:06 AM UTC 24 |
Sep 10 04:11:32 AM UTC 24 |
4326293026 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3140208027 |
|
|
Sep 10 03:40:04 AM UTC 24 |
Sep 10 04:11:57 AM UTC 24 |
14368806908 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3935514511 |
|
|
Sep 10 04:07:25 AM UTC 24 |
Sep 10 04:12:24 AM UTC 24 |
4000909888 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_lc_ctrl_transition.3882219042 |
|
|
Sep 10 04:03:05 AM UTC 24 |
Sep 10 04:13:32 AM UTC 24 |
5939880472 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1044829733 |
|
|
Sep 10 04:08:25 AM UTC 24 |
Sep 10 04:15:16 AM UTC 24 |
4060740310 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.2402577496 |
|
|
Sep 10 04:08:20 AM UTC 24 |
Sep 10 04:15:41 AM UTC 24 |
6826554617 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.1343974441 |
|
|
Sep 10 03:53:42 AM UTC 24 |
Sep 10 04:16:51 AM UTC 24 |
7920926890 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.3143254397 |
|
|
Sep 10 04:05:31 AM UTC 24 |
Sep 10 04:16:51 AM UTC 24 |
5089344840 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.2693240814 |
|
|
Sep 10 02:24:51 AM UTC 24 |
Sep 10 04:16:51 AM UTC 24 |
48916204606 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.165552428 |
|
|
Sep 10 02:22:36 AM UTC 24 |
Sep 10 04:16:52 AM UTC 24 |
49410916600 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_lc_ctrl_transition.3708393332 |
|
|
Sep 10 04:08:01 AM UTC 24 |
Sep 10 04:17:14 AM UTC 24 |
5992369378 ps |
| T1265 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.1123906747 |
|
|
Sep 10 03:57:34 AM UTC 24 |
Sep 10 04:17:27 AM UTC 24 |
11520933661 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.403860914 |
|
|
Sep 10 04:08:47 AM UTC 24 |
Sep 10 04:17:38 AM UTC 24 |
3831577304 ps |
| T1266 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.3535093982 |
|
|
Sep 10 04:08:15 AM UTC 24 |
Sep 10 04:17:45 AM UTC 24 |
3628968810 ps |
| T1267 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.1230239680 |
|
|
Sep 10 04:08:17 AM UTC 24 |
Sep 10 04:17:54 AM UTC 24 |
3541097660 ps |
| T1268 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.740169662 |
|
|
Sep 10 04:08:29 AM UTC 24 |
Sep 10 04:18:55 AM UTC 24 |
4174322856 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.3976156510 |
|
|
Sep 10 04:08:31 AM UTC 24 |
Sep 10 04:19:09 AM UTC 24 |
5088864824 ps |
| T1269 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.3158919680 |
|
|
Sep 10 04:08:29 AM UTC 24 |
Sep 10 04:19:24 AM UTC 24 |
7310030745 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2903638017 |
|
|
Sep 10 04:12:20 AM UTC 24 |
Sep 10 04:20:14 AM UTC 24 |
3942543420 ps |
| T1270 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1774080533 |
|
|
Sep 10 03:29:00 AM UTC 24 |
Sep 10 04:20:27 AM UTC 24 |
11118300298 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.632821026 |
|
|
Sep 10 04:13:07 AM UTC 24 |
Sep 10 04:20:33 AM UTC 24 |
3480093770 ps |
| T1271 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.499030964 |
|
|
Sep 10 04:00:35 AM UTC 24 |
Sep 10 04:20:57 AM UTC 24 |
13080954606 ps |
| T1272 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.1635962237 |
|
|
Sep 10 03:39:34 AM UTC 24 |
Sep 10 04:21:02 AM UTC 24 |
13418845060 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.907939691 |
|
|
Sep 10 04:08:30 AM UTC 24 |
Sep 10 04:21:16 AM UTC 24 |
5315949660 ps |
| T1273 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.950781007 |
|
|
Sep 10 04:12:20 AM UTC 24 |
Sep 10 04:21:23 AM UTC 24 |
5996233421 ps |
| T1274 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.4269085826 |
|
|
Sep 10 04:12:05 AM UTC 24 |
Sep 10 04:21:53 AM UTC 24 |
4235823536 ps |
| T1275 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.771811419 |
|
|
Sep 10 03:56:09 AM UTC 24 |
Sep 10 04:21:53 AM UTC 24 |
7782338328 ps |
| T1276 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.2210730206 |
|
|
Sep 10 04:12:37 AM UTC 24 |
Sep 10 04:22:40 AM UTC 24 |
4101518360 ps |
| T1277 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.3249952600 |
|
|
Sep 10 03:57:29 AM UTC 24 |
Sep 10 04:23:18 AM UTC 24 |
7946685960 ps |
| T1278 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.807503050 |
|
|
Sep 10 04:00:13 AM UTC 24 |
Sep 10 04:23:29 AM UTC 24 |
8275613364 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.2404091280 |
|
|
Sep 10 04:12:23 AM UTC 24 |
Sep 10 04:23:34 AM UTC 24 |
5072924856 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.4220081 |
|
|
Sep 10 04:16:22 AM UTC 24 |
Sep 10 04:23:38 AM UTC 24 |
4237022120 ps |
| T1279 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.1402996054 |
|
|
Sep 10 04:12:40 AM UTC 24 |
Sep 10 04:23:44 AM UTC 24 |
9835682160 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.3548044011 |
|
|
Sep 10 04:14:15 AM UTC 24 |
Sep 10 04:24:59 AM UTC 24 |
5312123300 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2503343901 |
|
|
Sep 10 04:19:06 AM UTC 24 |
Sep 10 04:25:01 AM UTC 24 |
3780885248 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.1700719178 |
|
|
Sep 10 04:12:24 AM UTC 24 |
Sep 10 04:25:11 AM UTC 24 |
5882391056 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.985580311 |
|
|
Sep 10 04:20:08 AM UTC 24 |
Sep 10 04:25:29 AM UTC 24 |
3406541224 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.4011558363 |
|
|
Sep 10 04:19:17 AM UTC 24 |
Sep 10 04:25:30 AM UTC 24 |
3591065108 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.126937621 |
|
|
Sep 10 04:19:17 AM UTC 24 |
Sep 10 04:25:40 AM UTC 24 |
3481036776 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_rst_inputs.2129123181 |
|
|
Sep 10 03:23:54 AM UTC 24 |
Sep 10 04:26:54 AM UTC 24 |
22506120856 ps |
| T1280 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.263913435 |
|
|
Sep 10 04:18:41 AM UTC 24 |
Sep 10 04:27:29 AM UTC 24 |
4399039298 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.1018525497 |
|
|
Sep 10 04:19:09 AM UTC 24 |
Sep 10 04:28:56 AM UTC 24 |
5442737000 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2727716995 |
|
|
Sep 10 04:22:16 AM UTC 24 |
Sep 10 04:28:58 AM UTC 24 |
3364323686 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.2748619479 |
|
|
Sep 10 04:19:15 AM UTC 24 |
Sep 10 04:29:03 AM UTC 24 |
5556016916 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1816528513 |
|
|
Sep 10 04:22:14 AM UTC 24 |
Sep 10 04:29:17 AM UTC 24 |
4340647864 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2870303429 |
|
|
Sep 10 04:22:02 AM UTC 24 |
Sep 10 04:29:39 AM UTC 24 |
3985933180 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3657254600 |
|
|
Sep 10 04:22:50 AM UTC 24 |
Sep 10 04:29:42 AM UTC 24 |
3831032500 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.3101090451 |
|
|
Sep 10 04:22:20 AM UTC 24 |
Sep 10 04:29:57 AM UTC 24 |
5678514660 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2594981274 |
|
|
Sep 10 04:23:21 AM UTC 24 |
Sep 10 04:30:41 AM UTC 24 |
3991730590 ps |
| T1281 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.2303381816 |
|
|
Sep 10 03:45:53 AM UTC 24 |
Sep 10 04:30:44 AM UTC 24 |
12574398736 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.2259848956 |
|
|
Sep 10 04:19:33 AM UTC 24 |
Sep 10 04:31:21 AM UTC 24 |
5331323752 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.408669931 |
|
|
Sep 10 04:25:09 AM UTC 24 |
Sep 10 04:31:28 AM UTC 24 |
3451870168 ps |
| T1282 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.1932438110 |
|
|
Sep 10 04:21:18 AM UTC 24 |
Sep 10 04:31:44 AM UTC 24 |
5167477520 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2258530089 |
|
|
Sep 10 04:26:48 AM UTC 24 |
Sep 10 04:31:59 AM UTC 24 |
3336635132 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2435680088 |
|
|
Sep 10 04:25:12 AM UTC 24 |
Sep 10 04:32:20 AM UTC 24 |
3623142750 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.904423224 |
|
|
Sep 10 04:21:57 AM UTC 24 |
Sep 10 04:32:34 AM UTC 24 |
5176822878 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3267874768 |
|
|
Sep 10 04:26:48 AM UTC 24 |
Sep 10 04:32:38 AM UTC 24 |
3818366200 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.4037875429 |
|
|
Sep 10 04:19:48 AM UTC 24 |
Sep 10 04:32:57 AM UTC 24 |
5985927734 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.916507953 |
|
|
Sep 10 04:25:08 AM UTC 24 |
Sep 10 04:33:04 AM UTC 24 |
3912230760 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2360949420 |
|
|
Sep 10 04:26:44 AM UTC 24 |
Sep 10 04:33:05 AM UTC 24 |
3823951338 ps |
| T1283 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3620313335 |
|
|
Sep 10 03:22:14 AM UTC 24 |
Sep 10 04:33:23 AM UTC 24 |
24274681406 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.4157183344 |
|
|
Sep 10 04:22:21 AM UTC 24 |
Sep 10 04:35:09 AM UTC 24 |
6264497524 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.1173939815 |
|
|
Sep 10 04:24:47 AM UTC 24 |
Sep 10 04:35:10 AM UTC 24 |
5096506772 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1757439900 |
|
|
Sep 10 04:28:12 AM UTC 24 |
Sep 10 04:35:13 AM UTC 24 |
4066571592 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.2969745573 |
|
|
Sep 10 04:22:49 AM UTC 24 |
Sep 10 04:35:43 AM UTC 24 |
6284318216 ps |
| T1284 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.3558892750 |
|
|
Sep 10 03:58:41 AM UTC 24 |
Sep 10 04:35:51 AM UTC 24 |
8971046064 ps |
| T1285 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.296533492 |
|
|
Sep 10 03:29:40 AM UTC 24 |
Sep 10 04:35:53 AM UTC 24 |
15148278800 ps |
| T1286 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.1452432110 |
|
|
Sep 10 03:29:02 AM UTC 24 |
Sep 10 04:36:10 AM UTC 24 |
14894307336 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.3244748458 |
|
|
Sep 10 04:25:08 AM UTC 24 |
Sep 10 04:36:15 AM UTC 24 |
5435873300 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.1426745661 |
|
|
Sep 10 04:26:51 AM UTC 24 |
Sep 10 04:36:47 AM UTC 24 |
5562451720 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.4051822310 |
|
|
Sep 10 04:26:42 AM UTC 24 |
Sep 10 04:36:51 AM UTC 24 |
3954762170 ps |
| T1287 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.3869328289 |
|
|
Sep 10 03:27:03 AM UTC 24 |
Sep 10 04:37:20 AM UTC 24 |
14788545801 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.290365968 |
|
|
Sep 10 04:30:58 AM UTC 24 |
Sep 10 04:37:57 AM UTC 24 |
4289056808 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.607021279 |
|
|
Sep 10 04:31:37 AM UTC 24 |
Sep 10 04:37:58 AM UTC 24 |
3668190490 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.190155959 |
|
|
Sep 10 04:32:42 AM UTC 24 |
Sep 10 04:38:04 AM UTC 24 |
3834251524 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.254199871 |
|
|
Sep 10 04:26:26 AM UTC 24 |
Sep 10 04:38:10 AM UTC 24 |
4758075800 ps |
| T1288 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.1324924706 |
|
|
Sep 10 03:28:59 AM UTC 24 |
Sep 10 04:38:23 AM UTC 24 |
27617181880 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.116585639 |
|
|
Sep 10 04:31:02 AM UTC 24 |
Sep 10 04:38:27 AM UTC 24 |
4023169960 ps |
| T1289 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2180262017 |
|
|
Sep 10 03:29:14 AM UTC 24 |
Sep 10 04:38:29 AM UTC 24 |
15435090966 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.981096868 |
|
|
Sep 10 04:31:01 AM UTC 24 |
Sep 10 04:38:40 AM UTC 24 |
4657331158 ps |
| T1290 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1218242198 |
|
|
Sep 10 04:32:25 AM UTC 24 |
Sep 10 04:38:58 AM UTC 24 |
3970929548 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.3333742713 |
|
|
Sep 10 04:25:13 AM UTC 24 |
Sep 10 04:39:10 AM UTC 24 |
5342339944 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.1008251226 |
|
|
Sep 10 04:27:37 AM UTC 24 |
Sep 10 04:39:14 AM UTC 24 |
5285495040 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.4245631940 |
|
|
Sep 10 04:30:49 AM UTC 24 |
Sep 10 04:39:22 AM UTC 24 |
4488873280 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.4285871986 |
|
|
Sep 10 04:30:58 AM UTC 24 |
Sep 10 04:40:03 AM UTC 24 |
5263935300 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.79201427 |
|
|
Sep 10 04:31:38 AM UTC 24 |
Sep 10 04:40:17 AM UTC 24 |
5346562680 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.881870674 |
|
|
Sep 10 04:34:40 AM UTC 24 |
Sep 10 04:40:20 AM UTC 24 |
3971262376 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2489855683 |
|
|
Sep 10 04:33:49 AM UTC 24 |
Sep 10 04:41:08 AM UTC 24 |
3888023544 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.1902017156 |
|
|
Sep 10 03:29:25 AM UTC 24 |
Sep 10 04:41:38 AM UTC 24 |
17047703074 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod_end.1235682587 |
|
|
Sep 10 03:30:07 AM UTC 24 |
Sep 10 04:41:38 AM UTC 24 |
16341588695 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3792169453 |
|
|
Sep 10 04:34:35 AM UTC 24 |
Sep 10 04:41:56 AM UTC 24 |
4506482120 ps |
| T1291 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.1455116046 |
|
|
Sep 10 04:15:59 AM UTC 24 |
Sep 10 04:42:15 AM UTC 24 |
7931728996 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.1372310889 |
|
|
Sep 10 04:33:46 AM UTC 24 |
Sep 10 04:42:16 AM UTC 24 |
5209901800 ps |
| T1292 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.4257875864 |
|
|
Sep 10 03:22:35 AM UTC 24 |
Sep 10 04:42:36 AM UTC 24 |
22252328807 ps |
| T1293 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2551728287 |
|
|
Sep 10 03:29:40 AM UTC 24 |
Sep 10 04:42:38 AM UTC 24 |
14936949368 ps |
| T1294 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod.3786282304 |
|
|
Sep 10 03:28:56 AM UTC 24 |
Sep 10 04:42:55 AM UTC 24 |
15728687280 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.4128619287 |
|
|
Sep 10 04:32:45 AM UTC 24 |
Sep 10 04:42:55 AM UTC 24 |
4517355524 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.68375515 |
|
|
Sep 10 04:37:39 AM UTC 24 |
Sep 10 04:43:16 AM UTC 24 |
3427525216 ps |
| T1295 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_dev.2346175402 |
|
|
Sep 10 03:28:46 AM UTC 24 |
Sep 10 04:43:25 AM UTC 24 |
16363879716 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.3899585923 |
|
|
Sep 10 04:30:59 AM UTC 24 |
Sep 10 04:43:33 AM UTC 24 |
6307129080 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.652513184 |
|
|
Sep 10 04:34:40 AM UTC 24 |
Sep 10 04:43:37 AM UTC 24 |
5313866084 ps |
| T1296 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2509566923 |
|
|
Sep 10 04:37:50 AM UTC 24 |
Sep 10 04:43:39 AM UTC 24 |
3722102424 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2405677579 |
|
|
Sep 10 04:37:45 AM UTC 24 |
Sep 10 04:43:44 AM UTC 24 |
3866172648 ps |
| T1297 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_rma.2436408663 |
|
|
Sep 10 03:29:53 AM UTC 24 |
Sep 10 04:43:51 AM UTC 24 |
14762743600 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.2545138668 |
|
|
Sep 10 04:34:38 AM UTC 24 |
Sep 10 04:43:56 AM UTC 24 |
5667949572 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3924157103 |
|
|
Sep 10 04:37:45 AM UTC 24 |
Sep 10 04:43:57 AM UTC 24 |
4205723502 ps |
| T1298 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.941829845 |
|
|
Sep 10 04:19:16 AM UTC 24 |
Sep 10 04:43:59 AM UTC 24 |
8135211088 ps |
| T1299 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.2145819107 |
|
|
Sep 10 04:34:41 AM UTC 24 |
Sep 10 04:44:04 AM UTC 24 |
5275039956 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2904642637 |
|
|
Sep 10 04:37:44 AM UTC 24 |
Sep 10 04:44:27 AM UTC 24 |
3658767704 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.558007827 |
|
|
Sep 10 04:32:40 AM UTC 24 |
Sep 10 04:44:36 AM UTC 24 |
6034978770 ps |
| T1300 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.4105621232 |
|
|
Sep 10 04:38:20 AM UTC 24 |
Sep 10 04:44:49 AM UTC 24 |
4001214620 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.3588069719 |
|
|
Sep 10 04:37:48 AM UTC 24 |
Sep 10 04:45:22 AM UTC 24 |
6060272856 ps |
| T1301 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.1947439211 |
|
|
Sep 10 04:20:04 AM UTC 24 |
Sep 10 04:45:54 AM UTC 24 |
7867617654 ps |
| T1302 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.166094482 |
|
|
Sep 10 04:38:20 AM UTC 24 |
Sep 10 04:46:08 AM UTC 24 |
5524236512 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.2323931294 |
|
|
Sep 10 04:38:23 AM UTC 24 |
Sep 10 04:46:28 AM UTC 24 |
6307772100 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.3970594243 |
|
|
Sep 10 04:37:49 AM UTC 24 |
Sep 10 04:46:41 AM UTC 24 |
4942809240 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.819886416 |
|
|
Sep 10 04:40:45 AM UTC 24 |
Sep 10 04:46:42 AM UTC 24 |
3635509190 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2754442697 |
|
|
Sep 10 04:42:00 AM UTC 24 |
Sep 10 04:47:01 AM UTC 24 |
3704745272 ps |
| T1303 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1625814646 |
|
|
Sep 10 04:42:01 AM UTC 24 |
Sep 10 04:47:07 AM UTC 24 |
3591492010 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.2704405522 |
|
|
Sep 10 04:38:20 AM UTC 24 |
Sep 10 04:47:17 AM UTC 24 |
4623241376 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.955686418 |
|
|
Sep 10 04:41:19 AM UTC 24 |
Sep 10 04:47:19 AM UTC 24 |
4129326520 ps |
| T1304 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.1324796524 |
|
|
Sep 10 04:02:37 AM UTC 24 |
Sep 10 04:47:21 AM UTC 24 |
13072864174 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.408757408 |
|
|
Sep 10 04:37:48 AM UTC 24 |
Sep 10 04:47:43 AM UTC 24 |
5181438296 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2557353061 |
|
|
Sep 10 04:42:05 AM UTC 24 |
Sep 10 04:47:58 AM UTC 24 |
3793631138 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1567008479 |
|
|
Sep 10 04:42:27 AM UTC 24 |
Sep 10 04:47:59 AM UTC 24 |
4057891128 ps |
| T1305 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.289575984 |
|
|
Sep 10 04:41:34 AM UTC 24 |
Sep 10 04:47:59 AM UTC 24 |
3635550000 ps |
| T1306 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2240217239 |
|
|
Sep 10 04:43:31 AM UTC 24 |
Sep 10 04:48:01 AM UTC 24 |
3497057038 ps |
| T1307 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_all_escalation_resets.2546948912 |
|
|
Sep 10 04:41:22 AM UTC 24 |
Sep 10 04:48:15 AM UTC 24 |
4874862228 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.319864650 |
|
|
Sep 10 04:43:42 AM UTC 24 |
Sep 10 04:48:22 AM UTC 24 |
3556674368 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.251618381 |
|
|
Sep 10 04:41:21 AM UTC 24 |
Sep 10 04:48:33 AM UTC 24 |
5059074464 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.2976614894 |
|
|
Sep 10 04:40:59 AM UTC 24 |
Sep 10 04:48:34 AM UTC 24 |
4780557490 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.154156874 |
|
|
Sep 10 04:42:02 AM UTC 24 |
Sep 10 04:48:48 AM UTC 24 |
3558266010 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.1462215139 |
|
|
Sep 10 04:42:02 AM UTC 24 |
Sep 10 04:49:27 AM UTC 24 |
4603474716 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.798430061 |
|
|
Sep 10 04:41:32 AM UTC 24 |
Sep 10 04:49:32 AM UTC 24 |
5073254510 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.4178860605 |
|
|
Sep 10 04:41:18 AM UTC 24 |
Sep 10 04:49:50 AM UTC 24 |
4509186168 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_all_escalation_resets.590663527 |
|
|
Sep 10 04:41:14 AM UTC 24 |
Sep 10 04:50:15 AM UTC 24 |
4867734616 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3453868102 |
|
|
Sep 10 04:45:26 AM UTC 24 |
Sep 10 04:50:21 AM UTC 24 |
3071791950 ps |
| T1308 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.3602949699 |
|
|
Sep 10 03:57:34 AM UTC 24 |
Sep 10 04:50:31 AM UTC 24 |
12613212356 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.4165228874 |
|
|
Sep 10 04:45:46 AM UTC 24 |
Sep 10 04:51:06 AM UTC 24 |
4244172112 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1060765591 |
|
|
Sep 10 04:46:07 AM UTC 24 |
Sep 10 04:51:21 AM UTC 24 |
3577681834 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2231694823 |
|
|
Sep 10 04:46:09 AM UTC 24 |
Sep 10 04:51:28 AM UTC 24 |
3723571836 ps |
| T1309 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.1954156302 |
|
|
Sep 10 04:41:32 AM UTC 24 |
Sep 10 04:51:47 AM UTC 24 |
6520053912 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1645653213 |
|
|
Sep 10 04:46:49 AM UTC 24 |
Sep 10 04:51:59 AM UTC 24 |
3076205474 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2937107168 |
|
|
Sep 10 04:47:39 AM UTC 24 |
Sep 10 04:51:59 AM UTC 24 |
3408247914 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3531946950 |
|
|
Sep 10 04:46:58 AM UTC 24 |
Sep 10 04:52:46 AM UTC 24 |
3264030720 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.56738722 |
|
|
Sep 10 04:47:16 AM UTC 24 |
Sep 10 04:53:24 AM UTC 24 |
3589468600 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1064311043 |
|
|
Sep 10 04:47:07 AM UTC 24 |
Sep 10 04:54:11 AM UTC 24 |
3665700288 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3505091048 |
|
|
Sep 10 04:47:35 AM UTC 24 |
Sep 10 04:54:15 AM UTC 24 |
3758376792 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.4224343995 |
|
|
Sep 10 04:44:55 AM UTC 24 |
Sep 10 04:54:31 AM UTC 24 |
5965576588 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.2917096947 |
|
|
Sep 10 04:44:55 AM UTC 24 |
Sep 10 04:54:33 AM UTC 24 |
5014953128 ps |
| T1310 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2151273785 |
|
|
Sep 10 04:48:53 AM UTC 24 |
Sep 10 04:54:40 AM UTC 24 |
3872361000 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.1224789577 |
|
|
Sep 10 04:46:25 AM UTC 24 |
Sep 10 04:55:11 AM UTC 24 |
5369205768 ps |
| T1311 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.2656901130 |
|
|
Sep 10 04:47:04 AM UTC 24 |
Sep 10 04:55:13 AM UTC 24 |
5033173880 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3196313821 |
|
|
Sep 10 04:50:09 AM UTC 24 |
Sep 10 04:55:14 AM UTC 24 |
2785754772 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_all_escalation_resets.1312984399 |
|
|
Sep 10 04:45:49 AM UTC 24 |
Sep 10 04:55:53 AM UTC 24 |
6389823052 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.757004471 |
|
|
Sep 10 04:49:44 AM UTC 24 |
Sep 10 04:55:58 AM UTC 24 |
3369884738 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3477699619 |
|
|
Sep 10 04:50:32 AM UTC 24 |
Sep 10 04:56:11 AM UTC 24 |
3658897348 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.3780779488 |
|
|
Sep 10 04:47:36 AM UTC 24 |
Sep 10 04:56:20 AM UTC 24 |
4420502892 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.954536935 |
|
|
Sep 10 04:47:02 AM UTC 24 |
Sep 10 04:56:20 AM UTC 24 |
5121669960 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2745667594 |
|
|
Sep 10 04:50:04 AM UTC 24 |
Sep 10 04:56:24 AM UTC 24 |
3463868064 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2583119080 |
|
|
Sep 10 04:50:35 AM UTC 24 |
Sep 10 04:56:48 AM UTC 24 |
4232051360 ps |
| T1312 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1013850682 |
|
|
Sep 10 04:51:08 AM UTC 24 |
Sep 10 04:56:49 AM UTC 24 |
3774959568 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.1050056570 |
|
|
Sep 10 04:47:17 AM UTC 24 |
Sep 10 04:56:59 AM UTC 24 |
6393511688 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3532478056 |
|
|
Sep 10 04:50:36 AM UTC 24 |
Sep 10 04:57:12 AM UTC 24 |
4063395910 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.4274551641 |
|
|
Sep 10 04:50:54 AM UTC 24 |
Sep 10 04:57:13 AM UTC 24 |
3931191864 ps |
| T1313 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.3337889583 |
|
|
Sep 10 04:47:23 AM UTC 24 |
Sep 10 04:57:15 AM UTC 24 |
5913952080 ps |
| T1314 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.4192057064 |
|
|
Sep 10 04:48:08 AM UTC 24 |
Sep 10 04:57:15 AM UTC 24 |
5489371662 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.431422993 |
|
|
Sep 10 04:47:23 AM UTC 24 |
Sep 10 04:57:22 AM UTC 24 |
5851141908 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.765556015 |
|
|
Sep 10 04:50:19 AM UTC 24 |
Sep 10 04:57:29 AM UTC 24 |
4257598140 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.567333370 |
|
|
Sep 10 04:50:48 AM UTC 24 |
Sep 10 04:57:35 AM UTC 24 |
4145479016 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.4271329800 |
|
|
Sep 10 04:47:34 AM UTC 24 |
Sep 10 04:57:57 AM UTC 24 |
5378872564 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.4033460403 |
|
|
Sep 10 04:51:08 AM UTC 24 |
Sep 10 04:58:05 AM UTC 24 |
4146038968 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2092256232 |
|
|
Sep 10 04:52:19 AM UTC 24 |
Sep 10 04:58:16 AM UTC 24 |
3806645920 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_all_escalation_resets.4135131117 |
|
|
Sep 10 04:50:30 AM UTC 24 |
Sep 10 04:58:17 AM UTC 24 |
5189942332 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.3747825582 |
|
|
Sep 10 04:48:53 AM UTC 24 |
Sep 10 04:59:23 AM UTC 24 |
6709450704 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3133358783 |
|
|
Sep 10 04:53:04 AM UTC 24 |
Sep 10 04:59:30 AM UTC 24 |
3799824704 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2365269894 |
|
|
Sep 10 04:52:07 AM UTC 24 |
Sep 10 04:59:35 AM UTC 24 |
4072023044 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3046906574 |
|
|
Sep 10 04:53:03 AM UTC 24 |
Sep 10 04:59:35 AM UTC 24 |
4154231348 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_all_escalation_resets.3012594122 |
|
|
Sep 10 04:52:02 AM UTC 24 |
Sep 10 04:59:37 AM UTC 24 |
5055904870 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.1280081971 |
|
|
Sep 10 04:50:51 AM UTC 24 |
Sep 10 04:59:49 AM UTC 24 |
5787517106 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2381114443 |
|
|
Sep 10 04:53:27 AM UTC 24 |
Sep 10 05:00:18 AM UTC 24 |
3348772218 ps |
| T1315 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.1739193014 |
|
|
Sep 10 04:51:07 AM UTC 24 |
Sep 10 05:00:32 AM UTC 24 |
5986930868 ps |
| T1316 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.2484588678 |
|
|
Sep 10 04:18:40 AM UTC 24 |
Sep 10 05:00:36 AM UTC 24 |
12982626372 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.3048899070 |
|
|
Sep 10 04:52:00 AM UTC 24 |
Sep 10 05:01:31 AM UTC 24 |
5458388200 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.1407571519 |
|
|
Sep 10 04:53:07 AM UTC 24 |
Sep 10 05:01:35 AM UTC 24 |
5669838980 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.4167325342 |
|
|
Sep 10 04:52:56 AM UTC 24 |
Sep 10 05:01:42 AM UTC 24 |
5165358882 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.1764163697 |
|
|
Sep 10 04:51:06 AM UTC 24 |
Sep 10 05:01:42 AM UTC 24 |
5056914432 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.1010350628 |
|
|
Sep 10 04:51:22 AM UTC 24 |
Sep 10 05:01:43 AM UTC 24 |
4559728314 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.2604866908 |
|
|
Sep 10 04:52:32 AM UTC 24 |
Sep 10 05:01:47 AM UTC 24 |
5392806620 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3588819841 |
|
|
Sep 10 04:56:05 AM UTC 24 |
Sep 10 05:02:03 AM UTC 24 |
3027444168 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.935606853 |
|
|
Sep 10 04:54:48 AM UTC 24 |
Sep 10 05:02:25 AM UTC 24 |
4265168200 ps |
| T1317 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.110025080 |
|
|
Sep 10 04:52:00 AM UTC 24 |
Sep 10 05:02:46 AM UTC 24 |
5809889816 ps |
| T1318 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1052985040 |
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|
Sep 10 04:56:02 AM UTC 24 |
Sep 10 05:02:48 AM UTC 24 |
3801409690 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.1260286631 |
|
|
Sep 10 04:52:01 AM UTC 24 |
Sep 10 05:03:20 AM UTC 24 |
4809873600 ps |
| T1319 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.2973071743 |
|
|
Sep 10 04:53:09 AM UTC 24 |
Sep 10 05:03:43 AM UTC 24 |
5815456040 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.978948414 |
|
|
Sep 10 04:55:38 AM UTC 24 |
Sep 10 05:03:51 AM UTC 24 |
5930862548 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.1252286239 |
|
|
Sep 10 04:53:08 AM UTC 24 |
Sep 10 05:04:27 AM UTC 24 |
6139864278 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3249462512 |
|
|
Sep 10 04:58:03 AM UTC 24 |
Sep 10 05:04:35 AM UTC 24 |
3726176120 ps |
| T1320 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.4095427504 |
|
|
Sep 10 04:57:54 AM UTC 24 |
Sep 10 05:05:01 AM UTC 24 |
4264833428 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.9600031 |
|
|
Sep 10 04:54:08 AM UTC 24 |
Sep 10 05:05:55 AM UTC 24 |
5028487264 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.3463429375 |
|
|
Sep 10 04:58:01 AM UTC 24 |
Sep 10 05:06:53 AM UTC 24 |
5040759524 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.3798577423 |
|
|
Sep 10 04:57:35 AM UTC 24 |
Sep 10 05:07:44 AM UTC 24 |
5036112320 ps |
| T1321 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_all_escalation_resets.3503521428 |
|
|
Sep 10 04:57:39 AM UTC 24 |
Sep 10 05:08:23 AM UTC 24 |
4906952074 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.3281063875 |
|
|
Sep 10 04:58:09 AM UTC 24 |
Sep 10 05:08:30 AM UTC 24 |
5201405760 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.4011841931 |
|
|
Sep 10 04:57:57 AM UTC 24 |
Sep 10 05:08:54 AM UTC 24 |
4384856480 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.921965345 |
|
|
Sep 10 04:57:39 AM UTC 24 |
Sep 10 05:09:02 AM UTC 24 |
4902666548 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_inject_scramble_seed.2009717271 |
|
|
Sep 10 12:45:57 AM UTC 24 |
Sep 10 05:09:55 AM UTC 24 |
66804309834 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.291837231 |
|
|
Sep 10 04:58:06 AM UTC 24 |
Sep 10 05:09:56 AM UTC 24 |
4701390232 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.3849172788 |
|
|
Sep 10 04:58:06 AM UTC 24 |
Sep 10 05:09:58 AM UTC 24 |
6092315512 ps |
| T1322 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.951343477 |
|
|
Sep 10 04:57:54 AM UTC 24 |
Sep 10 05:11:08 AM UTC 24 |
6717525512 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/91.chip_sw_all_escalation_resets.229265396 |
|
|
Sep 10 04:58:01 AM UTC 24 |
Sep 10 05:11:11 AM UTC 24 |
5303370134 ps |
| T1323 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.2837070167 |
|
|
Sep 10 04:58:04 AM UTC 24 |
Sep 10 05:11:40 AM UTC 24 |
6161553556 ps |
| T1324 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.3671959885 |
|
|
Sep 10 04:04:57 AM UTC 24 |
Sep 10 05:24:34 AM UTC 24 |
17934802410 ps |
| T1325 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.73568750 |
|
|
Sep 10 03:50:50 AM UTC 24 |
Sep 10 05:26:49 AM UTC 24 |
21043673162 ps |
| T1326 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.2183904956 |
|
|
Sep 10 03:41:17 AM UTC 24 |
Sep 10 05:27:15 AM UTC 24 |
23060669964 ps |
| T1327 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.2779752553 |
|
|
Sep 10 03:55:01 AM UTC 24 |
Sep 10 05:27:51 AM UTC 24 |
22107270356 ps |
| T1328 |
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.2882198407 |
|
|
Sep 10 03:29:14 AM UTC 24 |
Sep 10 05:45:00 AM UTC 24 |
26841582248 ps |