| T38 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.40590997 |
|
|
Sep 11 11:29:16 PM UTC 24 |
Sep 11 11:33:33 PM UTC 24 |
3274968550 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2085873565 |
|
|
Sep 11 10:28:27 PM UTC 24 |
Sep 11 11:34:16 PM UTC 24 |
14724460599 ps |
| T26 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.2137783135 |
|
|
Sep 11 11:29:21 PM UTC 24 |
Sep 11 11:34:45 PM UTC 24 |
2854572968 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.1831724536 |
|
|
Sep 11 11:29:21 PM UTC 24 |
Sep 11 11:34:47 PM UTC 24 |
3961833808 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3155142457 |
|
|
Sep 11 10:26:49 PM UTC 24 |
Sep 11 11:34:55 PM UTC 24 |
14761339550 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pattgen_ios.1042494664 |
|
|
Sep 11 11:29:59 PM UTC 24 |
Sep 11 11:35:08 PM UTC 24 |
2811594344 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3623432858 |
|
|
Sep 11 10:28:38 PM UTC 24 |
Sep 11 11:35:34 PM UTC 24 |
14564340401 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3131105568 |
|
|
Sep 11 10:29:03 PM UTC 24 |
Sep 11 11:36:19 PM UTC 24 |
14595568869 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.130588585 |
|
|
Sep 11 11:28:27 PM UTC 24 |
Sep 11 11:37:09 PM UTC 24 |
4643777444 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_exception_c.349522210 |
|
|
Sep 11 10:25:19 PM UTC 24 |
Sep 11 11:37:17 PM UTC 24 |
14266908576 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.493160140 |
|
|
Sep 11 10:25:16 PM UTC 24 |
Sep 11 11:37:22 PM UTC 24 |
15983845560 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1580480835 |
|
|
Sep 11 10:25:26 PM UTC 24 |
Sep 11 11:37:31 PM UTC 24 |
15664221272 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1480578565 |
|
|
Sep 11 10:31:55 PM UTC 24 |
Sep 11 11:37:59 PM UTC 24 |
15335876930 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1768303086 |
|
|
Sep 11 10:31:55 PM UTC 24 |
Sep 11 11:37:59 PM UTC 24 |
14809482702 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.2791804722 |
|
|
Sep 11 11:28:30 PM UTC 24 |
Sep 11 11:38:22 PM UTC 24 |
5877213908 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.167127232 |
|
|
Sep 11 11:28:31 PM UTC 24 |
Sep 11 11:38:55 PM UTC 24 |
4688538448 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2821798171 |
|
|
Sep 11 10:26:28 PM UTC 24 |
Sep 11 11:39:15 PM UTC 24 |
15718091620 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2483079776 |
|
|
Sep 11 10:29:40 PM UTC 24 |
Sep 11 11:39:32 PM UTC 24 |
14251139672 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.380320973 |
|
|
Sep 11 10:32:24 PM UTC 24 |
Sep 11 11:40:21 PM UTC 24 |
14553148328 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx2.3612183188 |
|
|
Sep 11 11:31:02 PM UTC 24 |
Sep 11 11:40:35 PM UTC 24 |
4530361132 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.2301325343 |
|
|
Sep 11 11:36:16 PM UTC 24 |
Sep 11 11:41:26 PM UTC 24 |
2719558620 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1826964 |
|
|
Sep 11 10:16:32 PM UTC 24 |
Sep 11 11:41:31 PM UTC 24 |
25335858637 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.883939964 |
|
|
Sep 11 10:28:27 PM UTC 24 |
Sep 11 11:41:32 PM UTC 24 |
16089185632 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_tpm.3295727548 |
|
|
Sep 11 11:36:15 PM UTC 24 |
Sep 11 11:41:34 PM UTC 24 |
3461203250 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx.1345936423 |
|
|
Sep 11 11:30:46 PM UTC 24 |
Sep 11 11:41:46 PM UTC 24 |
4224170998 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.3343668626 |
|
|
Sep 11 11:36:59 PM UTC 24 |
Sep 11 11:41:40 PM UTC 24 |
2885856577 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx3.1483433307 |
|
|
Sep 11 11:31:05 PM UTC 24 |
Sep 11 11:41:57 PM UTC 24 |
4649541148 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_rma.1718469660 |
|
|
Sep 11 10:46:50 PM UTC 24 |
Sep 11 11:42:31 PM UTC 24 |
41844055699 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1932523004 |
|
|
Sep 11 10:24:24 PM UTC 24 |
Sep 11 11:42:48 PM UTC 24 |
15433553620 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx1.4016070832 |
|
|
Sep 11 11:30:46 PM UTC 24 |
Sep 11 11:42:49 PM UTC 24 |
4586831930 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.183063323 |
|
|
Sep 11 10:30:46 PM UTC 24 |
Sep 11 11:43:01 PM UTC 24 |
15562486830 ps |
| T42 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.661083154 |
|
|
Sep 11 11:38:23 PM UTC 24 |
Sep 11 11:44:41 PM UTC 24 |
3795463543 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3788332567 |
|
|
Sep 11 11:39:54 PM UTC 24 |
Sep 11 11:45:02 PM UTC 24 |
3209546372 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod.3441226969 |
|
|
Sep 11 10:37:23 PM UTC 24 |
Sep 11 11:45:53 PM UTC 24 |
15432340236 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.783915580 |
|
|
Sep 11 11:34:55 PM UTC 24 |
Sep 11 11:45:59 PM UTC 24 |
4890913492 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3516358244 |
|
|
Sep 11 11:43:55 PM UTC 24 |
Sep 11 11:46:23 PM UTC 24 |
3111409923 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2218271963 |
|
|
Sep 11 11:34:21 PM UTC 24 |
Sep 11 11:46:31 PM UTC 24 |
4093804362 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.649645177 |
|
|
Sep 11 11:39:04 PM UTC 24 |
Sep 11 11:46:40 PM UTC 24 |
5071993144 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.4246452276 |
|
|
Sep 11 11:44:12 PM UTC 24 |
Sep 11 11:46:51 PM UTC 24 |
2205473811 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.393666458 |
|
|
Sep 11 11:43:01 PM UTC 24 |
Sep 11 11:47:02 PM UTC 24 |
2995284204 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through_collision.3115297534 |
|
|
Sep 11 11:39:03 PM UTC 24 |
Sep 11 11:47:08 PM UTC 24 |
4706006247 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.1499637646 |
|
|
Sep 11 11:36:11 PM UTC 24 |
Sep 11 11:47:22 PM UTC 24 |
4317892702 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1734782005 |
|
|
Sep 11 11:36:11 PM UTC 24 |
Sep 11 11:47:37 PM UTC 24 |
4682748562 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1028369894 |
|
|
Sep 11 11:45:40 PM UTC 24 |
Sep 11 11:47:46 PM UTC 24 |
2152350446 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.3250512979 |
|
|
Sep 11 11:43:33 PM UTC 24 |
Sep 11 11:48:00 PM UTC 24 |
2903321350 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3349639706 |
|
|
Sep 11 11:43:55 PM UTC 24 |
Sep 11 11:48:40 PM UTC 24 |
3146050856 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_smoketest.301355981 |
|
|
Sep 11 11:20:34 PM UTC 24 |
Sep 11 11:48:42 PM UTC 24 |
8794821436 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1847930588 |
|
|
Sep 11 11:46:42 PM UTC 24 |
Sep 11 11:48:58 PM UTC 24 |
2564994736 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.2067386146 |
|
|
Sep 11 09:52:47 PM UTC 24 |
Sep 11 11:49:04 PM UTC 24 |
23686824338 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.1754741553 |
|
|
Sep 11 11:38:44 PM UTC 24 |
Sep 11 11:49:20 PM UTC 24 |
3843361936 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod_end.742816516 |
|
|
Sep 11 10:39:35 PM UTC 24 |
Sep 11 11:49:26 PM UTC 24 |
15856502371 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3059081526 |
|
|
Sep 11 11:39:03 PM UTC 24 |
Sep 11 11:49:45 PM UTC 24 |
4216787031 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.516646106 |
|
|
Sep 11 11:35:55 PM UTC 24 |
Sep 11 11:50:13 PM UTC 24 |
5178814790 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.3947666831 |
|
|
Sep 11 11:38:23 PM UTC 24 |
Sep 11 11:50:13 PM UTC 24 |
6994855761 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.1781084968 |
|
|
Sep 11 11:29:59 PM UTC 24 |
Sep 11 11:50:37 PM UTC 24 |
8350618964 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4188051214 |
|
|
Sep 11 11:34:20 PM UTC 24 |
Sep 11 11:51:33 PM UTC 24 |
8996088049 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.1392362521 |
|
|
Sep 11 11:44:16 PM UTC 24 |
Sep 11 11:51:44 PM UTC 24 |
6388162573 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4189246129 |
|
|
Sep 11 11:43:01 PM UTC 24 |
Sep 11 11:53:48 PM UTC 24 |
4383891252 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pincfg.3725166548 |
|
|
Sep 11 09:31:41 PM UTC 24 |
Sep 11 11:54:03 PM UTC 24 |
31527463200 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.3483400703 |
|
|
Sep 11 11:48:24 PM UTC 24 |
Sep 11 11:54:07 PM UTC 24 |
2749438872 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_rma.3547813646 |
|
|
Sep 11 10:41:08 PM UTC 24 |
Sep 11 11:54:48 PM UTC 24 |
15432392165 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.626739213 |
|
|
Sep 11 11:39:07 PM UTC 24 |
Sep 11 11:54:58 PM UTC 24 |
5710106000 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.2426617836 |
|
|
Sep 11 11:47:56 PM UTC 24 |
Sep 11 11:55:12 PM UTC 24 |
4418384658 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1058966718 |
|
|
Sep 11 11:41:11 PM UTC 24 |
Sep 11 11:56:14 PM UTC 24 |
5872063857 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.4212658788 |
|
|
Sep 11 11:48:43 PM UTC 24 |
Sep 11 11:56:21 PM UTC 24 |
3849170334 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.1951527347 |
|
|
Sep 11 11:51:15 PM UTC 24 |
Sep 11 11:56:25 PM UTC 24 |
3158467478 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.247291533 |
|
|
Sep 11 11:39:35 PM UTC 24 |
Sep 11 11:56:30 PM UTC 24 |
5619596548 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2001543921 |
|
|
Sep 11 11:51:01 PM UTC 24 |
Sep 11 11:57:06 PM UTC 24 |
3622716832 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.69654166 |
|
|
Sep 11 11:52:25 PM UTC 24 |
Sep 11 11:57:28 PM UTC 24 |
2883971358 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.666417888 |
|
|
Sep 11 11:48:01 PM UTC 24 |
Sep 11 11:57:29 PM UTC 24 |
6795343950 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_dev.3993479846 |
|
|
Sep 11 10:44:58 PM UTC 24 |
Sep 11 11:58:11 PM UTC 24 |
31798921398 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.632226335 |
|
|
Sep 11 11:50:25 PM UTC 24 |
Sep 11 11:59:03 PM UTC 24 |
6803408864 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_dev.3227854437 |
|
|
Sep 11 10:36:37 PM UTC 24 |
Sep 11 11:59:10 PM UTC 24 |
15370958572 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.989080698 |
|
|
Sep 11 11:48:12 PM UTC 24 |
Sep 11 11:59:31 PM UTC 24 |
5699298684 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2303273606 |
|
|
Sep 11 11:51:02 PM UTC 24 |
Sep 12 12:00:02 AM UTC 24 |
4161687868 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.1052328483 |
|
|
Sep 11 11:34:14 PM UTC 24 |
Sep 12 12:00:25 AM UTC 24 |
8041969502 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1890919134 |
|
|
Sep 11 10:51:32 PM UTC 24 |
Sep 12 12:01:08 AM UTC 24 |
15506014720 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.821808777 |
|
|
Sep 11 11:54:28 PM UTC 24 |
Sep 12 12:01:13 AM UTC 24 |
5660809880 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2036915317 |
|
|
Sep 11 11:50:07 PM UTC 24 |
Sep 12 12:01:31 AM UTC 24 |
6565193652 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.1986004675 |
|
|
Sep 11 11:45:17 PM UTC 24 |
Sep 12 12:01:37 AM UTC 24 |
10225118650 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.3289585033 |
|
|
Sep 11 11:55:48 PM UTC 24 |
Sep 12 12:01:59 AM UTC 24 |
3793631288 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_outputs.4192182308 |
|
|
Sep 11 11:54:54 PM UTC 24 |
Sep 12 12:02:28 AM UTC 24 |
4132092360 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1068610206 |
|
|
Sep 11 11:54:23 PM UTC 24 |
Sep 12 12:03:26 AM UTC 24 |
5068619554 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3859381196 |
|
|
Sep 11 11:50:22 PM UTC 24 |
Sep 12 12:03:51 AM UTC 24 |
10322758220 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.3141476296 |
|
|
Sep 12 12:00:44 AM UTC 24 |
Sep 12 12:04:06 AM UTC 24 |
2390810781 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1613813919 |
|
|
Sep 11 11:55:53 PM UTC 24 |
Sep 12 12:04:34 AM UTC 24 |
7793454618 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2799432810 |
|
|
Sep 11 11:57:29 PM UTC 24 |
Sep 12 12:04:52 AM UTC 24 |
18540241388 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.795173819 |
|
|
Sep 12 12:01:05 AM UTC 24 |
Sep 12 12:05:00 AM UTC 24 |
2634916516 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.387563669 |
|
|
Sep 11 10:27:54 PM UTC 24 |
Sep 12 12:05:09 AM UTC 24 |
18153721040 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2932527422 |
|
|
Sep 11 11:43:56 PM UTC 24 |
Sep 12 12:05:24 AM UTC 24 |
7460244866 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.1547894960 |
|
|
Sep 12 12:00:08 AM UTC 24 |
Sep 12 12:05:33 AM UTC 24 |
3103247080 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2051782811 |
|
|
Sep 11 11:48:25 PM UTC 24 |
Sep 12 12:05:59 AM UTC 24 |
7284555462 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.4023899917 |
|
|
Sep 11 10:26:37 PM UTC 24 |
Sep 12 12:06:14 AM UTC 24 |
18627528696 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_mem_scramble.304162397 |
|
|
Sep 11 11:58:50 PM UTC 24 |
Sep 12 12:06:18 AM UTC 24 |
3242747800 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.4160673543 |
|
|
Sep 11 10:57:11 PM UTC 24 |
Sep 12 12:06:22 AM UTC 24 |
14993392734 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2373318773 |
|
|
Sep 11 11:57:25 PM UTC 24 |
Sep 12 12:06:30 AM UTC 24 |
3884048104 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.873524425 |
|
|
Sep 11 11:50:02 PM UTC 24 |
Sep 12 12:07:06 AM UTC 24 |
10211800696 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.3763580938 |
|
|
Sep 12 12:02:17 AM UTC 24 |
Sep 12 12:07:53 AM UTC 24 |
3297433223 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1261630183 |
|
|
Sep 11 11:44:06 PM UTC 24 |
Sep 12 12:08:07 AM UTC 24 |
7497179940 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.315553361 |
|
|
Sep 12 12:02:19 AM UTC 24 |
Sep 12 12:08:08 AM UTC 24 |
3228863288 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.396050516 |
|
|
Sep 11 11:44:08 PM UTC 24 |
Sep 12 12:08:11 AM UTC 24 |
9192314050 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1301573765 |
|
|
Sep 11 11:57:30 PM UTC 24 |
Sep 12 12:08:51 AM UTC 24 |
5107005490 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_timeout.966128033 |
|
|
Sep 12 12:02:24 AM UTC 24 |
Sep 12 12:09:16 AM UTC 24 |
4327775530 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1644572209 |
|
|
Sep 11 11:00:36 PM UTC 24 |
Sep 12 12:09:25 AM UTC 24 |
14531609144 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.398823073 |
|
|
Sep 12 12:05:12 AM UTC 24 |
Sep 12 12:09:50 AM UTC 24 |
3415629698 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1656480212 |
|
|
Sep 11 11:57:24 PM UTC 24 |
Sep 12 12:10:00 AM UTC 24 |
8848480280 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2811358523 |
|
|
Sep 12 12:03:22 AM UTC 24 |
Sep 12 12:10:06 AM UTC 24 |
3986608996 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.2015306669 |
|
|
Sep 12 12:06:01 AM UTC 24 |
Sep 12 12:10:20 AM UTC 24 |
2751594400 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.1252061249 |
|
|
Sep 12 12:02:35 AM UTC 24 |
Sep 12 12:10:42 AM UTC 24 |
4412514280 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.1973198635 |
|
|
Sep 12 12:06:12 AM UTC 24 |
Sep 12 12:11:01 AM UTC 24 |
3191454470 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1797842979 |
|
|
Sep 11 11:49:33 PM UTC 24 |
Sep 12 12:11:20 AM UTC 24 |
14935484504 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3615747194 |
|
|
Sep 11 11:59:53 PM UTC 24 |
Sep 12 12:11:37 AM UTC 24 |
4712336804 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_kat_test.3445510677 |
|
|
Sep 12 12:07:23 AM UTC 24 |
Sep 12 12:12:23 AM UTC 24 |
3238607684 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3412148823 |
|
|
Sep 12 12:07:44 AM UTC 24 |
Sep 12 12:12:26 AM UTC 24 |
2346751560 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.549151020 |
|
|
Sep 12 12:09:10 AM UTC 24 |
Sep 12 12:13:26 AM UTC 24 |
2689689920 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.2580310973 |
|
|
Sep 12 12:10:06 AM UTC 24 |
Sep 12 12:13:58 AM UTC 24 |
2832854752 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en.1016899835 |
|
|
Sep 12 12:09:28 AM UTC 24 |
Sep 12 12:13:59 AM UTC 24 |
2638291195 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.869480685 |
|
|
Sep 12 12:07:23 AM UTC 24 |
Sep 12 12:14:31 AM UTC 24 |
4144853000 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.2282795956 |
|
|
Sep 11 11:40:04 PM UTC 24 |
Sep 12 12:14:45 AM UTC 24 |
23758641350 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_randomness.4172450459 |
|
|
Sep 11 11:57:46 PM UTC 24 |
Sep 12 12:14:48 AM UTC 24 |
5953869510 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.903044629 |
|
|
Sep 12 12:06:17 AM UTC 24 |
Sep 12 12:15:22 AM UTC 24 |
3163562872 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.4221745229 |
|
|
Sep 11 11:48:39 PM UTC 24 |
Sep 12 12:15:42 AM UTC 24 |
13085257497 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.47903030 |
|
|
Sep 12 12:10:07 AM UTC 24 |
Sep 12 12:16:19 AM UTC 24 |
3183942190 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.3819085730 |
|
|
Sep 11 11:59:53 PM UTC 24 |
Sep 12 12:16:25 AM UTC 24 |
5848897488 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.1599809991 |
|
|
Sep 12 12:06:18 AM UTC 24 |
Sep 12 12:16:27 AM UTC 24 |
2895193160 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.3362630928 |
|
|
Sep 12 12:12:15 AM UTC 24 |
Sep 12 12:16:30 AM UTC 24 |
2454912368 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3482617216 |
|
|
Sep 12 12:07:24 AM UTC 24 |
Sep 12 12:16:36 AM UTC 24 |
7310088498 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.880726032 |
|
|
Sep 11 10:50:50 PM UTC 24 |
Sep 12 12:18:03 AM UTC 24 |
17479835458 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3681997770 |
|
|
Sep 12 12:13:10 AM UTC 24 |
Sep 12 12:18:20 AM UTC 24 |
3125352190 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_app_rom.2812762378 |
|
|
Sep 12 12:14:00 AM UTC 24 |
Sep 12 12:18:32 AM UTC 24 |
2832352048 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.149122611 |
|
|
Sep 12 12:13:09 AM UTC 24 |
Sep 12 12:18:40 AM UTC 24 |
3624781230 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.2969551686 |
|
|
Sep 12 12:14:45 AM UTC 24 |
Sep 12 12:18:53 AM UTC 24 |
3036816136 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2211008136 |
|
|
Sep 11 10:29:04 PM UTC 24 |
Sep 12 12:19:44 AM UTC 24 |
24399485560 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.2943867580 |
|
|
Sep 11 11:48:37 PM UTC 24 |
Sep 12 12:19:50 AM UTC 24 |
12705334324 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.449150207 |
|
|
Sep 11 10:26:21 PM UTC 24 |
Sep 12 12:20:47 AM UTC 24 |
23423857669 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2142935334 |
|
|
Sep 12 12:04:08 AM UTC 24 |
Sep 12 12:21:07 AM UTC 24 |
10239285376 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.2764226925 |
|
|
Sep 12 12:17:48 AM UTC 24 |
Sep 12 12:22:03 AM UTC 24 |
2619637668 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.4231780216 |
|
|
Sep 11 11:54:53 PM UTC 24 |
Sep 12 12:22:25 AM UTC 24 |
23762692980 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2477189688 |
|
|
Sep 12 12:14:46 AM UTC 24 |
Sep 12 12:22:51 AM UTC 24 |
8534449004 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1237143713 |
|
|
Sep 11 10:29:28 PM UTC 24 |
Sep 12 12:24:34 AM UTC 24 |
24146248580 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3385972997 |
|
|
Sep 12 12:17:40 AM UTC 24 |
Sep 12 12:24:57 AM UTC 24 |
5054419752 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.1724398764 |
|
|
Sep 12 12:17:38 AM UTC 24 |
Sep 12 12:25:10 AM UTC 24 |
3329591800 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.3255417708 |
|
|
Sep 12 12:19:30 AM UTC 24 |
Sep 12 12:25:13 AM UTC 24 |
3245511928 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1420073667 |
|
|
Sep 12 12:15:10 AM UTC 24 |
Sep 12 12:25:15 AM UTC 24 |
4798710414 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.3679607146 |
|
|
Sep 12 12:15:35 AM UTC 24 |
Sep 12 12:25:33 AM UTC 24 |
9327067630 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.978413020 |
|
|
Sep 12 12:16:00 AM UTC 24 |
Sep 12 12:25:47 AM UTC 24 |
6812403370 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.1420420465 |
|
|
Sep 12 12:08:31 AM UTC 24 |
Sep 12 12:26:51 AM UTC 24 |
5648543176 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.3712729689 |
|
|
Sep 12 12:02:39 AM UTC 24 |
Sep 12 12:27:03 AM UTC 24 |
7958762380 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1446978685 |
|
|
Sep 12 12:16:22 AM UTC 24 |
Sep 12 12:27:05 AM UTC 24 |
8236766840 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.485766145 |
|
|
Sep 12 12:20:32 AM UTC 24 |
Sep 12 12:27:05 AM UTC 24 |
4050274750 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1585063044 |
|
|
Sep 12 12:15:35 AM UTC 24 |
Sep 12 12:27:12 AM UTC 24 |
6225864250 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1165146155 |
|
|
Sep 12 12:19:37 AM UTC 24 |
Sep 12 12:27:16 AM UTC 24 |
4984557632 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3766605635 |
|
|
Sep 12 12:20:33 AM UTC 24 |
Sep 12 12:27:29 AM UTC 24 |
3508585070 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.4032417658 |
|
|
Sep 11 10:29:04 PM UTC 24 |
Sep 12 12:27:48 AM UTC 24 |
22641033590 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.1260343403 |
|
|
Sep 12 12:18:52 AM UTC 24 |
Sep 12 12:28:02 AM UTC 24 |
4651478504 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.770391378 |
|
|
Sep 12 12:09:12 AM UTC 24 |
Sep 12 12:29:24 AM UTC 24 |
6413241874 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2594597519 |
|
|
Sep 12 12:21:27 AM UTC 24 |
Sep 12 12:30:02 AM UTC 24 |
5761710520 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.3959605759 |
|
|
Sep 12 12:26:36 AM UTC 24 |
Sep 12 12:30:09 AM UTC 24 |
3049469147 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.1007947801 |
|
|
Sep 12 12:19:06 AM UTC 24 |
Sep 12 12:30:44 AM UTC 24 |
4397446092 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1822203065 |
|
|
Sep 12 12:21:45 AM UTC 24 |
Sep 12 12:30:49 AM UTC 24 |
7176425491 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs.887850639 |
|
|
Sep 12 12:09:11 AM UTC 24 |
Sep 12 12:30:50 AM UTC 24 |
7314631240 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.3673719495 |
|
|
Sep 12 12:06:12 AM UTC 24 |
Sep 12 12:31:04 AM UTC 24 |
6498543408 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.734610620 |
|
|
Sep 11 10:27:50 PM UTC 24 |
Sep 12 12:31:52 AM UTC 24 |
24036273456 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3281433153 |
|
|
Sep 11 11:48:43 PM UTC 24 |
Sep 12 12:32:08 AM UTC 24 |
23878271460 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3628564906 |
|
|
Sep 12 12:23:02 AM UTC 24 |
Sep 12 12:32:16 AM UTC 24 |
4918133712 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1836977558 |
|
|
Sep 11 10:25:30 PM UTC 24 |
Sep 12 12:32:18 AM UTC 24 |
24296337784 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2408099128 |
|
|
Sep 12 12:04:31 AM UTC 24 |
Sep 12 12:32:21 AM UTC 24 |
8793510872 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3447149632 |
|
|
Sep 12 12:23:30 AM UTC 24 |
Sep 12 12:33:04 AM UTC 24 |
4093256858 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation.183747124 |
|
|
Sep 12 12:11:19 AM UTC 24 |
Sep 12 12:33:13 AM UTC 24 |
6287847280 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.872708584 |
|
|
Sep 12 12:04:45 AM UTC 24 |
Sep 12 12:33:19 AM UTC 24 |
9144826920 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.498328567 |
|
|
Sep 12 12:26:23 AM UTC 24 |
Sep 12 12:33:47 AM UTC 24 |
3756395252 ps |
| T1037 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.713340971 |
|
|
Sep 12 12:31:27 AM UTC 24 |
Sep 12 12:34:07 AM UTC 24 |
2640260354 ps |
| T1038 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.892647147 |
|
|
Sep 12 12:22:43 AM UTC 24 |
Sep 12 12:34:12 AM UTC 24 |
4337966456 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.1837236684 |
|
|
Sep 12 12:31:45 AM UTC 24 |
Sep 12 12:34:21 AM UTC 24 |
2727571333 ps |
| T1039 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_reset_frequency.2767326111 |
|
|
Sep 12 12:26:19 AM UTC 24 |
Sep 12 12:34:27 AM UTC 24 |
3532760480 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.34524032 |
|
|
Sep 12 12:28:53 AM UTC 24 |
Sep 12 12:34:51 AM UTC 24 |
3707299218 ps |
| T1040 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3405647711 |
|
|
Sep 12 12:26:22 AM UTC 24 |
Sep 12 12:35:04 AM UTC 24 |
4028404250 ps |
| T1041 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2085613885 |
|
|
Sep 11 11:47:57 PM UTC 24 |
Sep 12 12:35:18 AM UTC 24 |
36644209868 ps |
| T1042 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.423182581 |
|
|
Sep 12 12:26:39 AM UTC 24 |
Sep 12 12:35:22 AM UTC 24 |
5141984384 ps |
| T1043 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3431321946 |
|
|
Sep 12 12:25:12 AM UTC 24 |
Sep 12 12:35:58 AM UTC 24 |
4747010122 ps |
| T1044 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1397803923 |
|
|
Sep 12 12:33:20 AM UTC 24 |
Sep 12 12:36:19 AM UTC 24 |
2488502480 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3777684512 |
|
|
Sep 12 12:30:05 AM UTC 24 |
Sep 12 12:36:26 AM UTC 24 |
5029817728 ps |
| T1045 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2855106675 |
|
|
Sep 11 10:27:26 PM UTC 24 |
Sep 12 12:36:33 AM UTC 24 |
23174919704 ps |
| T1046 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2744937279 |
|
|
Sep 12 12:25:36 AM UTC 24 |
Sep 12 12:36:50 AM UTC 24 |
4697453266 ps |
| T1047 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2572217527 |
|
|
Sep 11 10:25:58 PM UTC 24 |
Sep 12 12:36:53 AM UTC 24 |
25028196040 ps |
| T1048 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.99245144 |
|
|
Sep 12 12:11:05 AM UTC 24 |
Sep 12 12:36:58 AM UTC 24 |
7133086210 ps |
| T1049 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3773540175 |
|
|
Sep 12 12:11:16 AM UTC 24 |
Sep 12 12:37:05 AM UTC 24 |
8578638704 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.3785772964 |
|
|
Sep 12 12:30:50 AM UTC 24 |
Sep 12 12:37:12 AM UTC 24 |
4587117992 ps |
| T1050 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2612988320 |
|
|
Sep 12 12:34:07 AM UTC 24 |
Sep 12 12:37:13 AM UTC 24 |
2964559930 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2214141499 |
|
|
Sep 12 12:33:19 AM UTC 24 |
Sep 12 12:37:17 AM UTC 24 |
2625280136 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.1649822716 |
|
|
Sep 12 12:17:46 AM UTC 24 |
Sep 12 12:37:22 AM UTC 24 |
6574196152 ps |
| T1051 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1791756817 |
|
|
Sep 12 12:28:58 AM UTC 24 |
Sep 12 12:37:24 AM UTC 24 |
5814171928 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3467649063 |
|
|
Sep 12 12:33:19 AM UTC 24 |
Sep 12 12:37:46 AM UTC 24 |
2643564446 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1460230667 |
|
|
Sep 12 12:30:50 AM UTC 24 |
Sep 12 12:37:52 AM UTC 24 |
4985682456 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3783787799 |
|
|
Sep 12 12:29:00 AM UTC 24 |
Sep 12 12:38:03 AM UTC 24 |
7822307578 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_program_error.1510768461 |
|
|
Sep 12 12:29:00 AM UTC 24 |
Sep 12 12:38:22 AM UTC 24 |
5729015820 ps |
| T1052 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.2703013282 |
|
|
Sep 12 12:31:49 AM UTC 24 |
Sep 12 12:38:31 AM UTC 24 |
4894978060 ps |
| T1053 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3448768515 |
|
|
Sep 12 12:35:30 AM UTC 24 |
Sep 12 12:38:42 AM UTC 24 |
2425232965 ps |
| T1054 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.1972690861 |
|
|
Sep 12 12:34:06 AM UTC 24 |
Sep 12 12:38:56 AM UTC 24 |
3182633172 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.1475939848 |
|
|
Sep 12 12:32:24 AM UTC 24 |
Sep 12 12:39:06 AM UTC 24 |
5549606462 ps |
| T1055 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3938507679 |
|
|
Sep 12 12:35:43 AM UTC 24 |
Sep 12 12:39:19 AM UTC 24 |
2860598375 ps |
| T1056 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.663435242 |
|
|
Sep 12 12:19:36 AM UTC 24 |
Sep 12 12:40:16 AM UTC 24 |
9212246184 ps |
| T1057 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.2748954737 |
|
|
Sep 12 12:32:41 AM UTC 24 |
Sep 12 12:41:13 AM UTC 24 |
5986408785 ps |
| T1058 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.4121665062 |
|
|
Sep 12 12:36:06 AM UTC 24 |
Sep 12 12:41:19 AM UTC 24 |
3768993650 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.37434656 |
|
|
Sep 12 12:31:49 AM UTC 24 |
Sep 12 12:41:57 AM UTC 24 |
6326835986 ps |
| T1059 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.3227842114 |
|
|
Sep 12 12:29:02 AM UTC 24 |
Sep 12 12:43:11 AM UTC 24 |
8951280660 ps |
| T1060 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.2474972438 |
|
|
Sep 12 12:06:54 AM UTC 24 |
Sep 12 12:43:25 AM UTC 24 |
9543424102 ps |
| T1061 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_volatile_raw_unlock.3326427551 |
|
|
Sep 12 12:41:28 AM UTC 24 |
Sep 12 12:43:41 AM UTC 24 |
2754011608 ps |
| T1062 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2556821776 |
|
|
Sep 12 12:11:18 AM UTC 24 |
Sep 12 12:44:16 AM UTC 24 |
9433945514 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3179491328 |
|
|
Sep 12 12:36:07 AM UTC 24 |
Sep 12 12:44:18 AM UTC 24 |
3995065315 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.3401392075 |
|
|
Sep 12 12:34:05 AM UTC 24 |
Sep 12 12:44:44 AM UTC 24 |
5014459920 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.733909781 |
|
|
Sep 12 12:38:31 AM UTC 24 |
Sep 12 12:44:53 AM UTC 24 |
4659860520 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4208263606 |
|
|
Sep 12 12:34:24 AM UTC 24 |
Sep 12 12:45:20 AM UTC 24 |
5142227469 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.1841485847 |
|
|
Sep 12 12:42:29 AM UTC 24 |
Sep 12 12:45:32 AM UTC 24 |
2602772724 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_raw_unlock.530444419 |
|
|
Sep 12 12:41:57 AM UTC 24 |
Sep 12 12:46:31 AM UTC 24 |
5792664817 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.1762285092 |
|
|
Sep 12 12:42:53 AM UTC 24 |
Sep 12 12:47:25 AM UTC 24 |
2811871990 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.1837848674 |
|
|
Sep 12 12:27:28 AM UTC 24 |
Sep 12 12:47:34 AM UTC 24 |
13066343333 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.4170263680 |
|
|
Sep 12 12:38:55 AM UTC 24 |
Sep 12 12:47:57 AM UTC 24 |
4526007800 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.1226224736 |
|
|
Sep 12 12:11:22 AM UTC 24 |
Sep 12 12:48:17 AM UTC 24 |
11676623050 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.1044479816 |
|
|
Sep 12 12:42:57 AM UTC 24 |
Sep 12 12:48:33 AM UTC 24 |
3238963096 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.2230790839 |
|
|
Sep 12 12:42:58 AM UTC 24 |
Sep 12 12:48:47 AM UTC 24 |
2863967944 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1854457481 |
|
|
Sep 11 11:55:38 PM UTC 24 |
Sep 12 12:48:54 AM UTC 24 |
20452651672 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.3157135694 |
|
|
Sep 12 12:44:00 AM UTC 24 |
Sep 12 12:49:04 AM UTC 24 |
3003803740 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.1358171920 |
|
|
Sep 12 12:44:19 AM UTC 24 |
Sep 12 12:49:32 AM UTC 24 |
2841027641 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.2474670858 |
|
|
Sep 12 12:45:34 AM UTC 24 |
Sep 12 12:49:36 AM UTC 24 |
2396530008 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.1037736071 |
|
|
Sep 12 12:41:59 AM UTC 24 |
Sep 12 12:49:47 AM UTC 24 |
4369107200 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.1959990374 |
|
|
Sep 12 12:45:06 AM UTC 24 |
Sep 12 12:49:51 AM UTC 24 |
3342343082 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_plic_smoketest.510085060 |
|
|
Sep 12 12:47:11 AM UTC 24 |
Sep 12 12:50:25 AM UTC 24 |
2672210424 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.2696966470 |
|
|
Sep 12 12:49:17 AM UTC 24 |
Sep 12 12:51:12 AM UTC 24 |
2708727340 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_aes.791595344 |
|
|
Sep 12 12:11:38 AM UTC 24 |
Sep 12 12:51:27 AM UTC 24 |
11425995288 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_smoketest.1696876180 |
|
|
Sep 12 12:44:05 AM UTC 24 |
Sep 12 12:51:37 AM UTC 24 |
3765816832 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.2846969219 |
|
|
Sep 12 12:45:06 AM UTC 24 |
Sep 12 12:51:38 AM UTC 24 |
3863912112 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2009375152 |
|
|
Sep 12 12:29:04 AM UTC 24 |
Sep 12 12:52:07 AM UTC 24 |
22646373832 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.1707194164 |
|
|
Sep 12 12:49:09 AM UTC 24 |
Sep 12 12:52:13 AM UTC 24 |
2607739680 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.2985353700 |
|
|
Sep 12 12:48:15 AM UTC 24 |
Sep 12 12:52:21 AM UTC 24 |
3378609232 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.2920945881 |
|
|
Sep 12 12:49:43 AM UTC 24 |
Sep 12 12:52:23 AM UTC 24 |
2664731740 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.1805264155 |
|
|
Sep 12 12:48:14 AM UTC 24 |
Sep 12 12:52:29 AM UTC 24 |
3498283798 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_smoketest.4253248969 |
|
|
Sep 12 12:49:04 AM UTC 24 |
Sep 12 12:53:14 AM UTC 24 |
3328701632 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2004740154 |
|
|
Sep 12 12:35:31 AM UTC 24 |
Sep 12 12:53:22 AM UTC 24 |
7205470684 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2051164676 |
|
|
Sep 12 12:46:12 AM UTC 24 |
Sep 12 12:53:46 AM UTC 24 |
5870723736 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.2073981251 |
|
|
Sep 12 12:48:35 AM UTC 24 |
Sep 12 12:53:46 AM UTC 24 |
3095861336 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3743302435 |
|
|
Sep 12 12:28:59 AM UTC 24 |
Sep 12 12:54:32 AM UTC 24 |
22179269030 ps |
| T21 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1973258759 |
|
|
Sep 12 12:51:05 AM UTC 24 |
Sep 12 12:55:05 AM UTC 24 |
2345746478 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.2291595441 |
|
|
Sep 12 12:46:08 AM UTC 24 |
Sep 12 12:55:05 AM UTC 24 |
6065129446 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.193700518 |
|
|
Sep 12 12:49:44 AM UTC 24 |
Sep 12 12:55:08 AM UTC 24 |
2899495960 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1641723828 |
|
|
Sep 12 12:39:54 AM UTC 24 |
Sep 12 12:56:13 AM UTC 24 |
5340916026 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.1826813604 |
|
|
Sep 12 12:50:44 AM UTC 24 |
Sep 12 12:56:31 AM UTC 24 |
3329391528 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2363304976 |
|
|
Sep 12 12:36:01 AM UTC 24 |
Sep 12 12:56:54 AM UTC 24 |
9447827685 ps |
| T27 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.3159432943 |
|
|
Sep 12 12:51:52 AM UTC 24 |
Sep 12 12:57:03 AM UTC 24 |
2724903668 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3731576587 |
|
|
Sep 12 12:17:48 AM UTC 24 |
Sep 12 12:57:12 AM UTC 24 |
29660042048 ps |