| T554 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.2605792423 |
|
|
Sep 11 07:07:44 PM UTC 24 |
Sep 11 07:21:57 PM UTC 24 |
9625157227 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.4284948081 |
|
|
Sep 11 07:21:20 PM UTC 24 |
Sep 11 07:22:00 PM UTC 24 |
301853511 ps |
| T1421 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1723579618 |
|
|
Sep 11 07:21:46 PM UTC 24 |
Sep 11 07:22:22 PM UTC 24 |
252583419 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.3190008152 |
|
|
Sep 11 07:10:21 PM UTC 24 |
Sep 11 07:22:41 PM UTC 24 |
68870689711 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2649322532 |
|
|
Sep 11 07:22:05 PM UTC 24 |
Sep 11 07:22:45 PM UTC 24 |
44690768 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.2549342939 |
|
|
Sep 11 07:20:28 PM UTC 24 |
Sep 11 07:22:45 PM UTC 24 |
2228489643 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.1530302888 |
|
|
Sep 11 07:13:51 PM UTC 24 |
Sep 11 07:22:46 PM UTC 24 |
5594366710 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.3463972744 |
|
|
Sep 11 07:18:50 PM UTC 24 |
Sep 11 07:23:05 PM UTC 24 |
2588037360 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.2686948952 |
|
|
Sep 11 07:11:45 PM UTC 24 |
Sep 11 07:23:09 PM UTC 24 |
6008276148 ps |
| T1422 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.3353702078 |
|
|
Sep 11 07:23:07 PM UTC 24 |
Sep 11 07:23:18 PM UTC 24 |
46109014 ps |
| T1423 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1248318982 |
|
|
Sep 11 07:23:12 PM UTC 24 |
Sep 11 07:23:18 PM UTC 24 |
42657090 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.929698112 |
|
|
Sep 11 07:17:01 PM UTC 24 |
Sep 11 07:23:29 PM UTC 24 |
4730005658 ps |
| T1424 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.1787451050 |
|
|
Sep 11 07:23:35 PM UTC 24 |
Sep 11 07:23:47 PM UTC 24 |
52838069 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.3357088831 |
|
|
Sep 11 07:18:34 PM UTC 24 |
Sep 11 07:23:51 PM UTC 24 |
3031258561 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.1252436290 |
|
|
Sep 11 07:21:56 PM UTC 24 |
Sep 11 07:23:57 PM UTC 24 |
3149366628 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.5911972 |
|
|
Sep 11 07:22:13 PM UTC 24 |
Sep 11 07:23:59 PM UTC 24 |
283256926 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1748706919 |
|
|
Sep 11 06:55:05 PM UTC 24 |
Sep 11 07:24:04 PM UTC 24 |
129492744805 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.4112176769 |
|
|
Sep 11 07:11:33 PM UTC 24 |
Sep 11 07:24:07 PM UTC 24 |
15627519799 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.600985055 |
|
|
Sep 11 07:08:30 PM UTC 24 |
Sep 11 07:24:19 PM UTC 24 |
87090120131 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.3003884645 |
|
|
Sep 11 07:23:56 PM UTC 24 |
Sep 11 07:24:29 PM UTC 24 |
459451143 ps |
| T1425 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.243420441 |
|
|
Sep 11 07:24:24 PM UTC 24 |
Sep 11 07:24:43 PM UTC 24 |
299641225 ps |
| T1426 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.485025673 |
|
|
Sep 11 07:23:12 PM UTC 24 |
Sep 11 07:24:53 PM UTC 24 |
6222522055 ps |
| T1427 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.3774983309 |
|
|
Sep 11 07:24:23 PM UTC 24 |
Sep 11 07:24:56 PM UTC 24 |
519182623 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.3620816124 |
|
|
Sep 11 07:24:17 PM UTC 24 |
Sep 11 07:25:03 PM UTC 24 |
1450515280 ps |
| T1428 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.4222083727 |
|
|
Sep 11 07:22:10 PM UTC 24 |
Sep 11 07:25:06 PM UTC 24 |
5158029541 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.400321148 |
|
|
Sep 11 07:19:02 PM UTC 24 |
Sep 11 07:25:11 PM UTC 24 |
4908864782 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.2718097011 |
|
|
Sep 11 07:23:31 PM UTC 24 |
Sep 11 07:25:12 PM UTC 24 |
2528700323 ps |
| T1429 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.3557731537 |
|
|
Sep 11 07:23:12 PM UTC 24 |
Sep 11 07:25:16 PM UTC 24 |
7561697769 ps |
| T1430 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.13605524 |
|
|
Sep 11 07:25:08 PM UTC 24 |
Sep 11 07:25:16 PM UTC 24 |
7022562 ps |
| T1431 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.3535531986 |
|
|
Sep 11 07:25:31 PM UTC 24 |
Sep 11 07:25:43 PM UTC 24 |
125405247 ps |
| T1432 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3491527769 |
|
|
Sep 11 07:25:36 PM UTC 24 |
Sep 11 07:25:45 PM UTC 24 |
43089238 ps |
| T1433 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.2762156751 |
|
|
Sep 11 07:16:55 PM UTC 24 |
Sep 11 07:25:46 PM UTC 24 |
5233860686 ps |
| T1434 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.2297180397 |
|
|
Sep 11 07:24:24 PM UTC 24 |
Sep 11 07:26:01 PM UTC 24 |
2615950599 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.987733425 |
|
|
Sep 11 07:18:03 PM UTC 24 |
Sep 11 07:26:07 PM UTC 24 |
37051679020 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.3317559176 |
|
|
Sep 11 07:24:52 PM UTC 24 |
Sep 11 07:26:16 PM UTC 24 |
1264461931 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.3051492675 |
|
|
Sep 11 07:19:23 PM UTC 24 |
Sep 11 07:26:24 PM UTC 24 |
4877561320 ps |
| T1435 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.1822166362 |
|
|
Sep 11 07:26:08 PM UTC 24 |
Sep 11 07:26:32 PM UTC 24 |
569112138 ps |
| T1436 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.3191883359 |
|
|
Sep 11 07:26:10 PM UTC 24 |
Sep 11 07:26:50 PM UTC 24 |
446818235 ps |
| T1437 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.2364978851 |
|
|
Sep 11 07:26:50 PM UTC 24 |
Sep 11 07:27:22 PM UTC 24 |
735562093 ps |
| T1438 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.187701592 |
|
|
Sep 11 07:25:36 PM UTC 24 |
Sep 11 07:27:44 PM UTC 24 |
9188462686 ps |
| T1439 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.2775184745 |
|
|
Sep 11 07:26:58 PM UTC 24 |
Sep 11 07:27:46 PM UTC 24 |
953034359 ps |
| T1440 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.4155821567 |
|
|
Sep 11 07:25:42 PM UTC 24 |
Sep 11 07:27:48 PM UTC 24 |
6742769982 ps |
| T1441 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.512410461 |
|
|
Sep 11 07:26:13 PM UTC 24 |
Sep 11 07:27:53 PM UTC 24 |
10976858930 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.2691441458 |
|
|
Sep 11 07:26:31 PM UTC 24 |
Sep 11 07:27:54 PM UTC 24 |
1350927272 ps |
| T1442 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.1783062228 |
|
|
Sep 11 07:27:15 PM UTC 24 |
Sep 11 07:27:55 PM UTC 24 |
655870063 ps |
| T1443 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.1932958717 |
|
|
Sep 11 07:22:13 PM UTC 24 |
Sep 11 07:28:12 PM UTC 24 |
4571787886 ps |
| T1444 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2555802111 |
|
|
Sep 11 07:27:47 PM UTC 24 |
Sep 11 07:28:28 PM UTC 24 |
839307794 ps |
| T1445 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.3284574882 |
|
|
Sep 11 07:23:44 PM UTC 24 |
Sep 11 07:28:35 PM UTC 24 |
24080267805 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2260427374 |
|
|
Sep 11 06:56:37 PM UTC 24 |
Sep 11 07:28:58 PM UTC 24 |
112911056069 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.814193415 |
|
|
Sep 11 07:29:01 PM UTC 24 |
Sep 11 07:29:08 PM UTC 24 |
46380201 ps |
| T1446 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.1829330471 |
|
|
Sep 11 07:28:54 PM UTC 24 |
Sep 11 07:29:10 PM UTC 24 |
249416808 ps |
| T1447 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3989646966 |
|
|
Sep 11 07:28:17 PM UTC 24 |
Sep 11 07:29:24 PM UTC 24 |
256536317 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.3439009430 |
|
|
Sep 11 07:15:00 PM UTC 24 |
Sep 11 07:29:31 PM UTC 24 |
88596715370 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.880467334 |
|
|
Sep 11 07:22:46 PM UTC 24 |
Sep 11 07:29:51 PM UTC 24 |
5492283720 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.770641412 |
|
|
Sep 11 07:24:45 PM UTC 24 |
Sep 11 07:29:53 PM UTC 24 |
1509541395 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.301718475 |
|
|
Sep 11 07:15:30 PM UTC 24 |
Sep 11 07:30:17 PM UTC 24 |
60290316065 ps |
| T1448 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.3947716418 |
|
|
Sep 11 07:29:35 PM UTC 24 |
Sep 11 07:30:19 PM UTC 24 |
534488082 ps |
| T1449 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.1956019254 |
|
|
Sep 11 07:29:50 PM UTC 24 |
Sep 11 07:30:21 PM UTC 24 |
221695637 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.1333663151 |
|
|
Sep 11 07:28:09 PM UTC 24 |
Sep 11 07:30:23 PM UTC 24 |
3858297527 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.2709807329 |
|
|
Sep 11 07:24:30 PM UTC 24 |
Sep 11 07:30:26 PM UTC 24 |
9846875633 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2426348634 |
|
|
Sep 11 07:12:40 PM UTC 24 |
Sep 11 07:30:26 PM UTC 24 |
57435405889 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.1261912011 |
|
|
Sep 11 07:28:11 PM UTC 24 |
Sep 11 07:30:39 PM UTC 24 |
4710680018 ps |
| T1450 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3274695981 |
|
|
Sep 11 07:29:34 PM UTC 24 |
Sep 11 07:30:48 PM UTC 24 |
4607155758 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.3084747665 |
|
|
Sep 11 07:17:45 PM UTC 24 |
Sep 11 07:30:48 PM UTC 24 |
49187406115 ps |
| T1451 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.2078125600 |
|
|
Sep 11 07:13:56 PM UTC 24 |
Sep 11 07:30:51 PM UTC 24 |
13028273912 ps |
| T1452 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.626612978 |
|
|
Sep 11 07:29:24 PM UTC 24 |
Sep 11 07:31:03 PM UTC 24 |
8215316073 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.1651386953 |
|
|
Sep 11 07:17:37 PM UTC 24 |
Sep 11 07:31:10 PM UTC 24 |
79784829294 ps |
| T1453 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.1010877132 |
|
|
Sep 11 07:22:24 PM UTC 24 |
Sep 11 07:31:22 PM UTC 24 |
7950780918 ps |
| T1454 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.2658780367 |
|
|
Sep 11 07:30:45 PM UTC 24 |
Sep 11 07:31:23 PM UTC 24 |
404244691 ps |
| T1455 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.2341340086 |
|
|
Sep 11 07:31:12 PM UTC 24 |
Sep 11 07:31:25 PM UTC 24 |
51513098 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.4242783488 |
|
|
Sep 11 07:31:02 PM UTC 24 |
Sep 11 07:31:41 PM UTC 24 |
60558439 ps |
| T1456 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.1502916826 |
|
|
Sep 11 07:26:26 PM UTC 24 |
Sep 11 07:31:43 PM UTC 24 |
23702556360 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.424449473 |
|
|
Sep 11 07:30:19 PM UTC 24 |
Sep 11 07:31:45 PM UTC 24 |
1396005153 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.3049887215 |
|
|
Sep 11 07:28:42 PM UTC 24 |
Sep 11 07:31:46 PM UTC 24 |
3628317506 ps |
| T1457 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2496382937 |
|
|
Sep 11 07:30:51 PM UTC 24 |
Sep 11 07:31:46 PM UTC 24 |
1101359793 ps |
| T1458 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.2341280258 |
|
|
Sep 11 07:30:44 PM UTC 24 |
Sep 11 07:31:57 PM UTC 24 |
2382996076 ps |
| T1459 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.1901918446 |
|
|
Sep 11 07:31:49 PM UTC 24 |
Sep 11 07:31:59 PM UTC 24 |
48771191 ps |
| T1460 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.1527347809 |
|
|
Sep 11 07:31:50 PM UTC 24 |
Sep 11 07:32:01 PM UTC 24 |
52889390 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.2226865202 |
|
|
Sep 11 07:30:47 PM UTC 24 |
Sep 11 07:32:01 PM UTC 24 |
1540821767 ps |
| T1461 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.3549341574 |
|
|
Sep 11 07:19:10 PM UTC 24 |
Sep 11 07:32:25 PM UTC 24 |
6075373966 ps |
| T1462 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.2385243244 |
|
|
Sep 11 07:25:17 PM UTC 24 |
Sep 11 07:32:29 PM UTC 24 |
4505470980 ps |
| T1463 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2466888314 |
|
|
Sep 11 07:19:11 PM UTC 24 |
Sep 11 07:32:35 PM UTC 24 |
10453830148 ps |
| T1464 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.1517363207 |
|
|
Sep 11 07:32:08 PM UTC 24 |
Sep 11 07:32:49 PM UTC 24 |
923235933 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.602208866 |
|
|
Sep 11 07:25:19 PM UTC 24 |
Sep 11 07:32:51 PM UTC 24 |
6377587448 ps |
| T1465 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.397215909 |
|
|
Sep 11 07:32:11 PM UTC 24 |
Sep 11 07:32:54 PM UTC 24 |
520862724 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.3958940365 |
|
|
Sep 11 07:25:27 PM UTC 24 |
Sep 11 07:33:02 PM UTC 24 |
4352237815 ps |
| T1466 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.2975494656 |
|
|
Sep 11 07:31:14 PM UTC 24 |
Sep 11 07:33:08 PM UTC 24 |
2461614297 ps |
| T1467 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.4247060340 |
|
|
Sep 11 07:30:51 PM UTC 24 |
Sep 11 07:33:09 PM UTC 24 |
3509130186 ps |
| T1468 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.493831291 |
|
|
Sep 11 07:32:24 PM UTC 24 |
Sep 11 07:33:16 PM UTC 24 |
560108300 ps |
| T1469 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1957602470 |
|
|
Sep 11 07:33:00 PM UTC 24 |
Sep 11 07:33:26 PM UTC 24 |
306824633 ps |
| T1470 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.2746994540 |
|
|
Sep 11 07:32:08 PM UTC 24 |
Sep 11 07:33:35 PM UTC 24 |
5033499341 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.1243031384 |
|
|
Sep 11 07:32:22 PM UTC 24 |
Sep 11 07:33:35 PM UTC 24 |
928764993 ps |
| T1471 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.917093163 |
|
|
Sep 11 07:30:41 PM UTC 24 |
Sep 11 07:33:38 PM UTC 24 |
10652198651 ps |
| T1472 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.1039749411 |
|
|
Sep 11 07:32:51 PM UTC 24 |
Sep 11 07:33:46 PM UTC 24 |
542487129 ps |
| T1473 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.1085802130 |
|
|
Sep 11 07:32:54 PM UTC 24 |
Sep 11 07:33:48 PM UTC 24 |
340075809 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1125422582 |
|
|
Sep 11 07:26:42 PM UTC 24 |
Sep 11 07:33:52 PM UTC 24 |
28806952002 ps |
| T1474 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.2895480617 |
|
|
Sep 11 07:31:45 PM UTC 24 |
Sep 11 07:33:57 PM UTC 24 |
2826306120 ps |
| T1475 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.2519756865 |
|
|
Sep 11 07:33:49 PM UTC 24 |
Sep 11 07:34:06 PM UTC 24 |
234900362 ps |
| T1476 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.3355042056 |
|
|
Sep 11 07:33:59 PM UTC 24 |
Sep 11 07:34:06 PM UTC 24 |
45291221 ps |
| T1477 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.2220453502 |
|
|
Sep 11 07:32:04 PM UTC 24 |
Sep 11 07:34:19 PM UTC 24 |
9447599792 ps |
| T1478 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.690401951 |
|
|
Sep 11 07:34:13 PM UTC 24 |
Sep 11 07:34:34 PM UTC 24 |
209533746 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.1407727139 |
|
|
Sep 11 07:20:01 PM UTC 24 |
Sep 11 07:34:37 PM UTC 24 |
89048705525 ps |
| T1479 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.2210130207 |
|
|
Sep 11 07:34:44 PM UTC 24 |
Sep 11 07:34:59 PM UTC 24 |
188365818 ps |
| T1480 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.1934883372 |
|
|
Sep 11 07:34:02 PM UTC 24 |
Sep 11 07:35:14 PM UTC 24 |
3538717897 ps |
| T1481 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.646812625 |
|
|
Sep 11 07:35:03 PM UTC 24 |
Sep 11 07:35:14 PM UTC 24 |
43507779 ps |
| T1482 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.83108446 |
|
|
Sep 11 07:35:00 PM UTC 24 |
Sep 11 07:35:21 PM UTC 24 |
374000614 ps |
| T1483 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.3739326411 |
|
|
Sep 11 07:30:18 PM UTC 24 |
Sep 11 07:35:21 PM UTC 24 |
20906536996 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3654927014 |
|
|
Sep 11 07:18:44 PM UTC 24 |
Sep 11 07:35:23 PM UTC 24 |
7838252618 ps |
| T1484 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.3878550961 |
|
|
Sep 11 07:28:18 PM UTC 24 |
Sep 11 07:35:25 PM UTC 24 |
4382951000 ps |
| T1485 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.921355192 |
|
|
Sep 11 07:33:59 PM UTC 24 |
Sep 11 07:35:28 PM UTC 24 |
8211502163 ps |
| T1486 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.4126955918 |
|
|
Sep 11 07:33:14 PM UTC 24 |
Sep 11 07:35:33 PM UTC 24 |
3073184259 ps |
| T1487 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.229388155 |
|
|
Sep 11 07:35:23 PM UTC 24 |
Sep 11 07:35:40 PM UTC 24 |
117125676 ps |
| T1488 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.1029735350 |
|
|
Sep 11 07:33:17 PM UTC 24 |
Sep 11 07:35:51 PM UTC 24 |
2123918842 ps |
| T1489 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.2660287580 |
|
|
Sep 11 07:34:09 PM UTC 24 |
Sep 11 07:35:57 PM UTC 24 |
2156146611 ps |
| T1490 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.241383535 |
|
|
Sep 11 07:35:36 PM UTC 24 |
Sep 11 07:36:14 PM UTC 24 |
686646395 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.1381617077 |
|
|
Sep 11 07:34:32 PM UTC 24 |
Sep 11 07:36:15 PM UTC 24 |
2344069697 ps |
| T1491 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.2070770415 |
|
|
Sep 11 07:36:06 PM UTC 24 |
Sep 11 07:36:17 PM UTC 24 |
221711314 ps |
| T1492 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.3534427989 |
|
|
Sep 11 07:36:16 PM UTC 24 |
Sep 11 07:36:27 PM UTC 24 |
53492031 ps |
| T1493 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.3094477795 |
|
|
Sep 11 07:32:26 PM UTC 24 |
Sep 11 07:36:31 PM UTC 24 |
13553628759 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2369673881 |
|
|
Sep 11 07:28:12 PM UTC 24 |
Sep 11 07:36:52 PM UTC 24 |
8617525422 ps |
| T1494 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.3551813831 |
|
|
Sep 11 07:36:42 PM UTC 24 |
Sep 11 07:36:57 PM UTC 24 |
94041116 ps |
| T1495 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.2982647326 |
|
|
Sep 11 07:31:16 PM UTC 24 |
Sep 11 07:37:09 PM UTC 24 |
4486583396 ps |
| T1496 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.585637196 |
|
|
Sep 11 07:36:39 PM UTC 24 |
Sep 11 07:37:35 PM UTC 24 |
587195058 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.3444036351 |
|
|
Sep 11 07:37:20 PM UTC 24 |
Sep 11 07:37:39 PM UTC 24 |
516727152 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.3034489237 |
|
|
Sep 11 07:37:09 PM UTC 24 |
Sep 11 07:37:43 PM UTC 24 |
482865054 ps |
| T1497 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.3834477700 |
|
|
Sep 11 07:36:22 PM UTC 24 |
Sep 11 07:37:53 PM UTC 24 |
8768268914 ps |
| T1498 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.2689399031 |
|
|
Sep 11 07:37:35 PM UTC 24 |
Sep 11 07:38:16 PM UTC 24 |
426564857 ps |
| T1499 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.2440687783 |
|
|
Sep 11 07:36:40 PM UTC 24 |
Sep 11 07:38:17 PM UTC 24 |
5631693650 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3157739261 |
|
|
Sep 11 07:16:56 PM UTC 24 |
Sep 11 07:38:27 PM UTC 24 |
12383270978 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.4184843021 |
|
|
Sep 11 07:33:16 PM UTC 24 |
Sep 11 07:38:36 PM UTC 24 |
2946069354 ps |
| T1500 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.4138793114 |
|
|
Sep 11 07:38:04 PM UTC 24 |
Sep 11 07:38:45 PM UTC 24 |
280212933 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.2445137031 |
|
|
Sep 11 07:10:26 PM UTC 24 |
Sep 11 07:38:46 PM UTC 24 |
98511629422 ps |
| T1501 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.2302960037 |
|
|
Sep 11 07:38:01 PM UTC 24 |
Sep 11 07:39:01 PM UTC 24 |
1301809026 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.2683670173 |
|
|
Sep 11 07:35:46 PM UTC 24 |
Sep 11 07:39:09 PM UTC 24 |
3217096023 ps |
| T1502 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.2356753295 |
|
|
Sep 11 07:23:44 PM UTC 24 |
Sep 11 07:39:27 PM UTC 24 |
46472811325 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.1376111502 |
|
|
Sep 11 07:33:25 PM UTC 24 |
Sep 11 07:39:35 PM UTC 24 |
5207784240 ps |
| T1503 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.2030180788 |
|
|
Sep 11 07:39:24 PM UTC 24 |
Sep 11 07:39:37 PM UTC 24 |
173372612 ps |
| T1504 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.1505457971 |
|
|
Sep 11 07:39:33 PM UTC 24 |
Sep 11 07:39:44 PM UTC 24 |
47205144 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.75703519 |
|
|
Sep 11 07:33:26 PM UTC 24 |
Sep 11 07:39:45 PM UTC 24 |
2379365706 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.1928004220 |
|
|
Sep 11 07:38:18 PM UTC 24 |
Sep 11 07:39:56 PM UTC 24 |
276642263 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.2653989064 |
|
|
Sep 11 07:20:01 PM UTC 24 |
Sep 11 07:40:03 PM UTC 24 |
71228867795 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.1460035945 |
|
|
Sep 11 07:35:58 PM UTC 24 |
Sep 11 07:40:17 PM UTC 24 |
3703094056 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.2251631692 |
|
|
Sep 11 07:38:42 PM UTC 24 |
Sep 11 07:40:20 PM UTC 24 |
398523008 ps |
| T1505 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.3198896055 |
|
|
Sep 11 07:40:10 PM UTC 24 |
Sep 11 07:40:23 PM UTC 24 |
76760491 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.2650932791 |
|
|
Sep 11 07:35:38 PM UTC 24 |
Sep 11 07:40:43 PM UTC 24 |
449425172 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.1636397856 |
|
|
Sep 11 07:40:02 PM UTC 24 |
Sep 11 07:40:56 PM UTC 24 |
433230930 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.932457750 |
|
|
Sep 11 07:40:46 PM UTC 24 |
Sep 11 07:41:06 PM UTC 24 |
141784859 ps |
| T1506 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.1335213477 |
|
|
Sep 11 07:38:42 PM UTC 24 |
Sep 11 07:41:07 PM UTC 24 |
1839749185 ps |
| T1507 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.2090859566 |
|
|
Sep 11 07:40:48 PM UTC 24 |
Sep 11 07:41:09 PM UTC 24 |
646302170 ps |
| T1508 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.2167842149 |
|
|
Sep 11 07:34:16 PM UTC 24 |
Sep 11 07:41:15 PM UTC 24 |
43231604023 ps |
| T1509 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.3676046658 |
|
|
Sep 11 07:35:46 PM UTC 24 |
Sep 11 07:41:18 PM UTC 24 |
6994097238 ps |
| T1510 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.3605671811 |
|
|
Sep 11 07:41:08 PM UTC 24 |
Sep 11 07:41:18 PM UTC 24 |
158398154 ps |
| T1511 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.160695224 |
|
|
Sep 11 07:39:52 PM UTC 24 |
Sep 11 07:41:33 PM UTC 24 |
6408201484 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.639173730 |
|
|
Sep 11 07:11:59 PM UTC 24 |
Sep 11 07:41:36 PM UTC 24 |
18044948002 ps |
| T1512 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.2883381619 |
|
|
Sep 11 07:40:28 PM UTC 24 |
Sep 11 07:41:56 PM UTC 24 |
1664258970 ps |
| T1513 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.3759584315 |
|
|
Sep 11 07:41:18 PM UTC 24 |
Sep 11 07:42:05 PM UTC 24 |
1116144503 ps |
| T1514 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.1989669082 |
|
|
Sep 11 07:41:58 PM UTC 24 |
Sep 11 07:42:08 PM UTC 24 |
40562969 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.396336852 |
|
|
Sep 11 07:33:41 PM UTC 24 |
Sep 11 07:42:11 PM UTC 24 |
4489205790 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.3035838578 |
|
|
Sep 11 07:39:11 PM UTC 24 |
Sep 11 07:42:20 PM UTC 24 |
2892420744 ps |
| T1515 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.2364519424 |
|
|
Sep 11 07:42:20 PM UTC 24 |
Sep 11 07:42:31 PM UTC 24 |
55494951 ps |
| T1516 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2433549965 |
|
|
Sep 11 07:40:00 PM UTC 24 |
Sep 11 07:42:46 PM UTC 24 |
6729027504 ps |
| T1517 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.3383008585 |
|
|
Sep 11 07:42:46 PM UTC 24 |
Sep 11 07:43:00 PM UTC 24 |
71641226 ps |
| T1518 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.3672904762 |
|
|
Sep 11 07:42:38 PM UTC 24 |
Sep 11 07:43:16 PM UTC 24 |
741867879 ps |
| T1519 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.3093801159 |
|
|
Sep 11 07:33:30 PM UTC 24 |
Sep 11 07:43:24 PM UTC 24 |
6268906740 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.2490932868 |
|
|
Sep 11 07:34:31 PM UTC 24 |
Sep 11 07:43:33 PM UTC 24 |
40487879855 ps |
| T1520 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.153868087 |
|
|
Sep 11 07:32:23 PM UTC 24 |
Sep 11 07:43:39 PM UTC 24 |
40809367325 ps |
| T1521 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.886619200 |
|
|
Sep 11 07:42:33 PM UTC 24 |
Sep 11 07:43:46 PM UTC 24 |
3418749095 ps |
| T1522 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.2649418209 |
|
|
Sep 11 07:41:54 PM UTC 24 |
Sep 11 07:43:53 PM UTC 24 |
2572596814 ps |
| T1523 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.1088348072 |
|
|
Sep 11 07:38:52 PM UTC 24 |
Sep 11 07:44:05 PM UTC 24 |
4523792289 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.271553935 |
|
|
Sep 11 07:43:26 PM UTC 24 |
Sep 11 07:44:11 PM UTC 24 |
1315152711 ps |
| T1524 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.3872677366 |
|
|
Sep 11 07:44:05 PM UTC 24 |
Sep 11 07:44:17 PM UTC 24 |
51781392 ps |
| T1525 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.4128393567 |
|
|
Sep 11 07:29:56 PM UTC 24 |
Sep 11 07:44:20 PM UTC 24 |
95453415494 ps |
| T1526 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.2748601141 |
|
|
Sep 11 07:42:31 PM UTC 24 |
Sep 11 07:44:20 PM UTC 24 |
8736067518 ps |
| T1527 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.3846257401 |
|
|
Sep 11 07:38:07 PM UTC 24 |
Sep 11 07:44:21 PM UTC 24 |
9680775336 ps |
| T1528 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.418196710 |
|
|
Sep 11 07:41:33 PM UTC 24 |
Sep 11 07:44:34 PM UTC 24 |
2306602609 ps |
| T1529 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.730647366 |
|
|
Sep 11 07:35:44 PM UTC 24 |
Sep 11 07:44:35 PM UTC 24 |
5824200030 ps |
| T1530 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.3583247890 |
|
|
Sep 11 07:35:49 PM UTC 24 |
Sep 11 07:44:36 PM UTC 24 |
7371465064 ps |
| T1531 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.3267802709 |
|
|
Sep 11 07:44:09 PM UTC 24 |
Sep 11 07:44:40 PM UTC 24 |
669373004 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.3165497884 |
|
|
Sep 11 07:34:22 PM UTC 24 |
Sep 11 07:44:46 PM UTC 24 |
40634563341 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.3166408055 |
|
|
Sep 11 07:44:44 PM UTC 24 |
Sep 11 07:44:54 PM UTC 24 |
52531690 ps |
| T1532 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.1855350793 |
|
|
Sep 11 07:44:43 PM UTC 24 |
Sep 11 07:44:57 PM UTC 24 |
205754601 ps |
| T1533 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.4022218264 |
|
|
Sep 11 07:43:57 PM UTC 24 |
Sep 11 07:44:58 PM UTC 24 |
1394823116 ps |
| T1534 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.2789708735 |
|
|
Sep 11 07:44:58 PM UTC 24 |
Sep 11 07:45:08 PM UTC 24 |
58927615 ps |
| T1535 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.3786531288 |
|
|
Sep 11 07:43:47 PM UTC 24 |
Sep 11 07:45:11 PM UTC 24 |
2561497598 ps |
| T1536 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.3592253747 |
|
|
Sep 11 07:44:59 PM UTC 24 |
Sep 11 07:45:13 PM UTC 24 |
250442925 ps |
| T1537 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.2850191578 |
|
|
Sep 11 07:43:47 PM UTC 24 |
Sep 11 07:45:16 PM UTC 24 |
2109990154 ps |
| T1538 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.3010867575 |
|
|
Sep 11 07:28:19 PM UTC 24 |
Sep 11 07:45:21 PM UTC 24 |
9491942088 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.200967750 |
|
|
Sep 11 07:44:19 PM UTC 24 |
Sep 11 07:45:32 PM UTC 24 |
314425873 ps |
| T1539 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.717079530 |
|
|
Sep 11 07:44:45 PM UTC 24 |
Sep 11 07:45:35 PM UTC 24 |
4903026898 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.1222477762 |
|
|
Sep 11 07:44:30 PM UTC 24 |
Sep 11 07:45:45 PM UTC 24 |
1113945656 ps |
| T1540 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.3571970109 |
|
|
Sep 11 07:45:38 PM UTC 24 |
Sep 11 07:45:49 PM UTC 24 |
108057430 ps |
| T1541 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.2052464139 |
|
|
Sep 11 07:45:25 PM UTC 24 |
Sep 11 07:45:51 PM UTC 24 |
640514473 ps |
| T1542 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.3692054425 |
|
|
Sep 11 07:45:08 PM UTC 24 |
Sep 11 07:46:01 PM UTC 24 |
3869343707 ps |
| T1543 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.919034171 |
|
|
Sep 11 07:45:32 PM UTC 24 |
Sep 11 07:46:04 PM UTC 24 |
774490569 ps |
| T1544 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.3074209432 |
|
|
Sep 11 07:44:56 PM UTC 24 |
Sep 11 07:46:06 PM UTC 24 |
4278412214 ps |
| T1545 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.949922703 |
|
|
Sep 11 07:45:37 PM UTC 24 |
Sep 11 07:46:06 PM UTC 24 |
563881642 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.342240602 |
|
|
Sep 11 07:16:59 PM UTC 24 |
Sep 11 07:46:07 PM UTC 24 |
16191482593 ps |
| T1546 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.695483015 |
|
|
Sep 11 07:46:14 PM UTC 24 |
Sep 11 07:46:23 PM UTC 24 |
51271192 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.1935803657 |
|
|
Sep 11 07:08:44 PM UTC 24 |
Sep 11 07:46:24 PM UTC 24 |
141974789119 ps |
| T1547 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.3512589731 |
|
|
Sep 11 07:46:13 PM UTC 24 |
Sep 11 07:46:25 PM UTC 24 |
141280938 ps |
| T1548 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.1797261505 |
|
|
Sep 11 07:36:52 PM UTC 24 |
Sep 11 07:46:32 PM UTC 24 |
49329636630 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.2604546642 |
|
|
Sep 11 07:45:20 PM UTC 24 |
Sep 11 07:46:39 PM UTC 24 |
1127344909 ps |
| T1549 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.1864914904 |
|
|
Sep 11 07:36:56 PM UTC 24 |
Sep 11 07:47:00 PM UTC 24 |
41682753095 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.2089608823 |
|
|
Sep 11 07:45:57 PM UTC 24 |
Sep 11 07:47:16 PM UTC 24 |
959110872 ps |
| T1550 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.747974019 |
|
|
Sep 11 07:46:29 PM UTC 24 |
Sep 11 07:47:23 PM UTC 24 |
618509118 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.2425942695 |
|
|
Sep 11 07:14:08 PM UTC 24 |
Sep 11 07:47:25 PM UTC 24 |
16390398499 ps |
| T1551 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.260356994 |
|
|
Sep 11 07:31:28 PM UTC 24 |
Sep 11 07:47:26 PM UTC 24 |
9391149900 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2898257417 |
|
|
Sep 11 07:41:32 PM UTC 24 |
Sep 11 07:47:28 PM UTC 24 |
716848290 ps |
| T1552 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.665597449 |
|
|
Sep 11 07:46:32 PM UTC 24 |
Sep 11 07:47:29 PM UTC 24 |
1716252112 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.4164776673 |
|
|
Sep 11 07:44:39 PM UTC 24 |
Sep 11 07:47:30 PM UTC 24 |
3214740304 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.2870754393 |
|
|
Sep 11 07:46:50 PM UTC 24 |
Sep 11 07:47:41 PM UTC 24 |
922295236 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.4200768333 |
|
|
Sep 11 07:46:57 PM UTC 24 |
Sep 11 07:47:43 PM UTC 24 |
1170654706 ps |
| T1553 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.1218668696 |
|
|
Sep 11 07:47:03 PM UTC 24 |
Sep 11 07:47:43 PM UTC 24 |
1073442857 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.1871325867 |
|
|
Sep 11 07:41:29 PM UTC 24 |
Sep 11 07:47:52 PM UTC 24 |
3811553234 ps |
| T1554 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.19941170 |
|
|
Sep 11 07:41:43 PM UTC 24 |
Sep 11 07:47:55 PM UTC 24 |
4293548226 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.2142284091 |
|
|
Sep 11 07:46:28 PM UTC 24 |
Sep 11 07:47:57 PM UTC 24 |
5390122894 ps |
| T1555 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.4270695841 |
|
|
Sep 11 07:47:54 PM UTC 24 |
Sep 11 07:48:06 PM UTC 24 |
57442545 ps |
| T1556 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.1549444968 |
|
|
Sep 11 07:46:24 PM UTC 24 |
Sep 11 07:48:13 PM UTC 24 |
8003700093 ps |
| T1557 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.3808542888 |
|
|
Sep 11 07:48:06 PM UTC 24 |
Sep 11 07:48:15 PM UTC 24 |
38532157 ps |
| T1558 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.2491247299 |
|
|
Sep 11 07:47:40 PM UTC 24 |
Sep 11 07:48:17 PM UTC 24 |
736771558 ps |
| T1559 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.1378239828 |
|
|
Sep 11 07:47:25 PM UTC 24 |
Sep 11 07:48:18 PM UTC 24 |
1262296681 ps |
| T1560 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.2729562083 |
|
|
Sep 11 07:48:21 PM UTC 24 |
Sep 11 07:48:47 PM UTC 24 |
210604204 ps |
| T1561 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.3688311192 |
|
|
Sep 11 07:48:15 PM UTC 24 |
Sep 11 07:48:51 PM UTC 24 |
1005835565 ps |
| T1562 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.2019301841 |
|
|
Sep 11 07:48:43 PM UTC 24 |
Sep 11 07:49:01 PM UTC 24 |
206278897 ps |
| T1563 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.1099240807 |
|
|
Sep 11 07:48:06 PM UTC 24 |
Sep 11 07:49:09 PM UTC 24 |
6994878149 ps |
| T1564 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.3024734954 |
|
|
Sep 11 07:46:10 PM UTC 24 |
Sep 11 07:49:14 PM UTC 24 |
3097086188 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.1340289569 |
|
|
Sep 11 07:45:39 PM UTC 24 |
Sep 11 07:49:33 PM UTC 24 |
6143471876 ps |
| T1565 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.756844712 |
|
|
Sep 11 07:48:36 PM UTC 24 |
Sep 11 07:49:33 PM UTC 24 |
1203174654 ps |
| T1566 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.2992091316 |
|
|
Sep 11 07:49:12 PM UTC 24 |
Sep 11 07:49:35 PM UTC 24 |
555268374 ps |
| T1567 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.3647526556 |
|
|
Sep 11 07:49:16 PM UTC 24 |
Sep 11 07:49:37 PM UTC 24 |
119139733 ps |
| T1568 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.2232648185 |
|
|
Sep 11 07:47:54 PM UTC 24 |
Sep 11 07:49:58 PM UTC 24 |
190137980 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.3766692632 |
|
|
Sep 11 07:50:00 PM UTC 24 |
Sep 11 07:50:11 PM UTC 24 |
42620258 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.1333401806 |
|
|
Sep 11 07:50:01 PM UTC 24 |
Sep 11 07:50:11 PM UTC 24 |
47426372 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.868663123 |
|
|
Sep 11 07:39:01 PM UTC 24 |
Sep 11 07:50:12 PM UTC 24 |
6937843202 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.2344224202 |
|
|
Sep 11 07:48:09 PM UTC 24 |
Sep 11 07:50:13 PM UTC 24 |
5355317044 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.464758728 |
|
|
Sep 11 07:47:51 PM UTC 24 |
Sep 11 07:50:26 PM UTC 24 |
2656325260 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.3742264633 |
|
|
Sep 11 07:48:40 PM UTC 24 |
Sep 11 07:50:36 PM UTC 24 |
2662270853 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.1726367602 |
|
|
Sep 11 07:41:39 PM UTC 24 |
Sep 11 07:50:31 PM UTC 24 |
4125682720 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.2701813467 |
|
|
Sep 11 07:46:50 PM UTC 24 |
Sep 11 07:50:43 PM UTC 24 |
15287850707 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.140691664 |
|
|
Sep 11 07:50:36 PM UTC 24 |
Sep 11 07:50:49 PM UTC 24 |
64420204 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.3705169227 |
|
|
Sep 11 07:47:46 PM UTC 24 |
Sep 11 07:50:57 PM UTC 24 |
4275795032 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.3142588569 |
|
|
Sep 11 07:47:48 PM UTC 24 |
Sep 11 07:51:10 PM UTC 24 |
2287253571 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.3708687728 |
|
|
Sep 11 07:50:36 PM UTC 24 |
Sep 11 07:51:11 PM UTC 24 |
249212638 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.270331862 |
|
|
Sep 11 07:48:19 PM UTC 24 |
Sep 11 07:51:16 PM UTC 24 |
19228706571 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.3408345989 |
|
|
Sep 11 07:47:47 PM UTC 24 |
Sep 11 07:51:25 PM UTC 24 |
1741001664 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.3732291260 |
|
|
Sep 11 07:41:41 PM UTC 24 |
Sep 11 07:51:27 PM UTC 24 |
7261655117 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.1467849710 |
|
|
Sep 11 07:51:22 PM UTC 24 |
Sep 11 07:51:30 PM UTC 24 |
19302752 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.695053339 |
|
|
Sep 11 07:20:35 PM UTC 24 |
Sep 11 07:51:44 PM UTC 24 |
119877033135 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.4047008037 |
|
|
Sep 11 07:51:09 PM UTC 24 |
Sep 11 07:51:45 PM UTC 24 |
919678763 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.966257376 |
|
|
Sep 11 07:50:23 PM UTC 24 |
Sep 11 07:51:47 PM UTC 24 |
7033261533 ps |