| T2029 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.3132623753 |
|
|
Sep 11 08:26:20 PM UTC 24 |
Sep 11 08:30:22 PM UTC 24 |
2525458997 ps |
| T2030 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.3840334538 |
|
|
Sep 11 08:28:47 PM UTC 24 |
Sep 11 08:30:23 PM UTC 24 |
1505298654 ps |
| T2031 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.2705978155 |
|
|
Sep 11 08:30:18 PM UTC 24 |
Sep 11 08:30:29 PM UTC 24 |
48593454 ps |
| T2032 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.669071374 |
|
|
Sep 11 08:29:43 PM UTC 24 |
Sep 11 08:30:32 PM UTC 24 |
1087849038 ps |
| T2033 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.392359059 |
|
|
Sep 11 08:13:26 PM UTC 24 |
Sep 11 08:30:35 PM UTC 24 |
87375090621 ps |
| T2034 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.941619345 |
|
|
Sep 11 08:29:47 PM UTC 24 |
Sep 11 08:30:36 PM UTC 24 |
1543562399 ps |
| T2035 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.3365433568 |
|
|
Sep 11 08:29:15 PM UTC 24 |
Sep 11 08:30:40 PM UTC 24 |
5556182116 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.2586146660 |
|
|
Sep 11 08:29:52 PM UTC 24 |
Sep 11 08:30:42 PM UTC 24 |
115166485 ps |
| T2036 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.1355353214 |
|
|
Sep 11 08:29:37 PM UTC 24 |
Sep 11 08:30:44 PM UTC 24 |
1889071009 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.35099736 |
|
|
Sep 11 07:31:35 PM UTC 24 |
Sep 11 08:30:54 PM UTC 24 |
28200519415 ps |
| T2037 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.3808032484 |
|
|
Sep 11 08:29:14 PM UTC 24 |
Sep 11 08:30:54 PM UTC 24 |
9944938631 ps |
| T2038 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.4143800850 |
|
|
Sep 11 08:30:26 PM UTC 24 |
Sep 11 08:30:54 PM UTC 24 |
250397432 ps |
| T2039 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.558983714 |
|
|
Sep 11 08:30:33 PM UTC 24 |
Sep 11 08:30:56 PM UTC 24 |
405154866 ps |
| T2040 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.2112253148 |
|
|
Sep 11 08:30:33 PM UTC 24 |
Sep 11 08:30:57 PM UTC 24 |
675934272 ps |
| T2041 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.2099735686 |
|
|
Sep 11 08:26:23 PM UTC 24 |
Sep 11 08:31:01 PM UTC 24 |
9205668108 ps |
| T2042 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.2757680525 |
|
|
Sep 11 08:30:47 PM UTC 24 |
Sep 11 08:31:06 PM UTC 24 |
134985455 ps |
| T2043 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.3928522410 |
|
|
Sep 11 08:30:36 PM UTC 24 |
Sep 11 08:31:07 PM UTC 24 |
614889881 ps |
| T2044 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.2899265606 |
|
|
Sep 11 08:31:01 PM UTC 24 |
Sep 11 08:31:09 PM UTC 24 |
47806652 ps |
| T2045 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.3659919620 |
|
|
Sep 11 08:15:33 PM UTC 24 |
Sep 11 08:31:09 PM UTC 24 |
101369057147 ps |
| T2046 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.1069632754 |
|
|
Sep 11 08:31:01 PM UTC 24 |
Sep 11 08:31:11 PM UTC 24 |
163337799 ps |
| T2047 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.4134502490 |
|
|
Sep 11 08:30:21 PM UTC 24 |
Sep 11 08:31:13 PM UTC 24 |
5186373746 ps |
| T2048 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.1834886975 |
|
|
Sep 11 08:30:29 PM UTC 24 |
Sep 11 08:31:26 PM UTC 24 |
2634734092 ps |
| T2049 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.1796800463 |
|
|
Sep 11 08:31:19 PM UTC 24 |
Sep 11 08:31:32 PM UTC 24 |
78026246 ps |
| T2050 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.2016054039 |
|
|
Sep 11 08:03:10 PM UTC 24 |
Sep 11 08:31:37 PM UTC 24 |
106991675150 ps |
| T2051 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.2548293143 |
|
|
Sep 11 08:30:24 PM UTC 24 |
Sep 11 08:31:40 PM UTC 24 |
2418647804 ps |
| T2052 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.546380850 |
|
|
Sep 11 08:31:17 PM UTC 24 |
Sep 11 08:31:41 PM UTC 24 |
212028020 ps |
| T2053 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.336661944 |
|
|
Sep 11 08:30:27 PM UTC 24 |
Sep 11 08:31:53 PM UTC 24 |
1035200521 ps |
| T2054 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.252222285 |
|
|
Sep 11 08:26:24 PM UTC 24 |
Sep 11 08:31:54 PM UTC 24 |
2860295588 ps |
| T2055 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.1205093921 |
|
|
Sep 11 08:30:23 PM UTC 24 |
Sep 11 08:31:57 PM UTC 24 |
5858125187 ps |
| T2056 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.1007940502 |
|
|
Sep 11 08:31:31 PM UTC 24 |
Sep 11 08:31:59 PM UTC 24 |
434489217 ps |
| T2057 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.2816276015 |
|
|
Sep 11 08:31:35 PM UTC 24 |
Sep 11 08:32:05 PM UTC 24 |
730012173 ps |
| T2058 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.673395995 |
|
|
Sep 11 08:31:31 PM UTC 24 |
Sep 11 08:32:11 PM UTC 24 |
581373898 ps |
| T2059 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.2517465852 |
|
|
Sep 11 08:31:33 PM UTC 24 |
Sep 11 08:32:13 PM UTC 24 |
293443499 ps |
| T2060 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.3352202611 |
|
|
Sep 11 08:31:31 PM UTC 24 |
Sep 11 08:32:13 PM UTC 24 |
1150365875 ps |
| T2061 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.150001363 |
|
|
Sep 11 08:25:12 PM UTC 24 |
Sep 11 08:32:14 PM UTC 24 |
29532303009 ps |
| T2062 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.629842140 |
|
|
Sep 11 08:32:05 PM UTC 24 |
Sep 11 08:32:15 PM UTC 24 |
52184784 ps |
| T2063 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.2028273074 |
|
|
Sep 11 08:32:01 PM UTC 24 |
Sep 11 08:32:15 PM UTC 24 |
249928018 ps |
| T2064 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.2178072079 |
|
|
Sep 11 08:06:38 PM UTC 24 |
Sep 11 08:32:16 PM UTC 24 |
90460036327 ps |
| T2065 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.338783196 |
|
|
Sep 11 08:31:08 PM UTC 24 |
Sep 11 08:32:26 PM UTC 24 |
7220372960 ps |
| T2066 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.1801154890 |
|
|
Sep 11 08:31:22 PM UTC 24 |
Sep 11 08:32:28 PM UTC 24 |
1687477735 ps |
| T2067 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.3928503963 |
|
|
Sep 11 08:32:23 PM UTC 24 |
Sep 11 08:32:32 PM UTC 24 |
32577097 ps |
| T2068 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.872831621 |
|
|
Sep 11 08:29:51 PM UTC 24 |
Sep 11 08:32:34 PM UTC 24 |
2004341156 ps |
| T2069 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.2327066890 |
|
|
Sep 11 08:23:31 PM UTC 24 |
Sep 11 08:32:38 PM UTC 24 |
16040502697 ps |
| T2070 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.1412380381 |
|
|
Sep 11 08:32:40 PM UTC 24 |
Sep 11 08:33:00 PM UTC 24 |
89881532 ps |
| T2071 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.747480928 |
|
|
Sep 11 08:32:20 PM UTC 24 |
Sep 11 08:33:04 PM UTC 24 |
605808889 ps |
| T2072 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.4123418359 |
|
|
Sep 11 08:32:39 PM UTC 24 |
Sep 11 08:33:06 PM UTC 24 |
230768806 ps |
| T2073 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.147749393 |
|
|
Sep 11 08:33:00 PM UTC 24 |
Sep 11 08:33:10 PM UTC 24 |
46527673 ps |
| T2074 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.3618864049 |
|
|
Sep 11 08:31:07 PM UTC 24 |
Sep 11 08:33:11 PM UTC 24 |
5618423588 ps |
| T2075 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.2549010209 |
|
|
Sep 11 08:32:41 PM UTC 24 |
Sep 11 08:33:12 PM UTC 24 |
192506855 ps |
| T2076 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.2105986409 |
|
|
Sep 11 08:33:04 PM UTC 24 |
Sep 11 08:33:14 PM UTC 24 |
45176124 ps |
| T2077 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.1018690782 |
|
|
Sep 11 08:23:40 PM UTC 24 |
Sep 11 08:33:15 PM UTC 24 |
6361264990 ps |
| T2078 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.67939799 |
|
|
Sep 11 08:32:36 PM UTC 24 |
Sep 11 08:33:16 PM UTC 24 |
459952210 ps |
| T2079 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.2652639184 |
|
|
Sep 11 08:30:25 PM UTC 24 |
Sep 11 08:33:30 PM UTC 24 |
12137019828 ps |
| T2080 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.3117259754 |
|
|
Sep 11 08:32:07 PM UTC 24 |
Sep 11 08:33:41 PM UTC 24 |
9179304987 ps |
| T2081 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.1436201744 |
|
|
Sep 11 08:15:45 PM UTC 24 |
Sep 11 08:33:42 PM UTC 24 |
80090987346 ps |
| T2082 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.39725581 |
|
|
Sep 11 08:23:22 PM UTC 24 |
Sep 11 08:33:44 PM UTC 24 |
5329675755 ps |
| T2083 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.2092280152 |
|
|
Sep 11 08:32:36 PM UTC 24 |
Sep 11 08:33:53 PM UTC 24 |
2737461633 ps |
| T2084 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.236211120 |
|
|
Sep 11 08:32:19 PM UTC 24 |
Sep 11 08:33:54 PM UTC 24 |
6933381455 ps |
| T2085 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.850741028 |
|
|
Sep 11 08:26:56 PM UTC 24 |
Sep 11 08:34:00 PM UTC 24 |
43632951017 ps |
| T2086 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.3491891915 |
|
|
Sep 11 08:33:41 PM UTC 24 |
Sep 11 08:34:02 PM UTC 24 |
154201802 ps |
| T2087 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.371000342 |
|
|
Sep 11 08:33:27 PM UTC 24 |
Sep 11 08:34:10 PM UTC 24 |
833158863 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.18335371 |
|
|
Sep 11 08:28:48 PM UTC 24 |
Sep 11 08:34:15 PM UTC 24 |
8425994056 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.881839661 |
|
|
Sep 11 08:30:56 PM UTC 24 |
Sep 11 08:34:16 PM UTC 24 |
2417528368 ps |
| T2088 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.1829395958 |
|
|
Sep 11 08:27:34 PM UTC 24 |
Sep 11 08:34:17 PM UTC 24 |
10933784314 ps |
| T2089 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.403644724 |
|
|
Sep 11 08:33:34 PM UTC 24 |
Sep 11 08:34:17 PM UTC 24 |
490663326 ps |
| T2090 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.3356496265 |
|
|
Sep 11 08:33:56 PM UTC 24 |
Sep 11 08:34:21 PM UTC 24 |
236514905 ps |
| T2091 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.3195594771 |
|
|
Sep 11 08:34:08 PM UTC 24 |
Sep 11 08:34:28 PM UTC 24 |
522523743 ps |
| T2092 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.1449164228 |
|
|
Sep 11 08:33:26 PM UTC 24 |
Sep 11 08:34:31 PM UTC 24 |
4180925811 ps |
| T2093 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.3444450 |
|
|
Sep 11 08:34:07 PM UTC 24 |
Sep 11 08:34:32 PM UTC 24 |
151360261 ps |
| T2094 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.2463163587 |
|
|
Sep 11 08:32:42 PM UTC 24 |
Sep 11 08:34:32 PM UTC 24 |
1480104644 ps |
| T2095 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.3006375572 |
|
|
Sep 11 08:19:21 PM UTC 24 |
Sep 11 08:34:37 PM UTC 24 |
95257524518 ps |
| T2096 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.2926394513 |
|
|
Sep 11 08:34:27 PM UTC 24 |
Sep 11 08:34:41 PM UTC 24 |
237709041 ps |
| T2097 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.2054975897 |
|
|
Sep 11 08:34:35 PM UTC 24 |
Sep 11 08:34:45 PM UTC 24 |
44483092 ps |
| T2098 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.1258079950 |
|
|
Sep 11 08:34:08 PM UTC 24 |
Sep 11 08:34:51 PM UTC 24 |
306207464 ps |
| T2099 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.3891579084 |
|
|
Sep 11 08:28:44 PM UTC 24 |
Sep 11 08:34:54 PM UTC 24 |
3347545601 ps |
| T2100 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.2322865480 |
|
|
Sep 11 08:24:11 PM UTC 24 |
Sep 11 08:34:57 PM UTC 24 |
42107029490 ps |
| T2101 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.1347748705 |
|
|
Sep 11 07:35:52 PM UTC 24 |
Sep 11 08:35:12 PM UTC 24 |
30959076254 ps |
| T2102 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.2356295521 |
|
|
Sep 11 08:33:37 PM UTC 24 |
Sep 11 08:35:18 PM UTC 24 |
2800960121 ps |
| T2103 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.1947303708 |
|
|
Sep 11 08:34:42 PM UTC 24 |
Sep 11 08:35:26 PM UTC 24 |
416682360 ps |
| T2104 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.716477774 |
|
|
Sep 11 08:35:03 PM UTC 24 |
Sep 11 08:35:29 PM UTC 24 |
211221888 ps |
| T2105 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.786084121 |
|
|
Sep 11 08:35:03 PM UTC 24 |
Sep 11 08:35:30 PM UTC 24 |
585275024 ps |
| T2106 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.3799899595 |
|
|
Sep 11 08:34:57 PM UTC 24 |
Sep 11 08:35:33 PM UTC 24 |
1336558784 ps |
| T2107 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.834333103 |
|
|
Sep 11 08:33:25 PM UTC 24 |
Sep 11 08:35:36 PM UTC 24 |
8958196455 ps |
| T2108 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.3155078642 |
|
|
Sep 11 08:35:11 PM UTC 24 |
Sep 11 08:35:49 PM UTC 24 |
277708256 ps |
| T2109 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.3786569511 |
|
|
Sep 11 08:35:43 PM UTC 24 |
Sep 11 08:35:54 PM UTC 24 |
251672506 ps |
| T2110 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.1153825890 |
|
|
Sep 11 08:24:05 PM UTC 24 |
Sep 11 08:36:01 PM UTC 24 |
55051717882 ps |
| T2111 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.1978752968 |
|
|
Sep 11 08:34:41 PM UTC 24 |
Sep 11 08:36:01 PM UTC 24 |
2212469558 ps |
| T2112 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.3413208747 |
|
|
Sep 11 08:35:51 PM UTC 24 |
Sep 11 08:36:03 PM UTC 24 |
61195399 ps |
| T2113 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.292935235 |
|
|
Sep 11 08:34:39 PM UTC 24 |
Sep 11 08:36:03 PM UTC 24 |
5183263946 ps |
| T2114 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.131002779 |
|
|
Sep 11 08:34:39 PM UTC 24 |
Sep 11 08:36:06 PM UTC 24 |
7937367661 ps |
| T2115 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.1741847290 |
|
|
Sep 11 08:34:53 PM UTC 24 |
Sep 11 08:36:12 PM UTC 24 |
3979533175 ps |
| T2116 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.3523150205 |
|
|
Sep 11 08:34:57 PM UTC 24 |
Sep 11 08:36:18 PM UTC 24 |
1884368196 ps |
| T2117 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.1723678973 |
|
|
Sep 11 08:30:57 PM UTC 24 |
Sep 11 08:36:29 PM UTC 24 |
4853761921 ps |
| T2118 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.1595507254 |
|
|
Sep 11 08:36:02 PM UTC 24 |
Sep 11 08:36:41 PM UTC 24 |
429514553 ps |
| T2119 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.376796462 |
|
|
Sep 11 08:36:32 PM UTC 24 |
Sep 11 08:36:44 PM UTC 24 |
92322389 ps |
| T2120 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.542589797 |
|
|
Sep 11 08:31:57 PM UTC 24 |
Sep 11 08:36:44 PM UTC 24 |
1010491088 ps |
| T2121 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.1275222141 |
|
|
Sep 11 08:34:46 PM UTC 24 |
Sep 11 08:36:49 PM UTC 24 |
12926483354 ps |
| T2122 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.2536224978 |
|
|
Sep 11 08:36:37 PM UTC 24 |
Sep 11 08:36:50 PM UTC 24 |
83442595 ps |
| T2123 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.1836573752 |
|
|
Sep 11 08:36:23 PM UTC 24 |
Sep 11 08:36:50 PM UTC 24 |
615132605 ps |
| T2124 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.3326625468 |
|
|
Sep 11 08:31:51 PM UTC 24 |
Sep 11 08:36:57 PM UTC 24 |
9878100907 ps |
| T2125 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.2697586688 |
|
|
Sep 11 08:29:52 PM UTC 24 |
Sep 11 08:37:18 PM UTC 24 |
894385682 ps |
| T2126 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.2363767980 |
|
|
Sep 11 08:35:58 PM UTC 24 |
Sep 11 08:37:20 PM UTC 24 |
2264443852 ps |
| T2127 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.2346081926 |
|
|
Sep 11 08:36:24 PM UTC 24 |
Sep 11 08:37:22 PM UTC 24 |
2000584874 ps |
| T2128 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.3539546225 |
|
|
Sep 11 08:37:08 PM UTC 24 |
Sep 11 08:37:22 PM UTC 24 |
213689246 ps |
| T2129 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.1462419874 |
|
|
Sep 11 08:37:13 PM UTC 24 |
Sep 11 08:37:23 PM UTC 24 |
45269383 ps |
| T2130 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.2415751878 |
|
|
Sep 11 08:25:24 PM UTC 24 |
Sep 11 08:37:32 PM UTC 24 |
48522227835 ps |
| T2131 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.956247017 |
|
|
Sep 11 08:37:18 PM UTC 24 |
Sep 11 08:37:32 PM UTC 24 |
119474676 ps |
| T2132 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.3091751024 |
|
|
Sep 11 08:35:55 PM UTC 24 |
Sep 11 08:37:32 PM UTC 24 |
5133161265 ps |
| T2133 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.723328406 |
|
|
Sep 11 08:36:43 PM UTC 24 |
Sep 11 08:37:33 PM UTC 24 |
518547416 ps |
| T2134 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.2196843700 |
|
|
Sep 11 08:29:25 PM UTC 24 |
Sep 11 08:37:34 PM UTC 24 |
41679746444 ps |
| T2135 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.2756464130 |
|
|
Sep 11 08:18:33 PM UTC 24 |
Sep 11 08:37:42 PM UTC 24 |
85407285760 ps |
| T2136 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.765792857 |
|
|
Sep 11 08:35:54 PM UTC 24 |
Sep 11 08:37:48 PM UTC 24 |
8189775044 ps |
| T2137 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.616643731 |
|
|
Sep 11 08:34:20 PM UTC 24 |
Sep 11 08:37:50 PM UTC 24 |
6863653255 ps |
| T2138 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.3586399225 |
|
|
Sep 11 08:35:15 PM UTC 24 |
Sep 11 08:37:54 PM UTC 24 |
3145655662 ps |
| T2139 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.1309745983 |
|
|
Sep 11 08:37:44 PM UTC 24 |
Sep 11 08:38:05 PM UTC 24 |
206051916 ps |
| T2140 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.59523630 |
|
|
Sep 11 08:20:20 PM UTC 24 |
Sep 11 08:38:09 PM UTC 24 |
100680431785 ps |
| T2141 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3388864431 |
|
|
Sep 11 08:37:59 PM UTC 24 |
Sep 11 08:38:17 PM UTC 24 |
431149294 ps |
| T2142 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.3365677717 |
|
|
Sep 11 08:36:25 PM UTC 24 |
Sep 11 08:38:19 PM UTC 24 |
2654339628 ps |
| T2143 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.2324951997 |
|
|
Sep 11 08:35:24 PM UTC 24 |
Sep 11 08:38:20 PM UTC 24 |
2764717807 ps |
| T2144 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.4254517880 |
|
|
Sep 11 08:37:58 PM UTC 24 |
Sep 11 08:38:21 PM UTC 24 |
158149819 ps |
| T2145 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.3230230509 |
|
|
Sep 11 08:37:13 PM UTC 24 |
Sep 11 08:38:28 PM UTC 24 |
4122486764 ps |
| T2146 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.3098908479 |
|
|
Sep 11 08:31:39 PM UTC 24 |
Sep 11 08:38:29 PM UTC 24 |
4376590996 ps |
| T2147 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.1332602344 |
|
|
Sep 11 08:38:20 PM UTC 24 |
Sep 11 08:38:32 PM UTC 24 |
157350447 ps |
| T2148 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.3391018329 |
|
|
Sep 11 08:37:06 PM UTC 24 |
Sep 11 08:38:39 PM UTC 24 |
1384315142 ps |
| T2149 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.3441054244 |
|
|
Sep 11 08:38:30 PM UTC 24 |
Sep 11 08:38:41 PM UTC 24 |
51792917 ps |
| T2150 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.3318027916 |
|
|
Sep 11 08:37:58 PM UTC 24 |
Sep 11 08:38:41 PM UTC 24 |
366452162 ps |
| T2151 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.522010245 |
|
|
Sep 11 08:22:43 PM UTC 24 |
Sep 11 08:38:43 PM UTC 24 |
59007788311 ps |
| T2152 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.3727588580 |
|
|
Sep 11 08:37:56 PM UTC 24 |
Sep 11 08:38:44 PM UTC 24 |
479314446 ps |
| T2153 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.3421338822 |
|
|
Sep 11 08:32:58 PM UTC 24 |
Sep 11 08:38:45 PM UTC 24 |
2897128848 ps |
| T2154 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.1592681458 |
|
|
Sep 11 08:37:48 PM UTC 24 |
Sep 11 08:38:58 PM UTC 24 |
957280752 ps |
| T2155 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.4035112807 |
|
|
Sep 11 08:38:46 PM UTC 24 |
Sep 11 08:39:05 PM UTC 24 |
168150011 ps |
| T2156 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.768426672 |
|
|
Sep 11 08:32:54 PM UTC 24 |
Sep 11 08:39:05 PM UTC 24 |
10507086906 ps |
| T2157 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.353319051 |
|
|
Sep 11 08:37:16 PM UTC 24 |
Sep 11 08:39:06 PM UTC 24 |
8072782711 ps |
| T2158 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.3509508878 |
|
|
Sep 11 08:27:49 PM UTC 24 |
Sep 11 08:39:08 PM UTC 24 |
7909286683 ps |
| T2159 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.687480982 |
|
|
Sep 11 08:30:46 PM UTC 24 |
Sep 11 08:39:20 PM UTC 24 |
15799402227 ps |
| T2160 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.3572220586 |
|
|
Sep 11 08:39:07 PM UTC 24 |
Sep 11 08:39:30 PM UTC 24 |
662423100 ps |
| T2161 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.528732288 |
|
|
Sep 11 08:39:07 PM UTC 24 |
Sep 11 08:39:37 PM UTC 24 |
192303298 ps |
| T2162 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.3313590822 |
|
|
Sep 11 08:39:26 PM UTC 24 |
Sep 11 08:39:39 PM UTC 24 |
213261080 ps |
| T2163 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.2976489183 |
|
|
Sep 11 08:39:32 PM UTC 24 |
Sep 11 08:39:43 PM UTC 24 |
57281879 ps |
| T2164 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.253667392 |
|
|
Sep 11 08:38:45 PM UTC 24 |
Sep 11 08:39:47 PM UTC 24 |
1945491310 ps |
| T2165 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.3498926433 |
|
|
Sep 11 08:39:05 PM UTC 24 |
Sep 11 08:39:52 PM UTC 24 |
1048946404 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.3718494613 |
|
|
Sep 11 08:32:53 PM UTC 24 |
Sep 11 08:39:55 PM UTC 24 |
7225149094 ps |
| T2166 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.4143210083 |
|
|
Sep 11 08:38:34 PM UTC 24 |
Sep 11 08:39:59 PM UTC 24 |
8874629843 ps |
| T2167 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3512235351 |
|
|
Sep 11 08:39:09 PM UTC 24 |
Sep 11 08:40:01 PM UTC 24 |
1134849229 ps |
| T2168 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.455721811 |
|
|
Sep 11 08:38:16 PM UTC 24 |
Sep 11 08:40:02 PM UTC 24 |
1583790508 ps |
| T2169 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.3460589759 |
|
|
Sep 11 08:38:43 PM UTC 24 |
Sep 11 08:40:02 PM UTC 24 |
4773155132 ps |
| T2170 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.2481836247 |
|
|
Sep 11 08:29:25 PM UTC 24 |
Sep 11 08:40:12 PM UTC 24 |
43413782625 ps |
| T2171 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.1666752360 |
|
|
Sep 11 08:38:55 PM UTC 24 |
Sep 11 08:40:13 PM UTC 24 |
829373774 ps |
| T2172 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.3311985346 |
|
|
Sep 11 08:32:23 PM UTC 24 |
Sep 11 08:40:23 PM UTC 24 |
51079907406 ps |
| T2173 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.2710150361 |
|
|
Sep 11 08:37:07 PM UTC 24 |
Sep 11 08:40:24 PM UTC 24 |
5173214273 ps |
| T2174 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.322881479 |
|
|
Sep 11 08:38:47 PM UTC 24 |
Sep 11 08:40:30 PM UTC 24 |
9268082248 ps |
| T2175 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.3221514019 |
|
|
Sep 11 08:40:26 PM UTC 24 |
Sep 11 08:40:39 PM UTC 24 |
130874245 ps |
| T2176 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.4115455161 |
|
|
Sep 11 08:39:53 PM UTC 24 |
Sep 11 08:40:39 PM UTC 24 |
931004449 ps |
| T2177 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.2951337579 |
|
|
Sep 11 08:40:03 PM UTC 24 |
Sep 11 08:40:40 PM UTC 24 |
420090161 ps |
| T2178 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.25645017 |
|
|
Sep 11 08:39:34 PM UTC 24 |
Sep 11 08:40:42 PM UTC 24 |
4597492469 ps |
| T2179 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.1151547611 |
|
|
Sep 11 08:28:16 PM UTC 24 |
Sep 11 08:40:47 PM UTC 24 |
50121530354 ps |
| T2180 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.3477034852 |
|
|
Sep 11 08:40:49 PM UTC 24 |
Sep 11 08:40:56 PM UTC 24 |
8217045 ps |
| T2181 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.3506424613 |
|
|
Sep 11 08:40:50 PM UTC 24 |
Sep 11 08:41:04 PM UTC 24 |
225313121 ps |
| T2182 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.2111799140 |
|
|
Sep 11 08:40:54 PM UTC 24 |
Sep 11 08:41:04 PM UTC 24 |
44442364 ps |
| T2183 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.1526628016 |
|
|
Sep 11 08:40:27 PM UTC 24 |
Sep 11 08:41:06 PM UTC 24 |
710075745 ps |
| T2184 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.1749224847 |
|
|
Sep 11 08:40:23 PM UTC 24 |
Sep 11 08:41:19 PM UTC 24 |
1277987080 ps |
| T2185 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.1248126228 |
|
|
Sep 11 08:40:21 PM UTC 24 |
Sep 11 08:41:20 PM UTC 24 |
1979911455 ps |
| T2186 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.1456575317 |
|
|
Sep 11 08:41:04 PM UTC 24 |
Sep 11 08:41:21 PM UTC 24 |
396327184 ps |
| T2187 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_aliasing.1486610290 |
|
|
Sep 11 06:55:43 PM UTC 24 |
Sep 11 08:41:23 PM UTC 24 |
40406534312 ps |
| T2188 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.1331202487 |
|
|
Sep 11 08:41:07 PM UTC 24 |
Sep 11 08:41:28 PM UTC 24 |
143432268 ps |
| T2189 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.1506301608 |
|
|
Sep 11 08:40:10 PM UTC 24 |
Sep 11 08:41:32 PM UTC 24 |
1140136691 ps |
| T2190 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.1929070749 |
|
|
Sep 11 08:27:01 PM UTC 24 |
Sep 11 08:41:35 PM UTC 24 |
58060747441 ps |
| T2191 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.2406276328 |
|
|
Sep 11 08:41:32 PM UTC 24 |
Sep 11 08:41:50 PM UTC 24 |
134700235 ps |
| T2192 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.650897239 |
|
|
Sep 11 08:31:20 PM UTC 24 |
Sep 11 08:41:50 PM UTC 24 |
43289213886 ps |
| T2193 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.3165248186 |
|
|
Sep 11 08:38:53 PM UTC 24 |
Sep 11 08:41:56 PM UTC 24 |
12451675962 ps |
| T2194 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.2196576232 |
|
|
Sep 11 08:41:45 PM UTC 24 |
Sep 11 08:42:01 PM UTC 24 |
75930744 ps |
| T2195 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.4293489331 |
|
|
Sep 11 08:41:39 PM UTC 24 |
Sep 11 08:42:04 PM UTC 24 |
202100922 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.3857927330 |
|
|
Sep 11 08:36:56 PM UTC 24 |
Sep 11 08:42:04 PM UTC 24 |
788333226 ps |
| T2196 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.1549874834 |
|
|
Sep 11 08:39:45 PM UTC 24 |
Sep 11 08:42:04 PM UTC 24 |
6619080094 ps |
| T2197 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.430770732 |
|
|
Sep 11 08:41:44 PM UTC 24 |
Sep 11 08:42:05 PM UTC 24 |
268396397 ps |
| T2198 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.2036153069 |
|
|
Sep 11 08:41:05 PM UTC 24 |
Sep 11 08:42:10 PM UTC 24 |
4191408213 ps |
| T2199 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.4248955082 |
|
|
Sep 11 08:39:23 PM UTC 24 |
Sep 11 08:42:23 PM UTC 24 |
2116517693 ps |
| T2200 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.905697243 |
|
|
Sep 11 08:42:11 PM UTC 24 |
Sep 11 08:42:24 PM UTC 24 |
222960770 ps |
| T2201 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.2031105130 |
|
|
Sep 11 08:42:17 PM UTC 24 |
Sep 11 08:42:25 PM UTC 24 |
43638722 ps |
| T2202 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.2796593327 |
|
|
Sep 11 08:41:23 PM UTC 24 |
Sep 11 08:42:34 PM UTC 24 |
5053063675 ps |
| T2203 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.2806979561 |
|
|
Sep 11 08:42:26 PM UTC 24 |
Sep 11 08:42:36 PM UTC 24 |
71790155 ps |
| T2204 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.1829243920 |
|
|
Sep 11 08:30:27 PM UTC 24 |
Sep 11 08:42:40 PM UTC 24 |
70837893038 ps |
| T2205 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.2811634484 |
|
|
Sep 11 08:41:03 PM UTC 24 |
Sep 11 08:42:41 PM UTC 24 |
8989186152 ps |
| T2206 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.1547739012 |
|
|
Sep 11 08:42:27 PM UTC 24 |
Sep 11 08:42:41 PM UTC 24 |
122921857 ps |
| T2207 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.1681984924 |
|
|
Sep 11 08:34:17 PM UTC 24 |
Sep 11 08:42:50 PM UTC 24 |
6998077214 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.2351277407 |
|
|
Sep 11 08:39:30 PM UTC 24 |
Sep 11 08:42:53 PM UTC 24 |
736421956 ps |
| T2208 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.3394676166 |
|
|
Sep 11 08:41:59 PM UTC 24 |
Sep 11 08:43:04 PM UTC 24 |
214095001 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.540545596 |
|
|
Sep 11 08:40:39 PM UTC 24 |
Sep 11 08:43:12 PM UTC 24 |
304784132 ps |
| T2209 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.994976602 |
|
|
Sep 11 08:41:29 PM UTC 24 |
Sep 11 08:43:15 PM UTC 24 |
2558873734 ps |
| T2210 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.475265548 |
|
|
Sep 11 08:40:09 PM UTC 24 |
Sep 11 08:43:17 PM UTC 24 |
10155629364 ps |
| T2211 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.3202085335 |
|
|
Sep 11 08:42:22 PM UTC 24 |
Sep 11 08:43:21 PM UTC 24 |
3794323432 ps |
| T2212 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.1113091848 |
|
|
Sep 11 08:42:48 PM UTC 24 |
Sep 11 08:43:26 PM UTC 24 |
1390781813 ps |
| T2213 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.3778634432 |
|
|
Sep 11 08:43:19 PM UTC 24 |
Sep 11 08:43:30 PM UTC 24 |
149186113 ps |
| T2214 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.2186475501 |
|
|
Sep 11 08:43:28 PM UTC 24 |
Sep 11 08:43:37 PM UTC 24 |
43901644 ps |
| T2215 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.903473884 |
|
|
Sep 11 08:42:55 PM UTC 24 |
Sep 11 08:43:45 PM UTC 24 |
1323813796 ps |
| T2216 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.4178717648 |
|
|
Sep 11 08:30:54 PM UTC 24 |
Sep 11 08:43:51 PM UTC 24 |
11345620701 ps |
| T2217 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.1231360115 |
|
|
Sep 11 08:42:36 PM UTC 24 |
Sep 11 08:43:57 PM UTC 24 |
1072940782 ps |
| T2218 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.4228202857 |
|
|
Sep 11 08:43:47 PM UTC 24 |
Sep 11 08:44:00 PM UTC 24 |
71356463 ps |
| T2219 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.2019866787 |
|
|
Sep 11 08:43:02 PM UTC 24 |
Sep 11 08:44:05 PM UTC 24 |
1370423605 ps |
| T2220 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.1980712743 |
|
|
Sep 11 08:28:08 PM UTC 24 |
Sep 11 08:44:07 PM UTC 24 |
97598690857 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.3564147367 |
|
|
Sep 11 08:39:12 PM UTC 24 |
Sep 11 08:44:07 PM UTC 24 |
864328105 ps |
| T2221 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.1164425050 |
|
|
Sep 11 08:43:42 PM UTC 24 |
Sep 11 08:44:08 PM UTC 24 |
642703498 ps |
| T2222 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.538936887 |
|
|
Sep 11 08:42:16 PM UTC 24 |
Sep 11 08:44:18 PM UTC 24 |
9777744395 ps |
| T2223 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.696991561 |
|
|
Sep 11 08:42:44 PM UTC 24 |
Sep 11 08:44:25 PM UTC 24 |
2470243873 ps |
| T2224 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.2163106669 |
|
|
Sep 11 08:44:15 PM UTC 24 |
Sep 11 08:44:27 PM UTC 24 |
303088465 ps |
| T2225 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.316288757 |
|
|
Sep 11 08:35:38 PM UTC 24 |
Sep 11 08:44:40 PM UTC 24 |
4482520519 ps |
| T2226 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.312815107 |
|
|
Sep 11 08:44:23 PM UTC 24 |
Sep 11 08:44:45 PM UTC 24 |
362752508 ps |
| T2227 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.943938303 |
|
|
Sep 11 08:43:36 PM UTC 24 |
Sep 11 08:44:46 PM UTC 24 |
7413312348 ps |
| T2228 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.1945173040 |
|
|
Sep 11 08:37:59 PM UTC 24 |
Sep 11 08:44:50 PM UTC 24 |
12285198607 ps |
| T2229 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.1057564666 |
|
|
Sep 11 08:44:50 PM UTC 24 |
Sep 11 08:45:00 PM UTC 24 |
42690651 ps |
| T2230 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.2565283513 |
|
|
Sep 11 08:31:16 PM UTC 24 |
Sep 11 08:45:01 PM UTC 24 |
91890311242 ps |
| T2231 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.961578681 |
|
|
Sep 11 08:44:30 PM UTC 24 |
Sep 11 08:45:01 PM UTC 24 |
195177186 ps |
| T2232 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.4194488969 |
|
|
Sep 11 08:44:24 PM UTC 24 |
Sep 11 08:45:01 PM UTC 24 |
1005955174 ps |
| T2233 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.2843955775 |
|
|
Sep 11 08:44:53 PM UTC 24 |
Sep 11 08:45:03 PM UTC 24 |
44693229 ps |
| T2234 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.4057522428 |
|
|
Sep 11 08:43:40 PM UTC 24 |
Sep 11 08:45:07 PM UTC 24 |
5449667303 ps |
| T2235 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.2502608661 |
|
|
Sep 11 08:44:27 PM UTC 24 |
Sep 11 08:45:09 PM UTC 24 |
59831833 ps |
| T2236 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.445582607 |
|
|
Sep 11 08:42:29 PM UTC 24 |
Sep 11 08:45:16 PM UTC 24 |
8431090585 ps |
| T2237 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.3621531782 |
|
|
Sep 11 08:34:58 PM UTC 24 |
Sep 11 08:45:18 PM UTC 24 |
31985553443 ps |
| T2238 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.525916811 |
|
|
Sep 11 08:44:02 PM UTC 24 |
Sep 11 08:45:21 PM UTC 24 |
1502787631 ps |
| T2239 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.3644353849 |
|
|
Sep 11 08:45:26 PM UTC 24 |
Sep 11 08:45:37 PM UTC 24 |
207818274 ps |
| T2240 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.2212678728 |
|
|
Sep 11 08:38:14 PM UTC 24 |
Sep 11 08:45:41 PM UTC 24 |
12965931824 ps |
| T2241 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.3744077856 |
|
|
Sep 11 08:32:30 PM UTC 24 |
Sep 11 08:45:43 PM UTC 24 |
50823714176 ps |
| T2242 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.394575099 |
|
|
Sep 11 08:45:29 PM UTC 24 |
Sep 11 08:45:44 PM UTC 24 |
254881791 ps |
| T2243 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.4101043971 |
|
|
Sep 11 08:41:12 PM UTC 24 |
Sep 11 08:45:47 PM UTC 24 |
29551366220 ps |
| T2244 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.4028405247 |
|
|
Sep 11 08:08:04 PM UTC 24 |
Sep 11 08:45:57 PM UTC 24 |
159586307604 ps |
| T2245 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.3695041515 |
|
|
Sep 11 08:45:35 PM UTC 24 |
Sep 11 08:45:59 PM UTC 24 |
338903838 ps |
| T2246 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.2781354238 |
|
|
Sep 11 08:43:14 PM UTC 24 |
Sep 11 08:46:00 PM UTC 24 |
5681582918 ps |
| T2247 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.525283307 |
|
|
Sep 11 08:45:16 PM UTC 24 |
Sep 11 08:46:01 PM UTC 24 |
498741724 ps |
| T2248 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.1279757786 |
|
|
Sep 11 08:31:23 PM UTC 24 |
Sep 11 08:46:07 PM UTC 24 |
56493221798 ps |
| T2249 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.1063563940 |
|
|
Sep 11 08:24:10 PM UTC 24 |
Sep 11 08:46:08 PM UTC 24 |
97351469202 ps |
| T2250 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.2491741900 |
|
|
Sep 11 08:41:47 PM UTC 24 |
Sep 11 08:46:09 PM UTC 24 |
7130318355 ps |
| T2251 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.566622152 |
|
|
Sep 11 08:45:41 PM UTC 24 |
Sep 11 08:46:11 PM UTC 24 |
232463320 ps |
| T2252 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.393728902 |
|
|
Sep 11 08:40:28 PM UTC 24 |
Sep 11 08:46:11 PM UTC 24 |
7830342253 ps |
| T2253 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.3354004907 |
|
|
Sep 11 08:46:09 PM UTC 24 |
Sep 11 08:46:16 PM UTC 24 |
42555400 ps |
| T2254 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.4019282189 |
|
|
Sep 11 08:42:28 PM UTC 24 |
Sep 11 08:46:17 PM UTC 24 |
24549845732 ps |
| T2255 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.2792642656 |
|
|
Sep 11 08:46:09 PM UTC 24 |
Sep 11 08:46:19 PM UTC 24 |
46534297 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.2158070961 |
|
|
Sep 11 08:43:03 PM UTC 24 |
Sep 11 08:46:21 PM UTC 24 |
2663413139 ps |
| T2256 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1847268421 |
|
|
Sep 11 08:20:32 PM UTC 24 |
Sep 11 08:46:21 PM UTC 24 |
99205605354 ps |
| T2257 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2105498460 |
|
|
Sep 11 08:17:14 PM UTC 24 |
Sep 11 08:46:24 PM UTC 24 |
108349848878 ps |
| T2258 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.3770514375 |
|
|
Sep 11 08:45:28 PM UTC 24 |
Sep 11 08:46:30 PM UTC 24 |
908405595 ps |
| T2259 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3426899162 |
|
|
Sep 11 08:46:08 PM UTC 24 |
Sep 11 08:46:35 PM UTC 24 |
141948573 ps |
| T2260 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.1870859417 |
|
|
Sep 11 08:46:22 PM UTC 24 |
Sep 11 08:46:37 PM UTC 24 |
130690548 ps |
| T2261 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.489401064 |
|
|
Sep 11 08:36:17 PM UTC 24 |
Sep 11 08:46:39 PM UTC 24 |
42648746385 ps |
| T2262 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.975121679 |
|
|
Sep 11 08:44:43 PM UTC 24 |
Sep 11 08:46:43 PM UTC 24 |
331543041 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.235913836 |
|
|
Sep 11 08:34:23 PM UTC 24 |
Sep 11 08:46:47 PM UTC 24 |
8092787302 ps |
| T2263 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.772846154 |
|
|
Sep 11 08:46:31 PM UTC 24 |
Sep 11 08:47:41 PM UTC 24 |
2421058908 ps |
| T2264 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.2480463215 |
|
|
Sep 11 08:45:11 PM UTC 24 |
Sep 11 08:46:51 PM UTC 24 |
6803637774 ps |
| T2265 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.830239142 |
|
|
Sep 11 08:45:12 PM UTC 24 |
Sep 11 08:46:59 PM UTC 24 |
2414556490 ps |
| T2266 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.3523436882 |
|
|
Sep 11 08:46:39 PM UTC 24 |
Sep 11 08:46:59 PM UTC 24 |
275967765 ps |
| T2267 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.258955333 |
|
|
Sep 11 08:45:06 PM UTC 24 |
Sep 11 08:47:00 PM UTC 24 |
10204152606 ps |