| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 95.97 | 95.43 | 93.69 | 95.30 | 94.46 | 97.35 | 99.55 |
| T2762 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke.1728198495 | Sep 11 09:17:43 PM UTC 24 | Sep 11 09:17:53 PM UTC 24 | 48112583 ps | ||
| T2763 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_large_delays.4069008878 | Sep 11 09:15:56 PM UTC 24 | Sep 11 09:17:56 PM UTC 24 | 9600684359 ps | ||
| T2764 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_random.1543992264 | Sep 11 09:17:29 PM UTC 24 | Sep 11 09:17:56 PM UTC 24 | 618794447 ps | ||
| T2765 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_zero_delays.3788053445 | Sep 11 09:17:48 PM UTC 24 | Sep 11 09:17:58 PM UTC 24 | 41961696 ps | ||
| T2766 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all.2547969508 | Sep 11 09:16:36 PM UTC 24 | Sep 11 09:18:10 PM UTC 24 | 983853008 ps | ||
| T2767 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_large_delays.4055883948 | Sep 11 09:17:00 PM UTC 24 | Sep 11 09:18:11 PM UTC 24 | 7546648043 ps | ||
| T2768 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_unmapped_addr.2062587392 | Sep 11 09:17:30 PM UTC 24 | Sep 11 09:18:12 PM UTC 24 | 299400102 ps | ||
| T2769 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.2310621965 | Sep 11 09:17:31 PM UTC 24 | Sep 11 09:18:16 PM UTC 24 | 304854877 ps | ||
| T2770 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_error.3763220019 | Sep 11 09:13:12 PM UTC 24 | Sep 11 09:18:27 PM UTC 24 | 11157486351 ps | ||
| T2771 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.610715816 | Sep 11 09:16:57 PM UTC 24 | Sep 11 09:18:41 PM UTC 24 | 6440328052 ps | ||
| T2772 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device.2095715728 | Sep 11 09:18:21 PM UTC 24 | Sep 11 09:18:43 PM UTC 24 | 164951855 ps | ||
| T2773 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all.1573409523 | Sep 11 09:14:30 PM UTC 24 | Sep 11 09:18:45 PM UTC 24 | 3047557040 ps | ||
| T2774 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.570593872 | Sep 11 09:15:42 PM UTC 24 | Sep 11 09:18:45 PM UTC 24 | 647377051 ps | ||
| T2775 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.2179521632 | Sep 11 09:11:57 PM UTC 24 | Sep 11 09:18:50 PM UTC 24 | 2198404923 ps | ||
| T2776 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.1835712850 | Sep 11 08:50:58 PM UTC 24 | Sep 11 09:18:54 PM UTC 24 | 106721529697 ps | ||
| T2777 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random.2259949444 | Sep 11 09:18:17 PM UTC 24 | Sep 11 09:18:55 PM UTC 24 | 288069858 ps | ||
| T2778 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.73814719 | Sep 11 09:18:36 PM UTC 24 | Sep 11 09:18:56 PM UTC 24 | 122705015 ps | ||
| T2779 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_zero_delays.3761242520 | Sep 11 09:18:15 PM UTC 24 | Sep 11 09:19:01 PM UTC 24 | 476598867 ps | ||
| T2780 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.3625034024 | Sep 11 09:17:26 PM UTC 24 | Sep 11 09:19:06 PM UTC 24 | 5820455135 ps | ||
| T2781 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_large_delays.1030377392 | Sep 11 09:18:04 PM UTC 24 | Sep 11 09:19:06 PM UTC 24 | 6632583407 ps | ||
| T2782 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_same_source.3170754703 | Sep 11 09:18:19 PM UTC 24 | Sep 11 09:19:08 PM UTC 24 | 494792570 ps | ||
| T2783 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_large_delays.2266126611 | Sep 11 09:15:08 PM UTC 24 | Sep 11 09:19:11 PM UTC 24 | 28334696846 ps | ||
| T2784 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_unmapped_addr.2553466924 | Sep 11 09:18:37 PM UTC 24 | Sep 11 09:19:12 PM UTC 24 | 929567430 ps | ||
| T2785 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_error.1947756200 | Sep 11 09:09:31 PM UTC 24 | Sep 11 09:19:15 PM UTC 24 | 17276941369 ps | ||
| T2786 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_zero_delays.3075988988 | Sep 11 09:19:06 PM UTC 24 | Sep 11 09:19:15 PM UTC 24 | 48903220 ps | ||
| T2787 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.1841297392 | Sep 11 09:17:43 PM UTC 24 | Sep 11 09:19:17 PM UTC 24 | 491211890 ps | ||
| T2788 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke.39201303 | Sep 11 09:19:09 PM UTC 24 | Sep 11 09:19:22 PM UTC 24 | 175576015 ps | ||
| T2789 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_slow_rsp.1552453069 | Sep 11 09:07:46 PM UTC 24 | Sep 11 09:19:25 PM UTC 24 | 52769428695 ps | ||
| T2790 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_zero_delays.2618219136 | Sep 11 09:19:20 PM UTC 24 | Sep 11 09:19:30 PM UTC 24 | 64141358 ps | ||
| T2791 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.335478648 | Sep 11 09:18:14 PM UTC 24 | Sep 11 09:19:30 PM UTC 24 | 3723735574 ps | ||
| T2792 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_error.3982950409 | Sep 11 09:10:58 PM UTC 24 | Sep 11 09:19:42 PM UTC 24 | 15985107078 ps | ||
| T2793 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all.1874376868 | Sep 11 09:17:38 PM UTC 24 | Sep 11 09:19:45 PM UTC 24 | 1570706215 ps | ||
| T2794 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.3870060466 | Sep 11 09:19:36 PM UTC 24 | Sep 11 09:19:50 PM UTC 24 | 149034214 ps | ||
| T2795 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.2621725786 | Sep 11 09:19:17 PM UTC 24 | Sep 11 09:20:06 PM UTC 24 | 3667646827 ps | ||
| T2796 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke.1296443375 | Sep 11 09:19:57 PM UTC 24 | Sep 11 09:20:11 PM UTC 24 | 215506874 ps | ||
| T2797 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_large_delays.3971711909 | Sep 11 09:19:14 PM UTC 24 | Sep 11 09:20:15 PM UTC 24 | 6211613447 ps | ||
| T2798 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_zero_delays.2936969509 | Sep 11 09:20:07 PM UTC 24 | Sep 11 09:20:17 PM UTC 24 | 52589098 ps | ||
| T2799 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random.1166362566 | Sep 11 09:19:19 PM UTC 24 | Sep 11 09:20:22 PM UTC 24 | 2099925952 ps | ||
| T2800 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_random.1054674440 | Sep 11 09:18:34 PM UTC 24 | Sep 11 09:20:26 PM UTC 24 | 2657268302 ps | ||
| T2801 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device.821970532 | Sep 11 09:19:32 PM UTC 24 | Sep 11 09:20:29 PM UTC 24 | 690372113 ps | ||
| T2802 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_unmapped_addr.2596001868 | Sep 11 09:19:40 PM UTC 24 | Sep 11 09:20:30 PM UTC 24 | 851643817 ps | ||
| T2803 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_same_source.2994121297 | Sep 11 09:19:37 PM UTC 24 | Sep 11 09:20:34 PM UTC 24 | 1332047492 ps | ||
| T2804 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_random.2151125273 | Sep 11 09:19:33 PM UTC 24 | Sep 11 09:20:42 PM UTC 24 | 1667731097 ps | ||
| T2805 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.3661009938 | Sep 11 08:45:22 PM UTC 24 | Sep 11 09:20:45 PM UTC 24 | 136242763656 ps | ||
| T2806 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.3099387176 | Sep 11 09:19:47 PM UTC 24 | Sep 11 09:20:51 PM UTC 24 | 64462210 ps | ||
| T2807 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_large_delays.3591653226 | Sep 11 09:10:02 PM UTC 24 | Sep 11 09:20:53 PM UTC 24 | 65380807746 ps | ||
| T2808 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_error.4276928346 | Sep 11 09:17:44 PM UTC 24 | Sep 11 09:20:53 PM UTC 24 | 5194617345 ps | ||
| T2809 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_zero_delays.384871333 | Sep 11 09:20:37 PM UTC 24 | Sep 11 09:20:56 PM UTC 24 | 139284211 ps | ||
| T2810 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.881665341 | Sep 11 08:58:35 PM UTC 24 | Sep 11 09:21:01 PM UTC 24 | 79885093225 ps | ||
| T2811 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_error.4132361188 | Sep 11 09:19:05 PM UTC 24 | Sep 11 09:21:02 PM UTC 24 | 3969411655 ps | ||
| T2812 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_random.3272544356 | Sep 11 09:20:53 PM UTC 24 | Sep 11 09:21:10 PM UTC 24 | 133848239 ps | ||
| T2813 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_unmapped_addr.727282417 | Sep 11 09:21:00 PM UTC 24 | Sep 11 09:21:13 PM UTC 24 | 139343503 ps | ||
| T2814 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.238234941 | Sep 11 09:20:17 PM UTC 24 | Sep 11 09:21:18 PM UTC 24 | 4020870482 ps | ||
| T2815 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device.1668928321 | Sep 11 09:20:48 PM UTC 24 | Sep 11 09:21:20 PM UTC 24 | 584716167 ps | ||
| T2816 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.3570301457 | Sep 11 09:08:21 PM UTC 24 | Sep 11 09:21:22 PM UTC 24 | 15031846138 ps | ||
| T2817 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.2299681394 | Sep 11 09:16:41 PM UTC 24 | Sep 11 09:21:23 PM UTC 24 | 709534684 ps | ||
| T2818 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_error.386356325 | Sep 11 09:19:50 PM UTC 24 | Sep 11 09:21:24 PM UTC 24 | 1096994794 ps | ||
| T2819 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.3527740824 | Sep 11 09:21:08 PM UTC 24 | Sep 11 09:21:24 PM UTC 24 | 313221161 ps | ||
| T2820 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke.18458835 | Sep 11 09:21:20 PM UTC 24 | Sep 11 09:21:28 PM UTC 24 | 55484666 ps | ||
| T2821 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_zero_delays.2512001542 | Sep 11 09:21:26 PM UTC 24 | Sep 11 09:21:35 PM UTC 24 | 42280189 ps | ||
| T2822 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_same_source.2151388068 | Sep 11 09:20:52 PM UTC 24 | Sep 11 09:21:44 PM UTC 24 | 1929690561 ps | ||
| T2823 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random.1199768048 | Sep 11 09:20:31 PM UTC 24 | Sep 11 09:21:45 PM UTC 24 | 2211966763 ps | ||
| T2824 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_large_delays.2424969736 | Sep 11 09:09:00 PM UTC 24 | Sep 11 09:21:45 PM UTC 24 | 77515206327 ps | ||
| T2825 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_error.2758827570 | Sep 11 09:15:36 PM UTC 24 | Sep 11 09:21:46 PM UTC 24 | 10154055456 ps | ||
| T2826 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_large_delays.2264295729 | Sep 11 09:20:12 PM UTC 24 | Sep 11 09:21:47 PM UTC 24 | 7468091246 ps | ||
| T2827 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.1708507393 | Sep 11 09:19:09 PM UTC 24 | Sep 11 09:21:50 PM UTC 24 | 1075311017 ps | ||
| T2828 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all.2186005060 | Sep 11 09:18:40 PM UTC 24 | Sep 11 09:21:59 PM UTC 24 | 5686688007 ps | ||
| T2829 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.207673115 | Sep 11 09:07:55 PM UTC 24 | Sep 11 09:21:59 PM UTC 24 | 52390411322 ps | ||
| T2830 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random.1881701663 | Sep 11 09:21:35 PM UTC 24 | Sep 11 09:22:04 PM UTC 24 | 330776537 ps | ||
| T2831 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_zero_delays.736698806 | Sep 11 09:21:42 PM UTC 24 | Sep 11 09:22:08 PM UTC 24 | 182585024 ps | ||
| T2832 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_random.1906938726 | Sep 11 09:21:53 PM UTC 24 | Sep 11 09:22:09 PM UTC 24 | 131797732 ps | ||
| T2833 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.3179974194 | Sep 11 09:22:05 PM UTC 24 | Sep 11 09:22:16 PM UTC 24 | 40605202 ps | ||
| T2834 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_large_delays.3324355945 | Sep 11 09:13:54 PM UTC 24 | Sep 11 09:22:16 PM UTC 24 | 52921830040 ps | ||
| T2835 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.2525732541 | Sep 11 09:19:54 PM UTC 24 | Sep 11 09:22:16 PM UTC 24 | 461173515 ps | ||
| T2836 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_unmapped_addr.1085617382 | Sep 11 09:22:01 PM UTC 24 | Sep 11 09:22:25 PM UTC 24 | 586432961 ps | ||
| T2837 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke.785688414 | Sep 11 09:22:14 PM UTC 24 | Sep 11 09:22:27 PM UTC 24 | 172006639 ps | ||
| T2838 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device.3954318497 | Sep 11 09:21:47 PM UTC 24 | Sep 11 09:22:28 PM UTC 24 | 577448281 ps | ||
| T2839 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.89408154 | Sep 11 09:22:10 PM UTC 24 | Sep 11 09:22:30 PM UTC 24 | 23639234 ps | ||
| T2840 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_zero_delays.2042912999 | Sep 11 09:22:24 PM UTC 24 | Sep 11 09:22:32 PM UTC 24 | 48693493 ps | ||
| T2841 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_zero_delays.1077922410 | Sep 11 09:22:32 PM UTC 24 | Sep 11 09:22:44 PM UTC 24 | 63535364 ps | ||
| T2842 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.2535133610 | Sep 11 09:15:38 PM UTC 24 | Sep 11 09:22:46 PM UTC 24 | 3487899354 ps | ||
| T2843 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_slow_rsp.3796365027 | Sep 11 09:17:22 PM UTC 24 | Sep 11 09:22:51 PM UTC 24 | 21066515284 ps | ||
| T2844 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random.4207573672 | Sep 11 09:22:33 PM UTC 24 | Sep 11 09:22:55 PM UTC 24 | 180171353 ps | ||
| T2845 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_large_delays.713488608 | Sep 11 09:04:36 PM UTC 24 | Sep 11 09:22:55 PM UTC 24 | 92533290757 ps | ||
| T2846 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.3635919521 | Sep 11 09:21:36 PM UTC 24 | Sep 11 09:22:59 PM UTC 24 | 4664488493 ps | ||
| T2847 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.627137334 | Sep 11 09:14:39 PM UTC 24 | Sep 11 09:23:02 PM UTC 24 | 7527832085 ps | ||
| T2848 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_same_source.1588849486 | Sep 11 09:21:47 PM UTC 24 | Sep 11 09:23:03 PM UTC 24 | 2568490414 ps | ||
| T2849 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.469613321 | Sep 11 09:11:41 PM UTC 24 | Sep 11 09:23:14 PM UTC 24 | 47761078692 ps | ||
| T2850 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_same_source.2510314624 | Sep 11 09:22:51 PM UTC 24 | Sep 11 09:23:18 PM UTC 24 | 853003963 ps | ||
| T2851 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.390403476 | Sep 11 09:22:57 PM UTC 24 | Sep 11 09:23:22 PM UTC 24 | 148219797 ps | ||
| T2852 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device.3971133244 | Sep 11 09:22:39 PM UTC 24 | Sep 11 09:23:23 PM UTC 24 | 1007609586 ps | ||
| T2853 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_unmapped_addr.2446511562 | Sep 11 09:22:52 PM UTC 24 | Sep 11 09:23:25 PM UTC 24 | 610144453 ps | ||
| T2854 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke.3577101261 | Sep 11 09:23:21 PM UTC 24 | Sep 11 09:23:29 PM UTC 24 | 146771123 ps | ||
| T2855 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_large_delays.646559715 | Sep 11 09:21:26 PM UTC 24 | Sep 11 09:23:29 PM UTC 24 | 9440836634 ps | ||
| T2856 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.448676898 | Sep 11 09:21:18 PM UTC 24 | Sep 11 09:23:31 PM UTC 24 | 279058411 ps | ||
| T2857 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_large_delays.43114970 | Sep 11 09:22:24 PM UTC 24 | Sep 11 09:23:33 PM UTC 24 | 5535158034 ps | ||
| T2858 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_zero_delays.3558551554 | Sep 11 09:23:25 PM UTC 24 | Sep 11 09:23:35 PM UTC 24 | 45330720 ps | ||
| T2859 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_large_delays.4238669051 | Sep 11 09:17:20 PM UTC 24 | Sep 11 09:23:53 PM UTC 24 | 33398508381 ps | ||
| T2860 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all.2818652940 | Sep 11 09:19:43 PM UTC 24 | Sep 11 09:24:01 PM UTC 24 | 5799631336 ps | ||
| T2861 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_random.1508876709 | Sep 11 09:22:51 PM UTC 24 | Sep 11 09:24:10 PM UTC 24 | 1879387534 ps | ||
| T2862 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random.1912896097 | Sep 11 09:23:38 PM UTC 24 | Sep 11 09:24:14 PM UTC 24 | 312447175 ps | ||
| T2863 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.285300926 | Sep 11 09:09:05 PM UTC 24 | Sep 11 09:24:17 PM UTC 24 | 58668640050 ps | ||
| T2864 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_error.3656996633 | Sep 11 09:23:15 PM UTC 24 | Sep 11 09:24:19 PM UTC 24 | 2603185320 ps | ||
| T2865 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_error.1642008341 | Sep 11 09:21:19 PM UTC 24 | Sep 11 09:24:21 PM UTC 24 | 2814166956 ps | ||
| T2866 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_zero_delays.3589527693 | Sep 11 09:23:44 PM UTC 24 | Sep 11 09:24:22 PM UTC 24 | 313251688 ps | ||
| T2867 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.1203917453 | Sep 11 09:12:52 PM UTC 24 | Sep 11 09:24:26 PM UTC 24 | 46407378083 ps | ||
| T2868 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.538063209 | Sep 11 09:22:29 PM UTC 24 | Sep 11 09:24:29 PM UTC 24 | 5970145958 ps | ||
| T2869 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.1630366173 | Sep 11 09:24:01 PM UTC 24 | Sep 11 09:24:29 PM UTC 24 | 689150324 ps | ||
| T2870 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_unmapped_addr.2578387846 | Sep 11 09:23:58 PM UTC 24 | Sep 11 09:24:31 PM UTC 24 | 267912929 ps | ||
| T2871 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.849941811 | Sep 11 09:23:54 PM UTC 24 | Sep 11 09:24:39 PM UTC 24 | 2602010015 ps | ||
| T2872 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_random.253191130 | Sep 11 09:23:57 PM UTC 24 | Sep 11 09:24:39 PM UTC 24 | 994589091 ps | ||
| T2873 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_slow_rsp.3242116380 | Sep 11 09:22:40 PM UTC 24 | Sep 11 09:24:42 PM UTC 24 | 7797947588 ps | ||
| T2874 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_slow_rsp.1874510530 | Sep 11 09:18:19 PM UTC 24 | Sep 11 09:24:48 PM UTC 24 | 23456311523 ps | ||
| T2875 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.265668704 | Sep 11 09:21:48 PM UTC 24 | Sep 11 09:24:50 PM UTC 24 | 13218343797 ps | ||
| T2876 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_error.260592281 | Sep 11 09:16:44 PM UTC 24 | Sep 11 09:24:51 PM UTC 24 | 14345128863 ps | ||
| T2877 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_large_delays.1237729895 | Sep 11 09:23:28 PM UTC 24 | Sep 11 09:24:58 PM UTC 24 | 7243614243 ps | ||
| T2878 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device.358421117 | Sep 11 09:23:51 PM UTC 24 | Sep 11 09:24:59 PM UTC 24 | 709162174 ps | ||
| T2879 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.274129347 | Sep 11 09:23:26 PM UTC 24 | Sep 11 09:25:03 PM UTC 24 | 4956326803 ps | ||
| T2880 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_large_delays.131819473 | Sep 11 09:11:30 PM UTC 24 | Sep 11 09:25:04 PM UTC 24 | 70342716367 ps | ||
| T2881 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_same_source.1969420375 | Sep 11 09:23:54 PM UTC 24 | Sep 11 09:25:13 PM UTC 24 | 2040422598 ps | ||
| T2882 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all.122888863 | Sep 11 09:23:11 PM UTC 24 | Sep 11 09:25:21 PM UTC 24 | 3796651768 ps | ||
| T2883 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.2715101066 | Sep 11 09:21:19 PM UTC 24 | Sep 11 09:25:28 PM UTC 24 | 1277750372 ps | ||
| T2884 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.2796600862 | Sep 11 09:23:10 PM UTC 24 | Sep 11 09:25:28 PM UTC 24 | 123678515 ps | ||
| T2885 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.3673045917 | Sep 11 09:15:21 PM UTC 24 | Sep 11 09:25:32 PM UTC 24 | 43547570714 ps | ||
| T2886 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_slow_rsp.3839046165 | Sep 11 09:10:07 PM UTC 24 | Sep 11 09:25:51 PM UTC 24 | 69211098899 ps | ||
| T2887 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.1579885339 | Sep 11 09:14:04 PM UTC 24 | Sep 11 09:26:09 PM UTC 24 | 47642789546 ps | ||
| T2888 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_slow_rsp.2024995480 | Sep 11 09:12:47 PM UTC 24 | Sep 11 09:26:23 PM UTC 24 | 55986432630 ps | ||
| T2889 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all.903601532 | Sep 11 09:22:08 PM UTC 24 | Sep 11 09:26:25 PM UTC 24 | 6899324181 ps | ||
| T2890 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_slow_rsp.2988394681 | Sep 11 09:09:00 PM UTC 24 | Sep 11 09:26:38 PM UTC 24 | 64006507572 ps | ||
| T2891 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all.2730647012 | Sep 11 09:21:11 PM UTC 24 | Sep 11 09:26:42 PM UTC 24 | 4113538967 ps | ||
| T2892 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_error.1361686592 | Sep 11 09:24:34 PM UTC 24 | Sep 11 09:26:57 PM UTC 24 | 4850901585 ps | ||
| T2893 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.1887377454 | Sep 11 09:16:49 PM UTC 24 | Sep 11 09:27:11 PM UTC 24 | 7088604365 ps | ||
| T2894 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.1772047813 | Sep 11 09:24:40 PM UTC 24 | Sep 11 09:27:19 PM UTC 24 | 603058625 ps | ||
| T2895 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.2170656945 | Sep 11 09:24:27 PM UTC 24 | Sep 11 09:27:24 PM UTC 24 | 758140635 ps | ||
| T2896 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.2127709104 | Sep 11 09:18:52 PM UTC 24 | Sep 11 09:27:27 PM UTC 24 | 4495649734 ps | ||
| T2897 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_slow_rsp.345898190 | Sep 11 09:20:44 PM UTC 24 | Sep 11 09:27:29 PM UTC 24 | 25740010763 ps | ||
| T2898 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_error.2348619552 | Sep 11 09:22:09 PM UTC 24 | Sep 11 09:28:00 PM UTC 24 | 12125854169 ps | ||
| T2899 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all.2825593695 | Sep 11 09:24:16 PM UTC 24 | Sep 11 09:28:01 PM UTC 24 | 7152947010 ps | ||
| T2900 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.4033994818 | Sep 11 09:23:18 PM UTC 24 | Sep 11 09:28:04 PM UTC 24 | 3856068942 ps | ||
| T2901 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_slow_rsp.223601890 | Sep 11 09:15:07 PM UTC 24 | Sep 11 09:28:04 PM UTC 24 | 46526852028 ps | ||
| T2902 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.2494723955 | Sep 11 09:17:39 PM UTC 24 | Sep 11 09:28:22 PM UTC 24 | 5479987847 ps | ||
| T2903 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_slow_rsp.4073645892 | Sep 11 09:11:36 PM UTC 24 | Sep 11 09:28:32 PM UTC 24 | 67082195431 ps | ||
| T2904 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2135902609 | Sep 11 09:10:17 PM UTC 24 | Sep 11 09:28:35 PM UTC 24 | 63978894665 ps | ||
| T2905 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_slow_rsp.685450174 | Sep 11 09:19:28 PM UTC 24 | Sep 11 09:28:47 PM UTC 24 | 36772088888 ps | ||
| T2906 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_large_delays.1931355675 | Sep 11 09:18:16 PM UTC 24 | Sep 11 09:29:00 PM UTC 24 | 71775484917 ps | ||
| T2907 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_large_delays.1862941141 | Sep 11 09:23:48 PM UTC 24 | Sep 11 09:29:37 PM UTC 24 | 40372976776 ps | ||
| T2908 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.427920833 | Sep 11 09:03:39 PM UTC 24 | Sep 11 09:30:02 PM UTC 24 | 94773516528 ps | ||
| T2909 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.2075392336 | Sep 11 09:06:57 PM UTC 24 | Sep 11 09:30:09 PM UTC 24 | 92050217636 ps | ||
| T2910 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_large_delays.1859575286 | Sep 11 09:19:25 PM UTC 24 | Sep 11 09:30:30 PM UTC 24 | 63680597812 ps | ||
| T2911 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_large_delays.2860079366 | Sep 11 09:12:46 PM UTC 24 | Sep 11 09:30:41 PM UTC 24 | 99872548803 ps | ||
| T2912 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.1754905376 | Sep 11 09:02:17 PM UTC 24 | Sep 11 09:30:59 PM UTC 24 | 118090461344 ps | ||
| T2913 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_large_delays.996397172 | Sep 11 09:20:41 PM UTC 24 | Sep 11 09:31:58 PM UTC 24 | 73261430297 ps | ||
| T2914 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_slow_rsp.3036813014 | Sep 11 09:16:17 PM UTC 24 | Sep 11 09:32:51 PM UTC 24 | 67810330064 ps | ||
| T2915 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.3984699048 | Sep 11 09:22:50 PM UTC 24 | Sep 11 09:33:37 PM UTC 24 | 47975541696 ps | ||
| T2916 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.3657562783 | Sep 11 09:05:46 PM UTC 24 | Sep 11 09:34:37 PM UTC 24 | 121297358408 ps | ||
| T2917 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_slow_rsp.3213089837 | Sep 11 09:23:48 PM UTC 24 | Sep 11 09:34:40 PM UTC 24 | 48544279793 ps | ||
| T2918 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.1226458652 | Sep 11 09:00:17 PM UTC 24 | Sep 11 09:36:45 PM UTC 24 | 151070846725 ps | ||
| T450 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_aliasing.1722032698 | Sep 11 06:58:03 PM UTC 24 | Sep 11 09:37:12 PM UTC 24 | 55834085575 ps | ||
| T2919 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_large_delays.4029779021 | Sep 11 09:21:45 PM UTC 24 | Sep 11 09:37:39 PM UTC 24 | 91108682207 ps | ||
| T2920 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_large_delays.1574804867 | Sep 11 09:22:41 PM UTC 24 | Sep 11 09:37:51 PM UTC 24 | 84784262583 ps | ||
| T2921 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_slow_rsp.1775869953 | Sep 11 09:21:49 PM UTC 24 | Sep 11 09:37:54 PM UTC 24 | 69205775535 ps | ||
| T2922 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.4072771040 | Sep 11 09:22:07 PM UTC 24 | Sep 11 09:42:51 PM UTC 24 | 11319108407 ps | ||
| T2923 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.130183481 | Sep 11 09:20:49 PM UTC 24 | Sep 11 09:43:56 PM UTC 24 | 102850234631 ps | ||
| T2924 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.1053586776 | Sep 11 09:18:21 PM UTC 24 | Sep 11 09:49:24 PM UTC 24 | 128253093276 ps | ||
| T2925 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.2322530137 | Sep 11 09:19:31 PM UTC 24 | Sep 11 09:54:05 PM UTC 24 | 148357529329 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1283026468 | Sep 11 09:24:55 PM UTC 24 | Sep 11 09:27:40 PM UTC 24 | 5085686350 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.42490000 | Sep 11 09:24:50 PM UTC 24 | Sep 11 09:27:55 PM UTC 24 | 5295506305 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2345014238 | Sep 11 09:24:42 PM UTC 24 | Sep 11 09:28:06 PM UTC 24 | 4881879860 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.100060340 | Sep 11 09:24:47 PM UTC 24 | Sep 11 09:28:09 PM UTC 24 | 4997991016 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2946204658 | Sep 11 09:25:02 PM UTC 24 | Sep 11 09:28:17 PM UTC 24 | 4231784376 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1878718164 | Sep 11 09:25:04 PM UTC 24 | Sep 11 09:28:18 PM UTC 24 | 4245700670 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3471829689 | Sep 11 09:24:46 PM UTC 24 | Sep 11 09:28:19 PM UTC 24 | 5407608600 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2106207182 | Sep 11 09:24:50 PM UTC 24 | Sep 11 09:28:23 PM UTC 24 | 5726491072 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1636856402 | Sep 11 09:24:40 PM UTC 24 | Sep 11 09:28:59 PM UTC 24 | 4742693332 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1551862841 | Sep 11 09:24:49 PM UTC 24 | Sep 11 09:29:11 PM UTC 24 | 5281001280 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1781572244 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 2652782683 ps |
| CPU time | 280.55 seconds |
| Started | Sep 11 09:30:06 PM UTC 24 |
| Finished | Sep 11 09:34:51 PM UTC 24 |
| Peak memory | 623716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781572244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_ mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.1781572244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.512150406 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 5004618816 ps |
| CPU time | 284.36 seconds |
| Started | Sep 11 06:55:35 PM UTC 24 |
| Finished | Sep 11 07:00:23 PM UTC 24 |
| Peak memory | 618968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512150406 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.512150406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.3887826325 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 5132713280 ps |
| CPU time | 787.83 seconds |
| Started | Sep 11 10:01:34 PM UTC 24 |
| Finished | Sep 11 10:14:53 PM UTC 24 |
| Peak memory | 623688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3887826325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_plic_all_irqs_20.3887826325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_plic_all_irqs_20/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.3247871316 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 207944669 ps |
| CPU time | 18.38 seconds |
| Started | Sep 11 06:54:20 PM UTC 24 |
| Finished | Sep 11 06:54:39 PM UTC 24 |
| Peak memory | 596080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247871316 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3247871316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2260427374 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 112911056069 ps |
| CPU time | 1919.23 seconds |
| Started | Sep 11 06:56:37 PM UTC 24 |
| Finished | Sep 11 07:28:58 PM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260427374 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.2260427374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.583267982 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3390323544 ps |
| CPU time | 198.39 seconds |
| Started | Sep 11 09:30:04 PM UTC 24 |
| Finished | Sep 11 09:33:26 PM UTC 24 |
| Peak memory | 623760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=583267982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_sleep_pin_retention.583267982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1283026468 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 5085686350 ps |
| CPU time | 162.8 seconds |
| Started | Sep 11 09:24:55 PM UTC 24 |
| Finished | Sep 11 09:27:40 PM UTC 24 |
| Peak memory | 656280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283026 468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 7.chip_ padctrl_attributes.1283026468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.4112176769 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 15627519799 ps |
| CPU time | 745.4 seconds |
| Started | Sep 11 07:11:33 PM UTC 24 |
| Finished | Sep 11 07:24:07 PM UTC 24 |
| Peak memory | 598000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112176769 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.4112176769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.3687488481 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 3193557294 ps |
| CPU time | 315.7 seconds |
| Started | Sep 11 09:47:17 PM UTC 24 |
| Finished | Sep 11 09:52:38 PM UTC 24 |
| Peak memory | 625760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand om_seed=3687488481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aler t_test.3687488481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.4173762030 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 11269970221 ps |
| CPU time | 343.56 seconds |
| Started | Sep 11 06:54:18 PM UTC 24 |
| Finished | Sep 11 07:00:07 PM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173762030 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.4173762030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.164421787 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4073050748 ps |
| CPU time | 374.99 seconds |
| Started | Sep 11 09:32:16 PM UTC 24 |
| Finished | Sep 11 09:38:37 PM UTC 24 |
| Peak memory | 625812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164421787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctr l_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.164421787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.695053339 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 119877033135 ps |
| CPU time | 1847.04 seconds |
| Started | Sep 11 07:20:35 PM UTC 24 |
| Finished | Sep 11 07:51:44 PM UTC 24 |
| Peak memory | 595984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695053339 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.695053339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.2200271642 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 6136086568 ps |
| CPU time | 1045.3 seconds |
| Started | Sep 11 10:00:45 PM UTC 24 |
| Finished | Sep 11 10:18:25 PM UTC 24 |
| Peak memory | 623712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200271642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch ip_plic_all_irqs_0.2200271642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_plic_all_irqs_0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.29869044 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 67651754423 ps |
| CPU time | 1012.16 seconds |
| Started | Sep 11 06:54:21 PM UTC 24 |
| Finished | Sep 11 07:11:26 PM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29869044 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.29869044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.691726643 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 7892454532 ps |
| CPU time | 824.21 seconds |
| Started | Sep 11 09:38:46 PM UTC 24 |
| Finished | Sep 11 09:52:42 PM UTC 24 |
| Peak memory | 640196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691726643 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.691726643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.1797383309 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5599802498 ps |
| CPU time | 1369.68 seconds |
| Started | Sep 11 10:23:03 PM UTC 24 |
| Finished | Sep 11 10:46:11 PM UTC 24 |
| Peak memory | 640524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_tim eout_ns=400_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_ img_rma:4,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797383309 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_virus.1797383309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.2097245910 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 3444689029 ps |
| CPU time | 201.24 seconds |
| Started | Sep 11 06:54:12 PM UTC 24 |
| Finished | Sep 11 06:57:37 PM UTC 24 |
| Peak memory | 621216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097245910 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.2097245910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1017472773 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 3614618380 ps |
| CPU time | 348.43 seconds |
| Started | Sep 11 10:14:16 PM UTC 24 |
| Finished | Sep 11 10:20:10 PM UTC 24 |
| Peak memory | 623468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_im ages=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017472773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.1017472773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.4226277865 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 5485624528 ps |
| CPU time | 646.77 seconds |
| Started | Sep 11 09:34:34 PM UTC 24 |
| Finished | Sep 11 09:45:30 PM UTC 24 |
| Peak memory | 625700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226277865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ct rl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.4226277865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.1491956849 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 10818663688 ps |
| CPU time | 2354.89 seconds |
| Started | Sep 11 09:56:06 PM UTC 24 |
| Finished | Sep 11 10:35:51 PM UTC 24 |
| Peak memory | 625844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491956849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sidel oad_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.1491956849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1748706919 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 129492744805 ps |
| CPU time | 1720.13 seconds |
| Started | Sep 11 06:55:05 PM UTC 24 |
| Finished | Sep 11 07:24:04 PM UTC 24 |
| Peak memory | 595872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748706919 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.1748706919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.3781620137 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 2597653557 ps |
| CPU time | 141.17 seconds |
| Started | Sep 11 07:18:04 PM UTC 24 |
| Finished | Sep 11 07:20:28 PM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781620137 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3781620137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.1366195712 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 6006121102 ps |
| CPU time | 341.36 seconds |
| Started | Sep 11 06:54:30 PM UTC 24 |
| Finished | Sep 11 07:00:16 PM UTC 24 |
| Peak memory | 680460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366195712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_reset.1366195712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3775146263 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 7652745364 ps |
| CPU time | 343.69 seconds |
| Started | Sep 11 10:10:23 PM UTC 24 |
| Finished | Sep 11 10:16:12 PM UTC 24 |
| Peak memory | 625848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_w ake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3775146263 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3775146263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.2188544417 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2444118708 ps |
| CPU time | 89.67 seconds |
| Started | Sep 11 06:54:16 PM UTC 24 |
| Finished | Sep 11 06:55:48 PM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188544417 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.2188544417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.3810777602 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 6097916820 ps |
| CPU time | 985.27 seconds |
| Started | Sep 11 09:53:37 PM UTC 24 |
| Finished | Sep 11 10:10:15 PM UTC 24 |
| Peak memory | 625916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810777602 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.3810777602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.1546053946 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 11539802186 ps |
| CPU time | 1632.87 seconds |
| Started | Sep 11 10:41:53 PM UTC 24 |
| Finished | Sep 11 11:09:28 PM UTC 24 |
| Peak memory | 636180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_devic e=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546053946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jta g_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.1546053946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.424449473 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 1396005153 ps |
| CPU time | 83.64 seconds |
| Started | Sep 11 07:30:19 PM UTC 24 |
| Finished | Sep 11 07:31:45 PM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424449473 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.424449473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.920048987 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 10267843560 ps |
| CPU time | 1101.34 seconds |
| Started | Sep 11 09:49:49 PM UTC 24 |
| Finished | Sep 11 10:08:25 PM UTC 24 |
| Peak memory | 625864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920048987 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handl er_lpg_sleep_mode_pings.920048987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.4209716478 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 4188817762 ps |
| CPU time | 542.13 seconds |
| Started | Sep 11 10:01:33 PM UTC 24 |
| Finished | Sep 11 10:10:43 PM UTC 24 |
| Peak memory | 623652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4209716478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_plic_all_irqs_10.4209716478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_plic_all_irqs_10/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.879232803 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 123604038595 ps |
| CPU time | 1714.41 seconds |
| Started | Sep 11 08:00:15 PM UTC 24 |
| Finished | Sep 11 08:29:10 PM UTC 24 |
| Peak memory | 599152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879232803 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.879232803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.1956561234 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 44099056126 ps |
| CPU time | 5793.66 seconds |
| Started | Sep 11 09:31:23 PM UTC 24 |
| Finished | Sep 11 11:09:09 PM UTC 24 |
| Peak memory | 639084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw _build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956561234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip _earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.1956561234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.1263850415 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 6464658435 ps |
| CPU time | 65.53 seconds |
| Started | Sep 11 06:54:14 PM UTC 24 |
| Finished | Sep 11 06:55:22 PM UTC 24 |
| Peak memory | 593704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263850415 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1263850415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.2362526763 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 706848211 ps |
| CPU time | 56.32 seconds |
| Started | Sep 11 06:57:28 PM UTC 24 |
| Finished | Sep 11 06:58:26 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362526763 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.2362526763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.497137990 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 4165690796 ps |
| CPU time | 533.29 seconds |
| Started | Sep 11 09:32:37 PM UTC 24 |
| Finished | Sep 11 09:41:38 PM UTC 24 |
| Peak memory | 623776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=497137990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_gpio.497137990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_gpio/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2085873565 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 14724460599 ps |
| CPU time | 3901.19 seconds |
| Started | Sep 11 10:28:27 PM UTC 24 |
| Finished | Sep 11 11:34:16 PM UTC 24 |
| Peak memory | 623780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mas k_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2085873565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2085873565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.880467334 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 5492283720 ps |
| CPU time | 419.17 seconds |
| Started | Sep 11 07:22:46 PM UTC 24 |
| Finished | Sep 11 07:29:51 PM UTC 24 |
| Peak memory | 621080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880467334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.880467334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3931975711 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3367620270 ps |
| CPU time | 227.51 seconds |
| Started | Sep 11 09:35:51 PM UTC 24 |
| Finished | Sep 11 09:39:42 PM UTC 24 |
| Peak memory | 635968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931975711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.3931975711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.40590997 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3274968550 ps |
| CPU time | 252.55 seconds |
| Started | Sep 11 11:29:16 PM UTC 24 |
| Finished | Sep 11 11:33:33 PM UTC 24 |
| Peak memory | 623892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40590997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mi o_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.40590997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.666332940 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 6153497899 ps |
| CPU time | 582.21 seconds |
| Started | Sep 11 06:59:27 PM UTC 24 |
| Finished | Sep 11 07:09:17 PM UTC 24 |
| Peak memory | 614808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666332940 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.666332940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3951982559 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 5373198360 ps |
| CPU time | 487.69 seconds |
| Started | Sep 11 10:00:26 PM UTC 24 |
| Finished | Sep 11 10:08:41 PM UTC 24 |
| Peak memory | 625716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_im ages=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951982559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3951982559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1050503855 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 148539197177 ps |
| CPU time | 2059.41 seconds |
| Started | Sep 11 07:24:12 PM UTC 24 |
| Finished | Sep 11 07:58:55 PM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050503855 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.1050503855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3850556010 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 4220185546 ps |
| CPU time | 602.88 seconds |
| Started | Sep 11 09:45:58 PM UTC 24 |
| Finished | Sep 11 09:56:11 PM UTC 24 |
| Peak memory | 630100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3850556010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_sysrst_ctrl_in_irq.3850556010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.1252870796 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 6330063830 ps |
| CPU time | 607.84 seconds |
| Started | Sep 11 09:32:11 PM UTC 24 |
| Finished | Sep 11 09:42:27 PM UTC 24 |
| Peak memory | 625864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252870796 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.1252870796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1973258759 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 2345746478 ps |
| CPU time | 236.16 seconds |
| Started | Sep 12 12:51:05 AM UTC 24 |
| Finished | Sep 12 12:55:05 AM UTC 24 |
| Peak memory | 623544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973258759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_ mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.1973258759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.2331805300 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 2509775060 ps |
| CPU time | 246.33 seconds |
| Started | Sep 11 09:32:23 PM UTC 24 |
| Finished | Sep 11 09:36:34 PM UTC 24 |
| Peak memory | 623584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331805300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 0.chip_sw_spi_host_tx_rx.2331805300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.128718841 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 6418661459 ps |
| CPU time | 407.05 seconds |
| Started | Sep 11 06:55:31 PM UTC 24 |
| Finished | Sep 11 07:02:24 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128718841 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.128718841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2378996421 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 5658077896 ps |
| CPU time | 703.9 seconds |
| Started | Sep 11 09:52:50 PM UTC 24 |
| Finished | Sep 11 10:04:44 PM UTC 24 |
| Peak memory | 625896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_ otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378996421 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_lc_hw_debug_en_test.2378996421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.3689397848 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1947969629 ps |
| CPU time | 54.52 seconds |
| Started | Sep 11 06:54:19 PM UTC 24 |
| Finished | Sep 11 06:55:15 PM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689397848 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.3689397848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.929698112 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 4730005658 ps |
| CPU time | 382.54 seconds |
| Started | Sep 11 07:17:01 PM UTC 24 |
| Finished | Sep 11 07:23:29 PM UTC 24 |
| Peak memory | 621200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929698112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.929698112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.622577658 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 5023831076 ps |
| CPU time | 727.96 seconds |
| Started | Sep 11 09:38:59 PM UTC 24 |
| Finished | Sep 11 09:51:18 PM UTC 24 |
| Peak memory | 625816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622577658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_rstmgr_cpu_info.622577658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.1356024981 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3188862329 ps |
| CPU time | 257.24 seconds |
| Started | Sep 11 09:32:24 PM UTC 24 |
| Finished | Sep 11 09:36:45 PM UTC 24 |
| Peak memory | 636360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1356024981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_device_pinmux_sleep_retention.1356024981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1551862841 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 5281001280 ps |
| CPU time | 257.24 seconds |
| Started | Sep 11 09:24:49 PM UTC 24 |
| Finished | Sep 11 09:29:11 PM UTC 24 |
| Peak memory | 672356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551862 841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 5.chip_ padctrl_attributes.1551862841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.1726367602 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 4125682720 ps |
| CPU time | 525.1 seconds |
| Started | Sep 11 07:41:39 PM UTC 24 |
| Finished | Sep 11 07:50:31 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726367602 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.1726367602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.3553695702 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 5570163056 ps |
| CPU time | 679.5 seconds |
| Started | Sep 12 02:57:19 AM UTC 24 |
| Finished | Sep 12 03:08:48 AM UTC 24 |
| Peak memory | 674284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553695702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.3553695702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.2334469498 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 3862035436 ps |
| CPU time | 307.94 seconds |
| Started | Sep 11 10:13:15 PM UTC 24 |
| Finished | Sep 11 10:18:28 PM UTC 24 |
| Peak memory | 650548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334469498 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.2334469498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.4093263664 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 6358124110 ps |
| CPU time | 1632.89 seconds |
| Started | Sep 11 09:51:16 PM UTC 24 |
| Finished | Sep 11 10:18:51 PM UTC 24 |
| Peak memory | 625980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_ device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093263664 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_auto_mode.4093263664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.4152327838 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 4316535964 ps |
| CPU time | 381.07 seconds |
| Started | Sep 11 09:49:48 PM UTC 24 |
| Finished | Sep 11 09:56:15 PM UTC 24 |
| Peak memory | 672520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152327838 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_s leep_mode_alerts.4152327838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.2440816116 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 6278085170 ps |
| CPU time | 711.71 seconds |
| Started | Sep 12 02:58:45 AM UTC 24 |
| Finished | Sep 12 03:10:47 AM UTC 24 |
| Peak memory | 674296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440816116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.2440816116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.437025010 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 5496627882 ps |
| CPU time | 697.34 seconds |
| Started | Sep 12 03:03:31 AM UTC 24 |
| Finished | Sep 12 03:15:18 AM UTC 24 |
| Peak memory | 674540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437025010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.437025010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.2832388437 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3152673496 ps |
| CPU time | 310.13 seconds |
| Started | Sep 11 09:31:15 PM UTC 24 |
| Finished | Sep 11 09:36:30 PM UTC 24 |
| Peak memory | 625708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832388437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.2832388437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.3258667480 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3761094736 ps |
| CPU time | 534.51 seconds |
| Started | Sep 11 09:32:21 PM UTC 24 |
| Finished | Sep 11 09:41:23 PM UTC 24 |
| Peak memory | 623656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258667480 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.3258667480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.2629828455 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 6180917404 ps |
| CPU time | 1129.16 seconds |
| Started | Sep 12 01:52:39 AM UTC 24 |
| Finished | Sep 12 02:11:43 AM UTC 24 |
| Peak memory | 625576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629828455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_plic_all_irqs_0.2629828455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_plic_all_irqs_0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.4149775989 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 49861923456 ps |
| CPU time | 5908.32 seconds |
| Started | Sep 11 09:38:42 PM UTC 24 |
| Finished | Sep 11 11:18:22 PM UTC 24 |
| Peak memory | 643332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149775989 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_dev.4149775989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2675738373 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 5214367617 ps |
| CPU time | 518.76 seconds |
| Started | Sep 11 09:58:19 PM UTC 24 |
| Finished | Sep 11 10:07:05 PM UTC 24 |
| Peak memory | 625848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_ch eck=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675738373 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ct rl_scrambled_access_jitter_en.2675738373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.3051492675 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 4877561320 ps |
| CPU time | 415.02 seconds |
| Started | Sep 11 07:19:23 PM UTC 24 |
| Finished | Sep 11 07:26:24 PM UTC 24 |
| Peak memory | 620956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051492675 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.3051492675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.3106691904 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 11968744280 ps |
| CPU time | 1585.96 seconds |
| Started | Sep 11 09:39:27 PM UTC 24 |
| Finished | Sep 11 10:06:13 PM UTC 24 |
| Peak memory | 625776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_buil d_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106691904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.3106691904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.1600988141 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 8388332502 ps |
| CPU time | 841.16 seconds |
| Started | Sep 12 02:27:42 AM UTC 24 |
| Finished | Sep 12 02:41:55 AM UTC 24 |
| Peak memory | 625708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600988141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.1600988141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.3159432943 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2724903668 ps |
| CPU time | 306.15 seconds |
| Started | Sep 12 12:51:52 AM UTC 24 |
| Finished | Sep 12 12:57:03 AM UTC 24 |
| Peak memory | 625716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159432943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.3159432943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.3148179812 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 7350388818 ps |
| CPU time | 372.09 seconds |
| Started | Sep 11 07:02:04 PM UTC 24 |
| Finished | Sep 11 07:08:21 PM UTC 24 |
| Peak memory | 680212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148179812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_reset.3148179812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.2449390502 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 13425404287 ps |
| CPU time | 459.32 seconds |
| Started | Sep 11 06:59:02 PM UTC 24 |
| Finished | Sep 11 07:06:48 PM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449390502 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2449390502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.3400509104 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 3904215232 ps |
| CPU time | 545.56 seconds |
| Started | Sep 11 09:31:40 PM UTC 24 |
| Finished | Sep 11 09:40:53 PM UTC 24 |
| Peak memory | 640072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400509104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.3400509104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1856563102 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 94105247401 ps |
| CPU time | 1405.38 seconds |
| Started | Sep 11 07:51:02 PM UTC 24 |
| Finished | Sep 11 08:14:43 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856563102 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.1856563102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.955689773 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 12767332638 ps |
| CPU time | 700.25 seconds |
| Started | Sep 11 08:02:16 PM UTC 24 |
| Finished | Sep 11 08:14:05 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955689773 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.955689773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.3141507886 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 15150653203 ps |
| CPU time | 807.04 seconds |
| Started | Sep 11 07:01:52 PM UTC 24 |
| Finished | Sep 11 07:15:30 PM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141507886 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.3141507886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.140309784 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 3534996497 ps |
| CPU time | 299.31 seconds |
| Started | Sep 11 09:31:10 PM UTC 24 |
| Finished | Sep 11 09:36:14 PM UTC 24 |
| Peak memory | 636192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=140309784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.140309784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.2546885324 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 4484476150 ps |
| CPU time | 226.92 seconds |
| Started | Sep 11 06:57:50 PM UTC 24 |
| Finished | Sep 11 07:01:40 PM UTC 24 |
| Peak memory | 680540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546885324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_reset.2546885324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.1649822716 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 6574196152 ps |
| CPU time | 1161.03 seconds |
| Started | Sep 12 12:17:46 AM UTC 24 |
| Finished | Sep 12 12:37:22 AM UTC 24 |
| Peak memory | 623672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649822716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_plic_all_irqs_0.1649822716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_plic_all_irqs_0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.2836972864 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 22067534720 ps |
| CPU time | 2240.12 seconds |
| Started | Sep 11 10:18:35 PM UTC 24 |
| Finished | Sep 11 10:56:25 PM UTC 24 |
| Peak memory | 625836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_buil d_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836972864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.2836972864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2068355745 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 8489702027 ps |
| CPU time | 967.75 seconds |
| Started | Sep 11 09:31:38 PM UTC 24 |
| Finished | Sep 11 09:47:59 PM UTC 24 |
| Peak memory | 636160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068355745 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2068355745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.117737461 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5950193050 ps |
| CPU time | 466 seconds |
| Started | Sep 11 09:43:20 PM UTC 24 |
| Finished | Sep 11 09:51:13 PM UTC 24 |
| Peak memory | 625712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=117737461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.117737461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.4044148889 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 5754261916 ps |
| CPU time | 623.14 seconds |
| Started | Sep 11 07:53:58 PM UTC 24 |
| Finished | Sep 11 08:04:29 PM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044148889 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.4044148889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.639173730 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 18044948002 ps |
| CPU time | 1756.45 seconds |
| Started | Sep 11 07:11:59 PM UTC 24 |
| Finished | Sep 11 07:41:36 PM UTC 24 |
| Peak memory | 610884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=639173730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 9.chip_same_csr_outstanding.639173730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.2566653238 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 12379285375 ps |
| CPU time | 442.7 seconds |
| Started | Sep 11 07:13:12 PM UTC 24 |
| Finished | Sep 11 07:20:41 PM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566653238 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2566653238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.1831724536 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 3961833808 ps |
| CPU time | 321.19 seconds |
| Started | Sep 11 11:29:21 PM UTC 24 |
| Finished | Sep 11 11:34:47 PM UTC 24 |
| Peak memory | 623588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1831724536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_sleep_pin_retention.1831724536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.1066043934 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 6727287220 ps |
| CPU time | 646.01 seconds |
| Started | Sep 12 03:27:28 AM UTC 24 |
| Finished | Sep 12 03:38:23 AM UTC 24 |
| Peak memory | 674468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066043934 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.1066043934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.2372175547 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 4878384048 ps |
| CPU time | 434.48 seconds |
| Started | Sep 11 10:12:01 PM UTC 24 |
| Finished | Sep 11 10:19:22 PM UTC 24 |
| Peak memory | 635836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372175547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_ reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.2372175547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.3150557288 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 42985386404 ps |
| CPU time | 5930.12 seconds |
| Started | Sep 11 11:40:53 PM UTC 24 |
| Finished | Sep 12 01:20:59 AM UTC 24 |
| Peak memory | 639332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw _build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150557288 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip _earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.3150557288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.2760209069 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 5177243096 ps |
| CPU time | 870.12 seconds |
| Started | Sep 11 09:59:39 PM UTC 24 |
| Finished | Sep 11 10:14:21 PM UTC 24 |
| Peak memory | 625772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760209069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.2760209069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.1724398764 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 3329591800 ps |
| CPU time | 445.28 seconds |
| Started | Sep 12 12:17:38 AM UTC 24 |
| Finished | Sep 12 12:25:10 AM UTC 24 |
| Peak memory | 625820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724398764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.1724398764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.3861208558 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 5557464920 ps |
| CPU time | 829.59 seconds |
| Started | Sep 12 01:51:41 AM UTC 24 |
| Finished | Sep 12 02:05:42 AM UTC 24 |
| Peak memory | 623528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861208558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.3861208558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.1007947801 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 4397446092 ps |
| CPU time | 688.42 seconds |
| Started | Sep 12 12:19:06 AM UTC 24 |
| Finished | Sep 12 12:30:44 AM UTC 24 |
| Peak memory | 625708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1007947801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_plic_all_irqs_20.1007947801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_plic_all_irqs_20/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.4249544489 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 10068580175 ps |
| CPU time | 584.24 seconds |
| Started | Sep 11 07:57:17 PM UTC 24 |
| Finished | Sep 11 08:07:09 PM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249544489 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.4249544489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1686967284 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 142451631 ps |
| CPU time | 41.09 seconds |
| Started | Sep 11 06:54:29 PM UTC 24 |
| Finished | Sep 11 06:55:11 PM UTC 24 |
| Peak memory | 596136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686967284 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.1686967284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.1735785335 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 5601852759 ps |
| CPU time | 477.73 seconds |
| Started | Sep 11 06:54:33 PM UTC 24 |
| Finished | Sep 11 07:02:37 PM UTC 24 |
| Peak memory | 614824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735785335 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.1735785335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.704966496 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 3018299344 ps |
| CPU time | 262.71 seconds |
| Started | Sep 11 07:09:39 PM UTC 24 |
| Finished | Sep 11 07:14:07 PM UTC 24 |
| Peak memory | 621016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704966496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.704966496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.2445516166 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 9660559540 ps |
| CPU time | 542.84 seconds |
| Started | Sep 11 08:38:08 PM UTC 24 |
| Finished | Sep 11 08:47:18 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445516166 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_rand_reset.2445516166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.733909781 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 4659860520 ps |
| CPU time | 375.64 seconds |
| Started | Sep 12 12:38:31 AM UTC 24 |
| Finished | Sep 12 12:44:53 AM UTC 24 |
| Peak memory | 625724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=733909781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_power_sleep_load.733909781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_sleep_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.4233323085 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3512607976 ps |
| CPU time | 467.9 seconds |
| Started | Sep 11 09:31:47 PM UTC 24 |
| Finished | Sep 11 09:39:42 PM UTC 24 |
| Peak memory | 625516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233323085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.4233323085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.3926988701 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 2694579972 ps |
| CPU time | 106.32 seconds |
| Started | Sep 11 06:55:03 PM UTC 24 |
| Finished | Sep 11 06:56:52 PM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926988701 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.3926988701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.1723678973 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 4853761921 ps |
| CPU time | 327.27 seconds |
| Started | Sep 11 08:30:57 PM UTC 24 |
| Finished | Sep 11 08:36:29 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723678973 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_reset_error.1723678973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1717380180 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 19255068168 ps |
| CPU time | 480.8 seconds |
| Started | Sep 11 09:45:27 PM UTC 24 |
| Finished | Sep 11 09:53:35 PM UTC 24 |
| Peak memory | 636256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717380180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/c hip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1717380180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1788662970 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 4692044821 ps |
| CPU time | 472.31 seconds |
| Started | Sep 11 10:12:21 PM UTC 24 |
| Finished | Sep 11 10:20:21 PM UTC 24 |
| Peak memory | 640052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_han dler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788662970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_esc alation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.1788662970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3654927014 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 7838252618 ps |
| CPU time | 985.72 seconds |
| Started | Sep 11 07:18:44 PM UTC 24 |
| Finished | Sep 11 07:35:23 PM UTC 24 |
| Peak memory | 598156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654927014 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.3654927014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4208263606 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 5142227469 ps |
| CPU time | 646.51 seconds |
| Started | Sep 12 12:34:24 AM UTC 24 |
| Finished | Sep 12 12:45:20 AM UTC 24 |
| Peak memory | 625808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208263606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4208263606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.2058325194 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4926981998 ps |
| CPU time | 534.46 seconds |
| Started | Sep 11 09:29:41 PM UTC 24 |
| Finished | Sep 11 09:38:43 PM UTC 24 |
| Peak memory | 640008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058325194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.2058325194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2660405604 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 4151649704 ps |
| CPU time | 541.45 seconds |
| Started | Sep 11 10:05:33 PM UTC 24 |
| Finished | Sep 11 10:14:42 PM UTC 24 |
| Peak memory | 625528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660405604 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_dev.2660405604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.1952745881 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 44132685368 ps |
| CPU time | 5313.81 seconds |
| Started | Sep 12 01:04:43 AM UTC 24 |
| Finished | Sep 12 02:34:26 AM UTC 24 |
| Peak memory | 639152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw _build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952745881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip _earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.1952745881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1280845617 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 1734389697 ps |
| CPU time | 109.67 seconds |
| Started | Sep 12 01:07:11 AM UTC 24 |
| Finished | Sep 12 01:09:03 AM UTC 24 |
| Peak memory | 637208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_ access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1280845617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.1280845617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3369025492 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 20177443619 ps |
| CPU time | 3346.51 seconds |
| Started | Sep 11 09:44:43 PM UTC 24 |
| Finished | Sep 11 10:41:13 PM UTC 24 |
| Peak memory | 626836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3369025492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.3369025492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.1149061699 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 4798789770 ps |
| CPU time | 747.91 seconds |
| Started | Sep 12 01:53:40 AM UTC 24 |
| Finished | Sep 12 02:06:18 AM UTC 24 |
| Peak memory | 623780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1149061699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_plic_all_irqs_20.1149061699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_plic_all_irqs_20/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.3396415709 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 4338277791 ps |
| CPU time | 460.84 seconds |
| Started | Sep 12 12:58:41 AM UTC 24 |
| Finished | Sep 12 01:06:29 AM UTC 24 |
| Peak memory | 623516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3396415709 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_gpio.3396415709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_gpio/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.2561375197 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 712964431 ps |
| CPU time | 209.58 seconds |
| Started | Sep 11 08:08:28 PM UTC 24 |
| Finished | Sep 11 08:12:01 PM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561375197 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.2561375197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.2351277407 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 736421956 ps |
| CPU time | 200.39 seconds |
| Started | Sep 11 08:39:30 PM UTC 24 |
| Finished | Sep 11 08:42:53 PM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351277407 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_reset_error.2351277407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2369673881 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 8617525422 ps |
| CPU time | 513.04 seconds |
| Started | Sep 11 07:28:12 PM UTC 24 |
| Finished | Sep 11 07:36:52 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369673881 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.2369673881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.3747499830 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 4330072864 ps |
| CPU time | 555.26 seconds |
| Started | Sep 11 09:30:13 PM UTC 24 |
| Finished | Sep 11 09:39:36 PM UTC 24 |
| Peak memory | 639920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747499830 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.3747499830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.1260343403 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 4651478504 ps |
| CPU time | 541.92 seconds |
| Started | Sep 12 12:18:52 AM UTC 24 |
| Finished | Sep 12 12:28:02 AM UTC 24 |
| Peak memory | 623744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1260343403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_plic_all_irqs_10.1260343403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_plic_all_irqs_10/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.680139011 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 5877342568 ps |
| CPU time | 412.02 seconds |
| Started | Sep 11 07:49:33 PM UTC 24 |
| Finished | Sep 11 07:56:31 PM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680139011 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.680139011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.1799548606 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1139281795 ps |
| CPU time | 91.85 seconds |
| Started | Sep 11 07:50:57 PM UTC 24 |
| Finished | Sep 11 07:52:31 PM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799548606 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1799548606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/24.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.3753905300 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 5289414050 ps |
| CPU time | 567.7 seconds |
| Started | Sep 11 09:31:34 PM UTC 24 |
| Finished | Sep 11 09:41:10 PM UTC 24 |
| Peak memory | 674524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753905300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.3753905300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3415095298 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 19876454271 ps |
| CPU time | 4380.58 seconds |
| Started | Sep 11 09:45:54 PM UTC 24 |
| Finished | Sep 11 10:59:50 PM UTC 24 |
| Peak memory | 628980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415095298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3415095298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.1339604676 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 6211023560 ps |
| CPU time | 643.77 seconds |
| Started | Sep 12 02:50:59 AM UTC 24 |
| Finished | Sep 12 03:01:52 AM UTC 24 |
| Peak memory | 625996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339604676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.1339604676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.3357088831 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 3031258561 ps |
| CPU time | 311.6 seconds |
| Started | Sep 11 07:18:34 PM UTC 24 |
| Finished | Sep 11 07:23:51 PM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357088831 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.3357088831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.741671745 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 17511548515 ps |
| CPU time | 652.45 seconds |
| Started | Sep 11 07:53:36 PM UTC 24 |
| Finished | Sep 11 08:04:37 PM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741671745 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.741671745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/25.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.1681984924 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 6998077214 ps |
| CPU time | 506.21 seconds |
| Started | Sep 11 08:34:17 PM UTC 24 |
| Finished | Sep 11 08:42:50 PM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681984924 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_rand_reset.1681984924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.2999316973 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 361174543 ps |
| CPU time | 23.01 seconds |
| Started | Sep 11 06:54:22 PM UTC 24 |
| Finished | Sep 11 06:54:47 PM UTC 24 |
| Peak memory | 596084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999316973 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2999316973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.3765844284 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 6965862643 ps |
| CPU time | 652 seconds |
| Started | Sep 11 09:58:19 PM UTC 24 |
| Finished | Sep 11 10:09:20 PM UTC 24 |
| Peak memory | 625708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3765844284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.3765844284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.3604519540 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 6481665392 ps |
| CPU time | 1282.94 seconds |
| Started | Sep 11 09:53:38 PM UTC 24 |
| Finished | Sep 11 10:15:17 PM UTC 24 |
| Peak memory | 623864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_ srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604519540 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.3604519540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.1978118875 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 3317682414 ps |
| CPU time | 266.29 seconds |
| Started | Sep 11 10:00:27 PM UTC 24 |
| Finished | Sep 11 10:04:57 PM UTC 24 |
| Peak memory | 625904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978118875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_s tatus_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.1978118875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2811358523 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 3986608996 ps |
| CPU time | 397.43 seconds |
| Started | Sep 12 12:03:22 AM UTC 24 |
| Finished | Sep 12 12:10:06 AM UTC 24 |
| Peak memory | 672232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811358523 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_s leep_mode_alerts.2811358523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.167127232 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 4688538448 ps |
| CPU time | 614.75 seconds |
| Started | Sep 11 11:28:31 PM UTC 24 |
| Finished | Sep 11 11:38:55 PM UTC 24 |
| Peak memory | 674492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167127232 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.167127232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2675723930 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 3697906440 ps |
| CPU time | 361.2 seconds |
| Started | Sep 12 02:51:09 AM UTC 24 |
| Finished | Sep 12 02:57:16 AM UTC 24 |
| Peak memory | 672176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675723930 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2675723930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.4216625995 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 4542672984 ps |
| CPU time | 631.95 seconds |
| Started | Sep 12 02:48:09 AM UTC 24 |
| Finished | Sep 12 02:58:50 AM UTC 24 |
| Peak memory | 674348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216625995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.4216625995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.462223641 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 3872043116 ps |
| CPU time | 510.34 seconds |
| Started | Sep 12 02:50:38 AM UTC 24 |
| Finished | Sep 12 02:59:16 AM UTC 24 |
| Peak memory | 672440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462223641 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_alert_handler_lpg_s leep_mode_alerts.462223641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.3327705739 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 4776017900 ps |
| CPU time | 594.91 seconds |
| Started | Sep 12 02:50:50 AM UTC 24 |
| Finished | Sep 12 03:00:54 AM UTC 24 |
| Peak memory | 674500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327705739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.3327705739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.922593685 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 3758651180 ps |
| CPU time | 373.25 seconds |
| Started | Sep 12 02:53:36 AM UTC 24 |
| Finished | Sep 12 02:59:55 AM UTC 24 |
| Peak memory | 672428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922593685 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_alert_handler_lpg_s leep_mode_alerts.922593685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2489027387 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 3775788750 ps |
| CPU time | 372.75 seconds |
| Started | Sep 12 02:55:42 AM UTC 24 |
| Finished | Sep 12 03:02:01 AM UTC 24 |
| Peak memory | 672488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489027387 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2489027387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.1728362932 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 4985888700 ps |
| CPU time | 620.65 seconds |
| Started | Sep 12 02:54:12 AM UTC 24 |
| Finished | Sep 12 03:04:41 AM UTC 24 |
| Peak memory | 674364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728362932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.1728362932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2832213610 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 3668669760 ps |
| CPU time | 341.67 seconds |
| Started | Sep 12 02:56:57 AM UTC 24 |
| Finished | Sep 12 03:02:44 AM UTC 24 |
| Peak memory | 672424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832213610 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2832213610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.520865886 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 5618806824 ps |
| CPU time | 708.49 seconds |
| Started | Sep 12 02:55:43 AM UTC 24 |
| Finished | Sep 12 03:07:41 AM UTC 24 |
| Peak memory | 674280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520865886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.520865886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3133402158 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 3741686944 ps |
| CPU time | 422.08 seconds |
| Started | Sep 12 02:58:05 AM UTC 24 |
| Finished | Sep 12 03:05:13 AM UTC 24 |
| Peak memory | 672344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133402158 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3133402158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1476482001 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 4101619440 ps |
| CPU time | 401.07 seconds |
| Started | Sep 12 02:59:36 AM UTC 24 |
| Finished | Sep 12 03:06:23 AM UTC 24 |
| Peak memory | 672492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476482001 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1476482001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.56529458 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 3373785416 ps |
| CPU time | 453.99 seconds |
| Started | Sep 12 03:00:18 AM UTC 24 |
| Finished | Sep 12 03:07:59 AM UTC 24 |
| Peak memory | 672420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56529458 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_alert_handler_lpg_sl eep_mode_alerts.56529458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.1896237557 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 5485088332 ps |
| CPU time | 586.99 seconds |
| Started | Sep 12 02:59:36 AM UTC 24 |
| Finished | Sep 12 03:09:32 AM UTC 24 |
| Peak memory | 674288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896237557 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.1896237557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.2293938442 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 6005786226 ps |
| CPU time | 704.39 seconds |
| Started | Sep 12 03:00:17 AM UTC 24 |
| Finished | Sep 12 03:12:11 AM UTC 24 |
| Peak memory | 674416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293938442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.2293938442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.3513829292 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 5676276020 ps |
| CPU time | 745.9 seconds |
| Started | Sep 12 12:51:00 AM UTC 24 |
| Finished | Sep 12 01:03:36 AM UTC 24 |
| Peak memory | 674512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513829292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.3513829292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3585173679 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 4492998428 ps |
| CPU time | 382.74 seconds |
| Started | Sep 12 03:01:50 AM UTC 24 |
| Finished | Sep 12 03:08:18 AM UTC 24 |
| Peak memory | 672236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585173679 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3585173679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.4164338258 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 6213148536 ps |
| CPU time | 784.62 seconds |
| Started | Sep 12 03:01:49 AM UTC 24 |
| Finished | Sep 12 03:15:05 AM UTC 24 |
| Peak memory | 674292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164338258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.4164338258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.1069337514 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 4889120146 ps |
| CPU time | 575.07 seconds |
| Started | Sep 12 03:03:12 AM UTC 24 |
| Finished | Sep 12 03:12:55 AM UTC 24 |
| Peak memory | 674416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069337514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.1069337514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2724548515 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 3188311490 ps |
| CPU time | 342.17 seconds |
| Started | Sep 12 03:03:27 AM UTC 24 |
| Finished | Sep 12 03:09:14 AM UTC 24 |
| Peak memory | 672320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724548515 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2724548515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3443442800 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 3793268750 ps |
| CPU time | 336.26 seconds |
| Started | Sep 12 03:04:52 AM UTC 24 |
| Finished | Sep 12 03:10:34 AM UTC 24 |
| Peak memory | 672424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443442800 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3443442800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2463402370 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 3733097500 ps |
| CPU time | 395.21 seconds |
| Started | Sep 12 03:05:56 AM UTC 24 |
| Finished | Sep 12 03:12:37 AM UTC 24 |
| Peak memory | 672256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463402370 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2463402370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.1320057176 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 6072987864 ps |
| CPU time | 529.91 seconds |
| Started | Sep 12 03:05:20 AM UTC 24 |
| Finished | Sep 12 03:14:18 AM UTC 24 |
| Peak memory | 674512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320057176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.1320057176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2113514899 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3491149144 ps |
| CPU time | 405.23 seconds |
| Started | Sep 12 03:07:13 AM UTC 24 |
| Finished | Sep 12 03:14:05 AM UTC 24 |
| Peak memory | 672168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113514899 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2113514899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.3904897670 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 5603886454 ps |
| CPU time | 791.5 seconds |
| Started | Sep 12 03:05:57 AM UTC 24 |
| Finished | Sep 12 03:19:20 AM UTC 24 |
| Peak memory | 674280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904897670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.3904897670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1845337622 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 3683643644 ps |
| CPU time | 415.45 seconds |
| Started | Sep 12 03:07:44 AM UTC 24 |
| Finished | Sep 12 03:14:46 AM UTC 24 |
| Peak memory | 672172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845337622 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1845337622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.4041041649 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 3769885800 ps |
| CPU time | 349.79 seconds |
| Started | Sep 12 03:08:40 AM UTC 24 |
| Finished | Sep 12 03:14:35 AM UTC 24 |
| Peak memory | 672236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041041649 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_alert_handler_lpg_ sleep_mode_alerts.4041041649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.3251925478 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 5358407724 ps |
| CPU time | 515.74 seconds |
| Started | Sep 12 03:08:23 AM UTC 24 |
| Finished | Sep 12 03:17:06 AM UTC 24 |
| Peak memory | 674516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251925478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.3251925478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3441832429 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 3754495304 ps |
| CPU time | 408.68 seconds |
| Started | Sep 12 03:10:12 AM UTC 24 |
| Finished | Sep 12 03:17:07 AM UTC 24 |
| Peak memory | 672436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441832429 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3441832429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.209345015 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 5152429020 ps |
| CPU time | 517.64 seconds |
| Started | Sep 12 03:08:59 AM UTC 24 |
| Finished | Sep 12 03:17:44 AM UTC 24 |
| Peak memory | 674532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209345015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.209345015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2425189958 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 3462736374 ps |
| CPU time | 390.44 seconds |
| Started | Sep 12 03:10:28 AM UTC 24 |
| Finished | Sep 12 03:17:04 AM UTC 24 |
| Peak memory | 672428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425189958 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2425189958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.2800423324 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 5741666582 ps |
| CPU time | 627.84 seconds |
| Started | Sep 12 03:10:33 AM UTC 24 |
| Finished | Sep 12 03:21:09 AM UTC 24 |
| Peak memory | 674536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800423324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.2800423324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1397607545 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 3763083980 ps |
| CPU time | 408.13 seconds |
| Started | Sep 12 03:10:38 AM UTC 24 |
| Finished | Sep 12 03:17:32 AM UTC 24 |
| Peak memory | 672348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397607545 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1397607545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.1757210850 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 5244264820 ps |
| CPU time | 568.64 seconds |
| Started | Sep 12 03:10:39 AM UTC 24 |
| Finished | Sep 12 03:20:16 AM UTC 24 |
| Peak memory | 674344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757210850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.1757210850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3497184241 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 3276202512 ps |
| CPU time | 436.27 seconds |
| Started | Sep 12 03:11:23 AM UTC 24 |
| Finished | Sep 12 03:18:46 AM UTC 24 |
| Peak memory | 672192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497184241 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3497184241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.4161849105 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 3652043640 ps |
| CPU time | 365.59 seconds |
| Started | Sep 12 03:11:29 AM UTC 24 |
| Finished | Sep 12 03:17:40 AM UTC 24 |
| Peak memory | 672432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161849105 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_alert_handler_lpg_ sleep_mode_alerts.4161849105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3896125447 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 3850417004 ps |
| CPU time | 415.37 seconds |
| Started | Sep 12 03:14:05 AM UTC 24 |
| Finished | Sep 12 03:21:06 AM UTC 24 |
| Peak memory | 672244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896125447 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3896125447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.1544554598 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 5584403000 ps |
| CPU time | 569.44 seconds |
| Started | Sep 12 03:14:05 AM UTC 24 |
| Finished | Sep 12 03:23:43 AM UTC 24 |
| Peak memory | 674428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544554598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.1544554598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.2546134937 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 6091417968 ps |
| CPU time | 672.97 seconds |
| Started | Sep 12 03:14:11 AM UTC 24 |
| Finished | Sep 12 03:25:33 AM UTC 24 |
| Peak memory | 674520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546134937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.2546134937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.620236670 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 4545855550 ps |
| CPU time | 562.42 seconds |
| Started | Sep 12 03:14:07 AM UTC 24 |
| Finished | Sep 12 03:23:37 AM UTC 24 |
| Peak memory | 674360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620236670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.620236670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.324818015 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 3713848722 ps |
| CPU time | 348.53 seconds |
| Started | Sep 12 03:15:00 AM UTC 24 |
| Finished | Sep 12 03:20:53 AM UTC 24 |
| Peak memory | 672176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324818015 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_alert_handler_lpg_s leep_mode_alerts.324818015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.1429375099 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 5970804764 ps |
| CPU time | 656.46 seconds |
| Started | Sep 12 03:15:51 AM UTC 24 |
| Finished | Sep 12 03:26:56 AM UTC 24 |
| Peak memory | 674508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429375099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.1429375099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3452509024 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 4377745844 ps |
| CPU time | 396.25 seconds |
| Started | Sep 12 03:16:08 AM UTC 24 |
| Finished | Sep 12 03:22:50 AM UTC 24 |
| Peak memory | 672240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452509024 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3452509024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.1067347306 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 4807634452 ps |
| CPU time | 588.75 seconds |
| Started | Sep 12 03:16:05 AM UTC 24 |
| Finished | Sep 12 03:26:01 AM UTC 24 |
| Peak memory | 674516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067347306 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.1067347306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.3617563057 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 6416838240 ps |
| CPU time | 665.59 seconds |
| Started | Sep 12 02:29:18 AM UTC 24 |
| Finished | Sep 12 02:40:33 AM UTC 24 |
| Peak memory | 674412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617563057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.3617563057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2076164104 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 3855140548 ps |
| CPU time | 352.97 seconds |
| Started | Sep 12 03:16:28 AM UTC 24 |
| Finished | Sep 12 03:22:26 AM UTC 24 |
| Peak memory | 672176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076164104 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2076164104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.2874225320 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 5937844970 ps |
| CPU time | 562.65 seconds |
| Started | Sep 12 03:16:12 AM UTC 24 |
| Finished | Sep 12 03:25:43 AM UTC 24 |
| Peak memory | 674536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874225320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.2874225320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.549313516 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 3902657934 ps |
| CPU time | 422.96 seconds |
| Started | Sep 12 03:18:43 AM UTC 24 |
| Finished | Sep 12 03:25:52 AM UTC 24 |
| Peak memory | 672192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549313516 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_alert_handler_lpg_s leep_mode_alerts.549313516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.4137651289 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 5521075708 ps |
| CPU time | 458.37 seconds |
| Started | Sep 12 03:18:51 AM UTC 24 |
| Finished | Sep 12 03:26:36 AM UTC 24 |
| Peak memory | 674356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137651289 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.4137651289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2022085074 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 3542697470 ps |
| CPU time | 376.06 seconds |
| Started | Sep 12 03:23:36 AM UTC 24 |
| Finished | Sep 12 03:29:57 AM UTC 24 |
| Peak memory | 672172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022085074 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2022085074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.924099141 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 4553137720 ps |
| CPU time | 423.38 seconds |
| Started | Sep 12 03:26:33 AM UTC 24 |
| Finished | Sep 12 03:33:43 AM UTC 24 |
| Peak memory | 672240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924099141 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_alert_handler_lpg_s leep_mode_alerts.924099141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.1807689539 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 5080106904 ps |
| CPU time | 618.55 seconds |
| Started | Sep 12 02:35:27 AM UTC 24 |
| Finished | Sep 12 02:45:54 AM UTC 24 |
| Peak memory | 674280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807689539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.1807689539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.696970500 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 5572352160 ps |
| CPU time | 646.24 seconds |
| Started | Sep 12 03:28:34 AM UTC 24 |
| Finished | Sep 12 03:39:29 AM UTC 24 |
| Peak memory | 674420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696970500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.696970500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_all_escalation_resets.2855525424 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 5231060696 ps |
| CPU time | 563.25 seconds |
| Started | Sep 12 03:26:34 AM UTC 24 |
| Finished | Sep 12 03:36:05 AM UTC 24 |
| Peak memory | 674532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855525424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.2855525424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1777683648 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 4488721306 ps |
| CPU time | 413.93 seconds |
| Started | Sep 12 03:26:35 AM UTC 24 |
| Finished | Sep 12 03:33:35 AM UTC 24 |
| Peak memory | 672456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777683648 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1777683648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.2132244047 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 4902398840 ps |
| CPU time | 580.89 seconds |
| Started | Sep 12 03:27:53 AM UTC 24 |
| Finished | Sep 12 03:37:42 AM UTC 24 |
| Peak memory | 674528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132244047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.2132244047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.499977552 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 4848090752 ps |
| CPU time | 632.67 seconds |
| Started | Sep 12 03:28:03 AM UTC 24 |
| Finished | Sep 12 03:38:45 AM UTC 24 |
| Peak memory | 674432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499977552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.499977552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1828864339 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 3754174318 ps |
| CPU time | 354.68 seconds |
| Started | Sep 12 03:28:56 AM UTC 24 |
| Finished | Sep 12 03:34:56 AM UTC 24 |
| Peak memory | 672176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828864339 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1828864339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.4034021463 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 5634524462 ps |
| CPU time | 530.82 seconds |
| Started | Sep 12 03:28:28 AM UTC 24 |
| Finished | Sep 12 03:37:27 AM UTC 24 |
| Peak memory | 674500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034021463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.4034021463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.1012464093 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 4794749842 ps |
| CPU time | 490.74 seconds |
| Started | Sep 12 03:28:56 AM UTC 24 |
| Finished | Sep 12 03:37:13 AM UTC 24 |
| Peak memory | 674576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012464093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.1012464093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.551114867 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 5354248052 ps |
| CPU time | 447.57 seconds |
| Started | Sep 12 03:30:39 AM UTC 24 |
| Finished | Sep 12 03:38:12 AM UTC 24 |
| Peak memory | 674596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551114867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.551114867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.23676054 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 4371412400 ps |
| CPU time | 540.25 seconds |
| Started | Sep 12 02:41:58 AM UTC 24 |
| Finished | Sep 12 02:51:06 AM UTC 24 |
| Peak memory | 674524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23676054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esca lation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.23676054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.4277443543 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 4409021296 ps |
| CPU time | 507.8 seconds |
| Started | Sep 12 03:36:11 AM UTC 24 |
| Finished | Sep 12 03:44:45 AM UTC 24 |
| Peak memory | 674568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277443543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.4277443543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.123915410 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 4661930460 ps |
| CPU time | 501.62 seconds |
| Started | Sep 12 03:39:06 AM UTC 24 |
| Finished | Sep 12 03:47:34 AM UTC 24 |
| Peak memory | 674424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123915410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.123915410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.655879464 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 3585854950 ps |
| CPU time | 453.42 seconds |
| Started | Sep 12 02:45:52 AM UTC 24 |
| Finished | Sep 12 02:53:32 AM UTC 24 |
| Peak memory | 672420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655879464 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_alert_handler_lpg_sl eep_mode_alerts.655879464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.2762156751 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 5233860686 ps |
| CPU time | 524.46 seconds |
| Started | Sep 11 07:16:55 PM UTC 24 |
| Finished | Sep 11 07:25:46 PM UTC 24 |
| Peak memory | 615124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762156751 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.2762156751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.3958940365 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 4352237815 ps |
| CPU time | 448.4 seconds |
| Started | Sep 11 07:25:27 PM UTC 24 |
| Finished | Sep 11 07:33:02 PM UTC 24 |
| Peak memory | 621332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958940365 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.3958940365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2140032579 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 5439924312 ps |
| CPU time | 481.6 seconds |
| Started | Sep 11 10:12:00 PM UTC 24 |
| Finished | Sep 11 10:20:08 PM UTC 24 |
| Peak memory | 626016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140032579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2140032579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.34524032 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 3707299218 ps |
| CPU time | 353 seconds |
| Started | Sep 12 12:28:53 AM UTC 24 |
| Finished | Sep 12 12:34:51 AM UTC 24 |
| Peak memory | 623612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=34524032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.34524032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.2507177584 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 13183274624 ps |
| CPU time | 1805.44 seconds |
| Started | Sep 12 01:11:22 AM UTC 24 |
| Finished | Sep 12 01:41:51 AM UTC 24 |
| Peak memory | 625964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_buil d_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507177584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.2507177584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_rst_inputs.363986270 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 19174692184 ps |
| CPU time | 2835.96 seconds |
| Started | Sep 11 10:21:25 PM UTC 24 |
| Finished | Sep 11 11:09:14 PM UTC 24 |
| Peak memory | 628880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_ images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363986270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.363986270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.2267766370 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2773327768 ps |
| CPU time | 244.6 seconds |
| Started | Sep 11 10:01:35 PM UTC 24 |
| Finished | Sep 11 10:05:44 PM UTC 24 |
| Peak memory | 623540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2267766370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_plic_sw_irq.2267766370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.955705497 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 17329091740 ps |
| CPU time | 4280.28 seconds |
| Started | Sep 11 09:56:29 PM UTC 24 |
| Finished | Sep 11 11:08:41 PM UTC 24 |
| Peak memory | 626716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955705497 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.955705497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.4197078143 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 7939431826 ps |
| CPU time | 499.64 seconds |
| Started | Sep 11 09:35:51 PM UTC 24 |
| Finished | Sep 11 09:44:18 PM UTC 24 |
| Peak memory | 635892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=4197078143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_lc_ctrl_transition.4197078143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2463244782 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2905981357 ps |
| CPU time | 104.13 seconds |
| Started | Sep 11 09:34:35 PM UTC 24 |
| Finished | Sep 11 09:36:22 PM UTC 24 |
| Peak memory | 637412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_ access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2463244782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.2463244782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1175197442 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 26534281700 ps |
| CPU time | 1778.43 seconds |
| Started | Sep 11 10:11:11 PM UTC 24 |
| Finished | Sep 11 10:41:13 PM UTC 24 |
| Peak memory | 625648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175197442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1175197442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.1164833815 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 10713176963 ps |
| CPU time | 996.43 seconds |
| Started | Sep 12 02:27:41 AM UTC 24 |
| Finished | Sep 12 02:44:32 AM UTC 24 |
| Peak memory | 640608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164833815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.1164833815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.468336393 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 2835136392 ps |
| CPU time | 210.84 seconds |
| Started | Sep 11 07:14:07 PM UTC 24 |
| Finished | Sep 11 07:17:41 PM UTC 24 |
| Peak memory | 617044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468336393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.468336393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.203421769 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 88059141944 ps |
| CPU time | 1177.43 seconds |
| Started | Sep 11 07:48:39 PM UTC 24 |
| Finished | Sep 11 08:08:30 PM UTC 24 |
| Peak memory | 595984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203421769 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.203421769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.881839661 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 2417528368 ps |
| CPU time | 195.94 seconds |
| Started | Sep 11 08:30:56 PM UTC 24 |
| Finished | Sep 11 08:34:16 PM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881839661 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.881839661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/52.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4145003596 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 5334950780 ps |
| CPU time | 570.9 seconds |
| Started | Sep 11 10:16:07 PM UTC 24 |
| Finished | Sep 11 10:25:45 PM UTC 24 |
| Peak memory | 625580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145003596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4145003596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.1757258686 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 4236252402 ps |
| CPU time | 540.74 seconds |
| Started | Sep 11 09:31:39 PM UTC 24 |
| Finished | Sep 11 09:40:48 PM UTC 24 |
| Peak memory | 625856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1757258686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.1757258686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1180510082 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 5052185592 ps |
| CPU time | 761.97 seconds |
| Started | Sep 11 09:30:49 PM UTC 24 |
| Finished | Sep 11 09:43:41 PM UTC 24 |
| Peak memory | 623828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1180510082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.1180510082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pattgen_ios.1042494664 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2811594344 ps |
| CPU time | 302.81 seconds |
| Started | Sep 11 11:29:59 PM UTC 24 |
| Finished | Sep 11 11:35:08 PM UTC 24 |
| Peak memory | 623704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_im ages=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042494664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.1042494664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pattgen_ios/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.98435813 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 4692921888 ps |
| CPU time | 407.27 seconds |
| Started | Sep 11 10:02:43 PM UTC 24 |
| Finished | Sep 11 10:09:36 PM UTC 24 |
| Peak memory | 625812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=98435813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.98435813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2738882758 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 4397551750 ps |
| CPU time | 431.22 seconds |
| Started | Sep 11 09:39:44 PM UTC 24 |
| Finished | Sep 11 09:47:02 PM UTC 24 |
| Peak memory | 631744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738882758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_mai n_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.2738882758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.105629256 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 2713604570 ps |
| CPU time | 349.07 seconds |
| Started | Sep 12 12:57:56 AM UTC 24 |
| Finished | Sep 12 01:03:50 AM UTC 24 |
| Peak memory | 623796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105629256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_spi_host_tx_rx.105629256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3997115854 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 12066664153 ps |
| CPU time | 606.44 seconds |
| Started | Sep 11 06:54:15 PM UTC 24 |
| Finished | Sep 11 07:04:30 PM UTC 24 |
| Peak memory | 606416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_c pu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3997115854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. chip_rv_dm_lc_disabled.3997115854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1903380166 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 6501942504 ps |
| CPU time | 1272.78 seconds |
| Started | Sep 11 09:50:13 PM UTC 24 |
| Finished | Sep 11 10:11:43 PM UTC 24 |
| Peak memory | 625716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903380166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_ea rlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.1903380166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.1360765799 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 4778481520 ps |
| CPU time | 320.8 seconds |
| Started | Sep 11 10:10:22 PM UTC 24 |
| Finished | Sep 11 10:15:48 PM UTC 24 |
| Peak memory | 623600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360765799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_l c_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.1360765799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.176115295 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 49483663586 ps |
| CPU time | 5996.59 seconds |
| Started | Sep 11 09:39:10 PM UTC 24 |
| Finished | Sep 11 11:20:24 PM UTC 24 |
| Peak memory | 643312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176115295 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prod.176115295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.1019435153 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 2367719138 ps |
| CPU time | 183.39 seconds |
| Started | Sep 11 06:54:30 PM UTC 24 |
| Finished | Sep 11 06:57:36 PM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019435153 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1019435153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.396336852 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 4489205790 ps |
| CPU time | 503.53 seconds |
| Started | Sep 11 07:33:41 PM UTC 24 |
| Finished | Sep 11 07:42:11 PM UTC 24 |
| Peak memory | 620952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396336852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.396336852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.3707767684 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 8699654673 ps |
| CPU time | 285.57 seconds |
| Started | Sep 11 07:49:38 PM UTC 24 |
| Finished | Sep 11 07:54:28 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707767684 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.3707767684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/23.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.235913836 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 8092787302 ps |
| CPU time | 734.45 seconds |
| Started | Sep 11 08:34:23 PM UTC 24 |
| Finished | Sep 11 08:46:47 PM UTC 24 |
| Peak memory | 600112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235913836 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_reset_error.235913836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.2158070961 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 2663413139 ps |
| CPU time | 194.21 seconds |
| Started | Sep 11 08:43:03 PM UTC 24 |
| Finished | Sep 11 08:46:21 PM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158070961 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.2158070961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/62.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.1795014023 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 15357819699 ps |
| CPU time | 535.45 seconds |
| Started | Sep 11 08:49:26 PM UTC 24 |
| Finished | Sep 11 08:58:29 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795014023 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.1795014023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/68.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2970744709 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 5013391026 ps |
| CPU time | 647.19 seconds |
| Started | Sep 11 09:32:39 PM UTC 24 |
| Finished | Sep 11 09:43:35 PM UTC 24 |
| Peak memory | 625764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2970744709 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.2970744709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1512868846 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 4521612440 ps |
| CPU time | 482.96 seconds |
| Started | Sep 11 10:10:24 PM UTC 24 |
| Finished | Sep 11 10:18:34 PM UTC 24 |
| Peak memory | 623840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=1512868846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_pwrmgr_lowpower_cancel.1512868846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1478315372 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 4948522416 ps |
| CPU time | 744.42 seconds |
| Started | Sep 11 09:46:11 PM UTC 24 |
| Finished | Sep 11 09:58:46 PM UTC 24 |
| Peak memory | 623828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478315372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.1478315372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.661083154 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3795463543 ps |
| CPU time | 372.09 seconds |
| Started | Sep 11 11:38:23 PM UTC 24 |
| Finished | Sep 11 11:44:41 PM UTC 24 |
| Peak memory | 623764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=661083154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_gpio.661083154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_gpio/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.3041929882 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 3931586600 ps |
| CPU time | 500.69 seconds |
| Started | Sep 12 01:24:34 AM UTC 24 |
| Finished | Sep 12 01:33:02 AM UTC 24 |
| Peak memory | 623592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041929882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.3041929882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.3622885831 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 4115321080 ps |
| CPU time | 276.27 seconds |
| Started | Sep 11 10:07:49 PM UTC 24 |
| Finished | Sep 11 10:12:30 PM UTC 24 |
| Peak memory | 623004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362288 5831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_csr_rw.3622885831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.1475939848 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 5549606462 ps |
| CPU time | 396.46 seconds |
| Started | Sep 12 12:32:24 AM UTC 24 |
| Finished | Sep 12 12:39:06 AM UTC 24 |
| Peak memory | 650916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475939848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_tap_straps_rma.1475939848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.2323069731 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 5359367672 ps |
| CPU time | 251.89 seconds |
| Started | Sep 11 06:55:36 PM UTC 24 |
| Finished | Sep 11 06:59:52 PM UTC 24 |
| Peak memory | 680460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323069731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_reset.2323069731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.2067386146 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 23686824338 ps |
| CPU time | 6888.37 seconds |
| Started | Sep 11 09:52:47 PM UTC 24 |
| Finished | Sep 11 11:49:04 PM UTC 24 |
| Peak memory | 628972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2067386146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_csrng_edn_concurrency.2067386146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.2652306238 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 2853597880 ps |
| CPU time | 504.72 seconds |
| Started | Sep 11 09:51:31 PM UTC 24 |
| Finished | Sep 11 10:00:03 PM UTC 24 |
| Peak memory | 626012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_ device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652306238 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_boot_mode.2652306238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.659449291 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 10012157358 ps |
| CPU time | 1332.38 seconds |
| Started | Sep 11 09:39:49 PM UTC 24 |
| Finished | Sep 11 10:02:19 PM UTC 24 |
| Peak memory | 625712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659449291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_ all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.659449291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2057867018 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 2231067846 ps |
| CPU time | 152.64 seconds |
| Started | Sep 11 10:14:19 PM UTC 24 |
| Finished | Sep 11 10:16:55 PM UTC 24 |
| Peak memory | 631756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_ima ges=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2057867018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_gli tch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.2057867018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.4246452276 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 2205473811 ps |
| CPU time | 156.5 seconds |
| Started | Sep 11 11:44:12 PM UTC 24 |
| Finished | Sep 11 11:46:51 PM UTC 24 |
| Peak memory | 637408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_ access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=4246452276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.4246452276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2572217527 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 25028196040 ps |
| CPU time | 7758.94 seconds |
| Started | Sep 11 10:25:58 PM UTC 24 |
| Finished | Sep 12 12:36:53 AM UTC 24 |
| Peak memory | 626716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572217527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2572217527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.1689368035 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 29324756120 ps |
| CPU time | 4801.3 seconds |
| Started | Sep 11 06:54:09 PM UTC 24 |
| Finished | Sep 11 08:15:08 PM UTC 24 |
| Peak memory | 620068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1689368035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_ csr_aliasing.1689368035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.3120621479 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 36916163080 ps |
| CPU time | 4463.74 seconds |
| Started | Sep 11 06:54:08 PM UTC 24 |
| Finished | Sep 11 08:09:24 PM UTC 24 |
| Peak memory | 611700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3120621479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.chip_csr_bit_bash.3120621479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3874627985 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 9186354616 ps |
| CPU time | 839.82 seconds |
| Started | Sep 11 06:54:40 PM UTC 24 |
| Finished | Sep 11 07:08:52 PM UTC 24 |
| Peak memory | 670108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3874627985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.chip_csr_mem_rw_with_rand_reset.3874627985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.3204405540 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 7613157550 ps |
| CPU time | 359.35 seconds |
| Started | Sep 11 06:54:12 PM UTC 24 |
| Finished | Sep 11 07:00:17 PM UTC 24 |
| Peak memory | 608672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204405540 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.3204405540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.92868450 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 28473697924 ps |
| CPU time | 4071.26 seconds |
| Started | Sep 11 06:54:11 PM UTC 24 |
| Finished | Sep 11 08:02:51 PM UTC 24 |
| Peak memory | 613956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=92868450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 0.chip_same_csr_outstanding.92868450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.84376732 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 89225765 ps |
| CPU time | 12.58 seconds |
| Started | Sep 11 06:54:17 PM UTC 24 |
| Finished | Sep 11 06:54:31 PM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84376732 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.84376732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2420399445 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 151966390 ps |
| CPU time | 20.16 seconds |
| Started | Sep 11 06:54:20 PM UTC 24 |
| Finished | Sep 11 06:54:41 PM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420399445 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.2420399445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.3248200472 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 41708803547 ps |
| CPU time | 465.61 seconds |
| Started | Sep 11 06:54:16 PM UTC 24 |
| Finished | Sep 11 07:02:08 PM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248200472 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3248200472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.215486393 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 48758747430 ps |
| CPU time | 695.59 seconds |
| Started | Sep 11 06:54:18 PM UTC 24 |
| Finished | Sep 11 07:06:02 PM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215486393 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.215486393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.3725597504 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 466037819 ps |
| CPU time | 45.58 seconds |
| Started | Sep 11 06:54:19 PM UTC 24 |
| Finished | Sep 11 06:55:06 PM UTC 24 |
| Peak memory | 596100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725597504 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3725597504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.2930070906 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 158951347 ps |
| CPU time | 10.2 seconds |
| Started | Sep 11 06:54:15 PM UTC 24 |
| Finished | Sep 11 06:54:26 PM UTC 24 |
| Peak memory | 593900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930070906 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2930070906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1530334569 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 3143233823 ps |
| CPU time | 47.8 seconds |
| Started | Sep 11 06:54:16 PM UTC 24 |
| Finished | Sep 11 06:55:06 PM UTC 24 |
| Peak memory | 593892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530334569 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1530334569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1989833712 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 48757872 ps |
| CPU time | 8.6 seconds |
| Started | Sep 11 06:54:13 PM UTC 24 |
| Finished | Sep 11 06:54:23 PM UTC 24 |
| Peak memory | 593704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989833712 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1989833712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.4218343831 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1117757728 ps |
| CPU time | 245.06 seconds |
| Started | Sep 11 06:54:26 PM UTC 24 |
| Finished | Sep 11 06:58:36 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218343831 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.4218343831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.2062610681 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 30506890092 ps |
| CPU time | 5200.16 seconds |
| Started | Sep 11 06:54:48 PM UTC 24 |
| Finished | Sep 11 08:22:27 PM UTC 24 |
| Peak memory | 620148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2062610681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_ csr_aliasing.2062610681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.2877156621 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 41783077648 ps |
| CPU time | 4003.19 seconds |
| Started | Sep 11 06:54:42 PM UTC 24 |
| Finished | Sep 11 08:02:10 PM UTC 24 |
| Peak memory | 620104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2877156621 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.chip_csr_bit_bash.2877156621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3277233634 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 5709937640 ps |
| CPU time | 419.98 seconds |
| Started | Sep 11 06:55:40 PM UTC 24 |
| Finished | Sep 11 07:02:45 PM UTC 24 |
| Peak memory | 661992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3277233634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.chip_csr_mem_rw_with_rand_reset.3277233634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.1221066444 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 3764778322 ps |
| CPU time | 191.97 seconds |
| Started | Sep 11 06:54:49 PM UTC 24 |
| Finished | Sep 11 06:58:04 PM UTC 24 |
| Peak memory | 608680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221066444 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.1221066444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_prim_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2584609761 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 9088500338 ps |
| CPU time | 476.67 seconds |
| Started | Sep 11 06:54:49 PM UTC 24 |
| Finished | Sep 11 07:02:52 PM UTC 24 |
| Peak memory | 606348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_c pu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2584609761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. chip_rv_dm_lc_disabled.2584609761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.1632727928 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 30800167303 ps |
| CPU time | 3892.68 seconds |
| Started | Sep 11 06:54:45 PM UTC 24 |
| Finished | Sep 11 08:00:23 PM UTC 24 |
| Peak memory | 614008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1632727928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.chip_same_csr_outstanding.1632727928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.302508255 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 3472988702 ps |
| CPU time | 216.39 seconds |
| Started | Sep 11 06:54:48 PM UTC 24 |
| Finished | Sep 11 06:58:28 PM UTC 24 |
| Peak memory | 621092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302508255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.302508255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1455526238 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 796593012 ps |
| CPU time | 34.79 seconds |
| Started | Sep 11 06:55:28 PM UTC 24 |
| Finished | Sep 11 06:56:05 PM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455526238 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1455526238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.2667672222 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 190883979 ps |
| CPU time | 14.06 seconds |
| Started | Sep 11 06:55:08 PM UTC 24 |
| Finished | Sep 11 06:55:23 PM UTC 24 |
| Peak memory | 593780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667672222 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2667672222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.484454880 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 145709074 ps |
| CPU time | 17.17 seconds |
| Started | Sep 11 06:54:59 PM UTC 24 |
| Finished | Sep 11 06:55:18 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484454880 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.484454880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.3323904717 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 82377534993 ps |
| CPU time | 736.08 seconds |
| Started | Sep 11 06:55:01 PM UTC 24 |
| Finished | Sep 11 07:07:25 PM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323904717 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3323904717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.86312635 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 12809914707 ps |
| CPU time | 206.97 seconds |
| Started | Sep 11 06:55:00 PM UTC 24 |
| Finished | Sep 11 06:58:31 PM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86312635 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.86312635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.2884597962 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 212708000 ps |
| CPU time | 24.85 seconds |
| Started | Sep 11 06:54:59 PM UTC 24 |
| Finished | Sep 11 06:55:25 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884597962 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.2884597962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.3676249871 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 611413900 ps |
| CPU time | 30.91 seconds |
| Started | Sep 11 06:55:09 PM UTC 24 |
| Finished | Sep 11 06:55:42 PM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676249871 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3676249871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.1478793014 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 217743541 ps |
| CPU time | 14.05 seconds |
| Started | Sep 11 06:54:52 PM UTC 24 |
| Finished | Sep 11 06:55:07 PM UTC 24 |
| Peak memory | 593780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478793014 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1478793014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.3477633976 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 10414808005 ps |
| CPU time | 165.74 seconds |
| Started | Sep 11 06:54:58 PM UTC 24 |
| Finished | Sep 11 06:57:47 PM UTC 24 |
| Peak memory | 593976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477633976 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3477633976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3756185822 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 4760768169 ps |
| CPU time | 72.41 seconds |
| Started | Sep 11 06:54:57 PM UTC 24 |
| Finished | Sep 11 06:56:11 PM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756185822 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3756185822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1278738303 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 48186970 ps |
| CPU time | 8.58 seconds |
| Started | Sep 11 06:54:53 PM UTC 24 |
| Finished | Sep 11 06:55:03 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278738303 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1278738303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.801944869 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 3966237204 ps |
| CPU time | 173.06 seconds |
| Started | Sep 11 06:55:31 PM UTC 24 |
| Finished | Sep 11 06:58:27 PM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801944869 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.801944869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.899700811 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 9031258697 ps |
| CPU time | 273.65 seconds |
| Started | Sep 11 06:55:30 PM UTC 24 |
| Finished | Sep 11 07:00:08 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899700811 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.899700811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.496342011 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 4427191661 ps |
| CPU time | 173.52 seconds |
| Started | Sep 11 06:55:26 PM UTC 24 |
| Finished | Sep 11 06:58:23 PM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496342011 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.496342011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.2339072587 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 236174526 ps |
| CPU time | 33.58 seconds |
| Started | Sep 11 06:55:13 PM UTC 24 |
| Finished | Sep 11 06:55:48 PM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339072587 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2339072587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3157739261 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 12383270978 ps |
| CPU time | 1275.6 seconds |
| Started | Sep 11 07:16:56 PM UTC 24 |
| Finished | Sep 11 07:38:27 PM UTC 24 |
| Peak memory | 670328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3157739261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 10.chip_csr_mem_rw_with_rand_reset.3157739261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.2425942695 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 16390398499 ps |
| CPU time | 1971.58 seconds |
| Started | Sep 11 07:14:08 PM UTC 24 |
| Finished | Sep 11 07:47:25 PM UTC 24 |
| Peak memory | 610732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2425942695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.chip_same_csr_outstanding.2425942695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.1157407946 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 1002880228 ps |
| CPU time | 82.59 seconds |
| Started | Sep 11 07:15:24 PM UTC 24 |
| Finished | Sep 11 07:16:49 PM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157407946 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1157407946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.301718475 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 60290316065 ps |
| CPU time | 876.84 seconds |
| Started | Sep 11 07:15:30 PM UTC 24 |
| Finished | Sep 11 07:30:17 PM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301718475 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.301718475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3104250841 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 571275460 ps |
| CPU time | 34.02 seconds |
| Started | Sep 11 07:15:55 PM UTC 24 |
| Finished | Sep 11 07:16:30 PM UTC 24 |
| Peak memory | 596084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104250841 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.3104250841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.643444813 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 2043040204 ps |
| CPU time | 64.91 seconds |
| Started | Sep 11 07:15:45 PM UTC 24 |
| Finished | Sep 11 07:16:52 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643444813 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.643444813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.2685778436 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 227841336 ps |
| CPU time | 14.25 seconds |
| Started | Sep 11 07:14:50 PM UTC 24 |
| Finished | Sep 11 07:15:05 PM UTC 24 |
| Peak memory | 593804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685778436 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.2685778436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.3439009430 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 88596715370 ps |
| CPU time | 861.57 seconds |
| Started | Sep 11 07:15:00 PM UTC 24 |
| Finished | Sep 11 07:29:31 PM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439009430 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3439009430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.4271277644 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 8166488812 ps |
| CPU time | 151.76 seconds |
| Started | Sep 11 07:15:16 PM UTC 24 |
| Finished | Sep 11 07:17:51 PM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271277644 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.4271277644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.3724813326 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 214688568 ps |
| CPU time | 25.97 seconds |
| Started | Sep 11 07:14:54 PM UTC 24 |
| Finished | Sep 11 07:15:22 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724813326 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3724813326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.2607680191 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 2281759654 ps |
| CPU time | 59.64 seconds |
| Started | Sep 11 07:15:32 PM UTC 24 |
| Finished | Sep 11 07:16:33 PM UTC 24 |
| Peak memory | 596212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607680191 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2607680191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.2583176847 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 46633889 ps |
| CPU time | 9.02 seconds |
| Started | Sep 11 07:14:14 PM UTC 24 |
| Finished | Sep 11 07:14:24 PM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583176847 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2583176847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.2851436033 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 9023875212 ps |
| CPU time | 76.57 seconds |
| Started | Sep 11 07:14:32 PM UTC 24 |
| Finished | Sep 11 07:15:50 PM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851436033 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2851436033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.224449765 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 4895098398 ps |
| CPU time | 108.54 seconds |
| Started | Sep 11 07:14:31 PM UTC 24 |
| Finished | Sep 11 07:16:22 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224449765 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.224449765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2576294553 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 35047093 ps |
| CPU time | 8.11 seconds |
| Started | Sep 11 07:14:24 PM UTC 24 |
| Finished | Sep 11 07:14:34 PM UTC 24 |
| Peak memory | 593892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576294553 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.2576294553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.3340246874 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 480839242 ps |
| CPU time | 66.29 seconds |
| Started | Sep 11 07:15:58 PM UTC 24 |
| Finished | Sep 11 07:17:06 PM UTC 24 |
| Peak memory | 596032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340246874 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3340246874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.2236518838 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 3008289902 ps |
| CPU time | 146.87 seconds |
| Started | Sep 11 07:16:16 PM UTC 24 |
| Finished | Sep 11 07:18:46 PM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236518838 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2236518838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2489954512 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 93867793 ps |
| CPU time | 20.11 seconds |
| Started | Sep 11 07:16:14 PM UTC 24 |
| Finished | Sep 11 07:16:35 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489954512 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.2489954512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3348892717 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 1322452340 ps |
| CPU time | 149.84 seconds |
| Started | Sep 11 07:16:48 PM UTC 24 |
| Finished | Sep 11 07:19:20 PM UTC 24 |
| Peak memory | 595872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348892717 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.3348892717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.4216579821 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 217205438 ps |
| CPU time | 33.94 seconds |
| Started | Sep 11 07:15:53 PM UTC 24 |
| Finished | Sep 11 07:16:29 PM UTC 24 |
| Peak memory | 596148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216579821 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.4216579821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2466888314 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 10453830148 ps |
| CPU time | 793.41 seconds |
| Started | Sep 11 07:19:11 PM UTC 24 |
| Finished | Sep 11 07:32:35 PM UTC 24 |
| Peak memory | 670332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2466888314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 11.chip_csr_mem_rw_with_rand_reset.2466888314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.3549341574 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 6075373966 ps |
| CPU time | 785.05 seconds |
| Started | Sep 11 07:19:10 PM UTC 24 |
| Finished | Sep 11 07:32:25 PM UTC 24 |
| Peak memory | 616972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549341574 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.3549341574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.342240602 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 16191482593 ps |
| CPU time | 1726.94 seconds |
| Started | Sep 11 07:16:59 PM UTC 24 |
| Finished | Sep 11 07:46:07 PM UTC 24 |
| Peak memory | 610864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=342240602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 11.chip_same_csr_outstanding.342240602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.987733425 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 37051679020 ps |
| CPU time | 478.32 seconds |
| Started | Sep 11 07:18:03 PM UTC 24 |
| Finished | Sep 11 07:26:07 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987733425 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.987733425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1247180183 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 256775708 ps |
| CPU time | 30.34 seconds |
| Started | Sep 11 07:18:32 PM UTC 24 |
| Finished | Sep 11 07:19:04 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247180183 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.1247180183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.3006306728 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 1842958326 ps |
| CPU time | 77.73 seconds |
| Started | Sep 11 07:18:15 PM UTC 24 |
| Finished | Sep 11 07:19:35 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006306728 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3006306728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.3131433686 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 554605419 ps |
| CPU time | 33.73 seconds |
| Started | Sep 11 07:17:32 PM UTC 24 |
| Finished | Sep 11 07:18:07 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131433686 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.3131433686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.1651386953 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 79784829294 ps |
| CPU time | 803.97 seconds |
| Started | Sep 11 07:17:37 PM UTC 24 |
| Finished | Sep 11 07:31:10 PM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651386953 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1651386953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.3084747665 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 49187406115 ps |
| CPU time | 772.8 seconds |
| Started | Sep 11 07:17:45 PM UTC 24 |
| Finished | Sep 11 07:30:48 PM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084747665 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3084747665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.985052530 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 156826068 ps |
| CPU time | 17.32 seconds |
| Started | Sep 11 07:17:31 PM UTC 24 |
| Finished | Sep 11 07:17:50 PM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985052530 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.985052530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.2173059162 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 1718997180 ps |
| CPU time | 53.71 seconds |
| Started | Sep 11 07:18:10 PM UTC 24 |
| Finished | Sep 11 07:19:05 PM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173059162 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2173059162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.4174781439 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 46617720 ps |
| CPU time | 8.8 seconds |
| Started | Sep 11 07:17:02 PM UTC 24 |
| Finished | Sep 11 07:17:12 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174781439 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.4174781439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.2930489784 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 9345723627 ps |
| CPU time | 107.91 seconds |
| Started | Sep 11 07:17:14 PM UTC 24 |
| Finished | Sep 11 07:19:04 PM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930489784 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2930489784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2653978399 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 4784750553 ps |
| CPU time | 79.07 seconds |
| Started | Sep 11 07:17:18 PM UTC 24 |
| Finished | Sep 11 07:18:39 PM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653978399 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.2653978399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2296960003 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 39386085 ps |
| CPU time | 8.18 seconds |
| Started | Sep 11 07:17:11 PM UTC 24 |
| Finished | Sep 11 07:17:20 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296960003 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2296960003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.3463972744 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 2588037360 ps |
| CPU time | 251.03 seconds |
| Started | Sep 11 07:18:50 PM UTC 24 |
| Finished | Sep 11 07:23:05 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463972744 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3463972744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.400321148 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 4908864782 ps |
| CPU time | 363.28 seconds |
| Started | Sep 11 07:19:02 PM UTC 24 |
| Finished | Sep 11 07:25:11 PM UTC 24 |
| Peak memory | 596032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400321148 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.400321148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.1930997191 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 513874271 ps |
| CPU time | 29.27 seconds |
| Started | Sep 11 07:18:15 PM UTC 24 |
| Finished | Sep 11 07:18:45 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930997191 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1930997191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.1010877132 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 7950780918 ps |
| CPU time | 531.01 seconds |
| Started | Sep 11 07:22:24 PM UTC 24 |
| Finished | Sep 11 07:31:22 PM UTC 24 |
| Peak memory | 656012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1010877132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 12.chip_csr_mem_rw_with_rand_reset.1010877132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.1932958717 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 4571787886 ps |
| CPU time | 354.81 seconds |
| Started | Sep 11 07:22:13 PM UTC 24 |
| Finished | Sep 11 07:28:12 PM UTC 24 |
| Peak memory | 614680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932958717 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.1932958717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.535379125 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 31430631573 ps |
| CPU time | 4049.86 seconds |
| Started | Sep 11 07:19:17 PM UTC 24 |
| Finished | Sep 11 08:27:35 PM UTC 24 |
| Peak memory | 613800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=535379125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 12.chip_same_csr_outstanding.535379125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.2549342939 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 2228489643 ps |
| CPU time | 134.76 seconds |
| Started | Sep 11 07:20:28 PM UTC 24 |
| Finished | Sep 11 07:22:45 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549342939 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.2549342939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1723579618 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 252583419 ps |
| CPU time | 34.04 seconds |
| Started | Sep 11 07:21:46 PM UTC 24 |
| Finished | Sep 11 07:22:22 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723579618 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.1723579618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.1809525086 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 474688467 ps |
| CPU time | 36.98 seconds |
| Started | Sep 11 07:21:07 PM UTC 24 |
| Finished | Sep 11 07:21:45 PM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809525086 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1809525086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.3547580913 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 110063854 ps |
| CPU time | 17.1 seconds |
| Started | Sep 11 07:19:46 PM UTC 24 |
| Finished | Sep 11 07:20:05 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547580913 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.3547580913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.1407727139 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 89048705525 ps |
| CPU time | 866.22 seconds |
| Started | Sep 11 07:20:01 PM UTC 24 |
| Finished | Sep 11 07:34:37 PM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407727139 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1407727139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.2653989064 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 71228867795 ps |
| CPU time | 1187.9 seconds |
| Started | Sep 11 07:20:01 PM UTC 24 |
| Finished | Sep 11 07:40:03 PM UTC 24 |
| Peak memory | 595068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653989064 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2653989064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.3777092402 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 456680935 ps |
| CPU time | 56.18 seconds |
| Started | Sep 11 07:19:56 PM UTC 24 |
| Finished | Sep 11 07:20:54 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777092402 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.3777092402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.1846973514 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 1380628550 ps |
| CPU time | 54.15 seconds |
| Started | Sep 11 07:20:53 PM UTC 24 |
| Finished | Sep 11 07:21:48 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846973514 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1846973514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.3331171309 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 50809421 ps |
| CPU time | 9.28 seconds |
| Started | Sep 11 07:19:27 PM UTC 24 |
| Finished | Sep 11 07:19:38 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331171309 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3331171309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.4144501190 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 8380207145 ps |
| CPU time | 127.48 seconds |
| Started | Sep 11 07:19:30 PM UTC 24 |
| Finished | Sep 11 07:21:40 PM UTC 24 |
| Peak memory | 593704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144501190 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.4144501190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3867684861 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 4270905713 ps |
| CPU time | 96.26 seconds |
| Started | Sep 11 07:19:42 PM UTC 24 |
| Finished | Sep 11 07:21:20 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867684861 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3867684861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1342101731 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 53815508 ps |
| CPU time | 8.87 seconds |
| Started | Sep 11 07:19:29 PM UTC 24 |
| Finished | Sep 11 07:19:39 PM UTC 24 |
| Peak memory | 593876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342101731 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.1342101731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.1252436290 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 3149366628 ps |
| CPU time | 119.13 seconds |
| Started | Sep 11 07:21:56 PM UTC 24 |
| Finished | Sep 11 07:23:57 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252436290 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1252436290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.4222083727 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 5158029541 ps |
| CPU time | 173.28 seconds |
| Started | Sep 11 07:22:10 PM UTC 24 |
| Finished | Sep 11 07:25:06 PM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222083727 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.4222083727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2649322532 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 44690768 ps |
| CPU time | 38.5 seconds |
| Started | Sep 11 07:22:05 PM UTC 24 |
| Finished | Sep 11 07:22:45 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649322532 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.2649322532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.5911972 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 283256926 ps |
| CPU time | 103.18 seconds |
| Started | Sep 11 07:22:13 PM UTC 24 |
| Finished | Sep 11 07:23:59 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5911972 -assert nopostproc +UVM_TESTNAME=x bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.5911972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.4284948081 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 301853511 ps |
| CPU time | 38.53 seconds |
| Started | Sep 11 07:21:20 PM UTC 24 |
| Finished | Sep 11 07:22:00 PM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284948081 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.4284948081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.602208866 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 6377587448 ps |
| CPU time | 446.37 seconds |
| Started | Sep 11 07:25:19 PM UTC 24 |
| Finished | Sep 11 07:32:51 PM UTC 24 |
| Peak memory | 659988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=602208866 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.602208866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.2385243244 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 4505470980 ps |
| CPU time | 425.48 seconds |
| Started | Sep 11 07:25:17 PM UTC 24 |
| Finished | Sep 11 07:32:29 PM UTC 24 |
| Peak memory | 614920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385243244 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.2385243244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.3394543980 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 17339624539 ps |
| CPU time | 1825.68 seconds |
| Started | Sep 11 07:22:23 PM UTC 24 |
| Finished | Sep 11 07:53:11 PM UTC 24 |
| Peak memory | 610648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3394543980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.chip_same_csr_outstanding.3394543980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.3003884645 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 459451143 ps |
| CPU time | 31.78 seconds |
| Started | Sep 11 07:23:56 PM UTC 24 |
| Finished | Sep 11 07:24:29 PM UTC 24 |
| Peak memory | 595720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003884645 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.3003884645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.243420441 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 299641225 ps |
| CPU time | 17.18 seconds |
| Started | Sep 11 07:24:24 PM UTC 24 |
| Finished | Sep 11 07:24:43 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243420441 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.243420441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.2297180397 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 2615950599 ps |
| CPU time | 94.89 seconds |
| Started | Sep 11 07:24:24 PM UTC 24 |
| Finished | Sep 11 07:26:01 PM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297180397 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2297180397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.2718097011 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 2528700323 ps |
| CPU time | 98.99 seconds |
| Started | Sep 11 07:23:31 PM UTC 24 |
| Finished | Sep 11 07:25:12 PM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718097011 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.2718097011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.3284574882 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 24080267805 ps |
| CPU time | 287.29 seconds |
| Started | Sep 11 07:23:44 PM UTC 24 |
| Finished | Sep 11 07:28:35 PM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284574882 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3284574882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.2356753295 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 46472811325 ps |
| CPU time | 930.27 seconds |
| Started | Sep 11 07:23:44 PM UTC 24 |
| Finished | Sep 11 07:39:27 PM UTC 24 |
| Peak memory | 595984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356753295 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2356753295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.1787451050 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 52838069 ps |
| CPU time | 11.15 seconds |
| Started | Sep 11 07:23:35 PM UTC 24 |
| Finished | Sep 11 07:23:47 PM UTC 24 |
| Peak memory | 593656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787451050 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1787451050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.3620816124 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 1450515280 ps |
| CPU time | 44.19 seconds |
| Started | Sep 11 07:24:17 PM UTC 24 |
| Finished | Sep 11 07:25:03 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620816124 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3620816124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.3353702078 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 46109014 ps |
| CPU time | 8.99 seconds |
| Started | Sep 11 07:23:07 PM UTC 24 |
| Finished | Sep 11 07:23:18 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353702078 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.3353702078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.3557731537 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 7561697769 ps |
| CPU time | 121.23 seconds |
| Started | Sep 11 07:23:12 PM UTC 24 |
| Finished | Sep 11 07:25:16 PM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557731537 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3557731537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.485025673 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 6222522055 ps |
| CPU time | 98.76 seconds |
| Started | Sep 11 07:23:12 PM UTC 24 |
| Finished | Sep 11 07:24:53 PM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485025673 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.485025673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1248318982 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 42657090 ps |
| CPU time | 5.71 seconds |
| Started | Sep 11 07:23:12 PM UTC 24 |
| Finished | Sep 11 07:23:18 PM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248318982 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.1248318982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.2709807329 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 9846875633 ps |
| CPU time | 350.2 seconds |
| Started | Sep 11 07:24:30 PM UTC 24 |
| Finished | Sep 11 07:30:26 PM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709807329 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2709807329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.3317559176 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 1264461931 ps |
| CPU time | 82.13 seconds |
| Started | Sep 11 07:24:52 PM UTC 24 |
| Finished | Sep 11 07:26:16 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317559176 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3317559176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.770641412 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 1509541395 ps |
| CPU time | 303.78 seconds |
| Started | Sep 11 07:24:45 PM UTC 24 |
| Finished | Sep 11 07:29:53 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770641412 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.770641412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.13605524 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 7022562 ps |
| CPU time | 7.38 seconds |
| Started | Sep 11 07:25:08 PM UTC 24 |
| Finished | Sep 11 07:25:16 PM UTC 24 |
| Peak memory | 593568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13605524 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.13605524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.3774983309 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 519182623 ps |
| CPU time | 31.85 seconds |
| Started | Sep 11 07:24:23 PM UTC 24 |
| Finished | Sep 11 07:24:56 PM UTC 24 |
| Peak memory | 596032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774983309 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3774983309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.3010867575 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 9491942088 ps |
| CPU time | 1009.07 seconds |
| Started | Sep 11 07:28:19 PM UTC 24 |
| Finished | Sep 11 07:45:21 PM UTC 24 |
| Peak memory | 670108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3010867575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 14.chip_csr_mem_rw_with_rand_reset.3010867575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.3878550961 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 4382951000 ps |
| CPU time | 420.13 seconds |
| Started | Sep 11 07:28:18 PM UTC 24 |
| Finished | Sep 11 07:35:25 PM UTC 24 |
| Peak memory | 614884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878550961 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.3878550961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.2604307397 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 29336140994 ps |
| CPU time | 3456.88 seconds |
| Started | Sep 11 07:25:26 PM UTC 24 |
| Finished | Sep 11 08:23:44 PM UTC 24 |
| Peak memory | 613880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2604307397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.chip_same_csr_outstanding.2604307397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.2691441458 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 1350927272 ps |
| CPU time | 80.75 seconds |
| Started | Sep 11 07:26:31 PM UTC 24 |
| Finished | Sep 11 07:27:54 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691441458 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.2691441458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1125422582 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 28806952002 ps |
| CPU time | 423.4 seconds |
| Started | Sep 11 07:26:42 PM UTC 24 |
| Finished | Sep 11 07:33:52 PM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125422582 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.1125422582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2555802111 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 839307794 ps |
| CPU time | 39.68 seconds |
| Started | Sep 11 07:27:47 PM UTC 24 |
| Finished | Sep 11 07:28:28 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555802111 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2555802111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.2775184745 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 953034359 ps |
| CPU time | 46.65 seconds |
| Started | Sep 11 07:26:58 PM UTC 24 |
| Finished | Sep 11 07:27:46 PM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775184745 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2775184745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.1822166362 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 569112138 ps |
| CPU time | 22.66 seconds |
| Started | Sep 11 07:26:08 PM UTC 24 |
| Finished | Sep 11 07:26:32 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822166362 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.1822166362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.512410461 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 10976858930 ps |
| CPU time | 98.27 seconds |
| Started | Sep 11 07:26:13 PM UTC 24 |
| Finished | Sep 11 07:27:53 PM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512410461 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.512410461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.1502916826 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 23702556360 ps |
| CPU time | 313.1 seconds |
| Started | Sep 11 07:26:26 PM UTC 24 |
| Finished | Sep 11 07:31:43 PM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502916826 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1502916826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.3191883359 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 446818235 ps |
| CPU time | 38.66 seconds |
| Started | Sep 11 07:26:10 PM UTC 24 |
| Finished | Sep 11 07:26:50 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191883359 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.3191883359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.2364978851 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 735562093 ps |
| CPU time | 30.79 seconds |
| Started | Sep 11 07:26:50 PM UTC 24 |
| Finished | Sep 11 07:27:22 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364978851 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2364978851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.3535531986 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 125405247 ps |
| CPU time | 10.32 seconds |
| Started | Sep 11 07:25:31 PM UTC 24 |
| Finished | Sep 11 07:25:43 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535531986 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3535531986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.187701592 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 9188462686 ps |
| CPU time | 125.63 seconds |
| Started | Sep 11 07:25:36 PM UTC 24 |
| Finished | Sep 11 07:27:44 PM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187701592 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.187701592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.4155821567 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 6742769982 ps |
| CPU time | 123.56 seconds |
| Started | Sep 11 07:25:42 PM UTC 24 |
| Finished | Sep 11 07:27:48 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155821567 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.4155821567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3491527769 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 43089238 ps |
| CPU time | 8.51 seconds |
| Started | Sep 11 07:25:36 PM UTC 24 |
| Finished | Sep 11 07:25:45 PM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491527769 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.3491527769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.1333663151 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 3858297527 ps |
| CPU time | 131.79 seconds |
| Started | Sep 11 07:28:09 PM UTC 24 |
| Finished | Sep 11 07:30:23 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333663151 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1333663151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.1261912011 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 4710680018 ps |
| CPU time | 145.44 seconds |
| Started | Sep 11 07:28:11 PM UTC 24 |
| Finished | Sep 11 07:30:39 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261912011 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1261912011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3989646966 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 256536317 ps |
| CPU time | 65.55 seconds |
| Started | Sep 11 07:28:17 PM UTC 24 |
| Finished | Sep 11 07:29:24 PM UTC 24 |
| Peak memory | 596060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989646966 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.3989646966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.1783062228 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 655870063 ps |
| CPU time | 38.76 seconds |
| Started | Sep 11 07:27:15 PM UTC 24 |
| Finished | Sep 11 07:27:55 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783062228 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1783062228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.260356994 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 9391149900 ps |
| CPU time | 945.58 seconds |
| Started | Sep 11 07:31:28 PM UTC 24 |
| Finished | Sep 11 07:47:26 PM UTC 24 |
| Peak memory | 668180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=260356994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_mem_rw_with_rand_reset.260356994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.2982647326 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 4486583396 ps |
| CPU time | 347.26 seconds |
| Started | Sep 11 07:31:16 PM UTC 24 |
| Finished | Sep 11 07:37:09 PM UTC 24 |
| Peak memory | 614948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982647326 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.2982647326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.3241757635 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 15575770813 ps |
| CPU time | 2326.84 seconds |
| Started | Sep 11 07:28:36 PM UTC 24 |
| Finished | Sep 11 08:07:52 PM UTC 24 |
| Peak memory | 610928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3241757635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.chip_same_csr_outstanding.3241757635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.3049887215 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 3628317506 ps |
| CPU time | 181.43 seconds |
| Started | Sep 11 07:28:42 PM UTC 24 |
| Finished | Sep 11 07:31:46 PM UTC 24 |
| Peak memory | 620956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049887215 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.3049887215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.917093163 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 10652198651 ps |
| CPU time | 173.44 seconds |
| Started | Sep 11 07:30:41 PM UTC 24 |
| Finished | Sep 11 07:33:38 PM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917093163 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.917093163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2496382937 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 1101359793 ps |
| CPU time | 53.93 seconds |
| Started | Sep 11 07:30:51 PM UTC 24 |
| Finished | Sep 11 07:31:46 PM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496382937 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2496382937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.2658780367 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 404244691 ps |
| CPU time | 37.25 seconds |
| Started | Sep 11 07:30:45 PM UTC 24 |
| Finished | Sep 11 07:31:23 PM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658780367 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2658780367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.3947716418 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 534488082 ps |
| CPU time | 42.65 seconds |
| Started | Sep 11 07:29:35 PM UTC 24 |
| Finished | Sep 11 07:30:19 PM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947716418 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.3947716418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.4128393567 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 95453415494 ps |
| CPU time | 853.6 seconds |
| Started | Sep 11 07:29:56 PM UTC 24 |
| Finished | Sep 11 07:44:20 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128393567 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.4128393567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.3739326411 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 20906536996 ps |
| CPU time | 299.64 seconds |
| Started | Sep 11 07:30:18 PM UTC 24 |
| Finished | Sep 11 07:35:21 PM UTC 24 |
| Peak memory | 596012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739326411 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3739326411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.1956019254 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 221695637 ps |
| CPU time | 29.2 seconds |
| Started | Sep 11 07:29:50 PM UTC 24 |
| Finished | Sep 11 07:30:21 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956019254 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.1956019254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.2341280258 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 2382996076 ps |
| CPU time | 70.95 seconds |
| Started | Sep 11 07:30:44 PM UTC 24 |
| Finished | Sep 11 07:31:57 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341280258 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2341280258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.1829330471 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 249416808 ps |
| CPU time | 14.36 seconds |
| Started | Sep 11 07:28:54 PM UTC 24 |
| Finished | Sep 11 07:29:10 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829330471 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1829330471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.626612978 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 8215316073 ps |
| CPU time | 97.71 seconds |
| Started | Sep 11 07:29:24 PM UTC 24 |
| Finished | Sep 11 07:31:03 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626612978 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.626612978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3274695981 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 4607155758 ps |
| CPU time | 72.47 seconds |
| Started | Sep 11 07:29:34 PM UTC 24 |
| Finished | Sep 11 07:30:48 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274695981 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3274695981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.814193415 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 46380201 ps |
| CPU time | 5.78 seconds |
| Started | Sep 11 07:29:01 PM UTC 24 |
| Finished | Sep 11 07:29:08 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814193415 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.814193415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.4247060340 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 3509130186 ps |
| CPU time | 135.59 seconds |
| Started | Sep 11 07:30:51 PM UTC 24 |
| Finished | Sep 11 07:33:09 PM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247060340 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.4247060340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.2341340086 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 51513098 ps |
| CPU time | 10.99 seconds |
| Started | Sep 11 07:31:12 PM UTC 24 |
| Finished | Sep 11 07:31:25 PM UTC 24 |
| Peak memory | 596044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341340086 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2341340086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.4242783488 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 60558439 ps |
| CPU time | 37.5 seconds |
| Started | Sep 11 07:31:02 PM UTC 24 |
| Finished | Sep 11 07:31:41 PM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242783488 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.4242783488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.2975494656 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 2461614297 ps |
| CPU time | 110.69 seconds |
| Started | Sep 11 07:31:14 PM UTC 24 |
| Finished | Sep 11 07:33:08 PM UTC 24 |
| Peak memory | 596116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975494656 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.2975494656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.2226865202 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 1540821767 ps |
| CPU time | 72.81 seconds |
| Started | Sep 11 07:30:47 PM UTC 24 |
| Finished | Sep 11 07:32:01 PM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226865202 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2226865202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.3093801159 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 6268906740 ps |
| CPU time | 585.93 seconds |
| Started | Sep 11 07:33:30 PM UTC 24 |
| Finished | Sep 11 07:43:24 PM UTC 24 |
| Peak memory | 656012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3093801159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 16.chip_csr_mem_rw_with_rand_reset.3093801159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.1376111502 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 5207784240 ps |
| CPU time | 365.1 seconds |
| Started | Sep 11 07:33:25 PM UTC 24 |
| Finished | Sep 11 07:39:35 PM UTC 24 |
| Peak memory | 614680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376111502 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.1376111502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.35099736 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 28200519415 ps |
| CPU time | 3518.06 seconds |
| Started | Sep 11 07:31:35 PM UTC 24 |
| Finished | Sep 11 08:30:54 PM UTC 24 |
| Peak memory | 614028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=35099736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 16.chip_same_csr_outstanding.35099736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.2895480617 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 2826306120 ps |
| CPU time | 129.1 seconds |
| Started | Sep 11 07:31:45 PM UTC 24 |
| Finished | Sep 11 07:33:57 PM UTC 24 |
| Peak memory | 619052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895480617 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.2895480617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.1243031384 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 928764993 ps |
| CPU time | 71.84 seconds |
| Started | Sep 11 07:32:22 PM UTC 24 |
| Finished | Sep 11 07:33:35 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243031384 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.1243031384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.3094477795 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 13553628759 ps |
| CPU time | 241.28 seconds |
| Started | Sep 11 07:32:26 PM UTC 24 |
| Finished | Sep 11 07:36:31 PM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094477795 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.3094477795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1957602470 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 306824633 ps |
| CPU time | 24.32 seconds |
| Started | Sep 11 07:33:00 PM UTC 24 |
| Finished | Sep 11 07:33:26 PM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957602470 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1957602470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.1039749411 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 542487129 ps |
| CPU time | 52.53 seconds |
| Started | Sep 11 07:32:51 PM UTC 24 |
| Finished | Sep 11 07:33:46 PM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039749411 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1039749411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.1517363207 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 923235933 ps |
| CPU time | 39.63 seconds |
| Started | Sep 11 07:32:08 PM UTC 24 |
| Finished | Sep 11 07:32:49 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517363207 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.1517363207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.2144833252 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 93998513838 ps |
| CPU time | 1241.43 seconds |
| Started | Sep 11 07:32:13 PM UTC 24 |
| Finished | Sep 11 07:53:10 PM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144833252 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2144833252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.153868087 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 40809367325 ps |
| CPU time | 668.03 seconds |
| Started | Sep 11 07:32:23 PM UTC 24 |
| Finished | Sep 11 07:43:39 PM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153868087 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.153868087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.397215909 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 520862724 ps |
| CPU time | 42.08 seconds |
| Started | Sep 11 07:32:11 PM UTC 24 |
| Finished | Sep 11 07:32:54 PM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397215909 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.397215909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.493831291 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 560108300 ps |
| CPU time | 49.69 seconds |
| Started | Sep 11 07:32:24 PM UTC 24 |
| Finished | Sep 11 07:33:16 PM UTC 24 |
| Peak memory | 596044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493831291 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.493831291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.1901918446 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 48771191 ps |
| CPU time | 9.5 seconds |
| Started | Sep 11 07:31:49 PM UTC 24 |
| Finished | Sep 11 07:31:59 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901918446 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1901918446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.2220453502 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 9447599792 ps |
| CPU time | 132.72 seconds |
| Started | Sep 11 07:32:04 PM UTC 24 |
| Finished | Sep 11 07:34:19 PM UTC 24 |
| Peak memory | 593704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220453502 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2220453502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.2746994540 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 5033499341 ps |
| CPU time | 85.1 seconds |
| Started | Sep 11 07:32:08 PM UTC 24 |
| Finished | Sep 11 07:33:35 PM UTC 24 |
| Peak memory | 593900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746994540 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2746994540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.1527347809 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 52889390 ps |
| CPU time | 10.55 seconds |
| Started | Sep 11 07:31:50 PM UTC 24 |
| Finished | Sep 11 07:32:01 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527347809 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.1527347809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.4126955918 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 3073184259 ps |
| CPU time | 136.5 seconds |
| Started | Sep 11 07:33:14 PM UTC 24 |
| Finished | Sep 11 07:35:33 PM UTC 24 |
| Peak memory | 596096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126955918 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.4126955918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.1029735350 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 2123918842 ps |
| CPU time | 150.52 seconds |
| Started | Sep 11 07:33:17 PM UTC 24 |
| Finished | Sep 11 07:35:51 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029735350 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1029735350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.4184843021 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 2946069354 ps |
| CPU time | 315.3 seconds |
| Started | Sep 11 07:33:16 PM UTC 24 |
| Finished | Sep 11 07:38:36 PM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184843021 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.4184843021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.75703519 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 2379365706 ps |
| CPU time | 374 seconds |
| Started | Sep 11 07:33:26 PM UTC 24 |
| Finished | Sep 11 07:39:45 PM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75703519 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.75703519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.1085802130 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 340075809 ps |
| CPU time | 51.76 seconds |
| Started | Sep 11 07:32:54 PM UTC 24 |
| Finished | Sep 11 07:33:48 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085802130 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1085802130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.3583247890 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 7371465064 ps |
| CPU time | 519.71 seconds |
| Started | Sep 11 07:35:49 PM UTC 24 |
| Finished | Sep 11 07:44:36 PM UTC 24 |
| Peak memory | 660184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3583247890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 17.chip_csr_mem_rw_with_rand_reset.3583247890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.730647366 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 5824200030 ps |
| CPU time | 523.23 seconds |
| Started | Sep 11 07:35:44 PM UTC 24 |
| Finished | Sep 11 07:44:35 PM UTC 24 |
| Peak memory | 618776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730647366 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.730647366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.1852525379 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 15188526220 ps |
| CPU time | 2019.22 seconds |
| Started | Sep 11 07:33:35 PM UTC 24 |
| Finished | Sep 11 08:07:40 PM UTC 24 |
| Peak memory | 610652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1852525379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 17.chip_same_csr_outstanding.1852525379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.1381617077 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 2344069697 ps |
| CPU time | 100.39 seconds |
| Started | Sep 11 07:34:32 PM UTC 24 |
| Finished | Sep 11 07:36:15 PM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381617077 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.1381617077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.2490932868 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 40487879855 ps |
| CPU time | 534.58 seconds |
| Started | Sep 11 07:34:31 PM UTC 24 |
| Finished | Sep 11 07:43:33 PM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490932868 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.2490932868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.229388155 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 117125676 ps |
| CPU time | 15.67 seconds |
| Started | Sep 11 07:35:23 PM UTC 24 |
| Finished | Sep 11 07:35:40 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229388155 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.229388155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.83108446 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 374000614 ps |
| CPU time | 20.47 seconds |
| Started | Sep 11 07:35:00 PM UTC 24 |
| Finished | Sep 11 07:35:21 PM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83108446 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.83108446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.2660287580 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 2156146611 ps |
| CPU time | 105.52 seconds |
| Started | Sep 11 07:34:09 PM UTC 24 |
| Finished | Sep 11 07:35:57 PM UTC 24 |
| Peak memory | 595920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660287580 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.2660287580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.2167842149 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 43231604023 ps |
| CPU time | 414.12 seconds |
| Started | Sep 11 07:34:16 PM UTC 24 |
| Finished | Sep 11 07:41:15 PM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167842149 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2167842149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.3165497884 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 40634563341 ps |
| CPU time | 615.36 seconds |
| Started | Sep 11 07:34:22 PM UTC 24 |
| Finished | Sep 11 07:44:46 PM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165497884 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3165497884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.690401951 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 209533746 ps |
| CPU time | 20.35 seconds |
| Started | Sep 11 07:34:13 PM UTC 24 |
| Finished | Sep 11 07:34:34 PM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690401951 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.690401951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.2210130207 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 188365818 ps |
| CPU time | 14.27 seconds |
| Started | Sep 11 07:34:44 PM UTC 24 |
| Finished | Sep 11 07:34:59 PM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210130207 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2210130207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.2519756865 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 234900362 ps |
| CPU time | 16.08 seconds |
| Started | Sep 11 07:33:49 PM UTC 24 |
| Finished | Sep 11 07:34:06 PM UTC 24 |
| Peak memory | 593860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519756865 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2519756865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.921355192 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 8211502163 ps |
| CPU time | 87.43 seconds |
| Started | Sep 11 07:33:59 PM UTC 24 |
| Finished | Sep 11 07:35:28 PM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921355192 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.921355192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.1934883372 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 3538717897 ps |
| CPU time | 69.37 seconds |
| Started | Sep 11 07:34:02 PM UTC 24 |
| Finished | Sep 11 07:35:14 PM UTC 24 |
| Peak memory | 593784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934883372 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1934883372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.3355042056 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 45291221 ps |
| CPU time | 6.03 seconds |
| Started | Sep 11 07:33:59 PM UTC 24 |
| Finished | Sep 11 07:34:06 PM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355042056 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3355042056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.241383535 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 686646395 ps |
| CPU time | 36.62 seconds |
| Started | Sep 11 07:35:36 PM UTC 24 |
| Finished | Sep 11 07:36:14 PM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241383535 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.241383535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.3676046658 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 6994097238 ps |
| CPU time | 326.6 seconds |
| Started | Sep 11 07:35:46 PM UTC 24 |
| Finished | Sep 11 07:41:18 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676046658 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3676046658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.2650932791 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 449425172 ps |
| CPU time | 300.27 seconds |
| Started | Sep 11 07:35:38 PM UTC 24 |
| Finished | Sep 11 07:40:43 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650932791 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.2650932791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.2683670173 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 3217096023 ps |
| CPU time | 198.82 seconds |
| Started | Sep 11 07:35:46 PM UTC 24 |
| Finished | Sep 11 07:39:09 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683670173 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.2683670173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.646812625 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 43507779 ps |
| CPU time | 10.27 seconds |
| Started | Sep 11 07:35:03 PM UTC 24 |
| Finished | Sep 11 07:35:14 PM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646812625 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.646812625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.868663123 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 6937843202 ps |
| CPU time | 661.83 seconds |
| Started | Sep 11 07:39:01 PM UTC 24 |
| Finished | Sep 11 07:50:12 PM UTC 24 |
| Peak memory | 653980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=868663123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.868663123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.1088348072 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 4523792289 ps |
| CPU time | 308.97 seconds |
| Started | Sep 11 07:38:52 PM UTC 24 |
| Finished | Sep 11 07:44:05 PM UTC 24 |
| Peak memory | 616856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088348072 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.1088348072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.1347748705 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 30959076254 ps |
| CPU time | 3518.82 seconds |
| Started | Sep 11 07:35:52 PM UTC 24 |
| Finished | Sep 11 08:35:12 PM UTC 24 |
| Peak memory | 613960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1347748705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.chip_same_csr_outstanding.1347748705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.1460035945 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 3703094056 ps |
| CPU time | 254.6 seconds |
| Started | Sep 11 07:35:58 PM UTC 24 |
| Finished | Sep 11 07:40:17 PM UTC 24 |
| Peak memory | 619164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460035945 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.1460035945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.3034489237 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 482865054 ps |
| CPU time | 32.91 seconds |
| Started | Sep 11 07:37:09 PM UTC 24 |
| Finished | Sep 11 07:37:43 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034489237 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3034489237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3752683047 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 134497075034 ps |
| CPU time | 2415.94 seconds |
| Started | Sep 11 07:37:14 PM UTC 24 |
| Finished | Sep 11 08:17:59 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752683047 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.3752683047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.4138793114 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 280212933 ps |
| CPU time | 39.24 seconds |
| Started | Sep 11 07:38:04 PM UTC 24 |
| Finished | Sep 11 07:38:45 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138793114 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.4138793114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.2689399031 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 426564857 ps |
| CPU time | 40.49 seconds |
| Started | Sep 11 07:37:35 PM UTC 24 |
| Finished | Sep 11 07:38:16 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689399031 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2689399031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.585637196 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 587195058 ps |
| CPU time | 54.13 seconds |
| Started | Sep 11 07:36:39 PM UTC 24 |
| Finished | Sep 11 07:37:35 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585637196 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.585637196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.1797261505 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 49329636630 ps |
| CPU time | 572.15 seconds |
| Started | Sep 11 07:36:52 PM UTC 24 |
| Finished | Sep 11 07:46:32 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797261505 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1797261505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.1864914904 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 41682753095 ps |
| CPU time | 596.25 seconds |
| Started | Sep 11 07:36:56 PM UTC 24 |
| Finished | Sep 11 07:47:00 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864914904 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1864914904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.3551813831 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 94041116 ps |
| CPU time | 13.91 seconds |
| Started | Sep 11 07:36:42 PM UTC 24 |
| Finished | Sep 11 07:36:57 PM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551813831 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3551813831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.3444036351 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 516727152 ps |
| CPU time | 17.63 seconds |
| Started | Sep 11 07:37:20 PM UTC 24 |
| Finished | Sep 11 07:37:39 PM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444036351 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3444036351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.2070770415 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 221711314 ps |
| CPU time | 9.53 seconds |
| Started | Sep 11 07:36:06 PM UTC 24 |
| Finished | Sep 11 07:36:17 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070770415 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2070770415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.3834477700 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 8768268914 ps |
| CPU time | 88.47 seconds |
| Started | Sep 11 07:36:22 PM UTC 24 |
| Finished | Sep 11 07:37:53 PM UTC 24 |
| Peak memory | 593952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834477700 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3834477700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.2440687783 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 5631693650 ps |
| CPU time | 94.48 seconds |
| Started | Sep 11 07:36:40 PM UTC 24 |
| Finished | Sep 11 07:38:17 PM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440687783 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2440687783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.3534427989 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 53492031 ps |
| CPU time | 9.82 seconds |
| Started | Sep 11 07:36:16 PM UTC 24 |
| Finished | Sep 11 07:36:27 PM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534427989 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3534427989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.3846257401 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 9680775336 ps |
| CPU time | 368.69 seconds |
| Started | Sep 11 07:38:07 PM UTC 24 |
| Finished | Sep 11 07:44:21 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846257401 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.3846257401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.1335213477 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 1839749185 ps |
| CPU time | 142.08 seconds |
| Started | Sep 11 07:38:42 PM UTC 24 |
| Finished | Sep 11 07:41:07 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335213477 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1335213477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.1928004220 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 276642263 ps |
| CPU time | 95.99 seconds |
| Started | Sep 11 07:38:18 PM UTC 24 |
| Finished | Sep 11 07:39:56 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928004220 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.1928004220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.2251631692 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 398523008 ps |
| CPU time | 95.81 seconds |
| Started | Sep 11 07:38:42 PM UTC 24 |
| Finished | Sep 11 07:40:20 PM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251631692 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.2251631692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.2302960037 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 1301809026 ps |
| CPU time | 58.54 seconds |
| Started | Sep 11 07:38:01 PM UTC 24 |
| Finished | Sep 11 07:39:01 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302960037 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2302960037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.3732291260 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 7261655117 ps |
| CPU time | 577.9 seconds |
| Started | Sep 11 07:41:41 PM UTC 24 |
| Finished | Sep 11 07:51:27 PM UTC 24 |
| Peak memory | 661916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3732291260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 19.chip_csr_mem_rw_with_rand_reset.3732291260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.19941170 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 4293548226 ps |
| CPU time | 367.32 seconds |
| Started | Sep 11 07:41:43 PM UTC 24 |
| Finished | Sep 11 07:47:55 PM UTC 24 |
| Peak memory | 616976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19941170 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.19941170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.2856115490 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 15138062192 ps |
| CPU time | 1687 seconds |
| Started | Sep 11 07:39:10 PM UTC 24 |
| Finished | Sep 11 08:07:38 PM UTC 24 |
| Peak memory | 610800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2856115490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.chip_same_csr_outstanding.2856115490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.3035838578 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 2892420744 ps |
| CPU time | 186.1 seconds |
| Started | Sep 11 07:39:11 PM UTC 24 |
| Finished | Sep 11 07:42:20 PM UTC 24 |
| Peak memory | 619284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035838578 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.3035838578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.2883381619 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 1664258970 ps |
| CPU time | 86.28 seconds |
| Started | Sep 11 07:40:28 PM UTC 24 |
| Finished | Sep 11 07:41:56 PM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883381619 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.2883381619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.3880184880 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 58688500797 ps |
| CPU time | 977.7 seconds |
| Started | Sep 11 07:40:42 PM UTC 24 |
| Finished | Sep 11 07:57:12 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880184880 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.3880184880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.3759584315 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 1116144503 ps |
| CPU time | 45.1 seconds |
| Started | Sep 11 07:41:18 PM UTC 24 |
| Finished | Sep 11 07:42:05 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759584315 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3759584315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.2090859566 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 646302170 ps |
| CPU time | 20.03 seconds |
| Started | Sep 11 07:40:48 PM UTC 24 |
| Finished | Sep 11 07:41:09 PM UTC 24 |
| Peak memory | 595940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090859566 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2090859566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.1636397856 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 433230930 ps |
| CPU time | 51.96 seconds |
| Started | Sep 11 07:40:02 PM UTC 24 |
| Finished | Sep 11 07:40:56 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636397856 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.1636397856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.2544408329 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 81045068887 ps |
| CPU time | 812.82 seconds |
| Started | Sep 11 07:40:10 PM UTC 24 |
| Finished | Sep 11 07:53:54 PM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544408329 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2544408329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.3731904201 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 46174491147 ps |
| CPU time | 684.03 seconds |
| Started | Sep 11 07:40:18 PM UTC 24 |
| Finished | Sep 11 07:51:51 PM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731904201 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3731904201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.3198896055 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 76760491 ps |
| CPU time | 12.75 seconds |
| Started | Sep 11 07:40:10 PM UTC 24 |
| Finished | Sep 11 07:40:23 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198896055 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.3198896055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.932457750 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 141784859 ps |
| CPU time | 17.97 seconds |
| Started | Sep 11 07:40:46 PM UTC 24 |
| Finished | Sep 11 07:41:06 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932457750 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.932457750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.2030180788 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 173372612 ps |
| CPU time | 12.18 seconds |
| Started | Sep 11 07:39:24 PM UTC 24 |
| Finished | Sep 11 07:39:37 PM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030180788 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2030180788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.160695224 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 6408201484 ps |
| CPU time | 99.32 seconds |
| Started | Sep 11 07:39:52 PM UTC 24 |
| Finished | Sep 11 07:41:33 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160695224 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.160695224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2433549965 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 6729027504 ps |
| CPU time | 163.1 seconds |
| Started | Sep 11 07:40:00 PM UTC 24 |
| Finished | Sep 11 07:42:46 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433549965 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2433549965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.1505457971 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 47205144 ps |
| CPU time | 9.65 seconds |
| Started | Sep 11 07:39:33 PM UTC 24 |
| Finished | Sep 11 07:39:44 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505457971 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1505457971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.1871325867 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 3811553234 ps |
| CPU time | 377.78 seconds |
| Started | Sep 11 07:41:29 PM UTC 24 |
| Finished | Sep 11 07:47:52 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871325867 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1871325867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.418196710 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 2306602609 ps |
| CPU time | 177.5 seconds |
| Started | Sep 11 07:41:33 PM UTC 24 |
| Finished | Sep 11 07:44:34 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418196710 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.418196710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2898257417 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 716848290 ps |
| CPU time | 350.88 seconds |
| Started | Sep 11 07:41:32 PM UTC 24 |
| Finished | Sep 11 07:47:28 PM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898257417 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.2898257417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.3605671811 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 158398154 ps |
| CPU time | 8.83 seconds |
| Started | Sep 11 07:41:08 PM UTC 24 |
| Finished | Sep 11 07:41:18 PM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605671811 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3605671811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_aliasing.1486610290 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 40406534312 ps |
| CPU time | 6268.03 seconds |
| Started | Sep 11 06:55:43 PM UTC 24 |
| Finished | Sep 11 08:41:23 PM UTC 24 |
| Peak memory | 620060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1486610290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_ csr_aliasing.1486610290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_bit_bash.2969410123 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 8772289634 ps |
| CPU time | 911.59 seconds |
| Started | Sep 11 06:55:43 PM UTC 24 |
| Finished | Sep 11 07:11:07 PM UTC 24 |
| Peak memory | 616732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2969410123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.chip_csr_bit_bash.2969410123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.2844943565 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 10887633998 ps |
| CPU time | 876.87 seconds |
| Started | Sep 11 06:57:59 PM UTC 24 |
| Finished | Sep 11 07:12:47 PM UTC 24 |
| Peak memory | 670364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2844943565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.chip_csr_mem_rw_with_rand_reset.2844943565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.2406508408 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 6603473250 ps |
| CPU time | 574.64 seconds |
| Started | Sep 11 06:57:49 PM UTC 24 |
| Finished | Sep 11 07:07:31 PM UTC 24 |
| Peak memory | 618776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406508408 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.2406508408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.4170589431 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 6286486330 ps |
| CPU time | 238.41 seconds |
| Started | Sep 11 06:55:48 PM UTC 24 |
| Finished | Sep 11 06:59:50 PM UTC 24 |
| Peak memory | 606632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170589431 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.4170589431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_prim_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.2883606270 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 10331689587 ps |
| CPU time | 441.63 seconds |
| Started | Sep 11 06:56:06 PM UTC 24 |
| Finished | Sep 11 07:03:34 PM UTC 24 |
| Peak memory | 606672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_c pu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2883606270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. chip_rv_dm_lc_disabled.2883606270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.3621617845 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 27905094891 ps |
| CPU time | 3628.06 seconds |
| Started | Sep 11 06:55:43 PM UTC 24 |
| Finished | Sep 11 07:56:54 PM UTC 24 |
| Peak memory | 613948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3621617845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.chip_same_csr_outstanding.3621617845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.583367649 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 3004194184 ps |
| CPU time | 171.85 seconds |
| Started | Sep 11 06:55:47 PM UTC 24 |
| Finished | Sep 11 06:58:41 PM UTC 24 |
| Peak memory | 621204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583367649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.583367649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.282770451 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 1446178138 ps |
| CPU time | 81.53 seconds |
| Started | Sep 11 06:56:36 PM UTC 24 |
| Finished | Sep 11 06:58:01 PM UTC 24 |
| Peak memory | 596076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282770451 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.282770451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.360452449 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 193988610 ps |
| CPU time | 16.47 seconds |
| Started | Sep 11 06:57:17 PM UTC 24 |
| Finished | Sep 11 06:57:35 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360452449 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.360452449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.1710146532 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 631939023 ps |
| CPU time | 23.49 seconds |
| Started | Sep 11 06:57:00 PM UTC 24 |
| Finished | Sep 11 06:57:25 PM UTC 24 |
| Peak memory | 596116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710146532 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1710146532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.2308792437 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 521183438 ps |
| CPU time | 55.58 seconds |
| Started | Sep 11 06:56:11 PM UTC 24 |
| Finished | Sep 11 06:57:08 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308792437 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.2308792437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.2277460739 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 66265752391 ps |
| CPU time | 680.8 seconds |
| Started | Sep 11 06:56:15 PM UTC 24 |
| Finished | Sep 11 07:07:44 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277460739 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2277460739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.3498768936 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 45202281389 ps |
| CPU time | 750.09 seconds |
| Started | Sep 11 06:56:29 PM UTC 24 |
| Finished | Sep 11 07:09:09 PM UTC 24 |
| Peak memory | 596148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498768936 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3498768936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.1707802047 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 356417896 ps |
| CPU time | 29.78 seconds |
| Started | Sep 11 06:56:15 PM UTC 24 |
| Finished | Sep 11 06:56:46 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707802047 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.1707802047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.2429054614 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 83384466 ps |
| CPU time | 13.11 seconds |
| Started | Sep 11 06:56:42 PM UTC 24 |
| Finished | Sep 11 06:56:57 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429054614 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2429054614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.1998037310 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 199874257 ps |
| CPU time | 10.01 seconds |
| Started | Sep 11 06:56:05 PM UTC 24 |
| Finished | Sep 11 06:56:16 PM UTC 24 |
| Peak memory | 593900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998037310 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1998037310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.298587621 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 7042209786 ps |
| CPU time | 111.15 seconds |
| Started | Sep 11 06:56:11 PM UTC 24 |
| Finished | Sep 11 06:58:05 PM UTC 24 |
| Peak memory | 594040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298587621 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.298587621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.1957958112 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 4646468831 ps |
| CPU time | 73.41 seconds |
| Started | Sep 11 06:56:10 PM UTC 24 |
| Finished | Sep 11 06:57:25 PM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957958112 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1957958112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.226615675 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 47896459 ps |
| CPU time | 8.48 seconds |
| Started | Sep 11 06:56:06 PM UTC 24 |
| Finished | Sep 11 06:56:16 PM UTC 24 |
| Peak memory | 593812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226615675 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.226615675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.995202937 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1689387049 ps |
| CPU time | 61.77 seconds |
| Started | Sep 11 06:57:16 PM UTC 24 |
| Finished | Sep 11 06:58:20 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995202937 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.995202937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.46094752 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1226722950 ps |
| CPU time | 255.79 seconds |
| Started | Sep 11 06:57:21 PM UTC 24 |
| Finished | Sep 11 07:01:41 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46094752 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.46094752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.4092173773 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 71818896 ps |
| CPU time | 29.27 seconds |
| Started | Sep 11 06:57:34 PM UTC 24 |
| Finished | Sep 11 06:58:05 PM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092173773 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.4092173773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.1925101871 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 290876630 ps |
| CPU time | 45.16 seconds |
| Started | Sep 11 06:57:10 PM UTC 24 |
| Finished | Sep 11 06:57:57 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925101871 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1925101871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.2649418209 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 2572596814 ps |
| CPU time | 117.29 seconds |
| Started | Sep 11 07:41:54 PM UTC 24 |
| Finished | Sep 11 07:43:53 PM UTC 24 |
| Peak memory | 621008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649418209 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.2649418209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/20.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.271553935 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1315152711 ps |
| CPU time | 43.13 seconds |
| Started | Sep 11 07:43:26 PM UTC 24 |
| Finished | Sep 11 07:44:11 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271553935 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.271553935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/20.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.3447129430 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 150889893496 ps |
| CPU time | 2122.69 seconds |
| Started | Sep 11 07:43:40 PM UTC 24 |
| Finished | Sep 11 08:19:27 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447129430 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.3447129430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.3872677366 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 51781392 ps |
| CPU time | 11.68 seconds |
| Started | Sep 11 07:44:05 PM UTC 24 |
| Finished | Sep 11 07:44:17 PM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872677366 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.3872677366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.2850191578 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 2109990154 ps |
| CPU time | 86.4 seconds |
| Started | Sep 11 07:43:47 PM UTC 24 |
| Finished | Sep 11 07:45:16 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850191578 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.2850191578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/20.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.3672904762 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 741867879 ps |
| CPU time | 36.88 seconds |
| Started | Sep 11 07:42:38 PM UTC 24 |
| Finished | Sep 11 07:43:16 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672904762 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.3672904762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/20.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.1531125764 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 106532002205 ps |
| CPU time | 1028.26 seconds |
| Started | Sep 11 07:42:57 PM UTC 24 |
| Finished | Sep 11 08:00:17 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531125764 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1531125764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/20.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.984075726 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 44108535982 ps |
| CPU time | 571.36 seconds |
| Started | Sep 11 07:43:12 PM UTC 24 |
| Finished | Sep 11 07:52:50 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984075726 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.984075726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/20.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.3383008585 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 71641226 ps |
| CPU time | 13.24 seconds |
| Started | Sep 11 07:42:46 PM UTC 24 |
| Finished | Sep 11 07:43:00 PM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383008585 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.3383008585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/20.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.3786531288 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 2561497598 ps |
| CPU time | 82.06 seconds |
| Started | Sep 11 07:43:47 PM UTC 24 |
| Finished | Sep 11 07:45:11 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786531288 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3786531288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/20.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.1989669082 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 40562969 ps |
| CPU time | 8.66 seconds |
| Started | Sep 11 07:41:58 PM UTC 24 |
| Finished | Sep 11 07:42:08 PM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989669082 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1989669082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/20.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.2748601141 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 8736067518 ps |
| CPU time | 106.42 seconds |
| Started | Sep 11 07:42:31 PM UTC 24 |
| Finished | Sep 11 07:44:20 PM UTC 24 |
| Peak memory | 593776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748601141 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2748601141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/20.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.886619200 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 3418749095 ps |
| CPU time | 70.88 seconds |
| Started | Sep 11 07:42:33 PM UTC 24 |
| Finished | Sep 11 07:43:46 PM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886619200 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.886619200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.2364519424 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 55494951 ps |
| CPU time | 9.91 seconds |
| Started | Sep 11 07:42:20 PM UTC 24 |
| Finished | Sep 11 07:42:31 PM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364519424 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.2364519424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/20.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.3267802709 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 669373004 ps |
| CPU time | 28.88 seconds |
| Started | Sep 11 07:44:09 PM UTC 24 |
| Finished | Sep 11 07:44:40 PM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267802709 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3267802709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/20.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.1222477762 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 1113945656 ps |
| CPU time | 72.81 seconds |
| Started | Sep 11 07:44:30 PM UTC 24 |
| Finished | Sep 11 07:45:45 PM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222477762 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1222477762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/20.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.200967750 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 314425873 ps |
| CPU time | 71.43 seconds |
| Started | Sep 11 07:44:19 PM UTC 24 |
| Finished | Sep 11 07:45:32 PM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200967750 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.200967750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.2236123808 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 13022693984 ps |
| CPU time | 544.39 seconds |
| Started | Sep 11 07:44:35 PM UTC 24 |
| Finished | Sep 11 07:53:47 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236123808 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.2236123808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.4022218264 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 1394823116 ps |
| CPU time | 59.1 seconds |
| Started | Sep 11 07:43:57 PM UTC 24 |
| Finished | Sep 11 07:44:58 PM UTC 24 |
| Peak memory | 596080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022218264 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.4022218264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/20.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.4164776673 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 3214740304 ps |
| CPU time | 167.89 seconds |
| Started | Sep 11 07:44:39 PM UTC 24 |
| Finished | Sep 11 07:47:30 PM UTC 24 |
| Peak memory | 620956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164776673 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.4164776673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/21.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.2604546642 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 1127344909 ps |
| CPU time | 76.91 seconds |
| Started | Sep 11 07:45:20 PM UTC 24 |
| Finished | Sep 11 07:46:39 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604546642 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.2604546642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/21.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.888632657 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 136859705421 ps |
| CPU time | 1946.56 seconds |
| Started | Sep 11 07:45:21 PM UTC 24 |
| Finished | Sep 11 08:18:10 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888632657 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.888632657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.3571970109 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 108057430 ps |
| CPU time | 9.95 seconds |
| Started | Sep 11 07:45:38 PM UTC 24 |
| Finished | Sep 11 07:45:49 PM UTC 24 |
| Peak memory | 593780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571970109 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.3571970109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.919034171 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 774490569 ps |
| CPU time | 30.31 seconds |
| Started | Sep 11 07:45:32 PM UTC 24 |
| Finished | Sep 11 07:46:04 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919034171 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.919034171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/21.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.3592253747 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 250442925 ps |
| CPU time | 13.09 seconds |
| Started | Sep 11 07:44:59 PM UTC 24 |
| Finished | Sep 11 07:45:13 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592253747 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.3592253747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/21.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.671013251 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 73109454000 ps |
| CPU time | 798.75 seconds |
| Started | Sep 11 07:45:05 PM UTC 24 |
| Finished | Sep 11 07:58:34 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671013251 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.671013251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/21.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.3692054425 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 3869343707 ps |
| CPU time | 51.45 seconds |
| Started | Sep 11 07:45:08 PM UTC 24 |
| Finished | Sep 11 07:46:01 PM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692054425 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3692054425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/21.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.2789708735 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 58927615 ps |
| CPU time | 8.8 seconds |
| Started | Sep 11 07:44:58 PM UTC 24 |
| Finished | Sep 11 07:45:08 PM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789708735 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.2789708735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/21.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.2052464139 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 640514473 ps |
| CPU time | 25.04 seconds |
| Started | Sep 11 07:45:25 PM UTC 24 |
| Finished | Sep 11 07:45:51 PM UTC 24 |
| Peak memory | 595684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052464139 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2052464139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/21.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.1855350793 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 205754601 ps |
| CPU time | 12.71 seconds |
| Started | Sep 11 07:44:43 PM UTC 24 |
| Finished | Sep 11 07:44:57 PM UTC 24 |
| Peak memory | 593860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855350793 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1855350793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/21.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.717079530 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 4903026898 ps |
| CPU time | 48.36 seconds |
| Started | Sep 11 07:44:45 PM UTC 24 |
| Finished | Sep 11 07:45:35 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717079530 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.717079530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/21.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.3074209432 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 4278412214 ps |
| CPU time | 68.64 seconds |
| Started | Sep 11 07:44:56 PM UTC 24 |
| Finished | Sep 11 07:46:06 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074209432 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3074209432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.3166408055 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 52531690 ps |
| CPU time | 8.84 seconds |
| Started | Sep 11 07:44:44 PM UTC 24 |
| Finished | Sep 11 07:44:54 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166408055 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3166408055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/21.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.1340289569 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 6143471876 ps |
| CPU time | 230.01 seconds |
| Started | Sep 11 07:45:39 PM UTC 24 |
| Finished | Sep 11 07:49:33 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340289569 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1340289569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/21.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.2089608823 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 959110872 ps |
| CPU time | 77.46 seconds |
| Started | Sep 11 07:45:57 PM UTC 24 |
| Finished | Sep 11 07:47:16 PM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089608823 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2089608823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/21.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.3468163825 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 3233503734 ps |
| CPU time | 475.3 seconds |
| Started | Sep 11 07:45:46 PM UTC 24 |
| Finished | Sep 11 07:53:48 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468163825 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.3468163825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.825173560 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 11603637277 ps |
| CPU time | 624.37 seconds |
| Started | Sep 11 07:46:01 PM UTC 24 |
| Finished | Sep 11 07:56:33 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825173560 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.825173560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.949922703 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 563881642 ps |
| CPU time | 28.35 seconds |
| Started | Sep 11 07:45:37 PM UTC 24 |
| Finished | Sep 11 07:46:06 PM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949922703 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.949922703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/21.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.3024734954 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 3097086188 ps |
| CPU time | 180.81 seconds |
| Started | Sep 11 07:46:10 PM UTC 24 |
| Finished | Sep 11 07:49:14 PM UTC 24 |
| Peak memory | 620952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024734954 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.3024734954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/22.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.2870754393 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 922295236 ps |
| CPU time | 49.91 seconds |
| Started | Sep 11 07:46:50 PM UTC 24 |
| Finished | Sep 11 07:47:41 PM UTC 24 |
| Peak memory | 595920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870754393 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.2870754393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/22.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.2701813467 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 15287850707 ps |
| CPU time | 229.13 seconds |
| Started | Sep 11 07:46:50 PM UTC 24 |
| Finished | Sep 11 07:50:43 PM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701813467 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.2701813467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.2491247299 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 736771558 ps |
| CPU time | 35.84 seconds |
| Started | Sep 11 07:47:40 PM UTC 24 |
| Finished | Sep 11 07:48:17 PM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491247299 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.2491247299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.1218668696 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 1073442857 ps |
| CPU time | 38.55 seconds |
| Started | Sep 11 07:47:03 PM UTC 24 |
| Finished | Sep 11 07:47:43 PM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218668696 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1218668696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/22.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.665597449 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 1716252112 ps |
| CPU time | 55.15 seconds |
| Started | Sep 11 07:46:32 PM UTC 24 |
| Finished | Sep 11 07:47:29 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665597449 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.665597449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/22.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.2183644932 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 68048914937 ps |
| CPU time | 695.19 seconds |
| Started | Sep 11 07:46:29 PM UTC 24 |
| Finished | Sep 11 07:58:14 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183644932 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2183644932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/22.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.1694029210 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 36268919966 ps |
| CPU time | 530.94 seconds |
| Started | Sep 11 07:46:47 PM UTC 24 |
| Finished | Sep 11 07:55:45 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694029210 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1694029210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/22.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.747974019 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 618509118 ps |
| CPU time | 51.43 seconds |
| Started | Sep 11 07:46:29 PM UTC 24 |
| Finished | Sep 11 07:47:23 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747974019 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.747974019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/22.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.4200768333 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1170654706 ps |
| CPU time | 43.85 seconds |
| Started | Sep 11 07:46:57 PM UTC 24 |
| Finished | Sep 11 07:47:43 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200768333 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.4200768333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/22.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.3512589731 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 141280938 ps |
| CPU time | 10.82 seconds |
| Started | Sep 11 07:46:13 PM UTC 24 |
| Finished | Sep 11 07:46:25 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512589731 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3512589731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/22.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.1549444968 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 8003700093 ps |
| CPU time | 106.14 seconds |
| Started | Sep 11 07:46:24 PM UTC 24 |
| Finished | Sep 11 07:48:13 PM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549444968 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1549444968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/22.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.2142284091 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 5390122894 ps |
| CPU time | 85.66 seconds |
| Started | Sep 11 07:46:28 PM UTC 24 |
| Finished | Sep 11 07:47:57 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142284091 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2142284091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.695483015 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 51271192 ps |
| CPU time | 8.48 seconds |
| Started | Sep 11 07:46:14 PM UTC 24 |
| Finished | Sep 11 07:46:23 PM UTC 24 |
| Peak memory | 593772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695483015 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.695483015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/22.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.3705169227 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 4275795032 ps |
| CPU time | 187.44 seconds |
| Started | Sep 11 07:47:46 PM UTC 24 |
| Finished | Sep 11 07:50:57 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705169227 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3705169227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/22.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.3142588569 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 2287253571 ps |
| CPU time | 198.15 seconds |
| Started | Sep 11 07:47:48 PM UTC 24 |
| Finished | Sep 11 07:51:10 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142588569 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3142588569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/22.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.3408345989 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 1741001664 ps |
| CPU time | 214.26 seconds |
| Started | Sep 11 07:47:47 PM UTC 24 |
| Finished | Sep 11 07:51:25 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408345989 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.3408345989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.2232648185 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 190137980 ps |
| CPU time | 121.16 seconds |
| Started | Sep 11 07:47:54 PM UTC 24 |
| Finished | Sep 11 07:49:58 PM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232648185 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.2232648185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.1378239828 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 1262296681 ps |
| CPU time | 51.32 seconds |
| Started | Sep 11 07:47:25 PM UTC 24 |
| Finished | Sep 11 07:48:18 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378239828 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.1378239828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/22.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.464758728 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 2656325260 ps |
| CPU time | 151.78 seconds |
| Started | Sep 11 07:47:51 PM UTC 24 |
| Finished | Sep 11 07:50:26 PM UTC 24 |
| Peak memory | 619092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464758728 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.464758728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/23.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.756844712 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 1203174654 ps |
| CPU time | 55.17 seconds |
| Started | Sep 11 07:48:36 PM UTC 24 |
| Finished | Sep 11 07:49:33 PM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756844712 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.756844712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/23.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.3647526556 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 119139733 ps |
| CPU time | 19.52 seconds |
| Started | Sep 11 07:49:16 PM UTC 24 |
| Finished | Sep 11 07:49:37 PM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647526556 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.3647526556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.2019301841 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 206278897 ps |
| CPU time | 17.19 seconds |
| Started | Sep 11 07:48:43 PM UTC 24 |
| Finished | Sep 11 07:49:01 PM UTC 24 |
| Peak memory | 596000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019301841 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2019301841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/23.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.3688311192 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 1005835565 ps |
| CPU time | 34.06 seconds |
| Started | Sep 11 07:48:15 PM UTC 24 |
| Finished | Sep 11 07:48:51 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688311192 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.3688311192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/23.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.270331862 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 19228706571 ps |
| CPU time | 174.07 seconds |
| Started | Sep 11 07:48:19 PM UTC 24 |
| Finished | Sep 11 07:51:16 PM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270331862 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.270331862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/23.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.1079788462 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 47916478196 ps |
| CPU time | 707.55 seconds |
| Started | Sep 11 07:48:30 PM UTC 24 |
| Finished | Sep 11 08:00:27 PM UTC 24 |
| Peak memory | 596120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079788462 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1079788462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/23.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.2729562083 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 210604204 ps |
| CPU time | 24.66 seconds |
| Started | Sep 11 07:48:21 PM UTC 24 |
| Finished | Sep 11 07:48:47 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729562083 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.2729562083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/23.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.3742264633 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 2662270853 ps |
| CPU time | 113.39 seconds |
| Started | Sep 11 07:48:40 PM UTC 24 |
| Finished | Sep 11 07:50:36 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742264633 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3742264633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/23.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.4270695841 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 57442545 ps |
| CPU time | 10.14 seconds |
| Started | Sep 11 07:47:54 PM UTC 24 |
| Finished | Sep 11 07:48:06 PM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270695841 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.4270695841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/23.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.1099240807 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 6994878149 ps |
| CPU time | 61.49 seconds |
| Started | Sep 11 07:48:06 PM UTC 24 |
| Finished | Sep 11 07:49:09 PM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099240807 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1099240807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/23.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.2344224202 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 5355317044 ps |
| CPU time | 121.74 seconds |
| Started | Sep 11 07:48:09 PM UTC 24 |
| Finished | Sep 11 07:50:13 PM UTC 24 |
| Peak memory | 593908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344224202 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2344224202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.3808542888 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 38532157 ps |
| CPU time | 8.13 seconds |
| Started | Sep 11 07:48:06 PM UTC 24 |
| Finished | Sep 11 07:48:15 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808542888 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3808542888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/23.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.3442067361 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 13815521898 ps |
| CPU time | 523.39 seconds |
| Started | Sep 11 07:49:27 PM UTC 24 |
| Finished | Sep 11 07:58:18 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442067361 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3442067361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/23.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.4074856512 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 13628301230 ps |
| CPU time | 626.57 seconds |
| Started | Sep 11 07:49:59 PM UTC 24 |
| Finished | Sep 11 08:00:34 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074856512 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.4074856512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.2992091316 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 555268374 ps |
| CPU time | 22.01 seconds |
| Started | Sep 11 07:49:12 PM UTC 24 |
| Finished | Sep 11 07:49:35 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992091316 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2992091316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/23.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.3589631911 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 3894941904 ps |
| CPU time | 298.12 seconds |
| Started | Sep 11 07:49:59 PM UTC 24 |
| Finished | Sep 11 07:55:01 PM UTC 24 |
| Peak memory | 621084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589631911 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.3589631911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/24.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.822952080 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 616408963 ps |
| CPU time | 37.31 seconds |
| Started | Sep 11 07:51:33 PM UTC 24 |
| Finished | Sep 11 07:52:12 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822952080 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.822952080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.861444782 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 2193223102 ps |
| CPU time | 76.06 seconds |
| Started | Sep 11 07:51:15 PM UTC 24 |
| Finished | Sep 11 07:52:33 PM UTC 24 |
| Peak memory | 596012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861444782 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.861444782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/24.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.3708687728 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 249212638 ps |
| CPU time | 32.86 seconds |
| Started | Sep 11 07:50:36 PM UTC 24 |
| Finished | Sep 11 07:51:11 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708687728 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.3708687728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/24.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.397792308 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 21967724079 ps |
| CPU time | 244.06 seconds |
| Started | Sep 11 07:50:37 PM UTC 24 |
| Finished | Sep 11 07:54:45 PM UTC 24 |
| Peak memory | 595996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397792308 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.397792308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/24.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.415321307 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 45247928962 ps |
| CPU time | 822.2 seconds |
| Started | Sep 11 07:50:50 PM UTC 24 |
| Finished | Sep 11 08:04:43 PM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415321307 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.415321307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/24.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.140691664 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 64420204 ps |
| CPU time | 11.84 seconds |
| Started | Sep 11 07:50:36 PM UTC 24 |
| Finished | Sep 11 07:50:49 PM UTC 24 |
| Peak memory | 595792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140691664 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.140691664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/24.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.4047008037 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 919678763 ps |
| CPU time | 34.25 seconds |
| Started | Sep 11 07:51:09 PM UTC 24 |
| Finished | Sep 11 07:51:45 PM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047008037 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.4047008037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/24.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.3766692632 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 42620258 ps |
| CPU time | 9.53 seconds |
| Started | Sep 11 07:50:00 PM UTC 24 |
| Finished | Sep 11 07:50:11 PM UTC 24 |
| Peak memory | 593864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766692632 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3766692632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/24.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.966257376 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 7033261533 ps |
| CPU time | 82.46 seconds |
| Started | Sep 11 07:50:23 PM UTC 24 |
| Finished | Sep 11 07:51:47 PM UTC 24 |
| Peak memory | 593912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966257376 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.966257376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/24.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.1244388922 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 5167885810 ps |
| CPU time | 97 seconds |
| Started | Sep 11 07:50:34 PM UTC 24 |
| Finished | Sep 11 07:52:13 PM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244388922 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1244388922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.1333401806 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 47426372 ps |
| CPU time | 8.78 seconds |
| Started | Sep 11 07:50:01 PM UTC 24 |
| Finished | Sep 11 07:50:11 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333401806 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1333401806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/24.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.1759618932 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 6268016472 ps |
| CPU time | 269.12 seconds |
| Started | Sep 11 07:51:36 PM UTC 24 |
| Finished | Sep 11 07:56:09 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759618932 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1759618932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/24.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.1767572298 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 1093510917 ps |
| CPU time | 117.94 seconds |
| Started | Sep 11 07:51:51 PM UTC 24 |
| Finished | Sep 11 07:53:51 PM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767572298 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1767572298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/24.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.329767033 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 3093306486 ps |
| CPU time | 416.57 seconds |
| Started | Sep 11 07:51:41 PM UTC 24 |
| Finished | Sep 11 07:58:44 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329767033 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.329767033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.3205638866 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 15167363894 ps |
| CPU time | 936.1 seconds |
| Started | Sep 11 07:51:52 PM UTC 24 |
| Finished | Sep 11 08:07:40 PM UTC 24 |
| Peak memory | 599940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205638866 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.3205638866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.1467849710 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 19302752 ps |
| CPU time | 7 seconds |
| Started | Sep 11 07:51:22 PM UTC 24 |
| Finished | Sep 11 07:51:30 PM UTC 24 |
| Peak memory | 593772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467849710 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1467849710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/24.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.2325342024 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 2453896774 ps |
| CPU time | 115.73 seconds |
| Started | Sep 11 07:51:55 PM UTC 24 |
| Finished | Sep 11 07:53:53 PM UTC 24 |
| Peak memory | 617000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325342024 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.2325342024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/25.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.29729536 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 1325664646 ps |
| CPU time | 111.15 seconds |
| Started | Sep 11 07:52:57 PM UTC 24 |
| Finished | Sep 11 07:54:50 PM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29729536 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.29729536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/25.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.1176413551 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 51460120688 ps |
| CPU time | 819.9 seconds |
| Started | Sep 11 07:52:56 PM UTC 24 |
| Finished | Sep 11 08:06:46 PM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176413551 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.1176413551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.3571507728 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 276764529 ps |
| CPU time | 19.31 seconds |
| Started | Sep 11 07:53:34 PM UTC 24 |
| Finished | Sep 11 07:53:55 PM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571507728 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3571507728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.2075873065 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 942011009 ps |
| CPU time | 46.07 seconds |
| Started | Sep 11 07:53:23 PM UTC 24 |
| Finished | Sep 11 07:54:10 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075873065 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2075873065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/25.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.3078226228 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 1219569341 ps |
| CPU time | 47.16 seconds |
| Started | Sep 11 07:52:36 PM UTC 24 |
| Finished | Sep 11 07:53:25 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078226228 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.3078226228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/25.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.2429919210 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 110215564062 ps |
| CPU time | 1180.95 seconds |
| Started | Sep 11 07:52:46 PM UTC 24 |
| Finished | Sep 11 08:12:40 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429919210 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2429919210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/25.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.3038889153 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 43798315043 ps |
| CPU time | 712.59 seconds |
| Started | Sep 11 07:52:48 PM UTC 24 |
| Finished | Sep 11 08:04:49 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038889153 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3038889153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/25.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.793246846 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 116990789 ps |
| CPU time | 17.38 seconds |
| Started | Sep 11 07:52:39 PM UTC 24 |
| Finished | Sep 11 07:52:57 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793246846 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.793246846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/25.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.219149260 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 148951651 ps |
| CPU time | 16.23 seconds |
| Started | Sep 11 07:53:16 PM UTC 24 |
| Finished | Sep 11 07:53:33 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219149260 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.219149260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/25.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.4080164680 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 204817298 ps |
| CPU time | 10.54 seconds |
| Started | Sep 11 07:52:09 PM UTC 24 |
| Finished | Sep 11 07:52:21 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080164680 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.4080164680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/25.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.3335718082 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 5551366490 ps |
| CPU time | 67.81 seconds |
| Started | Sep 11 07:52:13 PM UTC 24 |
| Finished | Sep 11 07:53:23 PM UTC 24 |
| Peak memory | 593704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335718082 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3335718082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/25.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.1577144584 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 3576390184 ps |
| CPU time | 73.05 seconds |
| Started | Sep 11 07:52:17 PM UTC 24 |
| Finished | Sep 11 07:53:32 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577144584 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1577144584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.4274859209 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 47602599 ps |
| CPU time | 9.29 seconds |
| Started | Sep 11 07:52:11 PM UTC 24 |
| Finished | Sep 11 07:52:21 PM UTC 24 |
| Peak memory | 593908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274859209 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.4274859209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/25.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.1030504448 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 1851350279 ps |
| CPU time | 130.29 seconds |
| Started | Sep 11 07:53:50 PM UTC 24 |
| Finished | Sep 11 07:56:03 PM UTC 24 |
| Peak memory | 596084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030504448 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1030504448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/25.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.4053776850 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 27968847 ps |
| CPU time | 12.79 seconds |
| Started | Sep 11 07:53:48 PM UTC 24 |
| Finished | Sep 11 07:54:02 PM UTC 24 |
| Peak memory | 593880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053776850 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.4053776850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.3643546464 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 1111065856 ps |
| CPU time | 65.17 seconds |
| Started | Sep 11 07:53:30 PM UTC 24 |
| Finished | Sep 11 07:54:36 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643546464 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3643546464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/25.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.3280983696 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 3604326381 ps |
| CPU time | 159.15 seconds |
| Started | Sep 11 07:53:57 PM UTC 24 |
| Finished | Sep 11 07:56:39 PM UTC 24 |
| Peak memory | 618908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280983696 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.3280983696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/26.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.1066057485 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 859728537 ps |
| CPU time | 88.76 seconds |
| Started | Sep 11 07:54:46 PM UTC 24 |
| Finished | Sep 11 07:56:17 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066057485 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.1066057485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/26.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.856429611 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 137021751640 ps |
| CPU time | 1849.53 seconds |
| Started | Sep 11 07:54:48 PM UTC 24 |
| Finished | Sep 11 08:25:59 PM UTC 24 |
| Peak memory | 599152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856429611 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.856429611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.2232867637 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 199610394 ps |
| CPU time | 26.5 seconds |
| Started | Sep 11 07:55:09 PM UTC 24 |
| Finished | Sep 11 07:55:37 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232867637 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.2232867637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.1263797753 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 350939203 ps |
| CPU time | 38.76 seconds |
| Started | Sep 11 07:55:02 PM UTC 24 |
| Finished | Sep 11 07:55:42 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263797753 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1263797753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/26.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.508662662 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 1290121555 ps |
| CPU time | 46.34 seconds |
| Started | Sep 11 07:54:19 PM UTC 24 |
| Finished | Sep 11 07:55:07 PM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508662662 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.508662662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/26.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.2704330980 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 61207302543 ps |
| CPU time | 629.54 seconds |
| Started | Sep 11 07:54:22 PM UTC 24 |
| Finished | Sep 11 08:05:00 PM UTC 24 |
| Peak memory | 596032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704330980 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.2704330980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/26.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.3347976231 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 12033112284 ps |
| CPU time | 157.59 seconds |
| Started | Sep 11 07:54:35 PM UTC 24 |
| Finished | Sep 11 07:57:16 PM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347976231 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3347976231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/26.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.662900544 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 295661395 ps |
| CPU time | 23.65 seconds |
| Started | Sep 11 07:54:20 PM UTC 24 |
| Finished | Sep 11 07:54:44 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662900544 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.662900544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/26.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.2221019418 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 1872869385 ps |
| CPU time | 46.21 seconds |
| Started | Sep 11 07:54:53 PM UTC 24 |
| Finished | Sep 11 07:55:41 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221019418 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2221019418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/26.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.3658610803 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 187041270 ps |
| CPU time | 12.52 seconds |
| Started | Sep 11 07:54:10 PM UTC 24 |
| Finished | Sep 11 07:54:23 PM UTC 24 |
| Peak memory | 593784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658610803 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3658610803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/26.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.688229691 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 6469716150 ps |
| CPU time | 105.58 seconds |
| Started | Sep 11 07:54:15 PM UTC 24 |
| Finished | Sep 11 07:56:03 PM UTC 24 |
| Peak memory | 594104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688229691 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.688229691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/26.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.2563823900 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 5153703490 ps |
| CPU time | 109.66 seconds |
| Started | Sep 11 07:54:18 PM UTC 24 |
| Finished | Sep 11 07:56:10 PM UTC 24 |
| Peak memory | 594012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563823900 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.2563823900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.1257237238 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 47332775 ps |
| CPU time | 8.84 seconds |
| Started | Sep 11 07:54:12 PM UTC 24 |
| Finished | Sep 11 07:54:22 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257237238 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1257237238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/26.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.1078253733 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 4573551757 ps |
| CPU time | 173.16 seconds |
| Started | Sep 11 07:55:15 PM UTC 24 |
| Finished | Sep 11 07:58:11 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078253733 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1078253733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/26.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.1672371871 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 2142799256 ps |
| CPU time | 179.09 seconds |
| Started | Sep 11 07:55:31 PM UTC 24 |
| Finished | Sep 11 07:58:34 PM UTC 24 |
| Peak memory | 595884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672371871 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1672371871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/26.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.3065190022 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 185907061 ps |
| CPU time | 82.2 seconds |
| Started | Sep 11 07:55:24 PM UTC 24 |
| Finished | Sep 11 07:56:48 PM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065190022 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.3065190022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3485777477 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 7610802185 ps |
| CPU time | 703.91 seconds |
| Started | Sep 11 07:56:02 PM UTC 24 |
| Finished | Sep 11 08:07:55 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485777477 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.3485777477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.3059270500 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 1420270077 ps |
| CPU time | 54.06 seconds |
| Started | Sep 11 07:55:10 PM UTC 24 |
| Finished | Sep 11 07:56:05 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059270500 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.3059270500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/26.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.288063434 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 3852042205 ps |
| CPU time | 236.21 seconds |
| Started | Sep 11 07:56:07 PM UTC 24 |
| Finished | Sep 11 08:00:07 PM UTC 24 |
| Peak memory | 620952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288063434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.288063434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/27.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.3466607632 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 2255031270 ps |
| CPU time | 80.27 seconds |
| Started | Sep 11 07:56:42 PM UTC 24 |
| Finished | Sep 11 07:58:04 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466607632 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.3466607632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/27.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.1568704982 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 8297316155 ps |
| CPU time | 159.16 seconds |
| Started | Sep 11 07:56:41 PM UTC 24 |
| Finished | Sep 11 07:59:23 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568704982 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.1568704982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.609791 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 148808195 ps |
| CPU time | 24.06 seconds |
| Started | Sep 11 07:57:08 PM UTC 24 |
| Finished | Sep 11 07:57:33 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609791 -assert nopostproc +UVM_TESTNAME=xb ar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.609791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.3090453553 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 133678655 ps |
| CPU time | 10.83 seconds |
| Started | Sep 11 07:56:58 PM UTC 24 |
| Finished | Sep 11 07:57:10 PM UTC 24 |
| Peak memory | 593904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090453553 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3090453553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/27.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.1070853571 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 230370423 ps |
| CPU time | 23.33 seconds |
| Started | Sep 11 07:56:30 PM UTC 24 |
| Finished | Sep 11 07:56:55 PM UTC 24 |
| Peak memory | 595980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070853571 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.1070853571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/27.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.3610172345 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 44172972195 ps |
| CPU time | 395.29 seconds |
| Started | Sep 11 07:56:34 PM UTC 24 |
| Finished | Sep 11 08:03:15 PM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610172345 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3610172345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/27.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.420797960 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 60662299792 ps |
| CPU time | 933.39 seconds |
| Started | Sep 11 07:56:39 PM UTC 24 |
| Finished | Sep 11 08:12:24 PM UTC 24 |
| Peak memory | 595980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420797960 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.420797960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/27.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.2746524025 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 43493184 ps |
| CPU time | 7.77 seconds |
| Started | Sep 11 07:56:34 PM UTC 24 |
| Finished | Sep 11 07:56:43 PM UTC 24 |
| Peak memory | 593908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746524025 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2746524025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/27.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.3356476764 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 224846583 ps |
| CPU time | 25.16 seconds |
| Started | Sep 11 07:56:57 PM UTC 24 |
| Finished | Sep 11 07:57:23 PM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356476764 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3356476764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/27.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.3501211951 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 41553152 ps |
| CPU time | 8.56 seconds |
| Started | Sep 11 07:56:06 PM UTC 24 |
| Finished | Sep 11 07:56:16 PM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501211951 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3501211951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/27.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.1736114394 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 6608027112 ps |
| CPU time | 64.44 seconds |
| Started | Sep 11 07:56:24 PM UTC 24 |
| Finished | Sep 11 07:57:30 PM UTC 24 |
| Peak memory | 593900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736114394 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1736114394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/27.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.517794456 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 5389095949 ps |
| CPU time | 108.69 seconds |
| Started | Sep 11 07:56:25 PM UTC 24 |
| Finished | Sep 11 07:58:16 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517794456 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.517794456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.1534910784 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 49274677 ps |
| CPU time | 9.49 seconds |
| Started | Sep 11 07:56:07 PM UTC 24 |
| Finished | Sep 11 07:56:18 PM UTC 24 |
| Peak memory | 593636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534910784 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.1534910784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/27.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.1460339161 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 732100972 ps |
| CPU time | 28.12 seconds |
| Started | Sep 11 07:57:12 PM UTC 24 |
| Finished | Sep 11 07:57:42 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460339161 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1460339161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/27.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.3588144669 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 4700427229 ps |
| CPU time | 129.91 seconds |
| Started | Sep 11 07:57:19 PM UTC 24 |
| Finished | Sep 11 07:59:31 PM UTC 24 |
| Peak memory | 596004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588144669 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3588144669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/27.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.3390782394 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 2194636614 ps |
| CPU time | 187.57 seconds |
| Started | Sep 11 07:57:35 PM UTC 24 |
| Finished | Sep 11 08:00:45 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390782394 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.3390782394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.1793580553 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 790679904 ps |
| CPU time | 41.36 seconds |
| Started | Sep 11 07:57:04 PM UTC 24 |
| Finished | Sep 11 07:57:47 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793580553 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1793580553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/27.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.3809065740 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 3428943484 ps |
| CPU time | 208.99 seconds |
| Started | Sep 11 07:57:37 PM UTC 24 |
| Finished | Sep 11 08:01:09 PM UTC 24 |
| Peak memory | 621184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809065740 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.3809065740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/28.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.4140981124 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 278852941 ps |
| CPU time | 37.7 seconds |
| Started | Sep 11 07:58:25 PM UTC 24 |
| Finished | Sep 11 07:59:04 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140981124 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.4140981124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/28.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.1236624523 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 15053217201 ps |
| CPU time | 309.52 seconds |
| Started | Sep 11 07:58:34 PM UTC 24 |
| Finished | Sep 11 08:03:48 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236624523 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.1236624523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.3341010205 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 45285522 ps |
| CPU time | 9.97 seconds |
| Started | Sep 11 07:58:59 PM UTC 24 |
| Finished | Sep 11 07:59:10 PM UTC 24 |
| Peak memory | 593656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341010205 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.3341010205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.1594037508 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 1393861469 ps |
| CPU time | 61.96 seconds |
| Started | Sep 11 07:58:40 PM UTC 24 |
| Finished | Sep 11 07:59:43 PM UTC 24 |
| Peak memory | 596084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594037508 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1594037508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/28.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.1610725832 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 584995260 ps |
| CPU time | 69.01 seconds |
| Started | Sep 11 07:58:07 PM UTC 24 |
| Finished | Sep 11 07:59:18 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610725832 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.1610725832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/28.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.4272835279 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 11723379035 ps |
| CPU time | 109.16 seconds |
| Started | Sep 11 07:58:17 PM UTC 24 |
| Finished | Sep 11 08:00:08 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272835279 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.4272835279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/28.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.2089248248 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 42662001853 ps |
| CPU time | 668.25 seconds |
| Started | Sep 11 07:58:20 PM UTC 24 |
| Finished | Sep 11 08:09:36 PM UTC 24 |
| Peak memory | 596004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089248248 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2089248248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/28.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.3239687638 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 416440819 ps |
| CPU time | 39.25 seconds |
| Started | Sep 11 07:58:12 PM UTC 24 |
| Finished | Sep 11 07:58:52 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239687638 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.3239687638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/28.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.671484771 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 877251977 ps |
| CPU time | 36.84 seconds |
| Started | Sep 11 07:58:39 PM UTC 24 |
| Finished | Sep 11 07:59:17 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671484771 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.671484771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/28.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.1658472269 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 51298432 ps |
| CPU time | 9.29 seconds |
| Started | Sep 11 07:57:41 PM UTC 24 |
| Finished | Sep 11 07:57:51 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658472269 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1658472269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/28.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.1532687227 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 8900368621 ps |
| CPU time | 112.37 seconds |
| Started | Sep 11 07:57:55 PM UTC 24 |
| Finished | Sep 11 07:59:50 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532687227 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1532687227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/28.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.3777627258 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 5733816014 ps |
| CPU time | 88.88 seconds |
| Started | Sep 11 07:57:58 PM UTC 24 |
| Finished | Sep 11 07:59:29 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777627258 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3777627258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.2164861213 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 38401670 ps |
| CPU time | 8.91 seconds |
| Started | Sep 11 07:57:47 PM UTC 24 |
| Finished | Sep 11 07:57:57 PM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164861213 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.2164861213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/28.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.3157546325 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1273893423 ps |
| CPU time | 126.09 seconds |
| Started | Sep 11 07:59:00 PM UTC 24 |
| Finished | Sep 11 08:01:08 PM UTC 24 |
| Peak memory | 595964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157546325 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.3157546325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/28.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.684277138 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 5489328587 ps |
| CPU time | 207.82 seconds |
| Started | Sep 11 07:59:17 PM UTC 24 |
| Finished | Sep 11 08:02:49 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684277138 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.684277138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/28.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.324043084 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 464701647 ps |
| CPU time | 160.01 seconds |
| Started | Sep 11 07:59:08 PM UTC 24 |
| Finished | Sep 11 08:01:52 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324043084 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.324043084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.4130073442 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 277669128 ps |
| CPU time | 65.13 seconds |
| Started | Sep 11 07:59:19 PM UTC 24 |
| Finished | Sep 11 08:00:26 PM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130073442 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.4130073442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.4058105574 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 1458338032 ps |
| CPU time | 65.25 seconds |
| Started | Sep 11 07:58:43 PM UTC 24 |
| Finished | Sep 11 07:59:50 PM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058105574 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.4058105574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/28.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.2023994611 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 4443679640 ps |
| CPU time | 372.51 seconds |
| Started | Sep 11 07:59:29 PM UTC 24 |
| Finished | Sep 11 08:05:46 PM UTC 24 |
| Peak memory | 621332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023994611 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.2023994611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/29.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.1648459230 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 910604672 ps |
| CPU time | 64.61 seconds |
| Started | Sep 11 08:00:15 PM UTC 24 |
| Finished | Sep 11 08:01:21 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648459230 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1648459230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/29.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.2186274754 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 104267163 ps |
| CPU time | 19.09 seconds |
| Started | Sep 11 08:00:33 PM UTC 24 |
| Finished | Sep 11 08:00:54 PM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186274754 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.2186274754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.1339639686 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 233011739 ps |
| CPU time | 14.24 seconds |
| Started | Sep 11 08:00:20 PM UTC 24 |
| Finished | Sep 11 08:00:35 PM UTC 24 |
| Peak memory | 596072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339639686 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1339639686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/29.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.166892635 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 297512375 ps |
| CPU time | 26.6 seconds |
| Started | Sep 11 07:59:52 PM UTC 24 |
| Finished | Sep 11 08:00:20 PM UTC 24 |
| Peak memory | 596076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166892635 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.166892635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/29.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.798479593 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 22444413936 ps |
| CPU time | 219.28 seconds |
| Started | Sep 11 08:00:08 PM UTC 24 |
| Finished | Sep 11 08:03:51 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798479593 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.798479593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/29.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.2761295178 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 66515129502 ps |
| CPU time | 989.68 seconds |
| Started | Sep 11 08:00:11 PM UTC 24 |
| Finished | Sep 11 08:16:52 PM UTC 24 |
| Peak memory | 596112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761295178 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2761295178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/29.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.1936225088 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 315049723 ps |
| CPU time | 38.54 seconds |
| Started | Sep 11 07:59:54 PM UTC 24 |
| Finished | Sep 11 08:00:33 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936225088 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.1936225088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/29.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.1898112547 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 1171868010 ps |
| CPU time | 45.61 seconds |
| Started | Sep 11 08:00:17 PM UTC 24 |
| Finished | Sep 11 08:01:05 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898112547 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1898112547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/29.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.2879441693 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 236409970 ps |
| CPU time | 13.83 seconds |
| Started | Sep 11 07:59:33 PM UTC 24 |
| Finished | Sep 11 07:59:48 PM UTC 24 |
| Peak memory | 593976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879441693 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2879441693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/29.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.1286616350 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 8122701189 ps |
| CPU time | 82.63 seconds |
| Started | Sep 11 07:59:42 PM UTC 24 |
| Finished | Sep 11 08:01:06 PM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286616350 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1286616350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/29.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.1788385224 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 6495598186 ps |
| CPU time | 119.99 seconds |
| Started | Sep 11 07:59:48 PM UTC 24 |
| Finished | Sep 11 08:01:50 PM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788385224 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1788385224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.791933085 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 45097476 ps |
| CPU time | 9.03 seconds |
| Started | Sep 11 07:59:42 PM UTC 24 |
| Finished | Sep 11 07:59:52 PM UTC 24 |
| Peak memory | 593788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791933085 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.791933085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/29.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.2362569090 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 4368067523 ps |
| CPU time | 405.7 seconds |
| Started | Sep 11 08:00:38 PM UTC 24 |
| Finished | Sep 11 08:07:30 PM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362569090 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2362569090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/29.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.2795791856 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 2900866953 ps |
| CPU time | 92.42 seconds |
| Started | Sep 11 08:00:47 PM UTC 24 |
| Finished | Sep 11 08:02:22 PM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795791856 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.2795791856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/29.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.1496970217 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 7000443227 ps |
| CPU time | 713.45 seconds |
| Started | Sep 11 08:00:43 PM UTC 24 |
| Finished | Sep 11 08:12:46 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496970217 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.1496970217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.259415936 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 17327168061 ps |
| CPU time | 727.89 seconds |
| Started | Sep 11 08:00:49 PM UTC 24 |
| Finished | Sep 11 08:13:07 PM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259415936 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.259415936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.3670580030 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 258396051 ps |
| CPU time | 16.84 seconds |
| Started | Sep 11 08:00:29 PM UTC 24 |
| Finished | Sep 11 08:00:46 PM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670580030 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3670580030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/29.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_aliasing.1722032698 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 55834085575 ps |
| CPU time | 9440.69 seconds |
| Started | Sep 11 06:58:03 PM UTC 24 |
| Finished | Sep 11 09:37:12 PM UTC 24 |
| Peak memory | 662900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1722032698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_ csr_aliasing.1722032698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.3460423024 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 10221024925 ps |
| CPU time | 996.91 seconds |
| Started | Sep 11 06:58:02 PM UTC 24 |
| Finished | Sep 11 07:14:51 PM UTC 24 |
| Peak memory | 610724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3460423024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.chip_csr_bit_bash.3460423024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.2986473906 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 5651573204 ps |
| CPU time | 254.29 seconds |
| Started | Sep 11 06:59:25 PM UTC 24 |
| Finished | Sep 11 07:03:43 PM UTC 24 |
| Peak memory | 678172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986473906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_reset.2986473906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.2279643501 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 12288643698 ps |
| CPU time | 1040.52 seconds |
| Started | Sep 11 06:59:35 PM UTC 24 |
| Finished | Sep 11 07:17:09 PM UTC 24 |
| Peak memory | 670340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2279643501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.chip_csr_mem_rw_with_rand_reset.2279643501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.4121382342 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 30834520985 ps |
| CPU time | 4116.93 seconds |
| Started | Sep 11 06:58:12 PM UTC 24 |
| Finished | Sep 11 08:07:39 PM UTC 24 |
| Peak memory | 613816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=4121382342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.chip_same_csr_outstanding.4121382342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.4068853731 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 2814823074 ps |
| CPU time | 209.58 seconds |
| Started | Sep 11 06:58:17 PM UTC 24 |
| Finished | Sep 11 07:01:50 PM UTC 24 |
| Peak memory | 621088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068853731 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.4068853731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.2494806009 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 2453024254 ps |
| CPU time | 117.86 seconds |
| Started | Sep 11 06:58:43 PM UTC 24 |
| Finished | Sep 11 07:00:44 PM UTC 24 |
| Peak memory | 595996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494806009 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2494806009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.2799999588 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 39109395375 ps |
| CPU time | 537.6 seconds |
| Started | Sep 11 06:58:50 PM UTC 24 |
| Finished | Sep 11 07:07:55 PM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799999588 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.2799999588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.4272326104 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 145240411 ps |
| CPU time | 12 seconds |
| Started | Sep 11 06:58:57 PM UTC 24 |
| Finished | Sep 11 06:59:11 PM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272326104 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.4272326104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.580273013 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 247677525 ps |
| CPU time | 22.21 seconds |
| Started | Sep 11 06:58:54 PM UTC 24 |
| Finished | Sep 11 06:59:18 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580273013 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.580273013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.2487825146 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 273531517 ps |
| CPU time | 13 seconds |
| Started | Sep 11 06:58:31 PM UTC 24 |
| Finished | Sep 11 06:58:45 PM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487825146 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.2487825146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.3179591444 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 54519663493 ps |
| CPU time | 622.45 seconds |
| Started | Sep 11 06:58:42 PM UTC 24 |
| Finished | Sep 11 07:09:13 PM UTC 24 |
| Peak memory | 596000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179591444 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3179591444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.407303971 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 25022904147 ps |
| CPU time | 371.76 seconds |
| Started | Sep 11 06:58:45 PM UTC 24 |
| Finished | Sep 11 07:05:03 PM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407303971 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.407303971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.2145846974 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 205636582 ps |
| CPU time | 18.22 seconds |
| Started | Sep 11 06:58:41 PM UTC 24 |
| Finished | Sep 11 06:59:00 PM UTC 24 |
| Peak memory | 595820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145846974 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2145846974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.994141882 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 2536221988 ps |
| CPU time | 92.51 seconds |
| Started | Sep 11 06:58:47 PM UTC 24 |
| Finished | Sep 11 07:00:22 PM UTC 24 |
| Peak memory | 595756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994141882 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.994141882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.793995497 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 44842828 ps |
| CPU time | 8.3 seconds |
| Started | Sep 11 06:58:21 PM UTC 24 |
| Finished | Sep 11 06:58:30 PM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793995497 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.793995497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.782905279 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 8678754171 ps |
| CPU time | 93.57 seconds |
| Started | Sep 11 06:58:30 PM UTC 24 |
| Finished | Sep 11 07:00:05 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782905279 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.782905279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.4079612554 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 4761791847 ps |
| CPU time | 69.88 seconds |
| Started | Sep 11 06:58:30 PM UTC 24 |
| Finished | Sep 11 06:59:42 PM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079612554 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.4079612554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.1841834051 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 55626093 ps |
| CPU time | 9.17 seconds |
| Started | Sep 11 06:58:27 PM UTC 24 |
| Finished | Sep 11 06:58:38 PM UTC 24 |
| Peak memory | 593876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841834051 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1841834051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.3402410305 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 185360864 ps |
| CPU time | 24.44 seconds |
| Started | Sep 11 06:59:09 PM UTC 24 |
| Finished | Sep 11 06:59:35 PM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402410305 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3402410305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.798630873 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 8167930 ps |
| CPU time | 6.94 seconds |
| Started | Sep 11 06:59:03 PM UTC 24 |
| Finished | Sep 11 06:59:11 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798630873 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.798630873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.1970228362 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 776418530 ps |
| CPU time | 186.92 seconds |
| Started | Sep 11 06:59:20 PM UTC 24 |
| Finished | Sep 11 07:02:30 PM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970228362 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.1970228362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.293656640 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 23907488 ps |
| CPU time | 7.82 seconds |
| Started | Sep 11 06:58:54 PM UTC 24 |
| Finished | Sep 11 06:59:03 PM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293656640 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.293656640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.103647780 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 3030741345 ps |
| CPU time | 125.01 seconds |
| Started | Sep 11 08:01:27 PM UTC 24 |
| Finished | Sep 11 08:03:35 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103647780 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.103647780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/30.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.2345309802 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 115213724196 ps |
| CPU time | 1566.56 seconds |
| Started | Sep 11 08:01:28 PM UTC 24 |
| Finished | Sep 11 08:27:53 PM UTC 24 |
| Peak memory | 598504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345309802 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.2345309802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.497487223 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 967510322 ps |
| CPU time | 33.64 seconds |
| Started | Sep 11 08:01:47 PM UTC 24 |
| Finished | Sep 11 08:02:22 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497487223 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.497487223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.2197538310 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 651237310 ps |
| CPU time | 60.38 seconds |
| Started | Sep 11 08:01:33 PM UTC 24 |
| Finished | Sep 11 08:02:36 PM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197538310 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2197538310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/30.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.4083088560 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 2402658085 ps |
| CPU time | 112.26 seconds |
| Started | Sep 11 08:01:07 PM UTC 24 |
| Finished | Sep 11 08:03:02 PM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083088560 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.4083088560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/30.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.1180686800 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 90214152571 ps |
| CPU time | 990.52 seconds |
| Started | Sep 11 08:01:19 PM UTC 24 |
| Finished | Sep 11 08:18:02 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180686800 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1180686800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/30.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.2440392997 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 44012270460 ps |
| CPU time | 740.68 seconds |
| Started | Sep 11 08:01:28 PM UTC 24 |
| Finished | Sep 11 08:13:59 PM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440392997 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.2440392997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/30.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.2686546602 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 267079913 ps |
| CPU time | 23.98 seconds |
| Started | Sep 11 08:01:11 PM UTC 24 |
| Finished | Sep 11 08:01:36 PM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686546602 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.2686546602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/30.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.762738345 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 340076622 ps |
| CPU time | 17.6 seconds |
| Started | Sep 11 08:01:32 PM UTC 24 |
| Finished | Sep 11 08:01:51 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762738345 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.762738345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/30.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.3097425577 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 46861443 ps |
| CPU time | 9.3 seconds |
| Started | Sep 11 08:00:51 PM UTC 24 |
| Finished | Sep 11 08:01:02 PM UTC 24 |
| Peak memory | 593900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097425577 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3097425577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/30.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.1414316610 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 8994428731 ps |
| CPU time | 98 seconds |
| Started | Sep 11 08:00:57 PM UTC 24 |
| Finished | Sep 11 08:02:37 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414316610 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1414316610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/30.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.495328450 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 4562460180 ps |
| CPU time | 68.33 seconds |
| Started | Sep 11 08:00:56 PM UTC 24 |
| Finished | Sep 11 08:02:06 PM UTC 24 |
| Peak memory | 593784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495328450 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.495328450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2061107048 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 38337078 ps |
| CPU time | 7.04 seconds |
| Started | Sep 11 08:00:54 PM UTC 24 |
| Finished | Sep 11 08:01:02 PM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061107048 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2061107048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/30.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.2990130387 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 2756833037 ps |
| CPU time | 322.31 seconds |
| Started | Sep 11 08:02:02 PM UTC 24 |
| Finished | Sep 11 08:07:29 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990130387 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2990130387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/30.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.1949627262 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 1047021600 ps |
| CPU time | 65.49 seconds |
| Started | Sep 11 08:02:18 PM UTC 24 |
| Finished | Sep 11 08:03:25 PM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949627262 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1949627262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/30.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.1451695808 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 418152812 ps |
| CPU time | 111.03 seconds |
| Started | Sep 11 08:02:17 PM UTC 24 |
| Finished | Sep 11 08:04:10 PM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451695808 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.1451695808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.1093501555 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 1050264444 ps |
| CPU time | 46.31 seconds |
| Started | Sep 11 08:01:35 PM UTC 24 |
| Finished | Sep 11 08:02:23 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093501555 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1093501555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/30.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.3587662879 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 1210434374 ps |
| CPU time | 47.78 seconds |
| Started | Sep 11 08:03:07 PM UTC 24 |
| Finished | Sep 11 08:03:57 PM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587662879 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3587662879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/31.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.2016054039 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 106991675150 ps |
| CPU time | 1686.68 seconds |
| Started | Sep 11 08:03:10 PM UTC 24 |
| Finished | Sep 11 08:31:37 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016054039 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.2016054039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.390576722 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 451991838 ps |
| CPU time | 18.62 seconds |
| Started | Sep 11 08:03:48 PM UTC 24 |
| Finished | Sep 11 08:04:08 PM UTC 24 |
| Peak memory | 595964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390576722 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.390576722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.1238795103 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 1488568416 ps |
| CPU time | 56.55 seconds |
| Started | Sep 11 08:03:27 PM UTC 24 |
| Finished | Sep 11 08:04:25 PM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238795103 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1238795103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/31.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.3543466162 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 1685028146 ps |
| CPU time | 73.59 seconds |
| Started | Sep 11 08:02:49 PM UTC 24 |
| Finished | Sep 11 08:04:04 PM UTC 24 |
| Peak memory | 595884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543466162 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.3543466162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/31.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.2657829528 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 79411211997 ps |
| CPU time | 712.76 seconds |
| Started | Sep 11 08:03:03 PM UTC 24 |
| Finished | Sep 11 08:15:04 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657829528 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2657829528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/31.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.3242614399 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 20941364049 ps |
| CPU time | 348.58 seconds |
| Started | Sep 11 08:03:03 PM UTC 24 |
| Finished | Sep 11 08:08:56 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242614399 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.3242614399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/31.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.746167125 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 235125813 ps |
| CPU time | 22 seconds |
| Started | Sep 11 08:03:00 PM UTC 24 |
| Finished | Sep 11 08:03:24 PM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746167125 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.746167125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/31.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.1358056077 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 880639836 ps |
| CPU time | 37.05 seconds |
| Started | Sep 11 08:03:12 PM UTC 24 |
| Finished | Sep 11 08:03:51 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358056077 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1358056077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/31.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.1605302936 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 45290965 ps |
| CPU time | 5.82 seconds |
| Started | Sep 11 08:02:31 PM UTC 24 |
| Finished | Sep 11 08:02:38 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605302936 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.1605302936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/31.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.495397282 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 7149034740 ps |
| CPU time | 71.73 seconds |
| Started | Sep 11 08:02:47 PM UTC 24 |
| Finished | Sep 11 08:04:00 PM UTC 24 |
| Peak memory | 594152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495397282 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.495397282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/31.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.2808023001 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 6601349514 ps |
| CPU time | 92.43 seconds |
| Started | Sep 11 08:02:47 PM UTC 24 |
| Finished | Sep 11 08:04:22 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808023001 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2808023001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.3332378864 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 48854379 ps |
| CPU time | 9.46 seconds |
| Started | Sep 11 08:02:35 PM UTC 24 |
| Finished | Sep 11 08:02:46 PM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332378864 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3332378864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/31.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.1032173227 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 11469768580 ps |
| CPU time | 373.76 seconds |
| Started | Sep 11 08:03:51 PM UTC 24 |
| Finished | Sep 11 08:10:10 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032173227 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1032173227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/31.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.1756737492 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 10316278285 ps |
| CPU time | 368.3 seconds |
| Started | Sep 11 08:04:12 PM UTC 24 |
| Finished | Sep 11 08:10:26 PM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756737492 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1756737492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/31.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.3650930808 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 6260069438 ps |
| CPU time | 536.72 seconds |
| Started | Sep 11 08:04:01 PM UTC 24 |
| Finished | Sep 11 08:13:05 PM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650930808 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.3650930808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.3895262343 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 485043177 ps |
| CPU time | 105.5 seconds |
| Started | Sep 11 08:04:14 PM UTC 24 |
| Finished | Sep 11 08:06:02 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895262343 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.3895262343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.778833649 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 917284571 ps |
| CPU time | 50.49 seconds |
| Started | Sep 11 08:03:41 PM UTC 24 |
| Finished | Sep 11 08:04:33 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778833649 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.778833649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/31.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.2458697303 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 776005819 ps |
| CPU time | 66.2 seconds |
| Started | Sep 11 08:04:52 PM UTC 24 |
| Finished | Sep 11 08:06:00 PM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458697303 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2458697303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/32.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.1364181151 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 83515803666 ps |
| CPU time | 1289.1 seconds |
| Started | Sep 11 08:04:53 PM UTC 24 |
| Finished | Sep 11 08:26:37 PM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364181151 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.1364181151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.3134416963 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 944692752 ps |
| CPU time | 41.33 seconds |
| Started | Sep 11 08:05:07 PM UTC 24 |
| Finished | Sep 11 08:05:50 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134416963 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3134416963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.1526327485 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 507166304 ps |
| CPU time | 51.55 seconds |
| Started | Sep 11 08:04:56 PM UTC 24 |
| Finished | Sep 11 08:05:49 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526327485 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1526327485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/32.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.1742288643 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 825429587 ps |
| CPU time | 30.01 seconds |
| Started | Sep 11 08:04:31 PM UTC 24 |
| Finished | Sep 11 08:05:02 PM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742288643 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.1742288643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/32.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.720403833 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 29643592783 ps |
| CPU time | 286.57 seconds |
| Started | Sep 11 08:04:47 PM UTC 24 |
| Finished | Sep 11 08:09:38 PM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720403833 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.720403833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/32.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.3650609989 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 57070973988 ps |
| CPU time | 808.36 seconds |
| Started | Sep 11 08:04:47 PM UTC 24 |
| Finished | Sep 11 08:18:25 PM UTC 24 |
| Peak memory | 596136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650609989 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3650609989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/32.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.2420652382 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 38808907 ps |
| CPU time | 8.83 seconds |
| Started | Sep 11 08:04:34 PM UTC 24 |
| Finished | Sep 11 08:04:44 PM UTC 24 |
| Peak memory | 593876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420652382 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.2420652382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/32.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.4198711268 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 1837307849 ps |
| CPU time | 66.12 seconds |
| Started | Sep 11 08:04:49 PM UTC 24 |
| Finished | Sep 11 08:05:57 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198711268 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.4198711268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/32.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.2641963698 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 208015947 ps |
| CPU time | 10.31 seconds |
| Started | Sep 11 08:04:16 PM UTC 24 |
| Finished | Sep 11 08:04:28 PM UTC 24 |
| Peak memory | 593844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641963698 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2641963698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/32.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.3474582833 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 9897662222 ps |
| CPU time | 99.71 seconds |
| Started | Sep 11 08:04:22 PM UTC 24 |
| Finished | Sep 11 08:06:04 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474582833 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.3474582833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/32.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.3197980779 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 5497118221 ps |
| CPU time | 133.27 seconds |
| Started | Sep 11 08:04:29 PM UTC 24 |
| Finished | Sep 11 08:06:45 PM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197980779 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3197980779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.1664381731 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 50912415 ps |
| CPU time | 9.26 seconds |
| Started | Sep 11 08:04:20 PM UTC 24 |
| Finished | Sep 11 08:04:30 PM UTC 24 |
| Peak memory | 593772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664381731 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.1664381731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/32.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.543764072 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 1892987544 ps |
| CPU time | 183.85 seconds |
| Started | Sep 11 08:05:08 PM UTC 24 |
| Finished | Sep 11 08:08:15 PM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543764072 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.543764072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/32.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.258678522 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 4580000879 ps |
| CPU time | 160.3 seconds |
| Started | Sep 11 08:05:26 PM UTC 24 |
| Finished | Sep 11 08:08:09 PM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258678522 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.258678522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/32.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.1339212770 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 2391458318 ps |
| CPU time | 317.56 seconds |
| Started | Sep 11 08:05:13 PM UTC 24 |
| Finished | Sep 11 08:10:35 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339212770 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.1339212770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.1589577687 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 541975632 ps |
| CPU time | 155.22 seconds |
| Started | Sep 11 08:05:26 PM UTC 24 |
| Finished | Sep 11 08:08:04 PM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589577687 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.1589577687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.2988590129 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 796494586 ps |
| CPU time | 46.3 seconds |
| Started | Sep 11 08:05:00 PM UTC 24 |
| Finished | Sep 11 08:05:48 PM UTC 24 |
| Peak memory | 595920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988590129 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2988590129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/32.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.232376121 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 1196947115 ps |
| CPU time | 48.09 seconds |
| Started | Sep 11 08:06:29 PM UTC 24 |
| Finished | Sep 11 08:07:18 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232376121 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.232376121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/33.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.2178072079 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 90460036327 ps |
| CPU time | 1520.27 seconds |
| Started | Sep 11 08:06:38 PM UTC 24 |
| Finished | Sep 11 08:32:16 PM UTC 24 |
| Peak memory | 596452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178072079 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.2178072079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.1461923300 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 299724517 ps |
| CPU time | 39.14 seconds |
| Started | Sep 11 08:07:11 PM UTC 24 |
| Finished | Sep 11 08:07:52 PM UTC 24 |
| Peak memory | 595864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461923300 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.1461923300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.2257044071 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 587685140 ps |
| CPU time | 38.64 seconds |
| Started | Sep 11 08:06:58 PM UTC 24 |
| Finished | Sep 11 08:07:38 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257044071 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.2257044071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/33.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.46530313 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 401776596 ps |
| CPU time | 30.72 seconds |
| Started | Sep 11 08:06:16 PM UTC 24 |
| Finished | Sep 11 08:06:48 PM UTC 24 |
| Peak memory | 595884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46530313 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.46530313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/33.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.2176112307 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 109212163495 ps |
| CPU time | 1073.52 seconds |
| Started | Sep 11 08:06:22 PM UTC 24 |
| Finished | Sep 11 08:24:28 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176112307 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2176112307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/33.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.2144725133 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 37801329165 ps |
| CPU time | 614.2 seconds |
| Started | Sep 11 08:06:26 PM UTC 24 |
| Finished | Sep 11 08:16:49 PM UTC 24 |
| Peak memory | 595964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144725133 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2144725133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/33.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.1040955741 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 617883725 ps |
| CPU time | 64.35 seconds |
| Started | Sep 11 08:06:22 PM UTC 24 |
| Finished | Sep 11 08:07:28 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040955741 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.1040955741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/33.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.3372876319 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 528114493 ps |
| CPU time | 53.29 seconds |
| Started | Sep 11 08:06:43 PM UTC 24 |
| Finished | Sep 11 08:07:39 PM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372876319 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3372876319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/33.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.186875450 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 198178739 ps |
| CPU time | 11.86 seconds |
| Started | Sep 11 08:06:03 PM UTC 24 |
| Finished | Sep 11 08:06:16 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186875450 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.186875450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/33.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.3958088273 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 9859237969 ps |
| CPU time | 113.68 seconds |
| Started | Sep 11 08:06:14 PM UTC 24 |
| Finished | Sep 11 08:08:10 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958088273 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3958088273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/33.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.1635286450 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 4415075649 ps |
| CPU time | 78.33 seconds |
| Started | Sep 11 08:06:12 PM UTC 24 |
| Finished | Sep 11 08:07:33 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635286450 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1635286450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.295204236 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 50092397 ps |
| CPU time | 9.44 seconds |
| Started | Sep 11 08:06:10 PM UTC 24 |
| Finished | Sep 11 08:06:20 PM UTC 24 |
| Peak memory | 593916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295204236 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.295204236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/33.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.1639270309 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 12068070120 ps |
| CPU time | 477.42 seconds |
| Started | Sep 11 08:07:13 PM UTC 24 |
| Finished | Sep 11 08:15:17 PM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639270309 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1639270309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/33.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.4046644657 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 168804883 ps |
| CPU time | 24.25 seconds |
| Started | Sep 11 08:07:43 PM UTC 24 |
| Finished | Sep 11 08:08:09 PM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046644657 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.4046644657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/33.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.717451201 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 273810232 ps |
| CPU time | 126.26 seconds |
| Started | Sep 11 08:07:34 PM UTC 24 |
| Finished | Sep 11 08:09:43 PM UTC 24 |
| Peak memory | 595884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717451201 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.717451201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.576128174 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 3255231168 ps |
| CPU time | 222.7 seconds |
| Started | Sep 11 08:07:51 PM UTC 24 |
| Finished | Sep 11 08:11:37 PM UTC 24 |
| Peak memory | 596036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576128174 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.576128174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.779675472 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 147504913 ps |
| CPU time | 25.25 seconds |
| Started | Sep 11 08:07:11 PM UTC 24 |
| Finished | Sep 11 08:07:38 PM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779675472 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.779675472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/33.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.236721807 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 756752903 ps |
| CPU time | 73.78 seconds |
| Started | Sep 11 08:08:03 PM UTC 24 |
| Finished | Sep 11 08:09:19 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236721807 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.236721807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/34.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.4028405247 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 159586307604 ps |
| CPU time | 2246.24 seconds |
| Started | Sep 11 08:08:04 PM UTC 24 |
| Finished | Sep 11 08:45:57 PM UTC 24 |
| Peak memory | 598932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028405247 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.4028405247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.3851255620 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 94827055 ps |
| CPU time | 16.92 seconds |
| Started | Sep 11 08:08:19 PM UTC 24 |
| Finished | Sep 11 08:08:37 PM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851255620 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.3851255620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.508629329 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 2113180208 ps |
| CPU time | 79.11 seconds |
| Started | Sep 11 08:08:17 PM UTC 24 |
| Finished | Sep 11 08:09:38 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508629329 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.508629329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/34.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.3192666277 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 154898483 ps |
| CPU time | 20.53 seconds |
| Started | Sep 11 08:08:04 PM UTC 24 |
| Finished | Sep 11 08:08:25 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192666277 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.3192666277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/34.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.2613629317 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 108454135097 ps |
| CPU time | 1064.72 seconds |
| Started | Sep 11 08:08:04 PM UTC 24 |
| Finished | Sep 11 08:26:00 PM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613629317 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2613629317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/34.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.615824484 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 35999400749 ps |
| CPU time | 573.68 seconds |
| Started | Sep 11 08:08:03 PM UTC 24 |
| Finished | Sep 11 08:17:44 PM UTC 24 |
| Peak memory | 596152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615824484 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.615824484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/34.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.276252418 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 555675888 ps |
| CPU time | 49.45 seconds |
| Started | Sep 11 08:08:03 PM UTC 24 |
| Finished | Sep 11 08:08:54 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276252418 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.276252418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/34.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.3030833294 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 781998109 ps |
| CPU time | 31.11 seconds |
| Started | Sep 11 08:08:06 PM UTC 24 |
| Finished | Sep 11 08:08:39 PM UTC 24 |
| Peak memory | 595684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030833294 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3030833294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/34.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.2981253558 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 203393800 ps |
| CPU time | 8.05 seconds |
| Started | Sep 11 08:07:51 PM UTC 24 |
| Finished | Sep 11 08:08:00 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981253558 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2981253558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/34.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.3492569894 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 8921415259 ps |
| CPU time | 138.76 seconds |
| Started | Sep 11 08:07:53 PM UTC 24 |
| Finished | Sep 11 08:10:14 PM UTC 24 |
| Peak memory | 594124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492569894 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3492569894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/34.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.567108506 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 5312663175 ps |
| CPU time | 94.66 seconds |
| Started | Sep 11 08:07:58 PM UTC 24 |
| Finished | Sep 11 08:09:35 PM UTC 24 |
| Peak memory | 594088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567108506 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.567108506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.1449816435 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 54685880 ps |
| CPU time | 8.76 seconds |
| Started | Sep 11 08:07:54 PM UTC 24 |
| Finished | Sep 11 08:08:04 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449816435 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.1449816435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/34.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.3642609096 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 2489322571 ps |
| CPU time | 226.3 seconds |
| Started | Sep 11 08:08:25 PM UTC 24 |
| Finished | Sep 11 08:12:14 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642609096 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.3642609096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/34.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.1276353009 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 14785042952 ps |
| CPU time | 500.52 seconds |
| Started | Sep 11 08:08:27 PM UTC 24 |
| Finished | Sep 11 08:16:54 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276353009 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1276353009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/34.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2493175160 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 1501627699 ps |
| CPU time | 174.08 seconds |
| Started | Sep 11 08:08:34 PM UTC 24 |
| Finished | Sep 11 08:11:31 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493175160 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.2493175160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.2720041527 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 317377932 ps |
| CPU time | 37.96 seconds |
| Started | Sep 11 08:08:18 PM UTC 24 |
| Finished | Sep 11 08:08:57 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720041527 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2720041527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/34.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.3446300399 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 502292737 ps |
| CPU time | 44.86 seconds |
| Started | Sep 11 08:09:08 PM UTC 24 |
| Finished | Sep 11 08:09:55 PM UTC 24 |
| Peak memory | 595920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446300399 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.3446300399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/35.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.3240065784 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 46808673936 ps |
| CPU time | 754.22 seconds |
| Started | Sep 11 08:09:20 PM UTC 24 |
| Finished | Sep 11 08:22:03 PM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240065784 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.3240065784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.3035965101 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 555118412 ps |
| CPU time | 22.5 seconds |
| Started | Sep 11 08:09:45 PM UTC 24 |
| Finished | Sep 11 08:10:09 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035965101 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.3035965101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.3570820119 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 914614569 ps |
| CPU time | 33.28 seconds |
| Started | Sep 11 08:09:24 PM UTC 24 |
| Finished | Sep 11 08:09:59 PM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570820119 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3570820119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/35.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.2516048855 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 932297007 ps |
| CPU time | 44.69 seconds |
| Started | Sep 11 08:08:54 PM UTC 24 |
| Finished | Sep 11 08:09:41 PM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516048855 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.2516048855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/35.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.2373441053 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 17152637503 ps |
| CPU time | 245.6 seconds |
| Started | Sep 11 08:09:04 PM UTC 24 |
| Finished | Sep 11 08:13:14 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373441053 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2373441053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/35.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.3508084961 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 34391249668 ps |
| CPU time | 520.81 seconds |
| Started | Sep 11 08:09:07 PM UTC 24 |
| Finished | Sep 11 08:17:54 PM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508084961 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3508084961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/35.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.1800358891 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 145185450 ps |
| CPU time | 15.24 seconds |
| Started | Sep 11 08:09:02 PM UTC 24 |
| Finished | Sep 11 08:09:19 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800358891 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1800358891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/35.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.4193842956 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 2477828868 ps |
| CPU time | 69.83 seconds |
| Started | Sep 11 08:09:23 PM UTC 24 |
| Finished | Sep 11 08:10:34 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193842956 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.4193842956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/35.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.116803402 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 38109353 ps |
| CPU time | 5.38 seconds |
| Started | Sep 11 08:08:34 PM UTC 24 |
| Finished | Sep 11 08:08:41 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116803402 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.116803402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/35.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.95447661 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 5664353136 ps |
| CPU time | 76.25 seconds |
| Started | Sep 11 08:08:40 PM UTC 24 |
| Finished | Sep 11 08:09:58 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95447661 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.95447661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/35.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.3574615509 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 3431278767 ps |
| CPU time | 50.92 seconds |
| Started | Sep 11 08:08:47 PM UTC 24 |
| Finished | Sep 11 08:09:39 PM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574615509 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3574615509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.3719627716 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 53622270 ps |
| CPU time | 7.22 seconds |
| Started | Sep 11 08:08:34 PM UTC 24 |
| Finished | Sep 11 08:08:43 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719627716 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.3719627716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/35.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.3479094768 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 2167774028 ps |
| CPU time | 194.37 seconds |
| Started | Sep 11 08:09:45 PM UTC 24 |
| Finished | Sep 11 08:13:03 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479094768 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3479094768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/35.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.1584112050 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 2160747015 ps |
| CPU time | 171.25 seconds |
| Started | Sep 11 08:10:01 PM UTC 24 |
| Finished | Sep 11 08:12:55 PM UTC 24 |
| Peak memory | 596108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584112050 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1584112050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/35.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1810822427 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 5455568696 ps |
| CPU time | 380.03 seconds |
| Started | Sep 11 08:09:50 PM UTC 24 |
| Finished | Sep 11 08:16:15 PM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810822427 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.1810822427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.201686024 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 374387722 ps |
| CPU time | 142.07 seconds |
| Started | Sep 11 08:10:01 PM UTC 24 |
| Finished | Sep 11 08:12:25 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201686024 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.201686024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.2587744149 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 451774839 ps |
| CPU time | 22.28 seconds |
| Started | Sep 11 08:09:35 PM UTC 24 |
| Finished | Sep 11 08:09:59 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587744149 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2587744149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/35.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.3921794428 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 698817472 ps |
| CPU time | 53.9 seconds |
| Started | Sep 11 08:10:25 PM UTC 24 |
| Finished | Sep 11 08:11:21 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921794428 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.3921794428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/36.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.2907067993 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 65029627430 ps |
| CPU time | 1034.14 seconds |
| Started | Sep 11 08:10:35 PM UTC 24 |
| Finished | Sep 11 08:28:02 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907067993 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.2907067993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.1184270624 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 749847445 ps |
| CPU time | 40.55 seconds |
| Started | Sep 11 08:10:41 PM UTC 24 |
| Finished | Sep 11 08:11:23 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184270624 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.1184270624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.4075969293 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 2522119237 ps |
| CPU time | 90.14 seconds |
| Started | Sep 11 08:10:36 PM UTC 24 |
| Finished | Sep 11 08:12:08 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075969293 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.4075969293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/36.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.3902721448 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 2181061333 ps |
| CPU time | 76.22 seconds |
| Started | Sep 11 08:10:07 PM UTC 24 |
| Finished | Sep 11 08:11:25 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902721448 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.3902721448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/36.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.3848618141 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 45739116139 ps |
| CPU time | 507.44 seconds |
| Started | Sep 11 08:10:22 PM UTC 24 |
| Finished | Sep 11 08:18:56 PM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848618141 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3848618141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/36.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.3850960635 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 62250778030 ps |
| CPU time | 977.09 seconds |
| Started | Sep 11 08:10:24 PM UTC 24 |
| Finished | Sep 11 08:26:53 PM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850960635 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3850960635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/36.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.2511374544 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 464035301 ps |
| CPU time | 52.48 seconds |
| Started | Sep 11 08:10:16 PM UTC 24 |
| Finished | Sep 11 08:11:10 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511374544 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2511374544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/36.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.2189479672 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 1314210513 ps |
| CPU time | 35.24 seconds |
| Started | Sep 11 08:10:36 PM UTC 24 |
| Finished | Sep 11 08:11:12 PM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189479672 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2189479672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/36.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.232856349 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 166591095 ps |
| CPU time | 9.97 seconds |
| Started | Sep 11 08:10:02 PM UTC 24 |
| Finished | Sep 11 08:10:13 PM UTC 24 |
| Peak memory | 593632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232856349 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.232856349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/36.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.4048169638 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 7518750434 ps |
| CPU time | 82.12 seconds |
| Started | Sep 11 08:10:05 PM UTC 24 |
| Finished | Sep 11 08:11:29 PM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048169638 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.4048169638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/36.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.2914402611 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 3693954699 ps |
| CPU time | 50.36 seconds |
| Started | Sep 11 08:10:05 PM UTC 24 |
| Finished | Sep 11 08:10:57 PM UTC 24 |
| Peak memory | 594092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914402611 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2914402611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.3721140824 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 45922505 ps |
| CPU time | 8.4 seconds |
| Started | Sep 11 08:10:01 PM UTC 24 |
| Finished | Sep 11 08:10:11 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721140824 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.3721140824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/36.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.1238239159 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 15843680580 ps |
| CPU time | 560.21 seconds |
| Started | Sep 11 08:10:52 PM UTC 24 |
| Finished | Sep 11 08:20:20 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238239159 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1238239159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/36.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.3515067695 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 7344191814 ps |
| CPU time | 223.48 seconds |
| Started | Sep 11 08:10:58 PM UTC 24 |
| Finished | Sep 11 08:14:45 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515067695 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3515067695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/36.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.2585599531 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 51222479 ps |
| CPU time | 59.9 seconds |
| Started | Sep 11 08:10:58 PM UTC 24 |
| Finished | Sep 11 08:12:00 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585599531 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.2585599531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1293770902 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 718272754 ps |
| CPU time | 308.47 seconds |
| Started | Sep 11 08:11:19 PM UTC 24 |
| Finished | Sep 11 08:16:32 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293770902 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.1293770902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.3341280826 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 106116964 ps |
| CPU time | 20.48 seconds |
| Started | Sep 11 08:10:39 PM UTC 24 |
| Finished | Sep 11 08:11:01 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341280826 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.3341280826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/36.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.1348509849 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 1571417938 ps |
| CPU time | 78.56 seconds |
| Started | Sep 11 08:12:02 PM UTC 24 |
| Finished | Sep 11 08:13:23 PM UTC 24 |
| Peak memory | 596056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348509849 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.1348509849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/37.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.825589936 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 3194421577 ps |
| CPU time | 70.84 seconds |
| Started | Sep 11 08:12:03 PM UTC 24 |
| Finished | Sep 11 08:13:16 PM UTC 24 |
| Peak memory | 593720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825589936 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.825589936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.480587405 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 917061072 ps |
| CPU time | 49.25 seconds |
| Started | Sep 11 08:12:32 PM UTC 24 |
| Finished | Sep 11 08:13:23 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480587405 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.480587405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.1381137775 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 116396935 ps |
| CPU time | 16.16 seconds |
| Started | Sep 11 08:12:24 PM UTC 24 |
| Finished | Sep 11 08:12:42 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381137775 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1381137775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/37.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.117327122 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 377513014 ps |
| CPU time | 44.49 seconds |
| Started | Sep 11 08:11:46 PM UTC 24 |
| Finished | Sep 11 08:12:32 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117327122 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.117327122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/37.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.1390396567 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 59216606666 ps |
| CPU time | 615.24 seconds |
| Started | Sep 11 08:11:55 PM UTC 24 |
| Finished | Sep 11 08:22:17 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390396567 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.1390396567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/37.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.2689039629 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 62079184961 ps |
| CPU time | 975.06 seconds |
| Started | Sep 11 08:11:56 PM UTC 24 |
| Finished | Sep 11 08:28:24 PM UTC 24 |
| Peak memory | 596012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689039629 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2689039629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/37.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.384409259 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 486852647 ps |
| CPU time | 55.91 seconds |
| Started | Sep 11 08:11:50 PM UTC 24 |
| Finished | Sep 11 08:12:47 PM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384409259 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.384409259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/37.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.3904812619 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 1707699580 ps |
| CPU time | 69.51 seconds |
| Started | Sep 11 08:12:12 PM UTC 24 |
| Finished | Sep 11 08:13:23 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904812619 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3904812619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/37.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.2674747328 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 34798290 ps |
| CPU time | 8.3 seconds |
| Started | Sep 11 08:11:27 PM UTC 24 |
| Finished | Sep 11 08:11:37 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674747328 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2674747328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/37.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.1186727851 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 10570699775 ps |
| CPU time | 93.8 seconds |
| Started | Sep 11 08:11:37 PM UTC 24 |
| Finished | Sep 11 08:13:12 PM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186727851 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1186727851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/37.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.32326988 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 5758363249 ps |
| CPU time | 101.41 seconds |
| Started | Sep 11 08:11:48 PM UTC 24 |
| Finished | Sep 11 08:13:31 PM UTC 24 |
| Peak memory | 594052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32326988 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.32326988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.2667284951 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 46450205 ps |
| CPU time | 8.92 seconds |
| Started | Sep 11 08:11:36 PM UTC 24 |
| Finished | Sep 11 08:11:46 PM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667284951 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.2667284951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/37.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.4205123913 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 12577864458 ps |
| CPU time | 472.6 seconds |
| Started | Sep 11 08:12:40 PM UTC 24 |
| Finished | Sep 11 08:20:39 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205123913 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.4205123913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/37.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.4086070724 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 3476055669 ps |
| CPU time | 118.73 seconds |
| Started | Sep 11 08:12:48 PM UTC 24 |
| Finished | Sep 11 08:14:49 PM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086070724 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.4086070724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/37.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.103635351 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 2145460757 ps |
| CPU time | 434.34 seconds |
| Started | Sep 11 08:12:47 PM UTC 24 |
| Finished | Sep 11 08:20:08 PM UTC 24 |
| Peak memory | 595884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103635351 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.103635351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.6931227 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 69716092 ps |
| CPU time | 21.3 seconds |
| Started | Sep 11 08:12:56 PM UTC 24 |
| Finished | Sep 11 08:13:19 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6931227 -assert nopostproc +UVM_TESTNAME=x bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.6931227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.136192325 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 302830461 ps |
| CPU time | 36.79 seconds |
| Started | Sep 11 08:12:23 PM UTC 24 |
| Finished | Sep 11 08:13:02 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136192325 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.136192325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/37.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.3228696747 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 1268442783 ps |
| CPU time | 76.56 seconds |
| Started | Sep 11 08:13:32 PM UTC 24 |
| Finished | Sep 11 08:14:50 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228696747 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.3228696747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/38.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.3049743951 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 23794595011 ps |
| CPU time | 406.46 seconds |
| Started | Sep 11 08:13:34 PM UTC 24 |
| Finished | Sep 11 08:20:26 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049743951 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.3049743951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.3556111652 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 928476079 ps |
| CPU time | 46.89 seconds |
| Started | Sep 11 08:13:41 PM UTC 24 |
| Finished | Sep 11 08:14:30 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556111652 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3556111652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.1777112010 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 379775891 ps |
| CPU time | 33.37 seconds |
| Started | Sep 11 08:13:37 PM UTC 24 |
| Finished | Sep 11 08:14:12 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777112010 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.1777112010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/38.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.1717944308 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 1284912510 ps |
| CPU time | 40.78 seconds |
| Started | Sep 11 08:13:20 PM UTC 24 |
| Finished | Sep 11 08:14:02 PM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717944308 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.1717944308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/38.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.392359059 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 87375090621 ps |
| CPU time | 1017.15 seconds |
| Started | Sep 11 08:13:26 PM UTC 24 |
| Finished | Sep 11 08:30:35 PM UTC 24 |
| Peak memory | 596200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392359059 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.392359059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/38.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.157206488 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 21009431520 ps |
| CPU time | 287.18 seconds |
| Started | Sep 11 08:13:31 PM UTC 24 |
| Finished | Sep 11 08:18:23 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157206488 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.157206488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/38.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.3365446919 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 115651508 ps |
| CPU time | 12.23 seconds |
| Started | Sep 11 08:13:27 PM UTC 24 |
| Finished | Sep 11 08:13:40 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365446919 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.3365446919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/38.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.1322202215 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 89918442 ps |
| CPU time | 12.94 seconds |
| Started | Sep 11 08:13:37 PM UTC 24 |
| Finished | Sep 11 08:13:51 PM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322202215 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1322202215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/38.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.1545630424 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 51908509 ps |
| CPU time | 9.28 seconds |
| Started | Sep 11 08:13:04 PM UTC 24 |
| Finished | Sep 11 08:13:15 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545630424 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1545630424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/38.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.2898183465 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 7094071673 ps |
| CPU time | 63.17 seconds |
| Started | Sep 11 08:13:09 PM UTC 24 |
| Finished | Sep 11 08:14:14 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898183465 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2898183465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/38.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.590997885 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 5677176515 ps |
| CPU time | 84.85 seconds |
| Started | Sep 11 08:13:11 PM UTC 24 |
| Finished | Sep 11 08:14:38 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590997885 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.590997885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.1349162113 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 50176031 ps |
| CPU time | 9.57 seconds |
| Started | Sep 11 08:13:05 PM UTC 24 |
| Finished | Sep 11 08:13:16 PM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349162113 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1349162113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/38.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.2235313848 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 1382449750 ps |
| CPU time | 93.63 seconds |
| Started | Sep 11 08:13:43 PM UTC 24 |
| Finished | Sep 11 08:15:18 PM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235313848 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2235313848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/38.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.2753388190 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 12306940966 ps |
| CPU time | 412.04 seconds |
| Started | Sep 11 08:13:50 PM UTC 24 |
| Finished | Sep 11 08:20:48 PM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753388190 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2753388190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/38.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.1481119727 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 453589226 ps |
| CPU time | 46.47 seconds |
| Started | Sep 11 08:13:49 PM UTC 24 |
| Finished | Sep 11 08:14:37 PM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481119727 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.1481119727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.3741692332 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 864279519 ps |
| CPU time | 201.35 seconds |
| Started | Sep 11 08:13:48 PM UTC 24 |
| Finished | Sep 11 08:17:13 PM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741692332 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.3741692332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.3556543798 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 977438569 ps |
| CPU time | 38.82 seconds |
| Started | Sep 11 08:13:40 PM UTC 24 |
| Finished | Sep 11 08:14:20 PM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556543798 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3556543798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/38.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.166445712 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 110966297 ps |
| CPU time | 12.19 seconds |
| Started | Sep 11 08:14:36 PM UTC 24 |
| Finished | Sep 11 08:14:49 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166445712 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.166445712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/39.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.3487396445 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 59927322510 ps |
| CPU time | 920.24 seconds |
| Started | Sep 11 08:14:36 PM UTC 24 |
| Finished | Sep 11 08:30:07 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487396445 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.3487396445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.152779247 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 20296489 ps |
| CPU time | 5.52 seconds |
| Started | Sep 11 08:14:58 PM UTC 24 |
| Finished | Sep 11 08:15:05 PM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152779247 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.152779247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.3419682973 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 239500706 ps |
| CPU time | 22.09 seconds |
| Started | Sep 11 08:14:51 PM UTC 24 |
| Finished | Sep 11 08:15:15 PM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419682973 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3419682973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/39.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.2424813874 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 253292312 ps |
| CPU time | 24.8 seconds |
| Started | Sep 11 08:14:24 PM UTC 24 |
| Finished | Sep 11 08:14:50 PM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424813874 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.2424813874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/39.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.1027606952 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 16049420203 ps |
| CPU time | 204.84 seconds |
| Started | Sep 11 08:14:31 PM UTC 24 |
| Finished | Sep 11 08:17:59 PM UTC 24 |
| Peak memory | 596028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027606952 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1027606952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/39.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.3766733918 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 2794349192 ps |
| CPU time | 37.55 seconds |
| Started | Sep 11 08:14:31 PM UTC 24 |
| Finished | Sep 11 08:15:10 PM UTC 24 |
| Peak memory | 593976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766733918 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3766733918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/39.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.1675445677 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 100849613 ps |
| CPU time | 15.25 seconds |
| Started | Sep 11 08:14:27 PM UTC 24 |
| Finished | Sep 11 08:14:43 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675445677 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.1675445677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/39.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.3077048995 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 411618517 ps |
| CPU time | 38.17 seconds |
| Started | Sep 11 08:14:45 PM UTC 24 |
| Finished | Sep 11 08:15:24 PM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077048995 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3077048995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/39.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.1412364378 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 210628070 ps |
| CPU time | 12.58 seconds |
| Started | Sep 11 08:13:55 PM UTC 24 |
| Finished | Sep 11 08:14:09 PM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412364378 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1412364378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/39.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.1788126617 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 6882421302 ps |
| CPU time | 75.02 seconds |
| Started | Sep 11 08:14:13 PM UTC 24 |
| Finished | Sep 11 08:15:30 PM UTC 24 |
| Peak memory | 593704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788126617 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1788126617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/39.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.1894385504 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 5241540488 ps |
| CPU time | 91.33 seconds |
| Started | Sep 11 08:14:25 PM UTC 24 |
| Finished | Sep 11 08:15:58 PM UTC 24 |
| Peak memory | 593952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894385504 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1894385504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.4198284370 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 41582375 ps |
| CPU time | 6.24 seconds |
| Started | Sep 11 08:14:03 PM UTC 24 |
| Finished | Sep 11 08:14:10 PM UTC 24 |
| Peak memory | 593952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198284370 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.4198284370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/39.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.2187787914 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 1368398880 ps |
| CPU time | 92.53 seconds |
| Started | Sep 11 08:15:03 PM UTC 24 |
| Finished | Sep 11 08:16:37 PM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187787914 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.2187787914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/39.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.4130156633 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 1958566665 ps |
| CPU time | 131.88 seconds |
| Started | Sep 11 08:15:09 PM UTC 24 |
| Finished | Sep 11 08:17:23 PM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130156633 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.4130156633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/39.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.988537058 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 2149558520 ps |
| CPU time | 268.79 seconds |
| Started | Sep 11 08:15:06 PM UTC 24 |
| Finished | Sep 11 08:19:38 PM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988537058 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.988537058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.3645666327 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 2270734234 ps |
| CPU time | 197.82 seconds |
| Started | Sep 11 08:15:11 PM UTC 24 |
| Finished | Sep 11 08:18:32 PM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645666327 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.3645666327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.686547776 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 255901726 ps |
| CPU time | 33.1 seconds |
| Started | Sep 11 08:15:01 PM UTC 24 |
| Finished | Sep 11 08:15:35 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686547776 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.686547776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/39.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_aliasing.2930676266 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 28992466173 ps |
| CPU time | 4731.55 seconds |
| Started | Sep 11 06:59:43 PM UTC 24 |
| Finished | Sep 11 08:19:30 PM UTC 24 |
| Peak memory | 620148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2930676266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_ csr_aliasing.2930676266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.3909938367 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 43830829016 ps |
| CPU time | 4521.45 seconds |
| Started | Sep 11 06:59:33 PM UTC 24 |
| Finished | Sep 11 08:15:46 PM UTC 24 |
| Peak memory | 613748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3909938367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.chip_csr_bit_bash.3909938367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.630746060 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 6061732610 ps |
| CPU time | 426.47 seconds |
| Started | Sep 11 07:02:01 PM UTC 24 |
| Finished | Sep 11 07:09:13 PM UTC 24 |
| Peak memory | 656028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=630746060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.630746060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.3039827195 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 5002694740 ps |
| CPU time | 336.22 seconds |
| Started | Sep 11 07:02:05 PM UTC 24 |
| Finished | Sep 11 07:07:46 PM UTC 24 |
| Peak memory | 614932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039827195 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.3039827195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.1671815522 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 29781975215 ps |
| CPU time | 4101.38 seconds |
| Started | Sep 11 06:59:59 PM UTC 24 |
| Finished | Sep 11 08:09:09 PM UTC 24 |
| Peak memory | 613820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1671815522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.chip_same_csr_outstanding.1671815522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.959376551 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 3853121667 ps |
| CPU time | 163.06 seconds |
| Started | Sep 11 07:00:06 PM UTC 24 |
| Finished | Sep 11 07:02:51 PM UTC 24 |
| Peak memory | 621080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959376551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.959376551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.3974248308 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 958364167 ps |
| CPU time | 55.12 seconds |
| Started | Sep 11 07:00:46 PM UTC 24 |
| Finished | Sep 11 07:01:43 PM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974248308 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.3974248308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.3331166945 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 28319119286 ps |
| CPU time | 397.35 seconds |
| Started | Sep 11 07:00:49 PM UTC 24 |
| Finished | Sep 11 07:07:31 PM UTC 24 |
| Peak memory | 596152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331166945 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.3331166945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.3417334751 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 284690713 ps |
| CPU time | 40.92 seconds |
| Started | Sep 11 07:01:46 PM UTC 24 |
| Finished | Sep 11 07:02:29 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417334751 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3417334751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.3003534611 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 274556040 ps |
| CPU time | 34.65 seconds |
| Started | Sep 11 07:00:52 PM UTC 24 |
| Finished | Sep 11 07:01:29 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003534611 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3003534611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.3522397906 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 1648106704 ps |
| CPU time | 76.13 seconds |
| Started | Sep 11 07:00:29 PM UTC 24 |
| Finished | Sep 11 07:01:47 PM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522397906 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.3522397906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.412894243 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 97584383894 ps |
| CPU time | 1084.29 seconds |
| Started | Sep 11 07:00:41 PM UTC 24 |
| Finished | Sep 11 07:18:58 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412894243 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.412894243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.1184331176 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 51106903651 ps |
| CPU time | 730.21 seconds |
| Started | Sep 11 07:00:38 PM UTC 24 |
| Finished | Sep 11 07:12:58 PM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184331176 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1184331176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.872057925 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 476345556 ps |
| CPU time | 48.28 seconds |
| Started | Sep 11 07:00:31 PM UTC 24 |
| Finished | Sep 11 07:01:21 PM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872057925 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.872057925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.1128345919 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 774225308 ps |
| CPU time | 34.81 seconds |
| Started | Sep 11 07:00:49 PM UTC 24 |
| Finished | Sep 11 07:01:26 PM UTC 24 |
| Peak memory | 595812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128345919 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1128345919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.2881374250 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 133235662 ps |
| CPU time | 9.92 seconds |
| Started | Sep 11 07:00:14 PM UTC 24 |
| Finished | Sep 11 07:00:26 PM UTC 24 |
| Peak memory | 593632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881374250 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2881374250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.3273813437 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 8213979381 ps |
| CPU time | 95.49 seconds |
| Started | Sep 11 07:00:24 PM UTC 24 |
| Finished | Sep 11 07:02:02 PM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273813437 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3273813437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.3048179338 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 4019952024 ps |
| CPU time | 85.55 seconds |
| Started | Sep 11 07:00:29 PM UTC 24 |
| Finished | Sep 11 07:01:57 PM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048179338 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.3048179338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.132802300 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 53640214 ps |
| CPU time | 9.81 seconds |
| Started | Sep 11 07:00:16 PM UTC 24 |
| Finished | Sep 11 07:00:27 PM UTC 24 |
| Peak memory | 594028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132802300 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.132802300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.3415841367 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 2152142043 ps |
| CPU time | 74.06 seconds |
| Started | Sep 11 07:01:50 PM UTC 24 |
| Finished | Sep 11 07:03:06 PM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415841367 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3415841367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.4198807499 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 11447805011 ps |
| CPU time | 389.98 seconds |
| Started | Sep 11 07:01:53 PM UTC 24 |
| Finished | Sep 11 07:08:29 PM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198807499 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.4198807499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.4094178340 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 5902460147 ps |
| CPU time | 317.94 seconds |
| Started | Sep 11 07:01:49 PM UTC 24 |
| Finished | Sep 11 07:07:12 PM UTC 24 |
| Peak memory | 595984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094178340 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.4094178340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.1738469618 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 280981528 ps |
| CPU time | 44.77 seconds |
| Started | Sep 11 07:01:09 PM UTC 24 |
| Finished | Sep 11 07:01:56 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738469618 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1738469618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.1538961567 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 357014733 ps |
| CPU time | 22.01 seconds |
| Started | Sep 11 08:15:42 PM UTC 24 |
| Finished | Sep 11 08:16:05 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538961567 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.1538961567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/40.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.1436201744 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 80090987346 ps |
| CPU time | 1064.57 seconds |
| Started | Sep 11 08:15:45 PM UTC 24 |
| Finished | Sep 11 08:33:42 PM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436201744 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.1436201744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.4022080762 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 680813280 ps |
| CPU time | 36.58 seconds |
| Started | Sep 11 08:15:56 PM UTC 24 |
| Finished | Sep 11 08:16:34 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022080762 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.4022080762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.472726883 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 2433993225 ps |
| CPU time | 92.9 seconds |
| Started | Sep 11 08:15:50 PM UTC 24 |
| Finished | Sep 11 08:17:25 PM UTC 24 |
| Peak memory | 596140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472726883 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.472726883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/40.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.685100633 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 332782960 ps |
| CPU time | 35.97 seconds |
| Started | Sep 11 08:15:27 PM UTC 24 |
| Finished | Sep 11 08:16:04 PM UTC 24 |
| Peak memory | 595920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685100633 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.685100633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/40.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.3659919620 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 101369057147 ps |
| CPU time | 925.71 seconds |
| Started | Sep 11 08:15:33 PM UTC 24 |
| Finished | Sep 11 08:31:09 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659919620 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3659919620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/40.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.449561250 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 9113472888 ps |
| CPU time | 134.77 seconds |
| Started | Sep 11 08:15:40 PM UTC 24 |
| Finished | Sep 11 08:17:57 PM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449561250 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.449561250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/40.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.1010186854 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 279206207 ps |
| CPU time | 33.76 seconds |
| Started | Sep 11 08:15:31 PM UTC 24 |
| Finished | Sep 11 08:16:07 PM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010186854 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1010186854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/40.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.2666297460 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 2577004816 ps |
| CPU time | 83.68 seconds |
| Started | Sep 11 08:15:49 PM UTC 24 |
| Finished | Sep 11 08:17:15 PM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666297460 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2666297460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/40.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.2011187286 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 193398733 ps |
| CPU time | 12.35 seconds |
| Started | Sep 11 08:15:15 PM UTC 24 |
| Finished | Sep 11 08:15:29 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011187286 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2011187286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/40.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.1181108311 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 8706613159 ps |
| CPU time | 78.85 seconds |
| Started | Sep 11 08:15:16 PM UTC 24 |
| Finished | Sep 11 08:16:36 PM UTC 24 |
| Peak memory | 593988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181108311 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1181108311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/40.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.1777682329 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 4729850251 ps |
| CPU time | 95.45 seconds |
| Started | Sep 11 08:15:28 PM UTC 24 |
| Finished | Sep 11 08:17:05 PM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777682329 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1777682329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.3549617104 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 55526067 ps |
| CPU time | 7.84 seconds |
| Started | Sep 11 08:15:15 PM UTC 24 |
| Finished | Sep 11 08:15:24 PM UTC 24 |
| Peak memory | 593636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549617104 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.3549617104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/40.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.3088266186 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 10604206188 ps |
| CPU time | 376.6 seconds |
| Started | Sep 11 08:16:01 PM UTC 24 |
| Finished | Sep 11 08:22:23 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088266186 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3088266186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/40.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.1810436094 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 1414882232 ps |
| CPU time | 52.27 seconds |
| Started | Sep 11 08:16:24 PM UTC 24 |
| Finished | Sep 11 08:17:18 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810436094 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1810436094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/40.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.2612377167 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 1442856782 ps |
| CPU time | 254.29 seconds |
| Started | Sep 11 08:16:12 PM UTC 24 |
| Finished | Sep 11 08:20:30 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612377167 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.2612377167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3557231237 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 324032542 ps |
| CPU time | 163.3 seconds |
| Started | Sep 11 08:16:31 PM UTC 24 |
| Finished | Sep 11 08:19:18 PM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557231237 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.3557231237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.2645294195 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 1420629636 ps |
| CPU time | 77.17 seconds |
| Started | Sep 11 08:15:54 PM UTC 24 |
| Finished | Sep 11 08:17:13 PM UTC 24 |
| Peak memory | 596144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645294195 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2645294195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/40.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.521027945 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 3072697325 ps |
| CPU time | 110.24 seconds |
| Started | Sep 11 08:17:10 PM UTC 24 |
| Finished | Sep 11 08:19:02 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521027945 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.521027945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/41.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2105498460 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 108349848878 ps |
| CPU time | 1729.91 seconds |
| Started | Sep 11 08:17:14 PM UTC 24 |
| Finished | Sep 11 08:46:24 PM UTC 24 |
| Peak memory | 598932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105498460 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.2105498460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.1498428739 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 557142656 ps |
| CPU time | 27.88 seconds |
| Started | Sep 11 08:17:39 PM UTC 24 |
| Finished | Sep 11 08:18:09 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498428739 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.1498428739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.3576848863 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 1906954784 ps |
| CPU time | 74.15 seconds |
| Started | Sep 11 08:17:19 PM UTC 24 |
| Finished | Sep 11 08:18:35 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576848863 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3576848863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/41.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.3841381747 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 2430838932 ps |
| CPU time | 97.53 seconds |
| Started | Sep 11 08:16:57 PM UTC 24 |
| Finished | Sep 11 08:18:37 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841381747 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.3841381747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/41.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.1527693811 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 14747118191 ps |
| CPU time | 139.26 seconds |
| Started | Sep 11 08:17:01 PM UTC 24 |
| Finished | Sep 11 08:19:22 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527693811 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1527693811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/41.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.2427635691 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 34197318721 ps |
| CPU time | 622.52 seconds |
| Started | Sep 11 08:17:07 PM UTC 24 |
| Finished | Sep 11 08:27:38 PM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427635691 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2427635691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/41.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.401786613 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 565552420 ps |
| CPU time | 62.24 seconds |
| Started | Sep 11 08:17:02 PM UTC 24 |
| Finished | Sep 11 08:18:06 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401786613 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.401786613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/41.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.3496795472 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 2193731125 ps |
| CPU time | 66.14 seconds |
| Started | Sep 11 08:17:17 PM UTC 24 |
| Finished | Sep 11 08:18:25 PM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496795472 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3496795472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/41.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.215072550 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 213254178 ps |
| CPU time | 12.98 seconds |
| Started | Sep 11 08:16:32 PM UTC 24 |
| Finished | Sep 11 08:16:46 PM UTC 24 |
| Peak memory | 593876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215072550 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.215072550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/41.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.1413401082 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 9309419485 ps |
| CPU time | 127.3 seconds |
| Started | Sep 11 08:16:41 PM UTC 24 |
| Finished | Sep 11 08:18:50 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413401082 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.1413401082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/41.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.2044227402 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 5757234823 ps |
| CPU time | 97.37 seconds |
| Started | Sep 11 08:16:58 PM UTC 24 |
| Finished | Sep 11 08:18:37 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044227402 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2044227402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.2130585310 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 54022614 ps |
| CPU time | 7.68 seconds |
| Started | Sep 11 08:16:32 PM UTC 24 |
| Finished | Sep 11 08:16:41 PM UTC 24 |
| Peak memory | 593944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130585310 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2130585310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/41.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.1763905701 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 10509220951 ps |
| CPU time | 389.28 seconds |
| Started | Sep 11 08:17:39 PM UTC 24 |
| Finished | Sep 11 08:24:14 PM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763905701 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1763905701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/41.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.3634558981 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 677208199 ps |
| CPU time | 27.03 seconds |
| Started | Sep 11 08:17:44 PM UTC 24 |
| Finished | Sep 11 08:18:13 PM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634558981 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3634558981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/41.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.3435843072 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 10588179586 ps |
| CPU time | 632.3 seconds |
| Started | Sep 11 08:17:41 PM UTC 24 |
| Finished | Sep 11 08:28:22 PM UTC 24 |
| Peak memory | 596184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435843072 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.3435843072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.2241816115 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 98944030 ps |
| CPU time | 57.37 seconds |
| Started | Sep 11 08:17:47 PM UTC 24 |
| Finished | Sep 11 08:18:46 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241816115 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.2241816115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.3201788122 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 991598864 ps |
| CPU time | 52.44 seconds |
| Started | Sep 11 08:17:29 PM UTC 24 |
| Finished | Sep 11 08:18:23 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201788122 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3201788122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/41.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.724815980 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 676725930 ps |
| CPU time | 65.67 seconds |
| Started | Sep 11 08:18:31 PM UTC 24 |
| Finished | Sep 11 08:19:38 PM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724815980 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.724815980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/42.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.2756464130 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 85407285760 ps |
| CPU time | 1136.07 seconds |
| Started | Sep 11 08:18:33 PM UTC 24 |
| Finished | Sep 11 08:37:42 PM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756464130 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.2756464130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.2525117285 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 513045546 ps |
| CPU time | 26.26 seconds |
| Started | Sep 11 08:18:47 PM UTC 24 |
| Finished | Sep 11 08:19:15 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525117285 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2525117285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.4205740365 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 465215054 ps |
| CPU time | 44 seconds |
| Started | Sep 11 08:18:38 PM UTC 24 |
| Finished | Sep 11 08:19:23 PM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205740365 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.4205740365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/42.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.2544533725 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 1913658057 ps |
| CPU time | 66.86 seconds |
| Started | Sep 11 08:18:26 PM UTC 24 |
| Finished | Sep 11 08:19:34 PM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544533725 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.2544533725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/42.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.3231360221 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 10378518607 ps |
| CPU time | 135.65 seconds |
| Started | Sep 11 08:18:26 PM UTC 24 |
| Finished | Sep 11 08:20:44 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231360221 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3231360221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/42.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.765803544 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 40581387804 ps |
| CPU time | 618.7 seconds |
| Started | Sep 11 08:18:28 PM UTC 24 |
| Finished | Sep 11 08:28:55 PM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765803544 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.765803544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/42.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.2406267083 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 388579850 ps |
| CPU time | 31.12 seconds |
| Started | Sep 11 08:18:26 PM UTC 24 |
| Finished | Sep 11 08:18:58 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406267083 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.2406267083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/42.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.3375291738 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 270837409 ps |
| CPU time | 28.17 seconds |
| Started | Sep 11 08:18:34 PM UTC 24 |
| Finished | Sep 11 08:19:04 PM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375291738 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3375291738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/42.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.1220005244 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 192821355 ps |
| CPU time | 7.95 seconds |
| Started | Sep 11 08:17:51 PM UTC 24 |
| Finished | Sep 11 08:18:00 PM UTC 24 |
| Peak memory | 593864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220005244 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1220005244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/42.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.125002112 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 9265254366 ps |
| CPU time | 91.28 seconds |
| Started | Sep 11 08:18:20 PM UTC 24 |
| Finished | Sep 11 08:19:53 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125002112 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.125002112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/42.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.218528095 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 4966467554 ps |
| CPU time | 80.02 seconds |
| Started | Sep 11 08:18:22 PM UTC 24 |
| Finished | Sep 11 08:19:44 PM UTC 24 |
| Peak memory | 593952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218528095 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.218528095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.2198681932 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 44522784 ps |
| CPU time | 8.97 seconds |
| Started | Sep 11 08:18:10 PM UTC 24 |
| Finished | Sep 11 08:18:20 PM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198681932 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.2198681932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/42.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.4073820577 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 14128464575 ps |
| CPU time | 505.64 seconds |
| Started | Sep 11 08:18:48 PM UTC 24 |
| Finished | Sep 11 08:27:21 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073820577 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.4073820577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/42.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.156571190 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 2219162490 ps |
| CPU time | 168.1 seconds |
| Started | Sep 11 08:18:49 PM UTC 24 |
| Finished | Sep 11 08:21:40 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156571190 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.156571190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/42.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.1533505974 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 11813780536 ps |
| CPU time | 665.48 seconds |
| Started | Sep 11 08:18:46 PM UTC 24 |
| Finished | Sep 11 08:30:00 PM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533505974 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.1533505974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.1201450587 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 165998134 ps |
| CPU time | 76.67 seconds |
| Started | Sep 11 08:18:55 PM UTC 24 |
| Finished | Sep 11 08:20:13 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201450587 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.1201450587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.2864565181 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 1019568862 ps |
| CPU time | 41.06 seconds |
| Started | Sep 11 08:18:45 PM UTC 24 |
| Finished | Sep 11 08:19:27 PM UTC 24 |
| Peak memory | 596084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864565181 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2864565181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/42.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.3079885853 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 813379324 ps |
| CPU time | 60.42 seconds |
| Started | Sep 11 08:19:29 PM UTC 24 |
| Finished | Sep 11 08:20:31 PM UTC 24 |
| Peak memory | 596052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079885853 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.3079885853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/43.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.2727265437 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 107710373825 ps |
| CPU time | 1790.98 seconds |
| Started | Sep 11 08:19:35 PM UTC 24 |
| Finished | Sep 11 08:49:47 PM UTC 24 |
| Peak memory | 599072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727265437 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.2727265437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.92388146 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 924750649 ps |
| CPU time | 34.81 seconds |
| Started | Sep 11 08:19:43 PM UTC 24 |
| Finished | Sep 11 08:20:20 PM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92388146 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.92388146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.47261861 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 363038563 ps |
| CPU time | 17.35 seconds |
| Started | Sep 11 08:19:39 PM UTC 24 |
| Finished | Sep 11 08:19:57 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47261861 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.47261861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/43.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.162265740 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 575731427 ps |
| CPU time | 24.36 seconds |
| Started | Sep 11 08:19:16 PM UTC 24 |
| Finished | Sep 11 08:19:42 PM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162265740 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.162265740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/43.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.3006375572 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 95257524518 ps |
| CPU time | 904.99 seconds |
| Started | Sep 11 08:19:21 PM UTC 24 |
| Finished | Sep 11 08:34:37 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006375572 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3006375572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/43.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.2968390263 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 15237259844 ps |
| CPU time | 223.5 seconds |
| Started | Sep 11 08:19:27 PM UTC 24 |
| Finished | Sep 11 08:23:14 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968390263 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2968390263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/43.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.928461045 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 524904136 ps |
| CPU time | 45.25 seconds |
| Started | Sep 11 08:19:15 PM UTC 24 |
| Finished | Sep 11 08:20:01 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928461045 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.928461045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/43.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.958104968 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 1653906087 ps |
| CPU time | 60.01 seconds |
| Started | Sep 11 08:19:36 PM UTC 24 |
| Finished | Sep 11 08:20:38 PM UTC 24 |
| Peak memory | 595876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958104968 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.958104968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/43.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.35036600 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 180610226 ps |
| CPU time | 11.07 seconds |
| Started | Sep 11 08:18:58 PM UTC 24 |
| Finished | Sep 11 08:19:11 PM UTC 24 |
| Peak memory | 593900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35036600 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.35036600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/43.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.3296086363 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 7216911681 ps |
| CPU time | 77.55 seconds |
| Started | Sep 11 08:19:03 PM UTC 24 |
| Finished | Sep 11 08:20:23 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296086363 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3296086363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/43.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.1297722423 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 4956013620 ps |
| CPU time | 98.68 seconds |
| Started | Sep 11 08:19:12 PM UTC 24 |
| Finished | Sep 11 08:20:52 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297722423 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1297722423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.1962796851 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 52713443 ps |
| CPU time | 7.5 seconds |
| Started | Sep 11 08:19:02 PM UTC 24 |
| Finished | Sep 11 08:19:10 PM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962796851 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.1962796851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/43.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.996634087 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 13694693635 ps |
| CPU time | 510.83 seconds |
| Started | Sep 11 08:19:43 PM UTC 24 |
| Finished | Sep 11 08:28:22 PM UTC 24 |
| Peak memory | 595940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996634087 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.996634087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/43.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.2440041727 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 8840453165 ps |
| CPU time | 274.2 seconds |
| Started | Sep 11 08:19:51 PM UTC 24 |
| Finished | Sep 11 08:24:29 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440041727 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2440041727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/43.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.1893367176 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 2020848739 ps |
| CPU time | 358.62 seconds |
| Started | Sep 11 08:19:49 PM UTC 24 |
| Finished | Sep 11 08:25:53 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893367176 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.1893367176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.4093115876 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 1291754754 ps |
| CPU time | 102.12 seconds |
| Started | Sep 11 08:19:52 PM UTC 24 |
| Finished | Sep 11 08:21:37 PM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093115876 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.4093115876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.1526800451 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 201098853 ps |
| CPU time | 15.25 seconds |
| Started | Sep 11 08:19:40 PM UTC 24 |
| Finished | Sep 11 08:19:57 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526800451 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1526800451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/43.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.3916951394 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 708640366 ps |
| CPU time | 42.22 seconds |
| Started | Sep 11 08:20:27 PM UTC 24 |
| Finished | Sep 11 08:21:11 PM UTC 24 |
| Peak memory | 596072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916951394 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.3916951394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/44.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1847268421 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 99205605354 ps |
| CPU time | 1530.56 seconds |
| Started | Sep 11 08:20:32 PM UTC 24 |
| Finished | Sep 11 08:46:21 PM UTC 24 |
| Peak memory | 598932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847268421 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.1847268421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.3738111428 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 32737610 ps |
| CPU time | 7.75 seconds |
| Started | Sep 11 08:20:41 PM UTC 24 |
| Finished | Sep 11 08:20:50 PM UTC 24 |
| Peak memory | 593780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738111428 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.3738111428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.989375559 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 366414080 ps |
| CPU time | 29.74 seconds |
| Started | Sep 11 08:20:34 PM UTC 24 |
| Finished | Sep 11 08:21:05 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989375559 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.989375559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/44.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.785169372 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 1906963685 ps |
| CPU time | 55.23 seconds |
| Started | Sep 11 08:20:07 PM UTC 24 |
| Finished | Sep 11 08:21:04 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785169372 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.785169372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/44.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.59523630 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 100680431785 ps |
| CPU time | 1055.63 seconds |
| Started | Sep 11 08:20:20 PM UTC 24 |
| Finished | Sep 11 08:38:09 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59523630 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.59523630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/44.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.3058121665 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 34529589345 ps |
| CPU time | 501.03 seconds |
| Started | Sep 11 08:20:21 PM UTC 24 |
| Finished | Sep 11 08:28:48 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058121665 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3058121665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/44.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.3249565195 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 500714842 ps |
| CPU time | 44.19 seconds |
| Started | Sep 11 08:20:17 PM UTC 24 |
| Finished | Sep 11 08:21:02 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249565195 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.3249565195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/44.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.331108741 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 1875440905 ps |
| CPU time | 61.82 seconds |
| Started | Sep 11 08:20:32 PM UTC 24 |
| Finished | Sep 11 08:21:36 PM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331108741 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.331108741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/44.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.2105522396 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 53658508 ps |
| CPU time | 9.71 seconds |
| Started | Sep 11 08:19:56 PM UTC 24 |
| Finished | Sep 11 08:20:07 PM UTC 24 |
| Peak memory | 594024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105522396 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2105522396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/44.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.2838436073 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 7022322335 ps |
| CPU time | 92.46 seconds |
| Started | Sep 11 08:19:59 PM UTC 24 |
| Finished | Sep 11 08:21:34 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838436073 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2838436073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/44.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.3284619670 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 4524689409 ps |
| CPU time | 93.39 seconds |
| Started | Sep 11 08:20:01 PM UTC 24 |
| Finished | Sep 11 08:21:36 PM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284619670 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.3284619670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.1975952204 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 39611546 ps |
| CPU time | 8.56 seconds |
| Started | Sep 11 08:19:59 PM UTC 24 |
| Finished | Sep 11 08:20:09 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975952204 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.1975952204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/44.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.2336868416 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 4974869782 ps |
| CPU time | 422.31 seconds |
| Started | Sep 11 08:20:45 PM UTC 24 |
| Finished | Sep 11 08:27:53 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336868416 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.2336868416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/44.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.1867689881 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 4540945408 ps |
| CPU time | 192.89 seconds |
| Started | Sep 11 08:20:51 PM UTC 24 |
| Finished | Sep 11 08:24:07 PM UTC 24 |
| Peak memory | 595980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867689881 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1867689881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/44.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.1939527121 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 5466829675 ps |
| CPU time | 210.67 seconds |
| Started | Sep 11 08:20:49 PM UTC 24 |
| Finished | Sep 11 08:24:23 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939527121 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.1939527121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.4225080876 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 1674488264 ps |
| CPU time | 293.39 seconds |
| Started | Sep 11 08:20:56 PM UTC 24 |
| Finished | Sep 11 08:25:54 PM UTC 24 |
| Peak memory | 595880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225080876 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.4225080876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.1346346278 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 134973453 ps |
| CPU time | 19.85 seconds |
| Started | Sep 11 08:20:37 PM UTC 24 |
| Finished | Sep 11 08:20:58 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346346278 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1346346278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/44.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.12239597 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 1302718084 ps |
| CPU time | 89.16 seconds |
| Started | Sep 11 08:21:27 PM UTC 24 |
| Finished | Sep 11 08:22:58 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12239597 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.12239597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/45.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.4177295316 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 118351277434 ps |
| CPU time | 1689.92 seconds |
| Started | Sep 11 08:21:26 PM UTC 24 |
| Finished | Sep 11 08:49:55 PM UTC 24 |
| Peak memory | 599164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177295316 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.4177295316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.2597682209 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 739467210 ps |
| CPU time | 38.18 seconds |
| Started | Sep 11 08:21:38 PM UTC 24 |
| Finished | Sep 11 08:22:18 PM UTC 24 |
| Peak memory | 595964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597682209 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.2597682209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.1369661209 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 522068524 ps |
| CPU time | 38.1 seconds |
| Started | Sep 11 08:21:30 PM UTC 24 |
| Finished | Sep 11 08:22:11 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369661209 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1369661209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/45.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.1204655995 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 221216913 ps |
| CPU time | 26.31 seconds |
| Started | Sep 11 08:21:14 PM UTC 24 |
| Finished | Sep 11 08:21:41 PM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204655995 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.1204655995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/45.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.1972940251 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 21767955567 ps |
| CPU time | 278.09 seconds |
| Started | Sep 11 08:21:16 PM UTC 24 |
| Finished | Sep 11 08:25:59 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972940251 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.1972940251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/45.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.4058399516 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 8228577450 ps |
| CPU time | 120.66 seconds |
| Started | Sep 11 08:21:22 PM UTC 24 |
| Finished | Sep 11 08:23:24 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058399516 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.4058399516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/45.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.2236638004 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 599883129 ps |
| CPU time | 66.66 seconds |
| Started | Sep 11 08:21:14 PM UTC 24 |
| Finished | Sep 11 08:22:22 PM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236638004 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2236638004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/45.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.2946354171 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 262138473 ps |
| CPU time | 19.94 seconds |
| Started | Sep 11 08:21:29 PM UTC 24 |
| Finished | Sep 11 08:21:50 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946354171 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2946354171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/45.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.4102453518 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 220990340 ps |
| CPU time | 13.64 seconds |
| Started | Sep 11 08:20:51 PM UTC 24 |
| Finished | Sep 11 08:21:05 PM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102453518 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.4102453518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/45.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.1066842008 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 8202189939 ps |
| CPU time | 98.47 seconds |
| Started | Sep 11 08:21:04 PM UTC 24 |
| Finished | Sep 11 08:22:45 PM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066842008 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1066842008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/45.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.2215962202 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 5892427930 ps |
| CPU time | 96.54 seconds |
| Started | Sep 11 08:21:08 PM UTC 24 |
| Finished | Sep 11 08:22:46 PM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215962202 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.2215962202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.424272570 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 50298698 ps |
| CPU time | 7.43 seconds |
| Started | Sep 11 08:21:05 PM UTC 24 |
| Finished | Sep 11 08:21:13 PM UTC 24 |
| Peak memory | 593776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424272570 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.424272570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/45.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.1726490051 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 10220958063 ps |
| CPU time | 330.15 seconds |
| Started | Sep 11 08:22:00 PM UTC 24 |
| Finished | Sep 11 08:27:35 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726490051 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1726490051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/45.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.662895209 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 7725780266 ps |
| CPU time | 253.48 seconds |
| Started | Sep 11 08:22:02 PM UTC 24 |
| Finished | Sep 11 08:26:20 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662895209 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.662895209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/45.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.265979894 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 1799508099 ps |
| CPU time | 423.43 seconds |
| Started | Sep 11 08:22:01 PM UTC 24 |
| Finished | Sep 11 08:29:10 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265979894 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.265979894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.1361492606 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 2451142436 ps |
| CPU time | 134.38 seconds |
| Started | Sep 11 08:22:01 PM UTC 24 |
| Finished | Sep 11 08:24:17 PM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361492606 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.1361492606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.389638791 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 939376971 ps |
| CPU time | 48.67 seconds |
| Started | Sep 11 08:21:36 PM UTC 24 |
| Finished | Sep 11 08:22:26 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389638791 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.389638791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/45.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.4011272164 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 885822692 ps |
| CPU time | 59.83 seconds |
| Started | Sep 11 08:22:41 PM UTC 24 |
| Finished | Sep 11 08:23:42 PM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011272164 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.4011272164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/46.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.3530192193 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 102678380179 ps |
| CPU time | 1653.48 seconds |
| Started | Sep 11 08:22:49 PM UTC 24 |
| Finished | Sep 11 08:50:41 PM UTC 24 |
| Peak memory | 598816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530192193 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.3530192193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.1014269363 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 113399980 ps |
| CPU time | 14.01 seconds |
| Started | Sep 11 08:23:10 PM UTC 24 |
| Finished | Sep 11 08:23:25 PM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014269363 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.1014269363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.102077702 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 271223948 ps |
| CPU time | 24.07 seconds |
| Started | Sep 11 08:22:52 PM UTC 24 |
| Finished | Sep 11 08:23:18 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102077702 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.102077702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/46.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.3622535265 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 619988518 ps |
| CPU time | 68.97 seconds |
| Started | Sep 11 08:22:37 PM UTC 24 |
| Finished | Sep 11 08:23:48 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622535265 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.3622535265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/46.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.670752552 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 6078526835 ps |
| CPU time | 63.22 seconds |
| Started | Sep 11 08:22:42 PM UTC 24 |
| Finished | Sep 11 08:23:47 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670752552 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.670752552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/46.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.522010245 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 59007788311 ps |
| CPU time | 948.95 seconds |
| Started | Sep 11 08:22:43 PM UTC 24 |
| Finished | Sep 11 08:38:43 PM UTC 24 |
| Peak memory | 596156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522010245 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.522010245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/46.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.2094650957 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 269046195 ps |
| CPU time | 22.19 seconds |
| Started | Sep 11 08:22:42 PM UTC 24 |
| Finished | Sep 11 08:23:05 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094650957 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2094650957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/46.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.3775163886 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 1641451119 ps |
| CPU time | 46.7 seconds |
| Started | Sep 11 08:22:49 PM UTC 24 |
| Finished | Sep 11 08:23:37 PM UTC 24 |
| Peak memory | 595692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775163886 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3775163886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/46.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.3977495015 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 145736270 ps |
| CPU time | 10.87 seconds |
| Started | Sep 11 08:22:05 PM UTC 24 |
| Finished | Sep 11 08:22:17 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977495015 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3977495015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/46.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.3128791508 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 8415346099 ps |
| CPU time | 89.74 seconds |
| Started | Sep 11 08:22:16 PM UTC 24 |
| Finished | Sep 11 08:23:47 PM UTC 24 |
| Peak memory | 594144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128791508 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3128791508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/46.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.1898764352 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 4535662346 ps |
| CPU time | 67.55 seconds |
| Started | Sep 11 08:22:29 PM UTC 24 |
| Finished | Sep 11 08:23:39 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898764352 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1898764352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.2522438207 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 42804411 ps |
| CPU time | 9.19 seconds |
| Started | Sep 11 08:22:05 PM UTC 24 |
| Finished | Sep 11 08:22:16 PM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522438207 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.2522438207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/46.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.2488593987 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 1455581456 ps |
| CPU time | 110.18 seconds |
| Started | Sep 11 08:23:10 PM UTC 24 |
| Finished | Sep 11 08:25:03 PM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488593987 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2488593987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/46.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.2327066890 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 16040502697 ps |
| CPU time | 539.29 seconds |
| Started | Sep 11 08:23:31 PM UTC 24 |
| Finished | Sep 11 08:32:38 PM UTC 24 |
| Peak memory | 596012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327066890 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2327066890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/46.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.39725581 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 5329675755 ps |
| CPU time | 613.66 seconds |
| Started | Sep 11 08:23:22 PM UTC 24 |
| Finished | Sep 11 08:33:44 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39725581 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.39725581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.1018690782 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 6361264990 ps |
| CPU time | 567.45 seconds |
| Started | Sep 11 08:23:40 PM UTC 24 |
| Finished | Sep 11 08:33:15 PM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018690782 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.1018690782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.2036665750 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 207950235 ps |
| CPU time | 35.33 seconds |
| Started | Sep 11 08:22:54 PM UTC 24 |
| Finished | Sep 11 08:23:30 PM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036665750 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2036665750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/46.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.1591032065 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 101819382 ps |
| CPU time | 12.48 seconds |
| Started | Sep 11 08:24:12 PM UTC 24 |
| Finished | Sep 11 08:24:25 PM UTC 24 |
| Peak memory | 593808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591032065 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.1591032065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/47.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.1063563940 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 97351469202 ps |
| CPU time | 1303.69 seconds |
| Started | Sep 11 08:24:10 PM UTC 24 |
| Finished | Sep 11 08:46:08 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063563940 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.1063563940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.143314238 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 1287918380 ps |
| CPU time | 46.5 seconds |
| Started | Sep 11 08:24:32 PM UTC 24 |
| Finished | Sep 11 08:25:20 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143314238 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.143314238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.3554520940 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 164475547 ps |
| CPU time | 18.37 seconds |
| Started | Sep 11 08:24:25 PM UTC 24 |
| Finished | Sep 11 08:24:44 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554520940 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3554520940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/47.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.4208805446 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 635253767 ps |
| CPU time | 32.44 seconds |
| Started | Sep 11 08:24:03 PM UTC 24 |
| Finished | Sep 11 08:24:37 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208805446 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.4208805446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/47.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.1153825890 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 55051717882 ps |
| CPU time | 706.52 seconds |
| Started | Sep 11 08:24:05 PM UTC 24 |
| Finished | Sep 11 08:36:01 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153825890 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1153825890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/47.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.2322865480 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 42107029490 ps |
| CPU time | 638.88 seconds |
| Started | Sep 11 08:24:11 PM UTC 24 |
| Finished | Sep 11 08:34:57 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322865480 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2322865480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/47.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.1799719227 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 547989206 ps |
| CPU time | 44.22 seconds |
| Started | Sep 11 08:24:04 PM UTC 24 |
| Finished | Sep 11 08:24:50 PM UTC 24 |
| Peak memory | 596140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799719227 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.1799719227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/47.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.2322604770 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 368889640 ps |
| CPU time | 33.6 seconds |
| Started | Sep 11 08:24:13 PM UTC 24 |
| Finished | Sep 11 08:24:48 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322604770 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2322604770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/47.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.3374974533 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 234992694 ps |
| CPU time | 13.96 seconds |
| Started | Sep 11 08:23:43 PM UTC 24 |
| Finished | Sep 11 08:23:58 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374974533 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3374974533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/47.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.4216059744 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 7425697916 ps |
| CPU time | 67.35 seconds |
| Started | Sep 11 08:23:49 PM UTC 24 |
| Finished | Sep 11 08:24:58 PM UTC 24 |
| Peak memory | 593704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216059744 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.4216059744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/47.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.2934966467 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 5949892168 ps |
| CPU time | 105.2 seconds |
| Started | Sep 11 08:23:53 PM UTC 24 |
| Finished | Sep 11 08:25:41 PM UTC 24 |
| Peak memory | 594092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934966467 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2934966467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.2168357974 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 51518939 ps |
| CPU time | 9.05 seconds |
| Started | Sep 11 08:23:50 PM UTC 24 |
| Finished | Sep 11 08:24:00 PM UTC 24 |
| Peak memory | 593888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168357974 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.2168357974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/47.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.15359785 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 2259314356 ps |
| CPU time | 180.04 seconds |
| Started | Sep 11 08:24:40 PM UTC 24 |
| Finished | Sep 11 08:27:43 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15359785 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.15359785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/47.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.3073261835 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 7315639240 ps |
| CPU time | 268.22 seconds |
| Started | Sep 11 08:24:46 PM UTC 24 |
| Finished | Sep 11 08:29:18 PM UTC 24 |
| Peak memory | 595980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073261835 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3073261835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/47.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.2646029262 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 797719419 ps |
| CPU time | 242.44 seconds |
| Started | Sep 11 08:24:42 PM UTC 24 |
| Finished | Sep 11 08:28:48 PM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646029262 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.2646029262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.2334363274 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 116067885 ps |
| CPU time | 44.42 seconds |
| Started | Sep 11 08:24:48 PM UTC 24 |
| Finished | Sep 11 08:25:33 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334363274 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.2334363274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.1443251080 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 480392023 ps |
| CPU time | 20.46 seconds |
| Started | Sep 11 08:24:26 PM UTC 24 |
| Finished | Sep 11 08:24:48 PM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443251080 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1443251080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/47.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.3206635838 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 476312760 ps |
| CPU time | 41.99 seconds |
| Started | Sep 11 08:25:23 PM UTC 24 |
| Finished | Sep 11 08:26:06 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206635838 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3206635838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/48.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.1551013659 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 125943150334 ps |
| CPU time | 2099.71 seconds |
| Started | Sep 11 08:25:28 PM UTC 24 |
| Finished | Sep 11 09:00:52 PM UTC 24 |
| Peak memory | 599072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551013659 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.1551013659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.784382247 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 174086432 ps |
| CPU time | 25.35 seconds |
| Started | Sep 11 08:26:03 PM UTC 24 |
| Finished | Sep 11 08:26:30 PM UTC 24 |
| Peak memory | 595692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784382247 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.784382247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.2263373466 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 602451040 ps |
| CPU time | 50.37 seconds |
| Started | Sep 11 08:25:45 PM UTC 24 |
| Finished | Sep 11 08:26:37 PM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263373466 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2263373466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/48.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.1097751576 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 2684471320 ps |
| CPU time | 117.2 seconds |
| Started | Sep 11 08:25:13 PM UTC 24 |
| Finished | Sep 11 08:27:13 PM UTC 24 |
| Peak memory | 595920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097751576 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.1097751576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/48.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.150001363 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 29532303009 ps |
| CPU time | 415.8 seconds |
| Started | Sep 11 08:25:12 PM UTC 24 |
| Finished | Sep 11 08:32:14 PM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150001363 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.150001363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/48.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.2415751878 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 48522227835 ps |
| CPU time | 718.58 seconds |
| Started | Sep 11 08:25:24 PM UTC 24 |
| Finished | Sep 11 08:37:32 PM UTC 24 |
| Peak memory | 596200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415751878 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2415751878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/48.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.4072903205 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 539936580 ps |
| CPU time | 52.95 seconds |
| Started | Sep 11 08:25:14 PM UTC 24 |
| Finished | Sep 11 08:26:09 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072903205 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.4072903205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/48.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.3738961645 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 1179685640 ps |
| CPU time | 37.55 seconds |
| Started | Sep 11 08:25:30 PM UTC 24 |
| Finished | Sep 11 08:26:09 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738961645 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3738961645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/48.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.4160224939 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 248601567 ps |
| CPU time | 10.81 seconds |
| Started | Sep 11 08:24:52 PM UTC 24 |
| Finished | Sep 11 08:25:04 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160224939 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.4160224939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/48.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.742736372 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 8450472466 ps |
| CPU time | 95.57 seconds |
| Started | Sep 11 08:25:00 PM UTC 24 |
| Finished | Sep 11 08:26:37 PM UTC 24 |
| Peak memory | 594052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742736372 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.742736372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/48.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.2625465480 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 5949567410 ps |
| CPU time | 131.35 seconds |
| Started | Sep 11 08:25:10 PM UTC 24 |
| Finished | Sep 11 08:27:24 PM UTC 24 |
| Peak memory | 594092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625465480 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.2625465480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.2393431890 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 49180502 ps |
| CPU time | 7.68 seconds |
| Started | Sep 11 08:24:52 PM UTC 24 |
| Finished | Sep 11 08:25:01 PM UTC 24 |
| Peak memory | 594012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393431890 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2393431890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/48.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.3132623753 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 2525458997 ps |
| CPU time | 238.29 seconds |
| Started | Sep 11 08:26:20 PM UTC 24 |
| Finished | Sep 11 08:30:22 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132623753 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3132623753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/48.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.2099735686 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 9205668108 ps |
| CPU time | 273.7 seconds |
| Started | Sep 11 08:26:23 PM UTC 24 |
| Finished | Sep 11 08:31:01 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099735686 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2099735686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/48.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.2364050407 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 2413729419 ps |
| CPU time | 191.44 seconds |
| Started | Sep 11 08:26:19 PM UTC 24 |
| Finished | Sep 11 08:29:34 PM UTC 24 |
| Peak memory | 596056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364050407 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.2364050407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.252222285 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 2860295588 ps |
| CPU time | 324.47 seconds |
| Started | Sep 11 08:26:24 PM UTC 24 |
| Finished | Sep 11 08:31:54 PM UTC 24 |
| Peak memory | 596144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252222285 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.252222285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.3743327155 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 66578865 ps |
| CPU time | 9.3 seconds |
| Started | Sep 11 08:25:59 PM UTC 24 |
| Finished | Sep 11 08:26:09 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743327155 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3743327155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/48.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.4096882219 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 751012055 ps |
| CPU time | 57.35 seconds |
| Started | Sep 11 08:27:01 PM UTC 24 |
| Finished | Sep 11 08:28:00 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096882219 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.4096882219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/49.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.1929070749 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 58060747441 ps |
| CPU time | 863.31 seconds |
| Started | Sep 11 08:27:01 PM UTC 24 |
| Finished | Sep 11 08:41:35 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929070749 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.1929070749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.3315282727 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 491244570 ps |
| CPU time | 25.99 seconds |
| Started | Sep 11 08:27:22 PM UTC 24 |
| Finished | Sep 11 08:27:50 PM UTC 24 |
| Peak memory | 596068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315282727 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.3315282727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.736931971 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 68263589 ps |
| CPU time | 6.99 seconds |
| Started | Sep 11 08:26:59 PM UTC 24 |
| Finished | Sep 11 08:27:07 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736931971 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.736931971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/49.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.802791684 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 609579293 ps |
| CPU time | 58.17 seconds |
| Started | Sep 11 08:26:31 PM UTC 24 |
| Finished | Sep 11 08:27:31 PM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802791684 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.802791684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/49.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.850741028 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 43632951017 ps |
| CPU time | 418.7 seconds |
| Started | Sep 11 08:26:56 PM UTC 24 |
| Finished | Sep 11 08:34:00 PM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850741028 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.850741028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/49.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.1063952541 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 11377454821 ps |
| CPU time | 185.04 seconds |
| Started | Sep 11 08:27:00 PM UTC 24 |
| Finished | Sep 11 08:30:08 PM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063952541 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1063952541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/49.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.1016643522 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 145285258 ps |
| CPU time | 19.05 seconds |
| Started | Sep 11 08:26:41 PM UTC 24 |
| Finished | Sep 11 08:27:02 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016643522 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.1016643522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/49.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.2774686335 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 521701657 ps |
| CPU time | 36 seconds |
| Started | Sep 11 08:27:04 PM UTC 24 |
| Finished | Sep 11 08:27:41 PM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774686335 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2774686335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/49.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.2326195549 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 46055365 ps |
| CPU time | 9.4 seconds |
| Started | Sep 11 08:26:25 PM UTC 24 |
| Finished | Sep 11 08:26:35 PM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326195549 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2326195549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/49.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.551845323 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 7481468718 ps |
| CPU time | 111.93 seconds |
| Started | Sep 11 08:26:33 PM UTC 24 |
| Finished | Sep 11 08:28:27 PM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551845323 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.551845323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/49.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.3821239110 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 3640393862 ps |
| CPU time | 67.43 seconds |
| Started | Sep 11 08:26:34 PM UTC 24 |
| Finished | Sep 11 08:27:43 PM UTC 24 |
| Peak memory | 593784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821239110 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3821239110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3322526698 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 45177567 ps |
| CPU time | 6.56 seconds |
| Started | Sep 11 08:26:29 PM UTC 24 |
| Finished | Sep 11 08:26:37 PM UTC 24 |
| Peak memory | 593876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322526698 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3322526698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/49.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.1829395958 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 10933784314 ps |
| CPU time | 397.49 seconds |
| Started | Sep 11 08:27:34 PM UTC 24 |
| Finished | Sep 11 08:34:17 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829395958 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1829395958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/49.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.259634309 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 1304067538 ps |
| CPU time | 84.63 seconds |
| Started | Sep 11 08:27:45 PM UTC 24 |
| Finished | Sep 11 08:29:11 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259634309 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.259634309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/49.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.1003531703 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 274441292 ps |
| CPU time | 142.21 seconds |
| Started | Sep 11 08:27:37 PM UTC 24 |
| Finished | Sep 11 08:30:01 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003531703 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.1003531703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.3509508878 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 7909286683 ps |
| CPU time | 670.63 seconds |
| Started | Sep 11 08:27:49 PM UTC 24 |
| Finished | Sep 11 08:39:08 PM UTC 24 |
| Peak memory | 599868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509508878 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.3509508878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.2235947007 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 1410279635 ps |
| CPU time | 64.51 seconds |
| Started | Sep 11 08:27:18 PM UTC 24 |
| Finished | Sep 11 08:28:24 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235947007 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2235947007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/49.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.2012891587 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 9828202135 ps |
| CPU time | 677.8 seconds |
| Started | Sep 11 07:04:07 PM UTC 24 |
| Finished | Sep 11 07:15:33 PM UTC 24 |
| Peak memory | 670108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2012891587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 5.chip_csr_mem_rw_with_rand_reset.2012891587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.3427677563 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 3589871620 ps |
| CPU time | 278.06 seconds |
| Started | Sep 11 07:04:00 PM UTC 24 |
| Finished | Sep 11 07:08:42 PM UTC 24 |
| Peak memory | 616932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427677563 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.3427677563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.2565785525 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 31190223269 ps |
| CPU time | 3425.99 seconds |
| Started | Sep 11 07:02:08 PM UTC 24 |
| Finished | Sep 11 07:59:54 PM UTC 24 |
| Peak memory | 610788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2565785525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.chip_same_csr_outstanding.2565785525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.3992057246 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 3679436545 ps |
| CPU time | 301.29 seconds |
| Started | Sep 11 07:02:11 PM UTC 24 |
| Finished | Sep 11 07:07:18 PM UTC 24 |
| Peak memory | 620952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992057246 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.3992057246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.3317366633 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 2655808609 ps |
| CPU time | 93.61 seconds |
| Started | Sep 11 07:02:56 PM UTC 24 |
| Finished | Sep 11 07:04:32 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317366633 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3317366633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1035460207 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 25785172457 ps |
| CPU time | 529.95 seconds |
| Started | Sep 11 07:03:02 PM UTC 24 |
| Finished | Sep 11 07:11:59 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035460207 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.1035460207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.1830066862 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 256348591 ps |
| CPU time | 37.95 seconds |
| Started | Sep 11 07:03:30 PM UTC 24 |
| Finished | Sep 11 07:04:10 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830066862 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1830066862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.3243188061 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 649806721 ps |
| CPU time | 28.75 seconds |
| Started | Sep 11 07:03:17 PM UTC 24 |
| Finished | Sep 11 07:03:47 PM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243188061 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3243188061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.4242487632 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 2144793830 ps |
| CPU time | 97.78 seconds |
| Started | Sep 11 07:02:50 PM UTC 24 |
| Finished | Sep 11 07:04:30 PM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242487632 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.4242487632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.3463507241 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 35654075497 ps |
| CPU time | 383.67 seconds |
| Started | Sep 11 07:02:53 PM UTC 24 |
| Finished | Sep 11 07:09:22 PM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463507241 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3463507241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.2206767541 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 25832525739 ps |
| CPU time | 431.54 seconds |
| Started | Sep 11 07:02:56 PM UTC 24 |
| Finished | Sep 11 07:10:14 PM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206767541 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2206767541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.4188657423 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 372887304 ps |
| CPU time | 44.48 seconds |
| Started | Sep 11 07:02:54 PM UTC 24 |
| Finished | Sep 11 07:03:40 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188657423 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.4188657423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.4106401116 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 554750010 ps |
| CPU time | 23.31 seconds |
| Started | Sep 11 07:03:09 PM UTC 24 |
| Finished | Sep 11 07:03:34 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106401116 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.4106401116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.2849014019 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 186533576 ps |
| CPU time | 11.67 seconds |
| Started | Sep 11 07:02:18 PM UTC 24 |
| Finished | Sep 11 07:02:31 PM UTC 24 |
| Peak memory | 593636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849014019 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2849014019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.2992505341 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 8913076342 ps |
| CPU time | 118.98 seconds |
| Started | Sep 11 07:02:24 PM UTC 24 |
| Finished | Sep 11 07:04:25 PM UTC 24 |
| Peak memory | 593844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992505341 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2992505341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.4253474238 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 6419901188 ps |
| CPU time | 122.39 seconds |
| Started | Sep 11 07:02:30 PM UTC 24 |
| Finished | Sep 11 07:04:35 PM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253474238 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.4253474238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.1263484062 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 42930366 ps |
| CPU time | 9.17 seconds |
| Started | Sep 11 07:02:18 PM UTC 24 |
| Finished | Sep 11 07:02:28 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263484062 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.1263484062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.2979561548 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 9449151868 ps |
| CPU time | 460.66 seconds |
| Started | Sep 11 07:03:52 PM UTC 24 |
| Finished | Sep 11 07:11:39 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979561548 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2979561548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.2565322076 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 1704467855 ps |
| CPU time | 105.55 seconds |
| Started | Sep 11 07:03:57 PM UTC 24 |
| Finished | Sep 11 07:05:45 PM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565322076 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2565322076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.856693275 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 8689769794 ps |
| CPU time | 358.95 seconds |
| Started | Sep 11 07:03:58 PM UTC 24 |
| Finished | Sep 11 07:10:03 PM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856693275 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.856693275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.3739012873 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 3072513199 ps |
| CPU time | 251.85 seconds |
| Started | Sep 11 07:04:03 PM UTC 24 |
| Finished | Sep 11 07:08:19 PM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739012873 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.3739012873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.895166507 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 73344714 ps |
| CPU time | 16.86 seconds |
| Started | Sep 11 07:03:19 PM UTC 24 |
| Finished | Sep 11 07:03:38 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895166507 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.895166507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.3934357620 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 1191797370 ps |
| CPU time | 65.15 seconds |
| Started | Sep 11 08:28:19 PM UTC 24 |
| Finished | Sep 11 08:29:26 PM UTC 24 |
| Peak memory | 596072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934357620 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device.3934357620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/50.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.289829232 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 128851819829 ps |
| CPU time | 1779.96 seconds |
| Started | Sep 11 08:28:14 PM UTC 24 |
| Finished | Sep 11 08:58:15 PM UTC 24 |
| Peak memory | 599000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289829232 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device_slow_rsp.289829232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.721349737 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 1458590671 ps |
| CPU time | 49.6 seconds |
| Started | Sep 11 08:28:35 PM UTC 24 |
| Finished | Sep 11 08:29:26 PM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721349737 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_addr.721349737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.2210265992 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 2232833647 ps |
| CPU time | 89.57 seconds |
| Started | Sep 11 08:28:28 PM UTC 24 |
| Finished | Sep 11 08:30:00 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210265992 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.2210265992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/50.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.3999426710 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 1353782278 ps |
| CPU time | 53.39 seconds |
| Started | Sep 11 08:28:05 PM UTC 24 |
| Finished | Sep 11 08:29:00 PM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999426710 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.3999426710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/50.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.1980712743 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 97598690857 ps |
| CPU time | 947.25 seconds |
| Started | Sep 11 08:28:08 PM UTC 24 |
| Finished | Sep 11 08:44:07 PM UTC 24 |
| Peak memory | 595940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980712743 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.1980712743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/50.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.1151547611 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 50121530354 ps |
| CPU time | 741.86 seconds |
| Started | Sep 11 08:28:16 PM UTC 24 |
| Finished | Sep 11 08:40:47 PM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151547611 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.1151547611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/50.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.4060680470 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 69660694 ps |
| CPU time | 10.1 seconds |
| Started | Sep 11 08:28:09 PM UTC 24 |
| Finished | Sep 11 08:28:20 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060680470 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_delays.4060680470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/50.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.1370087028 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 1003853630 ps |
| CPU time | 28.06 seconds |
| Started | Sep 11 08:28:26 PM UTC 24 |
| Finished | Sep 11 08:28:55 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370087028 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.1370087028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/50.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.2606536942 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 47903213 ps |
| CPU time | 7.06 seconds |
| Started | Sep 11 08:27:54 PM UTC 24 |
| Finished | Sep 11 08:28:02 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606536942 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.2606536942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/50.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.3329826225 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 8040084259 ps |
| CPU time | 83.04 seconds |
| Started | Sep 11 08:27:57 PM UTC 24 |
| Finished | Sep 11 08:29:22 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329826225 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.3329826225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/50.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.108637698 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 5812277398 ps |
| CPU time | 87.41 seconds |
| Started | Sep 11 08:27:59 PM UTC 24 |
| Finished | Sep 11 08:29:29 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108637698 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.108637698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.1833590427 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 52432933 ps |
| CPU time | 8.97 seconds |
| Started | Sep 11 08:28:00 PM UTC 24 |
| Finished | Sep 11 08:28:11 PM UTC 24 |
| Peak memory | 593980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833590427 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delays.1833590427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/50.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.231403603 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 2073727498 ps |
| CPU time | 75.83 seconds |
| Started | Sep 11 08:28:45 PM UTC 24 |
| Finished | Sep 11 08:30:02 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231403603 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.231403603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/50.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.3840334538 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 1505298654 ps |
| CPU time | 94.06 seconds |
| Started | Sep 11 08:28:47 PM UTC 24 |
| Finished | Sep 11 08:30:23 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840334538 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.3840334538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/50.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.3891579084 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 3347545601 ps |
| CPU time | 364.38 seconds |
| Started | Sep 11 08:28:44 PM UTC 24 |
| Finished | Sep 11 08:34:54 PM UTC 24 |
| Peak memory | 596184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891579084 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_rand_reset.3891579084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.18335371 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 8425994056 ps |
| CPU time | 322.23 seconds |
| Started | Sep 11 08:28:48 PM UTC 24 |
| Finished | Sep 11 08:34:15 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18335371 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_reset_error.18335371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.1952116549 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 1248747550 ps |
| CPU time | 49.73 seconds |
| Started | Sep 11 08:28:28 PM UTC 24 |
| Finished | Sep 11 08:29:20 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952116549 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.1952116549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/50.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.3499407808 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 674133084 ps |
| CPU time | 26.33 seconds |
| Started | Sep 11 08:29:28 PM UTC 24 |
| Finished | Sep 11 08:29:55 PM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499407808 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device.3499407808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/51.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.3586922696 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 148303049929 ps |
| CPU time | 2317.32 seconds |
| Started | Sep 11 08:29:33 PM UTC 24 |
| Finished | Sep 11 09:08:37 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586922696 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device_slow_rsp.3586922696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.1234113192 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 197185250 ps |
| CPU time | 14.95 seconds |
| Started | Sep 11 08:29:42 PM UTC 24 |
| Finished | Sep 11 08:29:58 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234113192 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_addr.1234113192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.1355353214 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 1889071009 ps |
| CPU time | 64.97 seconds |
| Started | Sep 11 08:29:37 PM UTC 24 |
| Finished | Sep 11 08:30:44 PM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355353214 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.1355353214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/51.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.322974875 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 1033711996 ps |
| CPU time | 39.49 seconds |
| Started | Sep 11 08:29:19 PM UTC 24 |
| Finished | Sep 11 08:30:00 PM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322974875 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.322974875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/51.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.2196843700 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 41679746444 ps |
| CPU time | 483.11 seconds |
| Started | Sep 11 08:29:25 PM UTC 24 |
| Finished | Sep 11 08:37:34 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196843700 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.2196843700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/51.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.2481836247 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 43413782625 ps |
| CPU time | 639.55 seconds |
| Started | Sep 11 08:29:25 PM UTC 24 |
| Finished | Sep 11 08:40:12 PM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481836247 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.2481836247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/51.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.3242821901 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 410944563 ps |
| CPU time | 34.39 seconds |
| Started | Sep 11 08:29:22 PM UTC 24 |
| Finished | Sep 11 08:29:58 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242821901 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_delays.3242821901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/51.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.2180988274 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 287582907 ps |
| CPU time | 15.36 seconds |
| Started | Sep 11 08:29:34 PM UTC 24 |
| Finished | Sep 11 08:29:51 PM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180988274 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.2180988274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/51.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.223252692 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 172808858 ps |
| CPU time | 11.64 seconds |
| Started | Sep 11 08:28:51 PM UTC 24 |
| Finished | Sep 11 08:29:04 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223252692 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.223252692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/51.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.3808032484 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 9944938631 ps |
| CPU time | 97.69 seconds |
| Started | Sep 11 08:29:14 PM UTC 24 |
| Finished | Sep 11 08:30:54 PM UTC 24 |
| Peak memory | 593844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808032484 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.3808032484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/51.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.3365433568 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 5556182116 ps |
| CPU time | 82.84 seconds |
| Started | Sep 11 08:29:15 PM UTC 24 |
| Finished | Sep 11 08:30:40 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365433568 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.3365433568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.1700710124 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 47918408 ps |
| CPU time | 9.16 seconds |
| Started | Sep 11 08:28:50 PM UTC 24 |
| Finished | Sep 11 08:29:00 PM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700710124 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delays.1700710124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/51.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.941619345 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 1543562399 ps |
| CPU time | 47.84 seconds |
| Started | Sep 11 08:29:47 PM UTC 24 |
| Finished | Sep 11 08:30:36 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941619345 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.941619345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/51.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.872831621 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 2004341156 ps |
| CPU time | 159.21 seconds |
| Started | Sep 11 08:29:51 PM UTC 24 |
| Finished | Sep 11 08:32:34 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872831621 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.872831621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/51.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.2697586688 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 894385682 ps |
| CPU time | 439.9 seconds |
| Started | Sep 11 08:29:52 PM UTC 24 |
| Finished | Sep 11 08:37:18 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697586688 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_rand_reset.2697586688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.2586146660 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 115166485 ps |
| CPU time | 47.89 seconds |
| Started | Sep 11 08:29:52 PM UTC 24 |
| Finished | Sep 11 08:30:42 PM UTC 24 |
| Peak memory | 595996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586146660 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_reset_error.2586146660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.669071374 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 1087849038 ps |
| CPU time | 47.54 seconds |
| Started | Sep 11 08:29:43 PM UTC 24 |
| Finished | Sep 11 08:30:32 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669071374 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.669071374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/51.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.336661944 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 1035200521 ps |
| CPU time | 84.28 seconds |
| Started | Sep 11 08:30:27 PM UTC 24 |
| Finished | Sep 11 08:31:53 PM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336661944 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device.336661944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/52.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.1834886975 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 2634734092 ps |
| CPU time | 55.82 seconds |
| Started | Sep 11 08:30:29 PM UTC 24 |
| Finished | Sep 11 08:31:26 PM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834886975 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device_slow_rsp.1834886975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.2757680525 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 134985455 ps |
| CPU time | 17.9 seconds |
| Started | Sep 11 08:30:47 PM UTC 24 |
| Finished | Sep 11 08:31:06 PM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757680525 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_addr.2757680525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.558983714 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 405154866 ps |
| CPU time | 21.46 seconds |
| Started | Sep 11 08:30:33 PM UTC 24 |
| Finished | Sep 11 08:30:56 PM UTC 24 |
| Peak memory | 595864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558983714 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.558983714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/52.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.2548293143 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 2418647804 ps |
| CPU time | 74.49 seconds |
| Started | Sep 11 08:30:24 PM UTC 24 |
| Finished | Sep 11 08:31:40 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548293143 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.2548293143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/52.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.1829243920 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 70837893038 ps |
| CPU time | 724.88 seconds |
| Started | Sep 11 08:30:27 PM UTC 24 |
| Finished | Sep 11 08:42:40 PM UTC 24 |
| Peak memory | 596096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829243920 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.1829243920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/52.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.2652639184 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 12137019828 ps |
| CPU time | 181.91 seconds |
| Started | Sep 11 08:30:25 PM UTC 24 |
| Finished | Sep 11 08:33:30 PM UTC 24 |
| Peak memory | 596136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652639184 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.2652639184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/52.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.4143800850 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 250397432 ps |
| CPU time | 26.9 seconds |
| Started | Sep 11 08:30:26 PM UTC 24 |
| Finished | Sep 11 08:30:54 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143800850 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_delays.4143800850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/52.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.2112253148 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 675934272 ps |
| CPU time | 23.09 seconds |
| Started | Sep 11 08:30:33 PM UTC 24 |
| Finished | Sep 11 08:30:57 PM UTC 24 |
| Peak memory | 595684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112253148 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.2112253148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/52.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.2207188536 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 172018702 ps |
| CPU time | 10.5 seconds |
| Started | Sep 11 08:29:59 PM UTC 24 |
| Finished | Sep 11 08:30:11 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207188536 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.2207188536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/52.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.4134502490 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 5186373746 ps |
| CPU time | 49.93 seconds |
| Started | Sep 11 08:30:21 PM UTC 24 |
| Finished | Sep 11 08:31:13 PM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134502490 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.4134502490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/52.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.1205093921 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 5858125187 ps |
| CPU time | 91.22 seconds |
| Started | Sep 11 08:30:23 PM UTC 24 |
| Finished | Sep 11 08:31:57 PM UTC 24 |
| Peak memory | 593700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205093921 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.1205093921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.2705978155 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 48593454 ps |
| CPU time | 9.52 seconds |
| Started | Sep 11 08:30:18 PM UTC 24 |
| Finished | Sep 11 08:30:29 PM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705978155 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delays.2705978155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/52.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.687480982 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 15799402227 ps |
| CPU time | 506.51 seconds |
| Started | Sep 11 08:30:46 PM UTC 24 |
| Finished | Sep 11 08:39:20 PM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687480982 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.687480982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/52.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.4178717648 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 11345620701 ps |
| CPU time | 766.59 seconds |
| Started | Sep 11 08:30:54 PM UTC 24 |
| Finished | Sep 11 08:43:51 PM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178717648 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_rand_reset.4178717648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.3928522410 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 614889881 ps |
| CPU time | 29.34 seconds |
| Started | Sep 11 08:30:36 PM UTC 24 |
| Finished | Sep 11 08:31:07 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928522410 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.3928522410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/52.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.1801154890 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 1687477735 ps |
| CPU time | 64.47 seconds |
| Started | Sep 11 08:31:22 PM UTC 24 |
| Finished | Sep 11 08:32:28 PM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801154890 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device.1801154890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/53.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.1279757786 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 56493221798 ps |
| CPU time | 873.99 seconds |
| Started | Sep 11 08:31:23 PM UTC 24 |
| Finished | Sep 11 08:46:07 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279757786 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device_slow_rsp.1279757786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.2816276015 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 730012173 ps |
| CPU time | 27.59 seconds |
| Started | Sep 11 08:31:35 PM UTC 24 |
| Finished | Sep 11 08:32:05 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816276015 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_addr.2816276015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.3352202611 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 1150365875 ps |
| CPU time | 39.51 seconds |
| Started | Sep 11 08:31:31 PM UTC 24 |
| Finished | Sep 11 08:32:13 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352202611 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.3352202611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/53.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.1796800463 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 78026246 ps |
| CPU time | 11.58 seconds |
| Started | Sep 11 08:31:19 PM UTC 24 |
| Finished | Sep 11 08:31:32 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796800463 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.1796800463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/53.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.2565283513 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 91890311242 ps |
| CPU time | 816.29 seconds |
| Started | Sep 11 08:31:16 PM UTC 24 |
| Finished | Sep 11 08:45:01 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565283513 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.2565283513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/53.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.650897239 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 43289213886 ps |
| CPU time | 622.67 seconds |
| Started | Sep 11 08:31:20 PM UTC 24 |
| Finished | Sep 11 08:41:50 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650897239 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.650897239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/53.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.546380850 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 212028020 ps |
| CPU time | 22.29 seconds |
| Started | Sep 11 08:31:17 PM UTC 24 |
| Finished | Sep 11 08:31:41 PM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546380850 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_delays.546380850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/53.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.673395995 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 581373898 ps |
| CPU time | 38.88 seconds |
| Started | Sep 11 08:31:31 PM UTC 24 |
| Finished | Sep 11 08:32:11 PM UTC 24 |
| Peak memory | 595808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673395995 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.673395995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/53.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.1069632754 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 163337799 ps |
| CPU time | 8.9 seconds |
| Started | Sep 11 08:31:01 PM UTC 24 |
| Finished | Sep 11 08:31:11 PM UTC 24 |
| Peak memory | 593804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069632754 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.1069632754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/53.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.338783196 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 7220372960 ps |
| CPU time | 76.54 seconds |
| Started | Sep 11 08:31:08 PM UTC 24 |
| Finished | Sep 11 08:32:26 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338783196 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.338783196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/53.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.3618864049 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 5618423588 ps |
| CPU time | 120.87 seconds |
| Started | Sep 11 08:31:07 PM UTC 24 |
| Finished | Sep 11 08:33:11 PM UTC 24 |
| Peak memory | 594088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618864049 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.3618864049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.2899265606 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 47806652 ps |
| CPU time | 6.99 seconds |
| Started | Sep 11 08:31:01 PM UTC 24 |
| Finished | Sep 11 08:31:09 PM UTC 24 |
| Peak memory | 593864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899265606 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delays.2899265606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/53.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.2517465852 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 293443499 ps |
| CPU time | 37.57 seconds |
| Started | Sep 11 08:31:33 PM UTC 24 |
| Finished | Sep 11 08:32:13 PM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517465852 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.2517465852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/53.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.3326625468 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 9878100907 ps |
| CPU time | 301.02 seconds |
| Started | Sep 11 08:31:51 PM UTC 24 |
| Finished | Sep 11 08:36:57 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326625468 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.3326625468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/53.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.3098908479 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 4376590996 ps |
| CPU time | 405.06 seconds |
| Started | Sep 11 08:31:39 PM UTC 24 |
| Finished | Sep 11 08:38:29 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098908479 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_rand_reset.3098908479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.542589797 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 1010491088 ps |
| CPU time | 282.36 seconds |
| Started | Sep 11 08:31:57 PM UTC 24 |
| Finished | Sep 11 08:36:44 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542589797 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_reset_error.542589797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.1007940502 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 434489217 ps |
| CPU time | 25.04 seconds |
| Started | Sep 11 08:31:31 PM UTC 24 |
| Finished | Sep 11 08:31:59 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007940502 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.1007940502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/53.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.67939799 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 459952210 ps |
| CPU time | 38.95 seconds |
| Started | Sep 11 08:32:36 PM UTC 24 |
| Finished | Sep 11 08:33:16 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67939799 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device.67939799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/54.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.3271240117 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 119991897748 ps |
| CPU time | 1860.4 seconds |
| Started | Sep 11 08:32:39 PM UTC 24 |
| Finished | Sep 11 09:04:02 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271240117 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device_slow_rsp.3271240117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.2549010209 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 192506855 ps |
| CPU time | 29.42 seconds |
| Started | Sep 11 08:32:41 PM UTC 24 |
| Finished | Sep 11 08:33:12 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549010209 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_addr.2549010209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.4123418359 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 230768806 ps |
| CPU time | 25.36 seconds |
| Started | Sep 11 08:32:39 PM UTC 24 |
| Finished | Sep 11 08:33:06 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123418359 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.4123418359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/54.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.747480928 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 605808889 ps |
| CPU time | 42.44 seconds |
| Started | Sep 11 08:32:20 PM UTC 24 |
| Finished | Sep 11 08:33:04 PM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747480928 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.747480928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/54.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.3311985346 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 51079907406 ps |
| CPU time | 473.83 seconds |
| Started | Sep 11 08:32:23 PM UTC 24 |
| Finished | Sep 11 08:40:23 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311985346 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.3311985346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/54.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.3744077856 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 50823714176 ps |
| CPU time | 783.63 seconds |
| Started | Sep 11 08:32:30 PM UTC 24 |
| Finished | Sep 11 08:45:43 PM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744077856 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.3744077856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/54.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.3928503963 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 32577097 ps |
| CPU time | 7.64 seconds |
| Started | Sep 11 08:32:23 PM UTC 24 |
| Finished | Sep 11 08:32:32 PM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928503963 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_delays.3928503963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/54.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.2092280152 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 2737461633 ps |
| CPU time | 74.74 seconds |
| Started | Sep 11 08:32:36 PM UTC 24 |
| Finished | Sep 11 08:33:53 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092280152 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.2092280152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/54.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.2028273074 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 249928018 ps |
| CPU time | 12.62 seconds |
| Started | Sep 11 08:32:01 PM UTC 24 |
| Finished | Sep 11 08:32:15 PM UTC 24 |
| Peak memory | 593864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028273074 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.2028273074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/54.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.3117259754 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 9179304987 ps |
| CPU time | 92.29 seconds |
| Started | Sep 11 08:32:07 PM UTC 24 |
| Finished | Sep 11 08:33:41 PM UTC 24 |
| Peak memory | 593704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117259754 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.3117259754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/54.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.236211120 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 6933381455 ps |
| CPU time | 92.71 seconds |
| Started | Sep 11 08:32:19 PM UTC 24 |
| Finished | Sep 11 08:33:54 PM UTC 24 |
| Peak memory | 594072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236211120 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.236211120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.629842140 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 52184784 ps |
| CPU time | 9.23 seconds |
| Started | Sep 11 08:32:05 PM UTC 24 |
| Finished | Sep 11 08:32:15 PM UTC 24 |
| Peak memory | 593776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629842140 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delays.629842140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/54.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.2463163587 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 1480104644 ps |
| CPU time | 107.95 seconds |
| Started | Sep 11 08:32:42 PM UTC 24 |
| Finished | Sep 11 08:34:32 PM UTC 24 |
| Peak memory | 596092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463163587 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.2463163587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/54.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.768426672 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 10507086906 ps |
| CPU time | 365.71 seconds |
| Started | Sep 11 08:32:54 PM UTC 24 |
| Finished | Sep 11 08:39:05 PM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768426672 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.768426672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/54.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.3718494613 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 7225149094 ps |
| CPU time | 416.24 seconds |
| Started | Sep 11 08:32:53 PM UTC 24 |
| Finished | Sep 11 08:39:55 PM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718494613 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_rand_reset.3718494613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.3421338822 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 2897128848 ps |
| CPU time | 342.18 seconds |
| Started | Sep 11 08:32:58 PM UTC 24 |
| Finished | Sep 11 08:38:45 PM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421338822 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_reset_error.3421338822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.1412380381 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 89881532 ps |
| CPU time | 18.6 seconds |
| Started | Sep 11 08:32:40 PM UTC 24 |
| Finished | Sep 11 08:33:00 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412380381 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.1412380381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/54.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.2356295521 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 2800960121 ps |
| CPU time | 98.36 seconds |
| Started | Sep 11 08:33:37 PM UTC 24 |
| Finished | Sep 11 08:35:18 PM UTC 24 |
| Peak memory | 596004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356295521 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device.2356295521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/55.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.2907031353 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 136148987716 ps |
| CPU time | 2091.45 seconds |
| Started | Sep 11 08:33:35 PM UTC 24 |
| Finished | Sep 11 09:08:51 PM UTC 24 |
| Peak memory | 598932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907031353 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device_slow_rsp.2907031353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.1258079950 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 306207464 ps |
| CPU time | 40.97 seconds |
| Started | Sep 11 08:34:08 PM UTC 24 |
| Finished | Sep 11 08:34:51 PM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258079950 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_addr.1258079950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.3356496265 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 236514905 ps |
| CPU time | 23.32 seconds |
| Started | Sep 11 08:33:56 PM UTC 24 |
| Finished | Sep 11 08:34:21 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356496265 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.3356496265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/55.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.371000342 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 833158863 ps |
| CPU time | 41.42 seconds |
| Started | Sep 11 08:33:27 PM UTC 24 |
| Finished | Sep 11 08:34:10 PM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371000342 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.371000342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/55.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.3913460496 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 71780522790 ps |
| CPU time | 828.29 seconds |
| Started | Sep 11 08:33:36 PM UTC 24 |
| Finished | Sep 11 08:47:35 PM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913460496 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.3913460496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/55.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.3613004228 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 61158775241 ps |
| CPU time | 824.41 seconds |
| Started | Sep 11 08:33:35 PM UTC 24 |
| Finished | Sep 11 08:47:30 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613004228 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.3613004228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/55.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.403644724 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 490663326 ps |
| CPU time | 41.18 seconds |
| Started | Sep 11 08:33:34 PM UTC 24 |
| Finished | Sep 11 08:34:17 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403644724 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_delays.403644724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/55.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.3491891915 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 154201802 ps |
| CPU time | 19.79 seconds |
| Started | Sep 11 08:33:41 PM UTC 24 |
| Finished | Sep 11 08:34:02 PM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491891915 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.3491891915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/55.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.147749393 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 46527673 ps |
| CPU time | 8.72 seconds |
| Started | Sep 11 08:33:00 PM UTC 24 |
| Finished | Sep 11 08:33:10 PM UTC 24 |
| Peak memory | 593636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147749393 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.147749393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/55.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.834333103 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 8958196455 ps |
| CPU time | 128.21 seconds |
| Started | Sep 11 08:33:25 PM UTC 24 |
| Finished | Sep 11 08:35:36 PM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834333103 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.834333103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/55.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.1449164228 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 4180925811 ps |
| CPU time | 63.33 seconds |
| Started | Sep 11 08:33:26 PM UTC 24 |
| Finished | Sep 11 08:34:31 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449164228 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.1449164228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.2105986409 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 45176124 ps |
| CPU time | 8.76 seconds |
| Started | Sep 11 08:33:04 PM UTC 24 |
| Finished | Sep 11 08:33:14 PM UTC 24 |
| Peak memory | 593884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105986409 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delays.2105986409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/55.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.3195594771 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 522523743 ps |
| CPU time | 18 seconds |
| Started | Sep 11 08:34:08 PM UTC 24 |
| Finished | Sep 11 08:34:28 PM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195594771 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.3195594771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/55.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.616643731 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 6863653255 ps |
| CPU time | 206.32 seconds |
| Started | Sep 11 08:34:20 PM UTC 24 |
| Finished | Sep 11 08:37:50 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616643731 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.616643731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/55.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.3444450 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 151360261 ps |
| CPU time | 24.04 seconds |
| Started | Sep 11 08:34:07 PM UTC 24 |
| Finished | Sep 11 08:34:32 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444450 -assert nopostproc +UVM_TESTNAME=x bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.3444450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/55.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.3523150205 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 1884368196 ps |
| CPU time | 79.23 seconds |
| Started | Sep 11 08:34:57 PM UTC 24 |
| Finished | Sep 11 08:36:18 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523150205 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device.3523150205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/56.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.3621531782 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 31985553443 ps |
| CPU time | 612.06 seconds |
| Started | Sep 11 08:34:58 PM UTC 24 |
| Finished | Sep 11 08:45:18 PM UTC 24 |
| Peak memory | 595880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621531782 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device_slow_rsp.3621531782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.3155078642 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 277708256 ps |
| CPU time | 37.05 seconds |
| Started | Sep 11 08:35:11 PM UTC 24 |
| Finished | Sep 11 08:35:49 PM UTC 24 |
| Peak memory | 596052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155078642 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_addr.3155078642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.716477774 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 211221888 ps |
| CPU time | 24.15 seconds |
| Started | Sep 11 08:35:03 PM UTC 24 |
| Finished | Sep 11 08:35:29 PM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716477774 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.716477774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/56.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.1978752968 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 2212469558 ps |
| CPU time | 78.13 seconds |
| Started | Sep 11 08:34:41 PM UTC 24 |
| Finished | Sep 11 08:36:01 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978752968 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.1978752968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/56.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.1275222141 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 12926483354 ps |
| CPU time | 120.03 seconds |
| Started | Sep 11 08:34:46 PM UTC 24 |
| Finished | Sep 11 08:36:49 PM UTC 24 |
| Peak memory | 596032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275222141 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.1275222141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/56.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.1741847290 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 3979533175 ps |
| CPU time | 76.78 seconds |
| Started | Sep 11 08:34:53 PM UTC 24 |
| Finished | Sep 11 08:36:12 PM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741847290 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.1741847290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/56.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.1947303708 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 416682360 ps |
| CPU time | 42.09 seconds |
| Started | Sep 11 08:34:42 PM UTC 24 |
| Finished | Sep 11 08:35:26 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947303708 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_delays.1947303708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/56.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.3799899595 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 1336558784 ps |
| CPU time | 34.11 seconds |
| Started | Sep 11 08:34:57 PM UTC 24 |
| Finished | Sep 11 08:35:33 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799899595 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.3799899595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/56.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.2926394513 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 237709041 ps |
| CPU time | 12.1 seconds |
| Started | Sep 11 08:34:27 PM UTC 24 |
| Finished | Sep 11 08:34:41 PM UTC 24 |
| Peak memory | 594064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926394513 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.2926394513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/56.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.131002779 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 7937367661 ps |
| CPU time | 85.11 seconds |
| Started | Sep 11 08:34:39 PM UTC 24 |
| Finished | Sep 11 08:36:06 PM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131002779 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.131002779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/56.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.292935235 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 5183263946 ps |
| CPU time | 81.35 seconds |
| Started | Sep 11 08:34:39 PM UTC 24 |
| Finished | Sep 11 08:36:03 PM UTC 24 |
| Peak memory | 593784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292935235 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.292935235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.2054975897 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 44483092 ps |
| CPU time | 8.88 seconds |
| Started | Sep 11 08:34:35 PM UTC 24 |
| Finished | Sep 11 08:34:45 PM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054975897 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delays.2054975897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/56.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.3586399225 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 3145655662 ps |
| CPU time | 156.03 seconds |
| Started | Sep 11 08:35:15 PM UTC 24 |
| Finished | Sep 11 08:37:54 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586399225 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.3586399225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/56.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.2324951997 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 2764717807 ps |
| CPU time | 173.66 seconds |
| Started | Sep 11 08:35:24 PM UTC 24 |
| Finished | Sep 11 08:38:20 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324951997 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.2324951997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/56.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.1673896548 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 15010082588 ps |
| CPU time | 729.28 seconds |
| Started | Sep 11 08:35:20 PM UTC 24 |
| Finished | Sep 11 08:47:39 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673896548 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_rand_reset.1673896548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.316288757 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 4482520519 ps |
| CPU time | 534.42 seconds |
| Started | Sep 11 08:35:38 PM UTC 24 |
| Finished | Sep 11 08:44:40 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316288757 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_reset_error.316288757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.786084121 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 585275024 ps |
| CPU time | 24.91 seconds |
| Started | Sep 11 08:35:03 PM UTC 24 |
| Finished | Sep 11 08:35:30 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786084121 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.786084121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/56.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.3365677717 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 2654339628 ps |
| CPU time | 111.28 seconds |
| Started | Sep 11 08:36:25 PM UTC 24 |
| Finished | Sep 11 08:38:19 PM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365677717 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device.3365677717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/57.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.513609776 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 131862500563 ps |
| CPU time | 1925.96 seconds |
| Started | Sep 11 08:36:24 PM UTC 24 |
| Finished | Sep 11 09:08:51 PM UTC 24 |
| Peak memory | 598980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513609776 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device_slow_rsp.513609776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.2536224978 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 83442595 ps |
| CPU time | 12.01 seconds |
| Started | Sep 11 08:36:37 PM UTC 24 |
| Finished | Sep 11 08:36:50 PM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536224978 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_addr.2536224978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.2346081926 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 2000584874 ps |
| CPU time | 55.95 seconds |
| Started | Sep 11 08:36:24 PM UTC 24 |
| Finished | Sep 11 08:37:22 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346081926 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.2346081926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/57.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.2363767980 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 2264443852 ps |
| CPU time | 79.49 seconds |
| Started | Sep 11 08:35:58 PM UTC 24 |
| Finished | Sep 11 08:37:20 PM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363767980 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.2363767980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/57.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.446474857 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 98722129923 ps |
| CPU time | 1233.47 seconds |
| Started | Sep 11 08:36:15 PM UTC 24 |
| Finished | Sep 11 08:57:04 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446474857 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.446474857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/57.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.489401064 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 42648746385 ps |
| CPU time | 614.18 seconds |
| Started | Sep 11 08:36:17 PM UTC 24 |
| Finished | Sep 11 08:46:39 PM UTC 24 |
| Peak memory | 596156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489401064 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.489401064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/57.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.1595507254 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 429514553 ps |
| CPU time | 36.71 seconds |
| Started | Sep 11 08:36:02 PM UTC 24 |
| Finished | Sep 11 08:36:41 PM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595507254 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_delays.1595507254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/57.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.1836573752 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 615132605 ps |
| CPU time | 25.87 seconds |
| Started | Sep 11 08:36:23 PM UTC 24 |
| Finished | Sep 11 08:36:50 PM UTC 24 |
| Peak memory | 595820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836573752 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.1836573752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/57.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.3786569511 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 251672506 ps |
| CPU time | 9.48 seconds |
| Started | Sep 11 08:35:43 PM UTC 24 |
| Finished | Sep 11 08:35:54 PM UTC 24 |
| Peak memory | 594056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786569511 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.3786569511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/57.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.765792857 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 8189775044 ps |
| CPU time | 111.36 seconds |
| Started | Sep 11 08:35:54 PM UTC 24 |
| Finished | Sep 11 08:37:48 PM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765792857 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.765792857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/57.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.3091751024 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 5133161265 ps |
| CPU time | 94.45 seconds |
| Started | Sep 11 08:35:55 PM UTC 24 |
| Finished | Sep 11 08:37:32 PM UTC 24 |
| Peak memory | 593836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091751024 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.3091751024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.3413208747 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 61195399 ps |
| CPU time | 10.05 seconds |
| Started | Sep 11 08:35:51 PM UTC 24 |
| Finished | Sep 11 08:36:03 PM UTC 24 |
| Peak memory | 593636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413208747 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delays.3413208747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/57.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.723328406 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 518547416 ps |
| CPU time | 47.96 seconds |
| Started | Sep 11 08:36:43 PM UTC 24 |
| Finished | Sep 11 08:37:33 PM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723328406 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.723328406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/57.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.3391018329 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 1384315142 ps |
| CPU time | 90.46 seconds |
| Started | Sep 11 08:37:06 PM UTC 24 |
| Finished | Sep 11 08:38:39 PM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391018329 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.3391018329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/57.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.3857927330 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 788333226 ps |
| CPU time | 303.8 seconds |
| Started | Sep 11 08:36:56 PM UTC 24 |
| Finished | Sep 11 08:42:04 PM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857927330 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_rand_reset.3857927330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.2710150361 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 5173214273 ps |
| CPU time | 193.69 seconds |
| Started | Sep 11 08:37:07 PM UTC 24 |
| Finished | Sep 11 08:40:24 PM UTC 24 |
| Peak memory | 596124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710150361 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_reset_error.2710150361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.376796462 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 92322389 ps |
| CPU time | 10.78 seconds |
| Started | Sep 11 08:36:32 PM UTC 24 |
| Finished | Sep 11 08:36:44 PM UTC 24 |
| Peak memory | 593904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376796462 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.376796462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/57.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.1592681458 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 957280752 ps |
| CPU time | 67.84 seconds |
| Started | Sep 11 08:37:48 PM UTC 24 |
| Finished | Sep 11 08:38:58 PM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592681458 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device.1592681458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/58.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.3547797934 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 94273769646 ps |
| CPU time | 1301.73 seconds |
| Started | Sep 11 08:37:49 PM UTC 24 |
| Finished | Sep 11 08:59:45 PM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547797934 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device_slow_rsp.3547797934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3388864431 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 431149294 ps |
| CPU time | 16.15 seconds |
| Started | Sep 11 08:37:59 PM UTC 24 |
| Finished | Sep 11 08:38:17 PM UTC 24 |
| Peak memory | 595752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388864431 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_addr.3388864431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.3318027916 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 366452162 ps |
| CPU time | 40.76 seconds |
| Started | Sep 11 08:37:58 PM UTC 24 |
| Finished | Sep 11 08:38:41 PM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318027916 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.3318027916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/58.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.956247017 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 119474676 ps |
| CPU time | 12.36 seconds |
| Started | Sep 11 08:37:18 PM UTC 24 |
| Finished | Sep 11 08:37:32 PM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956247017 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.956247017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/58.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.414710341 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 109764868493 ps |
| CPU time | 1162.66 seconds |
| Started | Sep 11 08:37:45 PM UTC 24 |
| Finished | Sep 11 08:57:21 PM UTC 24 |
| Peak memory | 595756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414710341 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.414710341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/58.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.1881883196 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 41539067091 ps |
| CPU time | 618.1 seconds |
| Started | Sep 11 08:37:46 PM UTC 24 |
| Finished | Sep 11 08:48:12 PM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881883196 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.1881883196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/58.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.1309745983 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 206051916 ps |
| CPU time | 19.57 seconds |
| Started | Sep 11 08:37:44 PM UTC 24 |
| Finished | Sep 11 08:38:05 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309745983 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_delays.1309745983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/58.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.3727588580 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 479314446 ps |
| CPU time | 46.41 seconds |
| Started | Sep 11 08:37:56 PM UTC 24 |
| Finished | Sep 11 08:38:44 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727588580 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.3727588580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/58.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.3539546225 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 213689246 ps |
| CPU time | 12.79 seconds |
| Started | Sep 11 08:37:08 PM UTC 24 |
| Finished | Sep 11 08:37:22 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539546225 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.3539546225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/58.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.353319051 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 8072782711 ps |
| CPU time | 107.45 seconds |
| Started | Sep 11 08:37:16 PM UTC 24 |
| Finished | Sep 11 08:39:06 PM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353319051 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.353319051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/58.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.3230230509 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 4122486764 ps |
| CPU time | 72.39 seconds |
| Started | Sep 11 08:37:13 PM UTC 24 |
| Finished | Sep 11 08:38:28 PM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230230509 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.3230230509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.1462419874 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 45269383 ps |
| CPU time | 8.88 seconds |
| Started | Sep 11 08:37:13 PM UTC 24 |
| Finished | Sep 11 08:37:23 PM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462419874 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delays.1462419874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/58.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.1945173040 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 12285198607 ps |
| CPU time | 404.89 seconds |
| Started | Sep 11 08:37:59 PM UTC 24 |
| Finished | Sep 11 08:44:50 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945173040 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.1945173040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/58.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.2212678728 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 12965931824 ps |
| CPU time | 440.89 seconds |
| Started | Sep 11 08:38:14 PM UTC 24 |
| Finished | Sep 11 08:45:41 PM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212678728 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.2212678728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/58.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.455721811 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 1583790508 ps |
| CPU time | 103.05 seconds |
| Started | Sep 11 08:38:16 PM UTC 24 |
| Finished | Sep 11 08:40:02 PM UTC 24 |
| Peak memory | 595880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455721811 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_reset_error.455721811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.4254517880 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 158149819 ps |
| CPU time | 20.27 seconds |
| Started | Sep 11 08:37:58 PM UTC 24 |
| Finished | Sep 11 08:38:21 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254517880 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.4254517880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/58.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.1666752360 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 829373774 ps |
| CPU time | 76.15 seconds |
| Started | Sep 11 08:38:55 PM UTC 24 |
| Finished | Sep 11 08:40:13 PM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666752360 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device.1666752360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/59.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.887219163 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 110070383367 ps |
| CPU time | 1495.79 seconds |
| Started | Sep 11 08:38:58 PM UTC 24 |
| Finished | Sep 11 09:04:11 PM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887219163 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device_slow_rsp.887219163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3512235351 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 1134849229 ps |
| CPU time | 49.87 seconds |
| Started | Sep 11 08:39:09 PM UTC 24 |
| Finished | Sep 11 08:40:01 PM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512235351 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_addr.3512235351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.3572220586 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 662423100 ps |
| CPU time | 22.18 seconds |
| Started | Sep 11 08:39:07 PM UTC 24 |
| Finished | Sep 11 08:39:30 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572220586 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.3572220586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/59.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.253667392 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 1945491310 ps |
| CPU time | 60.18 seconds |
| Started | Sep 11 08:38:45 PM UTC 24 |
| Finished | Sep 11 08:39:47 PM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253667392 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.253667392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/59.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.322881479 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 9268082248 ps |
| CPU time | 101.18 seconds |
| Started | Sep 11 08:38:47 PM UTC 24 |
| Finished | Sep 11 08:40:30 PM UTC 24 |
| Peak memory | 595756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322881479 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.322881479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/59.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.3165248186 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 12451675962 ps |
| CPU time | 180.2 seconds |
| Started | Sep 11 08:38:53 PM UTC 24 |
| Finished | Sep 11 08:41:56 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165248186 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.3165248186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/59.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.4035112807 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 168150011 ps |
| CPU time | 16.91 seconds |
| Started | Sep 11 08:38:46 PM UTC 24 |
| Finished | Sep 11 08:39:05 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035112807 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_delays.4035112807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/59.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.3498926433 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 1048946404 ps |
| CPU time | 45.36 seconds |
| Started | Sep 11 08:39:05 PM UTC 24 |
| Finished | Sep 11 08:39:52 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498926433 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.3498926433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/59.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.1332602344 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 157350447 ps |
| CPU time | 10.74 seconds |
| Started | Sep 11 08:38:20 PM UTC 24 |
| Finished | Sep 11 08:38:32 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332602344 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.1332602344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/59.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.4143210083 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 8874629843 ps |
| CPU time | 83.14 seconds |
| Started | Sep 11 08:38:34 PM UTC 24 |
| Finished | Sep 11 08:39:59 PM UTC 24 |
| Peak memory | 593704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143210083 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.4143210083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/59.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.3460589759 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 4773155132 ps |
| CPU time | 77.75 seconds |
| Started | Sep 11 08:38:43 PM UTC 24 |
| Finished | Sep 11 08:40:02 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460589759 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.3460589759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.3441054244 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 51792917 ps |
| CPU time | 9.15 seconds |
| Started | Sep 11 08:38:30 PM UTC 24 |
| Finished | Sep 11 08:38:41 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441054244 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delays.3441054244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/59.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.2656654449 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 13011296984 ps |
| CPU time | 496.93 seconds |
| Started | Sep 11 08:39:10 PM UTC 24 |
| Finished | Sep 11 08:47:34 PM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656654449 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.2656654449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/59.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.4248955082 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 2116517693 ps |
| CPU time | 176.8 seconds |
| Started | Sep 11 08:39:23 PM UTC 24 |
| Finished | Sep 11 08:42:23 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248955082 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.4248955082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/59.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.3564147367 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 864328105 ps |
| CPU time | 290.6 seconds |
| Started | Sep 11 08:39:12 PM UTC 24 |
| Finished | Sep 11 08:44:07 PM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564147367 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_rand_reset.3564147367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.528732288 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 192303298 ps |
| CPU time | 28.79 seconds |
| Started | Sep 11 08:39:07 PM UTC 24 |
| Finished | Sep 11 08:39:37 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528732288 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.528732288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/59.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.2605792423 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 9625157227 ps |
| CPU time | 842.76 seconds |
| Started | Sep 11 07:07:44 PM UTC 24 |
| Finished | Sep 11 07:21:57 PM UTC 24 |
| Peak memory | 670468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2605792423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 6.chip_csr_mem_rw_with_rand_reset.2605792423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.481562042 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 5781027934 ps |
| CPU time | 603.18 seconds |
| Started | Sep 11 07:07:38 PM UTC 24 |
| Finished | Sep 11 07:17:49 PM UTC 24 |
| Peak memory | 614812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481562042 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.481562042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.2136382009 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 29754881812 ps |
| CPU time | 3757.19 seconds |
| Started | Sep 11 07:04:09 PM UTC 24 |
| Finished | Sep 11 08:07:30 PM UTC 24 |
| Peak memory | 614008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2136382009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.chip_same_csr_outstanding.2136382009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.3083711159 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 3378102530 ps |
| CPU time | 207.08 seconds |
| Started | Sep 11 07:04:36 PM UTC 24 |
| Finished | Sep 11 07:08:07 PM UTC 24 |
| Peak memory | 619036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083711159 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.3083711159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.1511526860 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 549748865 ps |
| CPU time | 72.93 seconds |
| Started | Sep 11 07:05:49 PM UTC 24 |
| Finished | Sep 11 07:07:04 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511526860 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.1511526860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.2612767535 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 146339154382 ps |
| CPU time | 2781.49 seconds |
| Started | Sep 11 07:06:09 PM UTC 24 |
| Finished | Sep 11 07:53:04 PM UTC 24 |
| Peak memory | 596144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612767535 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.2612767535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.192116447 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 552857373 ps |
| CPU time | 33.3 seconds |
| Started | Sep 11 07:06:53 PM UTC 24 |
| Finished | Sep 11 07:07:28 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192116447 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.192116447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.1700711856 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 179901636 ps |
| CPU time | 21.58 seconds |
| Started | Sep 11 07:06:25 PM UTC 24 |
| Finished | Sep 11 07:06:48 PM UTC 24 |
| Peak memory | 596084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700711856 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1700711856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.4041923862 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 175087133 ps |
| CPU time | 23.48 seconds |
| Started | Sep 11 07:04:59 PM UTC 24 |
| Finished | Sep 11 07:05:24 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041923862 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.4041923862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.3384656258 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 81336582419 ps |
| CPU time | 968.71 seconds |
| Started | Sep 11 07:05:27 PM UTC 24 |
| Finished | Sep 11 07:21:48 PM UTC 24 |
| Peak memory | 595756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384656258 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3384656258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.2854025832 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 64595953001 ps |
| CPU time | 949.93 seconds |
| Started | Sep 11 07:05:28 PM UTC 24 |
| Finished | Sep 11 07:21:29 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854025832 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2854025832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.1964960606 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 258556394 ps |
| CPU time | 32.26 seconds |
| Started | Sep 11 07:05:26 PM UTC 24 |
| Finished | Sep 11 07:06:00 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964960606 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1964960606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.3771269828 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 1919701882 ps |
| CPU time | 76.45 seconds |
| Started | Sep 11 07:06:24 PM UTC 24 |
| Finished | Sep 11 07:07:42 PM UTC 24 |
| Peak memory | 595940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771269828 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3771269828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.361812853 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 47943770 ps |
| CPU time | 9.34 seconds |
| Started | Sep 11 07:04:51 PM UTC 24 |
| Finished | Sep 11 07:05:01 PM UTC 24 |
| Peak memory | 593776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361812853 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.361812853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.2099221585 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 5709041801 ps |
| CPU time | 92.22 seconds |
| Started | Sep 11 07:04:54 PM UTC 24 |
| Finished | Sep 11 07:06:28 PM UTC 24 |
| Peak memory | 593704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099221585 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.2099221585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.2590389354 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 5215910315 ps |
| CPU time | 79.93 seconds |
| Started | Sep 11 07:04:58 PM UTC 24 |
| Finished | Sep 11 07:06:20 PM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590389354 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2590389354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.2739934163 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 47946740 ps |
| CPU time | 9.69 seconds |
| Started | Sep 11 07:04:55 PM UTC 24 |
| Finished | Sep 11 07:05:05 PM UTC 24 |
| Peak memory | 593788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739934163 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2739934163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.2286675493 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1891727306 ps |
| CPU time | 174.02 seconds |
| Started | Sep 11 07:07:13 PM UTC 24 |
| Finished | Sep 11 07:10:10 PM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286675493 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2286675493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.199480339 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 11872895157 ps |
| CPU time | 391.6 seconds |
| Started | Sep 11 07:07:29 PM UTC 24 |
| Finished | Sep 11 07:14:07 PM UTC 24 |
| Peak memory | 596040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199480339 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.199480339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.454044352 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 161929459 ps |
| CPU time | 114.53 seconds |
| Started | Sep 11 07:07:13 PM UTC 24 |
| Finished | Sep 11 07:09:09 PM UTC 24 |
| Peak memory | 596044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454044352 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.454044352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3500489995 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 1033708594 ps |
| CPU time | 261.66 seconds |
| Started | Sep 11 07:07:34 PM UTC 24 |
| Finished | Sep 11 07:12:00 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500489995 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.3500489995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.1161423716 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 131134068 ps |
| CPU time | 20.75 seconds |
| Started | Sep 11 07:06:46 PM UTC 24 |
| Finished | Sep 11 07:07:08 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161423716 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1161423716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.1506301608 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 1140136691 ps |
| CPU time | 79.26 seconds |
| Started | Sep 11 08:40:10 PM UTC 24 |
| Finished | Sep 11 08:41:32 PM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506301608 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device.1506301608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/60.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.2575269637 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 50323429684 ps |
| CPU time | 889.3 seconds |
| Started | Sep 11 08:40:17 PM UTC 24 |
| Finished | Sep 11 08:55:17 PM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575269637 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device_slow_rsp.2575269637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.1526628016 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 710075745 ps |
| CPU time | 37.88 seconds |
| Started | Sep 11 08:40:27 PM UTC 24 |
| Finished | Sep 11 08:41:06 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526628016 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_addr.1526628016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.1749224847 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 1277987080 ps |
| CPU time | 54.48 seconds |
| Started | Sep 11 08:40:23 PM UTC 24 |
| Finished | Sep 11 08:41:19 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749224847 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.1749224847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/60.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.4115455161 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 931004449 ps |
| CPU time | 44.79 seconds |
| Started | Sep 11 08:39:53 PM UTC 24 |
| Finished | Sep 11 08:40:39 PM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115455161 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.4115455161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/60.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.2915367828 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 107213198080 ps |
| CPU time | 1069.97 seconds |
| Started | Sep 11 08:40:04 PM UTC 24 |
| Finished | Sep 11 08:58:06 PM UTC 24 |
| Peak memory | 596032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915367828 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.2915367828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/60.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.475265548 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 10155629364 ps |
| CPU time | 184.76 seconds |
| Started | Sep 11 08:40:09 PM UTC 24 |
| Finished | Sep 11 08:43:17 PM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475265548 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.475265548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/60.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.2951337579 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 420090161 ps |
| CPU time | 35.15 seconds |
| Started | Sep 11 08:40:03 PM UTC 24 |
| Finished | Sep 11 08:40:40 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951337579 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_delays.2951337579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/60.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.1248126228 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 1979911455 ps |
| CPU time | 57.35 seconds |
| Started | Sep 11 08:40:21 PM UTC 24 |
| Finished | Sep 11 08:41:20 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248126228 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.1248126228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/60.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.3313590822 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 213261080 ps |
| CPU time | 11.47 seconds |
| Started | Sep 11 08:39:26 PM UTC 24 |
| Finished | Sep 11 08:39:39 PM UTC 24 |
| Peak memory | 593864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313590822 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.3313590822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/60.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.25645017 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 4597492469 ps |
| CPU time | 66.49 seconds |
| Started | Sep 11 08:39:34 PM UTC 24 |
| Finished | Sep 11 08:40:42 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25645017 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.25645017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/60.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.1549874834 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 6619080094 ps |
| CPU time | 136.09 seconds |
| Started | Sep 11 08:39:45 PM UTC 24 |
| Finished | Sep 11 08:42:04 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549874834 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.1549874834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.2976489183 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 57281879 ps |
| CPU time | 9.93 seconds |
| Started | Sep 11 08:39:32 PM UTC 24 |
| Finished | Sep 11 08:39:43 PM UTC 24 |
| Peak memory | 593980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976489183 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delays.2976489183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/60.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.393728902 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 7830342253 ps |
| CPU time | 338.2 seconds |
| Started | Sep 11 08:40:28 PM UTC 24 |
| Finished | Sep 11 08:46:11 PM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393728902 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.393728902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/60.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.790734070 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 15119366744 ps |
| CPU time | 466.37 seconds |
| Started | Sep 11 08:40:39 PM UTC 24 |
| Finished | Sep 11 08:48:31 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790734070 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.790734070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/60.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.540545596 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 304784132 ps |
| CPU time | 149.77 seconds |
| Started | Sep 11 08:40:39 PM UTC 24 |
| Finished | Sep 11 08:43:12 PM UTC 24 |
| Peak memory | 595884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540545596 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_rand_reset.540545596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.3477034852 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 8217045 ps |
| CPU time | 5.79 seconds |
| Started | Sep 11 08:40:49 PM UTC 24 |
| Finished | Sep 11 08:40:56 PM UTC 24 |
| Peak memory | 581704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477034852 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_reset_error.3477034852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.3221514019 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 130874245 ps |
| CPU time | 11.74 seconds |
| Started | Sep 11 08:40:26 PM UTC 24 |
| Finished | Sep 11 08:40:39 PM UTC 24 |
| Peak memory | 593988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221514019 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.3221514019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/60.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.994976602 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 2558873734 ps |
| CPU time | 103.63 seconds |
| Started | Sep 11 08:41:29 PM UTC 24 |
| Finished | Sep 11 08:43:15 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994976602 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device.994976602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/61.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.2061977367 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 20539420908 ps |
| CPU time | 349.05 seconds |
| Started | Sep 11 08:41:30 PM UTC 24 |
| Finished | Sep 11 08:47:24 PM UTC 24 |
| Peak memory | 596144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061977367 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device_slow_rsp.2061977367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.430770732 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 268396397 ps |
| CPU time | 18.72 seconds |
| Started | Sep 11 08:41:44 PM UTC 24 |
| Finished | Sep 11 08:42:05 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430770732 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_addr.430770732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.4293489331 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 202100922 ps |
| CPU time | 22.66 seconds |
| Started | Sep 11 08:41:39 PM UTC 24 |
| Finished | Sep 11 08:42:04 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293489331 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.4293489331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/61.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.1456575317 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 396327184 ps |
| CPU time | 16.03 seconds |
| Started | Sep 11 08:41:04 PM UTC 24 |
| Finished | Sep 11 08:41:21 PM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456575317 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.1456575317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/61.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.4101043971 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 29551366220 ps |
| CPU time | 271.21 seconds |
| Started | Sep 11 08:41:12 PM UTC 24 |
| Finished | Sep 11 08:45:47 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101043971 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.4101043971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/61.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.2796593327 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 5053063675 ps |
| CPU time | 69.65 seconds |
| Started | Sep 11 08:41:23 PM UTC 24 |
| Finished | Sep 11 08:42:34 PM UTC 24 |
| Peak memory | 593724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796593327 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.2796593327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/61.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.1331202487 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 143432268 ps |
| CPU time | 19.85 seconds |
| Started | Sep 11 08:41:07 PM UTC 24 |
| Finished | Sep 11 08:41:28 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331202487 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_delays.1331202487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/61.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.2406276328 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 134700235 ps |
| CPU time | 16.67 seconds |
| Started | Sep 11 08:41:32 PM UTC 24 |
| Finished | Sep 11 08:41:50 PM UTC 24 |
| Peak memory | 595684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406276328 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.2406276328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/61.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.3506424613 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 225313121 ps |
| CPU time | 12.43 seconds |
| Started | Sep 11 08:40:50 PM UTC 24 |
| Finished | Sep 11 08:41:04 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506424613 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.3506424613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/61.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.2811634484 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 8989186152 ps |
| CPU time | 95.8 seconds |
| Started | Sep 11 08:41:03 PM UTC 24 |
| Finished | Sep 11 08:42:41 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811634484 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.2811634484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/61.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.2036153069 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 4191408213 ps |
| CPU time | 63.18 seconds |
| Started | Sep 11 08:41:05 PM UTC 24 |
| Finished | Sep 11 08:42:10 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036153069 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.2036153069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.2111799140 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 44442364 ps |
| CPU time | 8.8 seconds |
| Started | Sep 11 08:40:54 PM UTC 24 |
| Finished | Sep 11 08:41:04 PM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111799140 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delays.2111799140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/61.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.2491741900 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 7130318355 ps |
| CPU time | 258.22 seconds |
| Started | Sep 11 08:41:47 PM UTC 24 |
| Finished | Sep 11 08:46:09 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491741900 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.2491741900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/61.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.1105783532 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 10945911734 ps |
| CPU time | 372.65 seconds |
| Started | Sep 11 08:41:57 PM UTC 24 |
| Finished | Sep 11 08:48:15 PM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105783532 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.1105783532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/61.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.3219694299 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 1793592603 ps |
| CPU time | 444.42 seconds |
| Started | Sep 11 08:41:53 PM UTC 24 |
| Finished | Sep 11 08:49:24 PM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219694299 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_rand_reset.3219694299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.3394676166 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 214095001 ps |
| CPU time | 62.58 seconds |
| Started | Sep 11 08:41:59 PM UTC 24 |
| Finished | Sep 11 08:43:04 PM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394676166 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_reset_error.3394676166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.2196576232 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 75930744 ps |
| CPU time | 14.75 seconds |
| Started | Sep 11 08:41:45 PM UTC 24 |
| Finished | Sep 11 08:42:01 PM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196576232 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.2196576232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/61.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.1231360115 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 1072940782 ps |
| CPU time | 79.19 seconds |
| Started | Sep 11 08:42:36 PM UTC 24 |
| Finished | Sep 11 08:43:57 PM UTC 24 |
| Peak memory | 596032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231360115 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device.1231360115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/62.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.777992661 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 47829309776 ps |
| CPU time | 878.84 seconds |
| Started | Sep 11 08:42:49 PM UTC 24 |
| Finished | Sep 11 08:57:39 PM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777992661 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device_slow_rsp.777992661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.2019866787 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 1370423605 ps |
| CPU time | 61.16 seconds |
| Started | Sep 11 08:43:02 PM UTC 24 |
| Finished | Sep 11 08:44:05 PM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019866787 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_addr.2019866787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.696991561 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 2470243873 ps |
| CPU time | 98.68 seconds |
| Started | Sep 11 08:42:44 PM UTC 24 |
| Finished | Sep 11 08:44:25 PM UTC 24 |
| Peak memory | 596208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696991561 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.696991561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/62.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.1547739012 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 122921857 ps |
| CPU time | 13.48 seconds |
| Started | Sep 11 08:42:27 PM UTC 24 |
| Finished | Sep 11 08:42:41 PM UTC 24 |
| Peak memory | 595812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547739012 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.1547739012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/62.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.4019282189 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 24549845732 ps |
| CPU time | 225.94 seconds |
| Started | Sep 11 08:42:28 PM UTC 24 |
| Finished | Sep 11 08:46:17 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019282189 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.4019282189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/62.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.445582607 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 8431090585 ps |
| CPU time | 163.93 seconds |
| Started | Sep 11 08:42:29 PM UTC 24 |
| Finished | Sep 11 08:45:16 PM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445582607 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.445582607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/62.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.2806979561 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 71790155 ps |
| CPU time | 8.89 seconds |
| Started | Sep 11 08:42:26 PM UTC 24 |
| Finished | Sep 11 08:42:36 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806979561 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_delays.2806979561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/62.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.1113091848 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 1390781813 ps |
| CPU time | 36.24 seconds |
| Started | Sep 11 08:42:48 PM UTC 24 |
| Finished | Sep 11 08:43:26 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113091848 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.1113091848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/62.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.905697243 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 222960770 ps |
| CPU time | 11.78 seconds |
| Started | Sep 11 08:42:11 PM UTC 24 |
| Finished | Sep 11 08:42:24 PM UTC 24 |
| Peak memory | 593636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905697243 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.905697243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/62.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.538936887 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 9777744395 ps |
| CPU time | 119.92 seconds |
| Started | Sep 11 08:42:16 PM UTC 24 |
| Finished | Sep 11 08:44:18 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538936887 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.538936887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/62.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.3202085335 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 3794323432 ps |
| CPU time | 57.51 seconds |
| Started | Sep 11 08:42:22 PM UTC 24 |
| Finished | Sep 11 08:43:21 PM UTC 24 |
| Peak memory | 593788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202085335 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.3202085335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.2031105130 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 43638722 ps |
| CPU time | 6.92 seconds |
| Started | Sep 11 08:42:17 PM UTC 24 |
| Finished | Sep 11 08:42:25 PM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031105130 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delays.2031105130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/62.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.1755456186 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 10274835389 ps |
| CPU time | 353.74 seconds |
| Started | Sep 11 08:43:06 PM UTC 24 |
| Finished | Sep 11 08:49:05 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755456186 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.1755456186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/62.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.2221207109 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 9986847736 ps |
| CPU time | 620.43 seconds |
| Started | Sep 11 08:43:06 PM UTC 24 |
| Finished | Sep 11 08:53:35 PM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221207109 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_rand_reset.2221207109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.2781354238 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 5681582918 ps |
| CPU time | 163.59 seconds |
| Started | Sep 11 08:43:14 PM UTC 24 |
| Finished | Sep 11 08:46:00 PM UTC 24 |
| Peak memory | 596112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781354238 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_reset_error.2781354238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.903473884 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 1323813796 ps |
| CPU time | 47.31 seconds |
| Started | Sep 11 08:42:55 PM UTC 24 |
| Finished | Sep 11 08:43:45 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903473884 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.903473884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/62.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.525916811 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 1502787631 ps |
| CPU time | 76.63 seconds |
| Started | Sep 11 08:44:02 PM UTC 24 |
| Finished | Sep 11 08:45:21 PM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525916811 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device.525916811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/63.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.1644773786 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 95763882476 ps |
| CPU time | 1341.27 seconds |
| Started | Sep 11 08:44:10 PM UTC 24 |
| Finished | Sep 11 09:06:48 PM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644773786 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device_slow_rsp.1644773786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.961578681 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 195177186 ps |
| CPU time | 29.54 seconds |
| Started | Sep 11 08:44:30 PM UTC 24 |
| Finished | Sep 11 08:45:01 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961578681 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_addr.961578681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.312815107 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 362752508 ps |
| CPU time | 20.79 seconds |
| Started | Sep 11 08:44:23 PM UTC 24 |
| Finished | Sep 11 08:44:45 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312815107 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.312815107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/63.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.1164425050 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 642703498 ps |
| CPU time | 24.57 seconds |
| Started | Sep 11 08:43:42 PM UTC 24 |
| Finished | Sep 11 08:44:08 PM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164425050 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.1164425050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/63.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.3837147760 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 80784923479 ps |
| CPU time | 858.07 seconds |
| Started | Sep 11 08:43:52 PM UTC 24 |
| Finished | Sep 11 08:58:21 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837147760 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.3837147760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/63.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.1824925653 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 15312980393 ps |
| CPU time | 227.84 seconds |
| Started | Sep 11 08:43:56 PM UTC 24 |
| Finished | Sep 11 08:47:47 PM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824925653 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.1824925653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/63.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.4228202857 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 71356463 ps |
| CPU time | 11.95 seconds |
| Started | Sep 11 08:43:47 PM UTC 24 |
| Finished | Sep 11 08:44:00 PM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228202857 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_delays.4228202857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/63.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.2163106669 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 303088465 ps |
| CPU time | 10.69 seconds |
| Started | Sep 11 08:44:15 PM UTC 24 |
| Finished | Sep 11 08:44:27 PM UTC 24 |
| Peak memory | 595684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163106669 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.2163106669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/63.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.3778634432 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 149186113 ps |
| CPU time | 10.6 seconds |
| Started | Sep 11 08:43:19 PM UTC 24 |
| Finished | Sep 11 08:43:30 PM UTC 24 |
| Peak memory | 593776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778634432 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.3778634432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/63.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.943938303 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 7413312348 ps |
| CPU time | 67.86 seconds |
| Started | Sep 11 08:43:36 PM UTC 24 |
| Finished | Sep 11 08:44:46 PM UTC 24 |
| Peak memory | 593836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943938303 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.943938303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/63.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.4057522428 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 5449667303 ps |
| CPU time | 85.4 seconds |
| Started | Sep 11 08:43:40 PM UTC 24 |
| Finished | Sep 11 08:45:07 PM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057522428 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.4057522428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.2186475501 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 43901644 ps |
| CPU time | 8.3 seconds |
| Started | Sep 11 08:43:28 PM UTC 24 |
| Finished | Sep 11 08:43:37 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186475501 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delays.2186475501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/63.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.1232414991 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 1483632561 ps |
| CPU time | 148.06 seconds |
| Started | Sep 11 08:44:32 PM UTC 24 |
| Finished | Sep 11 08:47:03 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232414991 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.1232414991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/63.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.2113790557 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 11210026730 ps |
| CPU time | 366.78 seconds |
| Started | Sep 11 08:44:34 PM UTC 24 |
| Finished | Sep 11 08:50:46 PM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113790557 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.2113790557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/63.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.2502608661 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 59831833 ps |
| CPU time | 40.47 seconds |
| Started | Sep 11 08:44:27 PM UTC 24 |
| Finished | Sep 11 08:45:09 PM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502608661 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_rand_reset.2502608661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.975121679 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 331543041 ps |
| CPU time | 117.64 seconds |
| Started | Sep 11 08:44:43 PM UTC 24 |
| Finished | Sep 11 08:46:43 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975121679 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_reset_error.975121679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.4194488969 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 1005955174 ps |
| CPU time | 35.05 seconds |
| Started | Sep 11 08:44:24 PM UTC 24 |
| Finished | Sep 11 08:45:01 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194488969 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.4194488969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/63.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.3770514375 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 908405595 ps |
| CPU time | 60.41 seconds |
| Started | Sep 11 08:45:28 PM UTC 24 |
| Finished | Sep 11 08:46:30 PM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770514375 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device.3770514375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/64.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.3661009938 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 136242763656 ps |
| CPU time | 2097.64 seconds |
| Started | Sep 11 08:45:22 PM UTC 24 |
| Finished | Sep 11 09:20:45 PM UTC 24 |
| Peak memory | 599104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661009938 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device_slow_rsp.3661009938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.566622152 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 232463320 ps |
| CPU time | 29.14 seconds |
| Started | Sep 11 08:45:41 PM UTC 24 |
| Finished | Sep 11 08:46:11 PM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566622152 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_addr.566622152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.394575099 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 254881791 ps |
| CPU time | 13.84 seconds |
| Started | Sep 11 08:45:29 PM UTC 24 |
| Finished | Sep 11 08:45:44 PM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394575099 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.394575099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/64.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.830239142 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 2414556490 ps |
| CPU time | 104.27 seconds |
| Started | Sep 11 08:45:12 PM UTC 24 |
| Finished | Sep 11 08:46:59 PM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830239142 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.830239142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/64.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.1672834889 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 31369104814 ps |
| CPU time | 323.88 seconds |
| Started | Sep 11 08:45:25 PM UTC 24 |
| Finished | Sep 11 08:50:53 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672834889 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.1672834889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/64.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.549404977 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 20291171799 ps |
| CPU time | 330.11 seconds |
| Started | Sep 11 08:45:24 PM UTC 24 |
| Finished | Sep 11 08:50:59 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549404977 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.549404977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/64.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.525283307 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 498741724 ps |
| CPU time | 43.11 seconds |
| Started | Sep 11 08:45:16 PM UTC 24 |
| Finished | Sep 11 08:46:01 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525283307 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_delays.525283307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/64.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.3644353849 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 207818274 ps |
| CPU time | 9.93 seconds |
| Started | Sep 11 08:45:26 PM UTC 24 |
| Finished | Sep 11 08:45:37 PM UTC 24 |
| Peak memory | 593636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644353849 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.3644353849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/64.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.1057564666 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 42690651 ps |
| CPU time | 8.91 seconds |
| Started | Sep 11 08:44:50 PM UTC 24 |
| Finished | Sep 11 08:45:00 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057564666 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.1057564666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/64.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.258955333 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 10204152606 ps |
| CPU time | 111.92 seconds |
| Started | Sep 11 08:45:06 PM UTC 24 |
| Finished | Sep 11 08:47:00 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258955333 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.258955333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/64.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.2480463215 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 6803637774 ps |
| CPU time | 98.18 seconds |
| Started | Sep 11 08:45:11 PM UTC 24 |
| Finished | Sep 11 08:46:51 PM UTC 24 |
| Peak memory | 593900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480463215 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.2480463215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.2843955775 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 44693229 ps |
| CPU time | 8.63 seconds |
| Started | Sep 11 08:44:53 PM UTC 24 |
| Finished | Sep 11 08:45:03 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843955775 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delays.2843955775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/64.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.2522209209 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 3807694251 ps |
| CPU time | 124.51 seconds |
| Started | Sep 11 08:45:44 PM UTC 24 |
| Finished | Sep 11 08:47:51 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522209209 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.2522209209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/64.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.3753697210 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 15050795046 ps |
| CPU time | 479.08 seconds |
| Started | Sep 11 08:46:02 PM UTC 24 |
| Finished | Sep 11 08:54:08 PM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753697210 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.3753697210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/64.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.528042208 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 7328551538 ps |
| CPU time | 443.27 seconds |
| Started | Sep 11 08:45:47 PM UTC 24 |
| Finished | Sep 11 08:53:16 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528042208 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_rand_reset.528042208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3426899162 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 141948573 ps |
| CPU time | 25.62 seconds |
| Started | Sep 11 08:46:08 PM UTC 24 |
| Finished | Sep 11 08:46:35 PM UTC 24 |
| Peak memory | 595880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426899162 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_reset_error.3426899162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.3695041515 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 338903838 ps |
| CPU time | 22.96 seconds |
| Started | Sep 11 08:45:35 PM UTC 24 |
| Finished | Sep 11 08:45:59 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695041515 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.3695041515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/64.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.233201486 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 380729884 ps |
| CPU time | 29.83 seconds |
| Started | Sep 11 08:46:30 PM UTC 24 |
| Finished | Sep 11 08:47:01 PM UTC 24 |
| Peak memory | 596028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233201486 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device.233201486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/65.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.572950871 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 126104027822 ps |
| CPU time | 1788.97 seconds |
| Started | Sep 11 08:46:32 PM UTC 24 |
| Finished | Sep 11 09:16:41 PM UTC 24 |
| Peak memory | 598932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572950871 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device_slow_rsp.572950871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.1850145585 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 255461604 ps |
| CPU time | 29.11 seconds |
| Started | Sep 11 08:46:42 PM UTC 24 |
| Finished | Sep 11 08:47:13 PM UTC 24 |
| Peak memory | 595980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850145585 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_addr.1850145585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.639168683 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 1356590299 ps |
| CPU time | 49.3 seconds |
| Started | Sep 11 08:46:31 PM UTC 24 |
| Finished | Sep 11 08:47:22 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639168683 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.639168683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/65.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.1870859417 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 130690548 ps |
| CPU time | 13.58 seconds |
| Started | Sep 11 08:46:22 PM UTC 24 |
| Finished | Sep 11 08:46:37 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870859417 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.1870859417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/65.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.4148482987 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 69316417408 ps |
| CPU time | 687.98 seconds |
| Started | Sep 11 08:46:25 PM UTC 24 |
| Finished | Sep 11 08:58:01 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148482987 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.4148482987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/65.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.3954049896 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 48410278594 ps |
| CPU time | 625.31 seconds |
| Started | Sep 11 08:46:28 PM UTC 24 |
| Finished | Sep 11 08:57:01 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954049896 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.3954049896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/65.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.1268505106 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 538865656 ps |
| CPU time | 43.62 seconds |
| Started | Sep 11 08:46:24 PM UTC 24 |
| Finished | Sep 11 08:47:09 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268505106 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_delays.1268505106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/65.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.772846154 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 2421058908 ps |
| CPU time | 68.35 seconds |
| Started | Sep 11 08:46:31 PM UTC 24 |
| Finished | Sep 11 08:47:41 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772846154 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.772846154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/65.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.2792642656 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 46534297 ps |
| CPU time | 9.07 seconds |
| Started | Sep 11 08:46:09 PM UTC 24 |
| Finished | Sep 11 08:46:19 PM UTC 24 |
| Peak memory | 593776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792642656 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.2792642656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/65.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.3484972171 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 7614513741 ps |
| CPU time | 87.8 seconds |
| Started | Sep 11 08:46:12 PM UTC 24 |
| Finished | Sep 11 08:47:42 PM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484972171 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.3484972171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/65.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.2519272044 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 6480595952 ps |
| CPU time | 116.05 seconds |
| Started | Sep 11 08:46:21 PM UTC 24 |
| Finished | Sep 11 08:48:19 PM UTC 24 |
| Peak memory | 593912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519272044 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.2519272044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.3354004907 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 42555400 ps |
| CPU time | 5.84 seconds |
| Started | Sep 11 08:46:09 PM UTC 24 |
| Finished | Sep 11 08:46:16 PM UTC 24 |
| Peak memory | 593952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354004907 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delays.3354004907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/65.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.1744880354 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 3280543246 ps |
| CPU time | 255.97 seconds |
| Started | Sep 11 08:46:42 PM UTC 24 |
| Finished | Sep 11 08:51:02 PM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744880354 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.1744880354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/65.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.3100281305 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 3590651020 ps |
| CPU time | 245.32 seconds |
| Started | Sep 11 08:46:45 PM UTC 24 |
| Finished | Sep 11 08:50:55 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100281305 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.3100281305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/65.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.3480335564 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 573256147 ps |
| CPU time | 171.23 seconds |
| Started | Sep 11 08:46:46 PM UTC 24 |
| Finished | Sep 11 08:49:41 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480335564 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_rand_reset.3480335564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.42495064 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 127780079 ps |
| CPU time | 40.6 seconds |
| Started | Sep 11 08:46:44 PM UTC 24 |
| Finished | Sep 11 08:47:27 PM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42495064 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_reset_error.42495064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.3523436882 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 275967765 ps |
| CPU time | 18.57 seconds |
| Started | Sep 11 08:46:39 PM UTC 24 |
| Finished | Sep 11 08:46:59 PM UTC 24 |
| Peak memory | 595920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523436882 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.3523436882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/65.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.2031887695 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 672625186 ps |
| CPU time | 29.12 seconds |
| Started | Sep 11 08:47:24 PM UTC 24 |
| Finished | Sep 11 08:47:54 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031887695 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device.2031887695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/66.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.2611298428 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 46393641733 ps |
| CPU time | 674.64 seconds |
| Started | Sep 11 08:47:21 PM UTC 24 |
| Finished | Sep 11 08:58:44 PM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611298428 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device_slow_rsp.2611298428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.774305532 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 305832498 ps |
| CPU time | 33.01 seconds |
| Started | Sep 11 08:47:33 PM UTC 24 |
| Finished | Sep 11 08:48:08 PM UTC 24 |
| Peak memory | 596012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774305532 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_addr.774305532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.3331573368 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 1489791419 ps |
| CPU time | 46.57 seconds |
| Started | Sep 11 08:47:23 PM UTC 24 |
| Finished | Sep 11 08:48:11 PM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331573368 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.3331573368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/66.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.2893925062 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 479051842 ps |
| CPU time | 45.92 seconds |
| Started | Sep 11 08:47:09 PM UTC 24 |
| Finished | Sep 11 08:47:57 PM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893925062 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.2893925062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/66.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.311352473 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 75961371445 ps |
| CPU time | 811.23 seconds |
| Started | Sep 11 08:47:17 PM UTC 24 |
| Finished | Sep 11 09:00:58 PM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311352473 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.311352473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/66.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.2618614455 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 47681575004 ps |
| CPU time | 664.72 seconds |
| Started | Sep 11 08:47:24 PM UTC 24 |
| Finished | Sep 11 08:58:38 PM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618614455 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.2618614455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/66.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.2266874928 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 572737449 ps |
| CPU time | 47.06 seconds |
| Started | Sep 11 08:47:10 PM UTC 24 |
| Finished | Sep 11 08:47:59 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266874928 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_delays.2266874928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/66.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.2212055974 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 1676624903 ps |
| CPU time | 56.19 seconds |
| Started | Sep 11 08:47:25 PM UTC 24 |
| Finished | Sep 11 08:48:23 PM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212055974 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.2212055974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/66.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.2757977542 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 178170413 ps |
| CPU time | 9.97 seconds |
| Started | Sep 11 08:46:52 PM UTC 24 |
| Finished | Sep 11 08:47:03 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757977542 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.2757977542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/66.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.2558578100 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 9693781449 ps |
| CPU time | 95.52 seconds |
| Started | Sep 11 08:47:02 PM UTC 24 |
| Finished | Sep 11 08:48:40 PM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558578100 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.2558578100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/66.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.2988551657 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 4990611771 ps |
| CPU time | 67.13 seconds |
| Started | Sep 11 08:47:06 PM UTC 24 |
| Finished | Sep 11 08:48:14 PM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988551657 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.2988551657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.91213317 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 42473778 ps |
| CPU time | 7.85 seconds |
| Started | Sep 11 08:47:01 PM UTC 24 |
| Finished | Sep 11 08:47:10 PM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91213317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delays.91213317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/66.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.1708665501 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 243801354 ps |
| CPU time | 14.12 seconds |
| Started | Sep 11 08:47:32 PM UTC 24 |
| Finished | Sep 11 08:47:47 PM UTC 24 |
| Peak memory | 593636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708665501 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.1708665501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/66.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.1557131279 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 12153689968 ps |
| CPU time | 396.67 seconds |
| Started | Sep 11 08:47:44 PM UTC 24 |
| Finished | Sep 11 08:54:26 PM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557131279 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.1557131279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/66.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.1441720849 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 2228091320 ps |
| CPU time | 352.33 seconds |
| Started | Sep 11 08:47:37 PM UTC 24 |
| Finished | Sep 11 08:53:34 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441720849 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_rand_reset.1441720849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.582324002 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 531887096 ps |
| CPU time | 118.87 seconds |
| Started | Sep 11 08:47:49 PM UTC 24 |
| Finished | Sep 11 08:49:50 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582324002 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_reset_error.582324002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.119023774 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 1315926366 ps |
| CPU time | 54.89 seconds |
| Started | Sep 11 08:47:28 PM UTC 24 |
| Finished | Sep 11 08:48:25 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119023774 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.119023774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/66.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.154388905 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 91017906 ps |
| CPU time | 14.91 seconds |
| Started | Sep 11 08:48:09 PM UTC 24 |
| Finished | Sep 11 08:48:25 PM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154388905 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device.154388905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/67.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.3478105704 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 8191780143 ps |
| CPU time | 135.23 seconds |
| Started | Sep 11 08:48:11 PM UTC 24 |
| Finished | Sep 11 08:50:29 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478105704 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device_slow_rsp.3478105704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.1615097993 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 306121478 ps |
| CPU time | 35.29 seconds |
| Started | Sep 11 08:48:23 PM UTC 24 |
| Finished | Sep 11 08:49:00 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615097993 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_addr.1615097993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.2540838074 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 295323067 ps |
| CPU time | 29.11 seconds |
| Started | Sep 11 08:48:15 PM UTC 24 |
| Finished | Sep 11 08:48:46 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540838074 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.2540838074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/67.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.562782722 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 1192029335 ps |
| CPU time | 36.09 seconds |
| Started | Sep 11 08:48:01 PM UTC 24 |
| Finished | Sep 11 08:48:39 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562782722 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.562782722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/67.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.2825095302 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 52895181682 ps |
| CPU time | 637.36 seconds |
| Started | Sep 11 08:48:06 PM UTC 24 |
| Finished | Sep 11 08:58:51 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825095302 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.2825095302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/67.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.179943745 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 28991095464 ps |
| CPU time | 458.56 seconds |
| Started | Sep 11 08:48:04 PM UTC 24 |
| Finished | Sep 11 08:55:49 PM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179943745 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.179943745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/67.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.1591543023 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 418442107 ps |
| CPU time | 38.1 seconds |
| Started | Sep 11 08:48:03 PM UTC 24 |
| Finished | Sep 11 08:48:42 PM UTC 24 |
| Peak memory | 595868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591543023 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_delays.1591543023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/67.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.2618742357 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 2428729112 ps |
| CPU time | 60.85 seconds |
| Started | Sep 11 08:48:17 PM UTC 24 |
| Finished | Sep 11 08:49:19 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618742357 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.2618742357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/67.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.1131804709 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 205778330 ps |
| CPU time | 11.2 seconds |
| Started | Sep 11 08:47:48 PM UTC 24 |
| Finished | Sep 11 08:48:00 PM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131804709 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.1131804709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/67.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.2635848571 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 7442903862 ps |
| CPU time | 73.41 seconds |
| Started | Sep 11 08:47:55 PM UTC 24 |
| Finished | Sep 11 08:49:10 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635848571 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.2635848571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/67.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.3481248310 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 6611500179 ps |
| CPU time | 118.09 seconds |
| Started | Sep 11 08:47:58 PM UTC 24 |
| Finished | Sep 11 08:49:59 PM UTC 24 |
| Peak memory | 593704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481248310 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.3481248310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.2740560564 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 38498613 ps |
| CPU time | 6.04 seconds |
| Started | Sep 11 08:47:52 PM UTC 24 |
| Finished | Sep 11 08:47:59 PM UTC 24 |
| Peak memory | 593864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740560564 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delays.2740560564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/67.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.3916436532 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 933276738 ps |
| CPU time | 69.21 seconds |
| Started | Sep 11 08:48:21 PM UTC 24 |
| Finished | Sep 11 08:49:32 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916436532 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.3916436532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/67.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.762372565 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 1775510923 ps |
| CPU time | 134.75 seconds |
| Started | Sep 11 08:48:29 PM UTC 24 |
| Finished | Sep 11 08:50:46 PM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762372565 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.762372565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/67.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.119716495 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 56315992 ps |
| CPU time | 12.02 seconds |
| Started | Sep 11 08:48:20 PM UTC 24 |
| Finished | Sep 11 08:48:33 PM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119716495 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_rand_reset.119716495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.2372941299 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 158528345 ps |
| CPU time | 65.38 seconds |
| Started | Sep 11 08:48:35 PM UTC 24 |
| Finished | Sep 11 08:49:42 PM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372941299 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_reset_error.2372941299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.234727038 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 306477246 ps |
| CPU time | 19.86 seconds |
| Started | Sep 11 08:48:19 PM UTC 24 |
| Finished | Sep 11 08:48:41 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234727038 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.234727038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/67.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.4080090305 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 2470045190 ps |
| CPU time | 81.03 seconds |
| Started | Sep 11 08:48:58 PM UTC 24 |
| Finished | Sep 11 08:50:21 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080090305 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device.4080090305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/68.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.402214007 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 53877148988 ps |
| CPU time | 811.88 seconds |
| Started | Sep 11 08:49:01 PM UTC 24 |
| Finished | Sep 11 09:02:43 PM UTC 24 |
| Peak memory | 596004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402214007 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device_slow_rsp.402214007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.2704632441 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 392939706 ps |
| CPU time | 22.79 seconds |
| Started | Sep 11 08:49:10 PM UTC 24 |
| Finished | Sep 11 08:49:35 PM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704632441 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_addr.2704632441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.2634638719 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 2092079516 ps |
| CPU time | 64.98 seconds |
| Started | Sep 11 08:49:07 PM UTC 24 |
| Finished | Sep 11 08:50:14 PM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634638719 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.2634638719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/68.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.1199794795 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 556373767 ps |
| CPU time | 58.88 seconds |
| Started | Sep 11 08:48:45 PM UTC 24 |
| Finished | Sep 11 08:49:46 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199794795 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.1199794795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/68.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.1014020128 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 56984300529 ps |
| CPU time | 598.61 seconds |
| Started | Sep 11 08:48:51 PM UTC 24 |
| Finished | Sep 11 08:58:57 PM UTC 24 |
| Peak memory | 596076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014020128 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.1014020128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/68.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.845705271 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 11518647671 ps |
| CPU time | 225.22 seconds |
| Started | Sep 11 08:48:58 PM UTC 24 |
| Finished | Sep 11 08:52:47 PM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845705271 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.845705271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/68.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.3878327217 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 343962034 ps |
| CPU time | 38.67 seconds |
| Started | Sep 11 08:48:49 PM UTC 24 |
| Finished | Sep 11 08:49:30 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878327217 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_delays.3878327217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/68.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.302943826 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 148236972 ps |
| CPU time | 15.46 seconds |
| Started | Sep 11 08:49:06 PM UTC 24 |
| Finished | Sep 11 08:49:23 PM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302943826 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.302943826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/68.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.3391255376 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 228336240 ps |
| CPU time | 11.75 seconds |
| Started | Sep 11 08:48:36 PM UTC 24 |
| Finished | Sep 11 08:48:49 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391255376 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.3391255376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/68.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.3550736808 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 6944521032 ps |
| CPU time | 69.8 seconds |
| Started | Sep 11 08:48:41 PM UTC 24 |
| Finished | Sep 11 08:49:52 PM UTC 24 |
| Peak memory | 593704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550736808 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.3550736808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/68.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.1653159457 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 3302961671 ps |
| CPU time | 43.89 seconds |
| Started | Sep 11 08:48:45 PM UTC 24 |
| Finished | Sep 11 08:49:30 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653159457 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.1653159457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.1317783754 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 46375034 ps |
| CPU time | 8.85 seconds |
| Started | Sep 11 08:48:41 PM UTC 24 |
| Finished | Sep 11 08:48:51 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317783754 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delays.1317783754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/68.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.213081339 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 17704063450 ps |
| CPU time | 603.11 seconds |
| Started | Sep 11 08:49:11 PM UTC 24 |
| Finished | Sep 11 08:59:22 PM UTC 24 |
| Peak memory | 596028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213081339 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.213081339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/68.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.4115854730 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 3498454914 ps |
| CPU time | 325.85 seconds |
| Started | Sep 11 08:49:15 PM UTC 24 |
| Finished | Sep 11 08:54:46 PM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115854730 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_rand_reset.4115854730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.1716923948 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 551027021 ps |
| CPU time | 115.58 seconds |
| Started | Sep 11 08:49:31 PM UTC 24 |
| Finished | Sep 11 08:51:29 PM UTC 24 |
| Peak memory | 596060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716923948 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_reset_error.1716923948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.2253439050 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 83862527 ps |
| CPU time | 9.51 seconds |
| Started | Sep 11 08:49:08 PM UTC 24 |
| Finished | Sep 11 08:49:19 PM UTC 24 |
| Peak memory | 593636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253439050 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.2253439050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/68.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.1574393148 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 282638191 ps |
| CPU time | 12.51 seconds |
| Started | Sep 11 08:49:59 PM UTC 24 |
| Finished | Sep 11 08:50:13 PM UTC 24 |
| Peak memory | 593660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574393148 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device.1574393148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/69.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.2940614267 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 30902608121 ps |
| CPU time | 530.25 seconds |
| Started | Sep 11 08:50:07 PM UTC 24 |
| Finished | Sep 11 08:59:04 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940614267 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device_slow_rsp.2940614267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.1719802074 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 717344331 ps |
| CPU time | 25.15 seconds |
| Started | Sep 11 08:50:11 PM UTC 24 |
| Finished | Sep 11 08:50:37 PM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719802074 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_addr.1719802074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.521132707 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 435483909 ps |
| CPU time | 38.07 seconds |
| Started | Sep 11 08:50:09 PM UTC 24 |
| Finished | Sep 11 08:50:49 PM UTC 24 |
| Peak memory | 596048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521132707 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.521132707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/69.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.3936618994 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 333735583 ps |
| CPU time | 30.3 seconds |
| Started | Sep 11 08:49:50 PM UTC 24 |
| Finished | Sep 11 08:50:22 PM UTC 24 |
| Peak memory | 596000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936618994 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.3936618994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/69.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.3425724384 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 2021720400 ps |
| CPU time | 26.66 seconds |
| Started | Sep 11 08:49:56 PM UTC 24 |
| Finished | Sep 11 08:50:24 PM UTC 24 |
| Peak memory | 593656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425724384 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.3425724384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/69.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.3834473306 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 39441938834 ps |
| CPU time | 604.77 seconds |
| Started | Sep 11 08:49:55 PM UTC 24 |
| Finished | Sep 11 09:00:08 PM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834473306 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.3834473306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/69.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.2389585706 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 197742206 ps |
| CPU time | 19.18 seconds |
| Started | Sep 11 08:49:53 PM UTC 24 |
| Finished | Sep 11 08:50:14 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389585706 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_delays.2389585706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/69.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.1965909314 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 1241802449 ps |
| CPU time | 37.34 seconds |
| Started | Sep 11 08:50:07 PM UTC 24 |
| Finished | Sep 11 08:50:46 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965909314 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.1965909314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/69.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.1467588060 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 212591891 ps |
| CPU time | 12.31 seconds |
| Started | Sep 11 08:49:33 PM UTC 24 |
| Finished | Sep 11 08:49:47 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467588060 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.1467588060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/69.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.1115265159 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 6124048601 ps |
| CPU time | 98.17 seconds |
| Started | Sep 11 08:49:46 PM UTC 24 |
| Finished | Sep 11 08:51:27 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115265159 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.1115265159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/69.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.759118687 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 5367228331 ps |
| CPU time | 107.81 seconds |
| Started | Sep 11 08:49:47 PM UTC 24 |
| Finished | Sep 11 08:51:38 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759118687 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.759118687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.974954474 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 53507133 ps |
| CPU time | 8.85 seconds |
| Started | Sep 11 08:49:42 PM UTC 24 |
| Finished | Sep 11 08:49:52 PM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974954474 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delays.974954474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/69.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.1713171178 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 3757590698 ps |
| CPU time | 253 seconds |
| Started | Sep 11 08:50:15 PM UTC 24 |
| Finished | Sep 11 08:54:32 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713171178 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.1713171178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/69.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.3540203297 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 1094569116 ps |
| CPU time | 66.43 seconds |
| Started | Sep 11 08:50:18 PM UTC 24 |
| Finished | Sep 11 08:51:27 PM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540203297 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.3540203297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/69.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.3854227828 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 300175449 ps |
| CPU time | 124.05 seconds |
| Started | Sep 11 08:50:17 PM UTC 24 |
| Finished | Sep 11 08:52:24 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854227828 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_rand_reset.3854227828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.902827163 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 5551078404 ps |
| CPU time | 311.58 seconds |
| Started | Sep 11 08:50:21 PM UTC 24 |
| Finished | Sep 11 08:55:37 PM UTC 24 |
| Peak memory | 596100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902827163 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_reset_error.902827163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.900473342 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 908145400 ps |
| CPU time | 45.84 seconds |
| Started | Sep 11 08:50:08 PM UTC 24 |
| Finished | Sep 11 08:50:55 PM UTC 24 |
| Peak memory | 595880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900473342 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.900473342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/69.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.2836942972 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 7174530708 ps |
| CPU time | 474.68 seconds |
| Started | Sep 11 07:09:38 PM UTC 24 |
| Finished | Sep 11 07:17:40 PM UTC 24 |
| Peak memory | 653928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2836942972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 7.chip_csr_mem_rw_with_rand_reset.2836942972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.3407454028 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 4717861354 ps |
| CPU time | 319.1 seconds |
| Started | Sep 11 07:09:35 PM UTC 24 |
| Finished | Sep 11 07:14:59 PM UTC 24 |
| Peak memory | 614820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407454028 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.3407454028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.4223791572 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 33337521910 ps |
| CPU time | 3426.46 seconds |
| Started | Sep 11 07:07:50 PM UTC 24 |
| Finished | Sep 11 08:05:37 PM UTC 24 |
| Peak memory | 613924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=4223791572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.chip_same_csr_outstanding.4223791572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.371362628 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 3845723712 ps |
| CPU time | 170.89 seconds |
| Started | Sep 11 07:07:53 PM UTC 24 |
| Finished | Sep 11 07:10:47 PM UTC 24 |
| Peak memory | 621328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371362628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.371362628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.1180949398 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 412037341 ps |
| CPU time | 48.68 seconds |
| Started | Sep 11 07:08:32 PM UTC 24 |
| Finished | Sep 11 07:09:23 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180949398 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.1180949398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.1935803657 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 141974789119 ps |
| CPU time | 2232.75 seconds |
| Started | Sep 11 07:08:44 PM UTC 24 |
| Finished | Sep 11 07:46:24 PM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935803657 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.1935803657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.1313656374 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 190477082 ps |
| CPU time | 22.75 seconds |
| Started | Sep 11 07:09:04 PM UTC 24 |
| Finished | Sep 11 07:09:28 PM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313656374 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.1313656374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.1054751751 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 137277325 ps |
| CPU time | 17.83 seconds |
| Started | Sep 11 07:08:51 PM UTC 24 |
| Finished | Sep 11 07:09:10 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054751751 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.1054751751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.875000378 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 170820260 ps |
| CPU time | 13.05 seconds |
| Started | Sep 11 07:08:11 PM UTC 24 |
| Finished | Sep 11 07:08:25 PM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875000378 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.875000378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.600985055 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 87090120131 ps |
| CPU time | 937.93 seconds |
| Started | Sep 11 07:08:30 PM UTC 24 |
| Finished | Sep 11 07:24:19 PM UTC 24 |
| Peak memory | 595756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600985055 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.600985055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.2767067168 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 32727175814 ps |
| CPU time | 490.59 seconds |
| Started | Sep 11 07:08:31 PM UTC 24 |
| Finished | Sep 11 07:16:47 PM UTC 24 |
| Peak memory | 596220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767067168 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2767067168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.452078318 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 170364001 ps |
| CPU time | 17.15 seconds |
| Started | Sep 11 07:08:20 PM UTC 24 |
| Finished | Sep 11 07:08:38 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452078318 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.452078318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.1591996403 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 399080780 ps |
| CPU time | 29.72 seconds |
| Started | Sep 11 07:08:46 PM UTC 24 |
| Finished | Sep 11 07:09:17 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591996403 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1591996403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.3187486222 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 228054903 ps |
| CPU time | 11.06 seconds |
| Started | Sep 11 07:07:57 PM UTC 24 |
| Finished | Sep 11 07:08:09 PM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187486222 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3187486222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.666612953 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 8880157151 ps |
| CPU time | 93.66 seconds |
| Started | Sep 11 07:08:07 PM UTC 24 |
| Finished | Sep 11 07:09:43 PM UTC 24 |
| Peak memory | 594036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666612953 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.666612953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.274244751 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 6307193971 ps |
| CPU time | 116.19 seconds |
| Started | Sep 11 07:08:10 PM UTC 24 |
| Finished | Sep 11 07:10:08 PM UTC 24 |
| Peak memory | 594068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274244751 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.274244751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.831198495 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 47211352 ps |
| CPU time | 8.44 seconds |
| Started | Sep 11 07:07:56 PM UTC 24 |
| Finished | Sep 11 07:08:05 PM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831198495 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.831198495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.2502084613 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 1206639467 ps |
| CPU time | 114.15 seconds |
| Started | Sep 11 07:09:07 PM UTC 24 |
| Finished | Sep 11 07:11:04 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502084613 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2502084613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.3452244124 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 591661201 ps |
| CPU time | 63.13 seconds |
| Started | Sep 11 07:09:32 PM UTC 24 |
| Finished | Sep 11 07:10:37 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452244124 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3452244124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.4109637456 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 285494615 ps |
| CPU time | 172.09 seconds |
| Started | Sep 11 07:09:17 PM UTC 24 |
| Finished | Sep 11 07:12:12 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109637456 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.4109637456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.958341682 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 100124589 ps |
| CPU time | 20.26 seconds |
| Started | Sep 11 07:09:34 PM UTC 24 |
| Finished | Sep 11 07:09:56 PM UTC 24 |
| Peak memory | 595880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958341682 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.958341682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.2239439162 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 178218036 ps |
| CPU time | 32.55 seconds |
| Started | Sep 11 07:08:55 PM UTC 24 |
| Finished | Sep 11 07:09:29 PM UTC 24 |
| Peak memory | 596072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239439162 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2239439162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.3455065413 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 221058228 ps |
| CPU time | 31.79 seconds |
| Started | Sep 11 08:50:56 PM UTC 24 |
| Finished | Sep 11 08:51:29 PM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455065413 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device.3455065413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/70.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.1835712850 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 106721529697 ps |
| CPU time | 1656.37 seconds |
| Started | Sep 11 08:50:58 PM UTC 24 |
| Finished | Sep 11 09:18:54 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835712850 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device_slow_rsp.1835712850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.2522522314 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 1273175045 ps |
| CPU time | 40.94 seconds |
| Started | Sep 11 08:51:08 PM UTC 24 |
| Finished | Sep 11 08:51:51 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522522314 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_addr.2522522314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.1884252164 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 2097298904 ps |
| CPU time | 65.21 seconds |
| Started | Sep 11 08:51:08 PM UTC 24 |
| Finished | Sep 11 08:52:15 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884252164 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.1884252164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/70.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.877611543 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 1065252468 ps |
| CPU time | 39.95 seconds |
| Started | Sep 11 08:50:39 PM UTC 24 |
| Finished | Sep 11 08:51:21 PM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877611543 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.877611543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/70.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.3006541294 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 65324444891 ps |
| CPU time | 632.16 seconds |
| Started | Sep 11 08:50:50 PM UTC 24 |
| Finished | Sep 11 09:01:29 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006541294 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.3006541294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/70.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.2624134100 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 13031214124 ps |
| CPU time | 169.04 seconds |
| Started | Sep 11 08:50:50 PM UTC 24 |
| Finished | Sep 11 08:53:42 PM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624134100 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.2624134100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/70.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.2635081585 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 127166491 ps |
| CPU time | 12.27 seconds |
| Started | Sep 11 08:50:47 PM UTC 24 |
| Finished | Sep 11 08:51:01 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635081585 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_delays.2635081585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/70.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.2778962075 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 2151085743 ps |
| CPU time | 50.12 seconds |
| Started | Sep 11 08:51:03 PM UTC 24 |
| Finished | Sep 11 08:51:55 PM UTC 24 |
| Peak memory | 595980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778962075 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.2778962075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/70.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.3049796317 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 248077442 ps |
| CPU time | 10.14 seconds |
| Started | Sep 11 08:50:24 PM UTC 24 |
| Finished | Sep 11 08:50:36 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049796317 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.3049796317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/70.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.3784430767 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 8863429761 ps |
| CPU time | 89.28 seconds |
| Started | Sep 11 08:50:36 PM UTC 24 |
| Finished | Sep 11 08:52:07 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784430767 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.3784430767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/70.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.2950483092 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 6801245205 ps |
| CPU time | 93.24 seconds |
| Started | Sep 11 08:50:38 PM UTC 24 |
| Finished | Sep 11 08:52:13 PM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950483092 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.2950483092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.2675754904 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 58120441 ps |
| CPU time | 8.8 seconds |
| Started | Sep 11 08:50:36 PM UTC 24 |
| Finished | Sep 11 08:50:46 PM UTC 24 |
| Peak memory | 593984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675754904 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delays.2675754904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/70.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.54884847 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 2953894097 ps |
| CPU time | 270.21 seconds |
| Started | Sep 11 08:51:12 PM UTC 24 |
| Finished | Sep 11 08:55:46 PM UTC 24 |
| Peak memory | 596140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54884847 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.54884847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/70.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.2670140691 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 2500096543 ps |
| CPU time | 213.29 seconds |
| Started | Sep 11 08:51:17 PM UTC 24 |
| Finished | Sep 11 08:54:54 PM UTC 24 |
| Peak memory | 596112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670140691 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.2670140691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/70.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.264039716 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 393057461 ps |
| CPU time | 162.71 seconds |
| Started | Sep 11 08:51:13 PM UTC 24 |
| Finished | Sep 11 08:53:58 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264039716 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_rand_reset.264039716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.1797435088 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 11210515531 ps |
| CPU time | 364.63 seconds |
| Started | Sep 11 08:51:15 PM UTC 24 |
| Finished | Sep 11 08:57:25 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797435088 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_reset_error.1797435088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.2257076941 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 24780841 ps |
| CPU time | 5.75 seconds |
| Started | Sep 11 08:51:06 PM UTC 24 |
| Finished | Sep 11 08:51:12 PM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257076941 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.2257076941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/70.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.898837558 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 1367384764 ps |
| CPU time | 63.26 seconds |
| Started | Sep 11 08:51:55 PM UTC 24 |
| Finished | Sep 11 08:53:00 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898837558 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device.898837558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/71.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.38522595 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 56544355765 ps |
| CPU time | 950.45 seconds |
| Started | Sep 11 08:51:52 PM UTC 24 |
| Finished | Sep 11 09:07:54 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38522595 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device_slow_rsp.38522595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.977817996 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 1219270566 ps |
| CPU time | 52.67 seconds |
| Started | Sep 11 08:52:17 PM UTC 24 |
| Finished | Sep 11 08:53:11 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977817996 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_addr.977817996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.675013379 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 818865203 ps |
| CPU time | 36.84 seconds |
| Started | Sep 11 08:51:56 PM UTC 24 |
| Finished | Sep 11 08:52:34 PM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675013379 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.675013379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/71.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.1106714131 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 1935451198 ps |
| CPU time | 72.12 seconds |
| Started | Sep 11 08:51:38 PM UTC 24 |
| Finished | Sep 11 08:52:52 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106714131 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.1106714131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/71.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.1543336769 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 88919040347 ps |
| CPU time | 902.53 seconds |
| Started | Sep 11 08:51:51 PM UTC 24 |
| Finished | Sep 11 09:07:04 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543336769 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.1543336769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/71.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.618461330 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 33460574950 ps |
| CPU time | 474.09 seconds |
| Started | Sep 11 08:51:52 PM UTC 24 |
| Finished | Sep 11 08:59:52 PM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618461330 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.618461330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/71.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.918695158 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 369591161 ps |
| CPU time | 42.75 seconds |
| Started | Sep 11 08:51:44 PM UTC 24 |
| Finished | Sep 11 08:52:29 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918695158 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_delays.918695158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/71.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.1000366931 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 1535976912 ps |
| CPU time | 46.53 seconds |
| Started | Sep 11 08:51:54 PM UTC 24 |
| Finished | Sep 11 08:52:42 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000366931 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.1000366931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/71.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.3179554907 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 142002991 ps |
| CPU time | 10.64 seconds |
| Started | Sep 11 08:51:18 PM UTC 24 |
| Finished | Sep 11 08:51:30 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179554907 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.3179554907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/71.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.3547590147 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 8652731333 ps |
| CPU time | 87.36 seconds |
| Started | Sep 11 08:51:23 PM UTC 24 |
| Finished | Sep 11 08:52:52 PM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547590147 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.3547590147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/71.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.2013055291 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 5557705526 ps |
| CPU time | 106.05 seconds |
| Started | Sep 11 08:51:26 PM UTC 24 |
| Finished | Sep 11 08:53:15 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013055291 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.2013055291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.4018371716 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 49431647 ps |
| CPU time | 9.28 seconds |
| Started | Sep 11 08:51:22 PM UTC 24 |
| Finished | Sep 11 08:51:32 PM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018371716 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delays.4018371716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/71.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.4013057391 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 4304579028 ps |
| CPU time | 293.33 seconds |
| Started | Sep 11 08:52:21 PM UTC 24 |
| Finished | Sep 11 08:57:18 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013057391 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.4013057391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/71.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.3755541845 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 1344461555 ps |
| CPU time | 95.59 seconds |
| Started | Sep 11 08:52:38 PM UTC 24 |
| Finished | Sep 11 08:54:16 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755541845 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.3755541845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/71.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.2133754029 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 9491368073 ps |
| CPU time | 813.09 seconds |
| Started | Sep 11 08:52:32 PM UTC 24 |
| Finished | Sep 11 09:06:16 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133754029 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_rand_reset.2133754029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.3274120821 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 975468957 ps |
| CPU time | 225.69 seconds |
| Started | Sep 11 08:52:42 PM UTC 24 |
| Finished | Sep 11 08:56:31 PM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274120821 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_reset_error.3274120821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.2440772888 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 278224547 ps |
| CPU time | 42.98 seconds |
| Started | Sep 11 08:51:59 PM UTC 24 |
| Finished | Sep 11 08:52:44 PM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440772888 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.2440772888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/71.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.1603480576 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 1693355228 ps |
| CPU time | 78.26 seconds |
| Started | Sep 11 08:53:26 PM UTC 24 |
| Finished | Sep 11 08:54:46 PM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603480576 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device.1603480576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/72.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.3591424526 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 2596789247 ps |
| CPU time | 52.36 seconds |
| Started | Sep 11 08:53:27 PM UTC 24 |
| Finished | Sep 11 08:54:21 PM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591424526 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device_slow_rsp.3591424526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.2357428678 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 693988455 ps |
| CPU time | 34.69 seconds |
| Started | Sep 11 08:53:43 PM UTC 24 |
| Finished | Sep 11 08:54:19 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357428678 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_addr.2357428678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.4053779218 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 779839182 ps |
| CPU time | 36.9 seconds |
| Started | Sep 11 08:53:37 PM UTC 24 |
| Finished | Sep 11 08:54:16 PM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053779218 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.4053779218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/72.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.1358079903 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 1888329870 ps |
| CPU time | 74.88 seconds |
| Started | Sep 11 08:53:09 PM UTC 24 |
| Finished | Sep 11 08:54:26 PM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358079903 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.1358079903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/72.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.1798218078 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 62131700644 ps |
| CPU time | 681.92 seconds |
| Started | Sep 11 08:53:14 PM UTC 24 |
| Finished | Sep 11 09:04:44 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798218078 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.1798218078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/72.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.1792783676 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 50911454969 ps |
| CPU time | 715.6 seconds |
| Started | Sep 11 08:53:18 PM UTC 24 |
| Finished | Sep 11 09:05:22 PM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792783676 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.1792783676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/72.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.2171406464 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 356411730 ps |
| CPU time | 39.83 seconds |
| Started | Sep 11 08:53:12 PM UTC 24 |
| Finished | Sep 11 08:53:53 PM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171406464 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_delays.2171406464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/72.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.4012591784 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 166021001 ps |
| CPU time | 21 seconds |
| Started | Sep 11 08:53:32 PM UTC 24 |
| Finished | Sep 11 08:53:55 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012591784 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.4012591784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/72.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.3871984735 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 230193958 ps |
| CPU time | 13.39 seconds |
| Started | Sep 11 08:52:49 PM UTC 24 |
| Finished | Sep 11 08:53:04 PM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871984735 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.3871984735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/72.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.1068741497 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 7285794707 ps |
| CPU time | 63.46 seconds |
| Started | Sep 11 08:52:58 PM UTC 24 |
| Finished | Sep 11 08:54:03 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068741497 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.1068741497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/72.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.3099785142 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 4532133710 ps |
| CPU time | 92.41 seconds |
| Started | Sep 11 08:53:05 PM UTC 24 |
| Finished | Sep 11 08:54:40 PM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099785142 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.3099785142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.4189764956 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 49755521 ps |
| CPU time | 9.11 seconds |
| Started | Sep 11 08:52:56 PM UTC 24 |
| Finished | Sep 11 08:53:06 PM UTC 24 |
| Peak memory | 593916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189764956 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delays.4189764956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/72.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.1643117001 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 2462102678 ps |
| CPU time | 76.83 seconds |
| Started | Sep 11 08:54:01 PM UTC 24 |
| Finished | Sep 11 08:55:20 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643117001 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.1643117001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/72.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.2641728426 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 2767524211 ps |
| CPU time | 161.29 seconds |
| Started | Sep 11 08:54:08 PM UTC 24 |
| Finished | Sep 11 08:56:52 PM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641728426 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.2641728426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/72.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.1489274908 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 7578304630 ps |
| CPU time | 265.99 seconds |
| Started | Sep 11 08:54:00 PM UTC 24 |
| Finished | Sep 11 08:58:30 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489274908 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_rand_reset.1489274908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.2624422321 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 5049489926 ps |
| CPU time | 281.04 seconds |
| Started | Sep 11 08:54:20 PM UTC 24 |
| Finished | Sep 11 08:59:05 PM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624422321 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_reset_error.2624422321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.938953654 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 328322662 ps |
| CPU time | 14.55 seconds |
| Started | Sep 11 08:53:41 PM UTC 24 |
| Finished | Sep 11 08:53:56 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938953654 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.938953654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/72.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.3117526968 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 1884958469 ps |
| CPU time | 71.1 seconds |
| Started | Sep 11 08:54:46 PM UTC 24 |
| Finished | Sep 11 08:55:59 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117526968 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device.3117526968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/73.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.3980142539 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 16024362226 ps |
| CPU time | 238.16 seconds |
| Started | Sep 11 08:54:52 PM UTC 24 |
| Finished | Sep 11 08:58:53 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980142539 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device_slow_rsp.3980142539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.1123869921 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 812553860 ps |
| CPU time | 45.83 seconds |
| Started | Sep 11 08:54:58 PM UTC 24 |
| Finished | Sep 11 08:55:46 PM UTC 24 |
| Peak memory | 595864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123869921 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_addr.1123869921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.2172195300 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 494212408 ps |
| CPU time | 40.66 seconds |
| Started | Sep 11 08:54:56 PM UTC 24 |
| Finished | Sep 11 08:55:38 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172195300 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.2172195300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/73.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.2093493076 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 2561503189 ps |
| CPU time | 102.76 seconds |
| Started | Sep 11 08:54:35 PM UTC 24 |
| Finished | Sep 11 08:56:20 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093493076 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.2093493076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/73.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.693023536 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 79349156253 ps |
| CPU time | 892.59 seconds |
| Started | Sep 11 08:54:39 PM UTC 24 |
| Finished | Sep 11 09:09:43 PM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693023536 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.693023536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/73.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.1280752632 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 35368995803 ps |
| CPU time | 564.6 seconds |
| Started | Sep 11 08:54:43 PM UTC 24 |
| Finished | Sep 11 09:04:15 PM UTC 24 |
| Peak memory | 596136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280752632 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.1280752632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/73.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.2417499375 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 442589838 ps |
| CPU time | 41.43 seconds |
| Started | Sep 11 08:54:40 PM UTC 24 |
| Finished | Sep 11 08:55:23 PM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417499375 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_delays.2417499375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/73.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.2684144487 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 1510097394 ps |
| CPU time | 45.94 seconds |
| Started | Sep 11 08:54:50 PM UTC 24 |
| Finished | Sep 11 08:55:38 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684144487 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.2684144487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/73.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.1333552528 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 231653482 ps |
| CPU time | 10.71 seconds |
| Started | Sep 11 08:54:20 PM UTC 24 |
| Finished | Sep 11 08:54:32 PM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333552528 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.1333552528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/73.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.2172637461 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 5449060138 ps |
| CPU time | 56.07 seconds |
| Started | Sep 11 08:54:25 PM UTC 24 |
| Finished | Sep 11 08:55:23 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172637461 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.2172637461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/73.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.229307633 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 5418374645 ps |
| CPU time | 91.96 seconds |
| Started | Sep 11 08:54:29 PM UTC 24 |
| Finished | Sep 11 08:56:03 PM UTC 24 |
| Peak memory | 593952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229307633 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.229307633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.390559585 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 39938030 ps |
| CPU time | 6.12 seconds |
| Started | Sep 11 08:54:23 PM UTC 24 |
| Finished | Sep 11 08:54:30 PM UTC 24 |
| Peak memory | 594088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390559585 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delays.390559585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/73.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.1022449011 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 1944052925 ps |
| CPU time | 160.92 seconds |
| Started | Sep 11 08:55:03 PM UTC 24 |
| Finished | Sep 11 08:57:47 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022449011 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.1022449011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/73.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.3842049413 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 5093507044 ps |
| CPU time | 365.49 seconds |
| Started | Sep 11 08:55:12 PM UTC 24 |
| Finished | Sep 11 09:01:23 PM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842049413 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.3842049413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/73.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.3596640749 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 18990924456 ps |
| CPU time | 802.63 seconds |
| Started | Sep 11 08:55:11 PM UTC 24 |
| Finished | Sep 11 09:08:43 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596640749 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_rand_reset.3596640749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.3778710046 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 988331500 ps |
| CPU time | 270.84 seconds |
| Started | Sep 11 08:55:16 PM UTC 24 |
| Finished | Sep 11 08:59:51 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778710046 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_reset_error.3778710046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.208188577 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 81773032 ps |
| CPU time | 10.53 seconds |
| Started | Sep 11 08:54:58 PM UTC 24 |
| Finished | Sep 11 08:55:09 PM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208188577 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.208188577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/73.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.1968039925 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 38012244 ps |
| CPU time | 9.14 seconds |
| Started | Sep 11 08:56:11 PM UTC 24 |
| Finished | Sep 11 08:56:22 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968039925 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device.1968039925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/74.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.1293209673 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 67055714607 ps |
| CPU time | 1034.38 seconds |
| Started | Sep 11 08:56:11 PM UTC 24 |
| Finished | Sep 11 09:13:38 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293209673 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device_slow_rsp.1293209673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.47520147 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 197238669 ps |
| CPU time | 23.36 seconds |
| Started | Sep 11 08:56:24 PM UTC 24 |
| Finished | Sep 11 08:56:49 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47520147 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_addr.47520147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.1267929161 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 61255711 ps |
| CPU time | 9.69 seconds |
| Started | Sep 11 08:56:15 PM UTC 24 |
| Finished | Sep 11 08:56:26 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267929161 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.1267929161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/74.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.3723651439 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 390758049 ps |
| CPU time | 16.33 seconds |
| Started | Sep 11 08:55:49 PM UTC 24 |
| Finished | Sep 11 08:56:07 PM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723651439 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.3723651439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/74.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.3409902708 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 8233681355 ps |
| CPU time | 102.86 seconds |
| Started | Sep 11 08:56:04 PM UTC 24 |
| Finished | Sep 11 08:57:49 PM UTC 24 |
| Peak memory | 593912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409902708 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.3409902708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/74.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.3735419691 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 45005267633 ps |
| CPU time | 630.44 seconds |
| Started | Sep 11 08:56:00 PM UTC 24 |
| Finished | Sep 11 09:06:38 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735419691 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.3735419691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/74.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.3762359654 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 539041368 ps |
| CPU time | 44.95 seconds |
| Started | Sep 11 08:55:59 PM UTC 24 |
| Finished | Sep 11 08:56:46 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762359654 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_delays.3762359654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/74.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.2440793803 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 74586174 ps |
| CPU time | 11.94 seconds |
| Started | Sep 11 08:56:07 PM UTC 24 |
| Finished | Sep 11 08:56:21 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440793803 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.2440793803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/74.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.784828628 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 55819268 ps |
| CPU time | 9.69 seconds |
| Started | Sep 11 08:55:35 PM UTC 24 |
| Finished | Sep 11 08:55:46 PM UTC 24 |
| Peak memory | 593764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784828628 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.784828628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/74.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.2521247823 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 8464217767 ps |
| CPU time | 126.12 seconds |
| Started | Sep 11 08:55:46 PM UTC 24 |
| Finished | Sep 11 08:57:56 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521247823 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.2521247823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/74.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.1025666167 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 4320449293 ps |
| CPU time | 92.63 seconds |
| Started | Sep 11 08:55:49 PM UTC 24 |
| Finished | Sep 11 08:57:24 PM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025666167 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.1025666167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.1469854227 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 41507474 ps |
| CPU time | 6.04 seconds |
| Started | Sep 11 08:55:43 PM UTC 24 |
| Finished | Sep 11 08:55:51 PM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469854227 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delays.1469854227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/74.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.2106897200 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 10172334415 ps |
| CPU time | 320.78 seconds |
| Started | Sep 11 08:56:30 PM UTC 24 |
| Finished | Sep 11 09:01:55 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106897200 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.2106897200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/74.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.1954415791 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 13138069315 ps |
| CPU time | 415.29 seconds |
| Started | Sep 11 08:56:46 PM UTC 24 |
| Finished | Sep 11 09:03:48 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954415791 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.1954415791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/74.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.3579583563 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 19232310 ps |
| CPU time | 13.77 seconds |
| Started | Sep 11 08:56:32 PM UTC 24 |
| Finished | Sep 11 08:56:47 PM UTC 24 |
| Peak memory | 593656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579583563 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_rand_reset.3579583563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.2087160423 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 372360866 ps |
| CPU time | 168.65 seconds |
| Started | Sep 11 08:56:41 PM UTC 24 |
| Finished | Sep 11 08:59:33 PM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087160423 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_reset_error.2087160423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.299505347 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 832854576 ps |
| CPU time | 40.59 seconds |
| Started | Sep 11 08:56:14 PM UTC 24 |
| Finished | Sep 11 08:56:56 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299505347 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.299505347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/74.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.3334506464 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 700438547 ps |
| CPU time | 39.14 seconds |
| Started | Sep 11 08:57:19 PM UTC 24 |
| Finished | Sep 11 08:58:00 PM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334506464 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device.3334506464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/75.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.3251845466 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 5365989279 ps |
| CPU time | 86.65 seconds |
| Started | Sep 11 08:57:24 PM UTC 24 |
| Finished | Sep 11 08:58:52 PM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251845466 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device_slow_rsp.3251845466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.3221095790 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 718021679 ps |
| CPU time | 33.83 seconds |
| Started | Sep 11 08:57:44 PM UTC 24 |
| Finished | Sep 11 08:58:20 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221095790 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_addr.3221095790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.2931921518 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 397712907 ps |
| CPU time | 34.49 seconds |
| Started | Sep 11 08:57:30 PM UTC 24 |
| Finished | Sep 11 08:58:06 PM UTC 24 |
| Peak memory | 596084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931921518 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.2931921518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/75.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.3385767544 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 2189862440 ps |
| CPU time | 63.78 seconds |
| Started | Sep 11 08:57:12 PM UTC 24 |
| Finished | Sep 11 08:58:18 PM UTC 24 |
| Peak memory | 596056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385767544 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.3385767544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/75.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.2333577879 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 101244832780 ps |
| CPU time | 1035.47 seconds |
| Started | Sep 11 08:57:15 PM UTC 24 |
| Finished | Sep 11 09:14:43 PM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333577879 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.2333577879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/75.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.4214743040 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 5754654883 ps |
| CPU time | 100.48 seconds |
| Started | Sep 11 08:57:21 PM UTC 24 |
| Finished | Sep 11 08:59:04 PM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214743040 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.4214743040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/75.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.592751238 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 588852858 ps |
| CPU time | 43.73 seconds |
| Started | Sep 11 08:57:13 PM UTC 24 |
| Finished | Sep 11 08:57:59 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592751238 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_delays.592751238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/75.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.3097560066 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 851923683 ps |
| CPU time | 36.59 seconds |
| Started | Sep 11 08:57:27 PM UTC 24 |
| Finished | Sep 11 08:58:05 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097560066 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.3097560066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/75.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.1495732526 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 50332635 ps |
| CPU time | 7.99 seconds |
| Started | Sep 11 08:56:48 PM UTC 24 |
| Finished | Sep 11 08:56:57 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495732526 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.1495732526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/75.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.1117942790 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 7689792008 ps |
| CPU time | 83.73 seconds |
| Started | Sep 11 08:56:57 PM UTC 24 |
| Finished | Sep 11 08:58:22 PM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117942790 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.1117942790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/75.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.1410374395 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 4044583251 ps |
| CPU time | 62.13 seconds |
| Started | Sep 11 08:57:08 PM UTC 24 |
| Finished | Sep 11 08:58:12 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410374395 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.1410374395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.4197724322 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 37632372 ps |
| CPU time | 8.73 seconds |
| Started | Sep 11 08:56:48 PM UTC 24 |
| Finished | Sep 11 08:56:58 PM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197724322 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delays.4197724322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/75.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.3511179786 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 2416837368 ps |
| CPU time | 198.2 seconds |
| Started | Sep 11 08:57:51 PM UTC 24 |
| Finished | Sep 11 09:01:13 PM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511179786 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.3511179786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/75.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.1854285051 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 2362467776 ps |
| CPU time | 147.07 seconds |
| Started | Sep 11 08:58:04 PM UTC 24 |
| Finished | Sep 11 09:00:35 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854285051 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.1854285051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/75.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.4206002506 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 5088323441 ps |
| CPU time | 707.79 seconds |
| Started | Sep 11 08:57:50 PM UTC 24 |
| Finished | Sep 11 09:09:48 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206002506 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_rand_reset.4206002506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.1356843798 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 209561777 ps |
| CPU time | 141.28 seconds |
| Started | Sep 11 08:58:13 PM UTC 24 |
| Finished | Sep 11 09:00:37 PM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356843798 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_reset_error.1356843798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.3086208624 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 142246449 ps |
| CPU time | 23.67 seconds |
| Started | Sep 11 08:57:44 PM UTC 24 |
| Finished | Sep 11 08:58:10 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086208624 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.3086208624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/75.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.3599281295 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 2094616032 ps |
| CPU time | 81 seconds |
| Started | Sep 11 08:58:34 PM UTC 24 |
| Finished | Sep 11 08:59:57 PM UTC 24 |
| Peak memory | 596056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599281295 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device.3599281295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/76.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.881665341 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 79885093225 ps |
| CPU time | 1329.01 seconds |
| Started | Sep 11 08:58:35 PM UTC 24 |
| Finished | Sep 11 09:21:01 PM UTC 24 |
| Peak memory | 598828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881665341 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device_slow_rsp.881665341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.1527317747 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 240520480 ps |
| CPU time | 30.48 seconds |
| Started | Sep 11 08:58:42 PM UTC 24 |
| Finished | Sep 11 08:59:14 PM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527317747 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_addr.1527317747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.1844881567 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 439841628 ps |
| CPU time | 15.44 seconds |
| Started | Sep 11 08:58:40 PM UTC 24 |
| Finished | Sep 11 08:58:57 PM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844881567 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.1844881567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/76.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.1877661800 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 1389457636 ps |
| CPU time | 67.18 seconds |
| Started | Sep 11 08:58:24 PM UTC 24 |
| Finished | Sep 11 08:59:33 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877661800 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.1877661800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/76.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.3164095580 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 108884386460 ps |
| CPU time | 1033.16 seconds |
| Started | Sep 11 08:58:28 PM UTC 24 |
| Finished | Sep 11 09:15:53 PM UTC 24 |
| Peak memory | 596140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164095580 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.3164095580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/76.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.486864317 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 53345449921 ps |
| CPU time | 982.24 seconds |
| Started | Sep 11 08:58:32 PM UTC 24 |
| Finished | Sep 11 09:15:07 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486864317 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.486864317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/76.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.3352385465 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 424768204 ps |
| CPU time | 35.38 seconds |
| Started | Sep 11 08:58:29 PM UTC 24 |
| Finished | Sep 11 08:59:06 PM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352385465 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_delays.3352385465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/76.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.3286654170 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 112377312 ps |
| CPU time | 11.75 seconds |
| Started | Sep 11 08:58:38 PM UTC 24 |
| Finished | Sep 11 08:58:52 PM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286654170 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.3286654170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/76.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.3485889220 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 50318961 ps |
| CPU time | 8.11 seconds |
| Started | Sep 11 08:58:14 PM UTC 24 |
| Finished | Sep 11 08:58:23 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485889220 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.3485889220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/76.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.1578704502 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 7479590455 ps |
| CPU time | 79.84 seconds |
| Started | Sep 11 08:58:21 PM UTC 24 |
| Finished | Sep 11 08:59:43 PM UTC 24 |
| Peak memory | 593952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578704502 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.1578704502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/76.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.260962712 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 4811913620 ps |
| CPU time | 94.27 seconds |
| Started | Sep 11 08:58:26 PM UTC 24 |
| Finished | Sep 11 09:00:02 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260962712 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.260962712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.2162776700 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 40475450 ps |
| CPU time | 7.77 seconds |
| Started | Sep 11 08:58:20 PM UTC 24 |
| Finished | Sep 11 08:58:29 PM UTC 24 |
| Peak memory | 593980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162776700 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays.2162776700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/76.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.1750177923 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 6513307178 ps |
| CPU time | 208.21 seconds |
| Started | Sep 11 08:58:45 PM UTC 24 |
| Finished | Sep 11 09:02:17 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750177923 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.1750177923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/76.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.3777247017 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 9291887529 ps |
| CPU time | 286.53 seconds |
| Started | Sep 11 08:58:55 PM UTC 24 |
| Finished | Sep 11 09:03:46 PM UTC 24 |
| Peak memory | 596108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777247017 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.3777247017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/76.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.1709542269 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 325232102 ps |
| CPU time | 83.45 seconds |
| Started | Sep 11 08:58:47 PM UTC 24 |
| Finished | Sep 11 09:00:13 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709542269 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_rand_reset.1709542269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.3234022188 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 6575351110 ps |
| CPU time | 654.44 seconds |
| Started | Sep 11 08:58:54 PM UTC 24 |
| Finished | Sep 11 09:09:57 PM UTC 24 |
| Peak memory | 596044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234022188 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_reset_error.3234022188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.1577265189 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 1274565216 ps |
| CPU time | 45.35 seconds |
| Started | Sep 11 08:58:42 PM UTC 24 |
| Finished | Sep 11 08:59:29 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577265189 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.1577265189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/76.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.2067084202 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 878733619 ps |
| CPU time | 63.66 seconds |
| Started | Sep 11 08:59:21 PM UTC 24 |
| Finished | Sep 11 09:00:26 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067084202 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device.2067084202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/77.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.806482035 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 60657166477 ps |
| CPU time | 917.72 seconds |
| Started | Sep 11 08:59:26 PM UTC 24 |
| Finished | Sep 11 09:14:55 PM UTC 24 |
| Peak memory | 596116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806482035 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device_slow_rsp.806482035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.181413580 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 1056545716 ps |
| CPU time | 33.57 seconds |
| Started | Sep 11 08:59:27 PM UTC 24 |
| Finished | Sep 11 09:00:02 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181413580 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_addr.181413580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.1489418733 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 2027685528 ps |
| CPU time | 64.45 seconds |
| Started | Sep 11 08:59:29 PM UTC 24 |
| Finished | Sep 11 09:00:35 PM UTC 24 |
| Peak memory | 596080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489418733 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.1489418733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/77.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.2069854311 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 110185380 ps |
| CPU time | 12.05 seconds |
| Started | Sep 11 08:59:16 PM UTC 24 |
| Finished | Sep 11 08:59:29 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069854311 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.2069854311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/77.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.2183536784 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 75912461773 ps |
| CPU time | 708.52 seconds |
| Started | Sep 11 08:59:14 PM UTC 24 |
| Finished | Sep 11 09:11:11 PM UTC 24 |
| Peak memory | 596012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183536784 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.2183536784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/77.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.1387981804 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 27169416980 ps |
| CPU time | 409.43 seconds |
| Started | Sep 11 08:59:19 PM UTC 24 |
| Finished | Sep 11 09:06:14 PM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387981804 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.1387981804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/77.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.4266572246 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 203552041 ps |
| CPU time | 25.94 seconds |
| Started | Sep 11 08:59:17 PM UTC 24 |
| Finished | Sep 11 08:59:44 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266572246 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_delays.4266572246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/77.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.3106146019 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 1572185348 ps |
| CPU time | 39.68 seconds |
| Started | Sep 11 08:59:24 PM UTC 24 |
| Finished | Sep 11 09:00:06 PM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106146019 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.3106146019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/77.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.2751930185 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 44548460 ps |
| CPU time | 7.37 seconds |
| Started | Sep 11 08:58:56 PM UTC 24 |
| Finished | Sep 11 08:59:04 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751930185 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.2751930185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/77.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.489647419 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 7082641289 ps |
| CPU time | 65.21 seconds |
| Started | Sep 11 08:59:09 PM UTC 24 |
| Finished | Sep 11 09:00:16 PM UTC 24 |
| Peak memory | 593836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489647419 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.489647419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/77.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.3277669562 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 6088792958 ps |
| CPU time | 135.86 seconds |
| Started | Sep 11 08:59:13 PM UTC 24 |
| Finished | Sep 11 09:01:32 PM UTC 24 |
| Peak memory | 593836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277669562 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.3277669562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.2782011462 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 55677654 ps |
| CPU time | 9.85 seconds |
| Started | Sep 11 08:59:02 PM UTC 24 |
| Finished | Sep 11 08:59:13 PM UTC 24 |
| Peak memory | 593980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782011462 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delays.2782011462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/77.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.3558139397 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 3853201157 ps |
| CPU time | 128.1 seconds |
| Started | Sep 11 08:59:32 PM UTC 24 |
| Finished | Sep 11 09:01:43 PM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558139397 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.3558139397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/77.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.4024375563 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 3526215389 ps |
| CPU time | 219.87 seconds |
| Started | Sep 11 08:59:43 PM UTC 24 |
| Finished | Sep 11 09:03:26 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024375563 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.4024375563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/77.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.3010254046 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 223563941 ps |
| CPU time | 94.74 seconds |
| Started | Sep 11 08:59:36 PM UTC 24 |
| Finished | Sep 11 09:01:14 PM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010254046 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_rand_reset.3010254046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.286138293 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 386457816 ps |
| CPU time | 137.25 seconds |
| Started | Sep 11 08:59:51 PM UTC 24 |
| Finished | Sep 11 09:02:11 PM UTC 24 |
| Peak memory | 596084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286138293 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_reset_error.286138293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.1135440894 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 220377692 ps |
| CPU time | 27.66 seconds |
| Started | Sep 11 08:59:24 PM UTC 24 |
| Finished | Sep 11 08:59:54 PM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135440894 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.1135440894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/77.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.2118659926 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 2370090330 ps |
| CPU time | 98.98 seconds |
| Started | Sep 11 09:00:17 PM UTC 24 |
| Finished | Sep 11 09:01:58 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118659926 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device.2118659926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/78.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.1226458652 |
| Short name | T2918 |
| Test name | |
| Test status | |
| Simulation time | 151070846725 ps |
| CPU time | 2162.4 seconds |
| Started | Sep 11 09:00:17 PM UTC 24 |
| Finished | Sep 11 09:36:45 PM UTC 24 |
| Peak memory | 598936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226458652 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device_slow_rsp.1226458652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.394481351 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 377461359 ps |
| CPU time | 14.75 seconds |
| Started | Sep 11 09:00:31 PM UTC 24 |
| Finished | Sep 11 09:00:47 PM UTC 24 |
| Peak memory | 595964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394481351 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_addr.394481351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.3585414252 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 1470400645 ps |
| CPU time | 48.73 seconds |
| Started | Sep 11 09:00:25 PM UTC 24 |
| Finished | Sep 11 09:01:16 PM UTC 24 |
| Peak memory | 596072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585414252 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.3585414252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/78.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.882014331 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 268534828 ps |
| CPU time | 23.12 seconds |
| Started | Sep 11 09:00:04 PM UTC 24 |
| Finished | Sep 11 09:00:30 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882014331 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.882014331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/78.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_large_delays.3910411804 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 53588387938 ps |
| CPU time | 493.34 seconds |
| Started | Sep 11 09:00:13 PM UTC 24 |
| Finished | Sep 11 09:08:33 PM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910411804 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.3910411804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/78.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.829039911 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 66487498047 ps |
| CPU time | 969.66 seconds |
| Started | Sep 11 09:00:15 PM UTC 24 |
| Finished | Sep 11 09:16:36 PM UTC 24 |
| Peak memory | 595996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829039911 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.829039911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/78.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.701805685 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 510629895 ps |
| CPU time | 45.27 seconds |
| Started | Sep 11 09:00:09 PM UTC 24 |
| Finished | Sep 11 09:00:56 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701805685 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_delays.701805685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/78.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.2288050422 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 1400064996 ps |
| CPU time | 41.13 seconds |
| Started | Sep 11 09:00:30 PM UTC 24 |
| Finished | Sep 11 09:01:12 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288050422 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.2288050422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/78.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.2298087372 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 45696904 ps |
| CPU time | 8.81 seconds |
| Started | Sep 11 08:59:52 PM UTC 24 |
| Finished | Sep 11 09:00:02 PM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298087372 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.2298087372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/78.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.1484049710 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 7357809636 ps |
| CPU time | 67.61 seconds |
| Started | Sep 11 08:59:56 PM UTC 24 |
| Finished | Sep 11 09:01:05 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484049710 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.1484049710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/78.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.800245619 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 4734807893 ps |
| CPU time | 68.72 seconds |
| Started | Sep 11 09:00:06 PM UTC 24 |
| Finished | Sep 11 09:01:16 PM UTC 24 |
| Peak memory | 594084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800245619 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.800245619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.3546196977 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 55646341 ps |
| CPU time | 8.72 seconds |
| Started | Sep 11 08:59:58 PM UTC 24 |
| Finished | Sep 11 09:00:08 PM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546196977 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delays.3546196977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/78.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.534172123 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 2165615966 ps |
| CPU time | 183.77 seconds |
| Started | Sep 11 09:00:29 PM UTC 24 |
| Finished | Sep 11 09:03:36 PM UTC 24 |
| Peak memory | 596112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534172123 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.534172123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/78.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.3499408613 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 9802355995 ps |
| CPU time | 362.49 seconds |
| Started | Sep 11 09:00:36 PM UTC 24 |
| Finished | Sep 11 09:06:45 PM UTC 24 |
| Peak memory | 596212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499408613 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.3499408613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/78.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.2798612986 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 850615148 ps |
| CPU time | 271.04 seconds |
| Started | Sep 11 09:00:31 PM UTC 24 |
| Finished | Sep 11 09:05:06 PM UTC 24 |
| Peak memory | 596108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798612986 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_rand_reset.2798612986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.759578503 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 191221423 ps |
| CPU time | 51.69 seconds |
| Started | Sep 11 09:00:39 PM UTC 24 |
| Finished | Sep 11 09:01:33 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759578503 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_reset_error.759578503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.1157300971 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 297731514 ps |
| CPU time | 31.46 seconds |
| Started | Sep 11 09:00:29 PM UTC 24 |
| Finished | Sep 11 09:01:02 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157300971 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.1157300971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/78.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.3038487656 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 1632357594 ps |
| CPU time | 76.86 seconds |
| Started | Sep 11 09:01:22 PM UTC 24 |
| Finished | Sep 11 09:02:41 PM UTC 24 |
| Peak memory | 596060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038487656 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device.3038487656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/79.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.3072840926 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 30739515660 ps |
| CPU time | 539.82 seconds |
| Started | Sep 11 09:01:24 PM UTC 24 |
| Finished | Sep 11 09:10:32 PM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072840926 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device_slow_rsp.3072840926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.3740339891 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 22034952 ps |
| CPU time | 7.71 seconds |
| Started | Sep 11 09:01:38 PM UTC 24 |
| Finished | Sep 11 09:01:47 PM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740339891 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_addr.3740339891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.2678725037 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 750018500 ps |
| CPU time | 26.76 seconds |
| Started | Sep 11 09:01:25 PM UTC 24 |
| Finished | Sep 11 09:01:53 PM UTC 24 |
| Peak memory | 596080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678725037 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.2678725037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/79.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.3754174190 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 1746110196 ps |
| CPU time | 72.87 seconds |
| Started | Sep 11 09:01:03 PM UTC 24 |
| Finished | Sep 11 09:02:18 PM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754174190 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.3754174190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/79.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_large_delays.2654098942 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 65954327872 ps |
| CPU time | 617.85 seconds |
| Started | Sep 11 09:01:15 PM UTC 24 |
| Finished | Sep 11 09:11:40 PM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654098942 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.2654098942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/79.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_slow_rsp.1855508803 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 27733872877 ps |
| CPU time | 485.21 seconds |
| Started | Sep 11 09:01:22 PM UTC 24 |
| Finished | Sep 11 09:09:34 PM UTC 24 |
| Peak memory | 595980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855508803 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.1855508803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/79.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.1023720649 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 248329988 ps |
| CPU time | 27.05 seconds |
| Started | Sep 11 09:01:12 PM UTC 24 |
| Finished | Sep 11 09:01:41 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023720649 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_delays.1023720649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/79.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.1320232633 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 157404688 ps |
| CPU time | 8.26 seconds |
| Started | Sep 11 09:01:26 PM UTC 24 |
| Finished | Sep 11 09:01:36 PM UTC 24 |
| Peak memory | 594028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320232633 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.1320232633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/79.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.1363820604 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 178358355 ps |
| CPU time | 8.73 seconds |
| Started | Sep 11 09:00:52 PM UTC 24 |
| Finished | Sep 11 09:01:02 PM UTC 24 |
| Peak memory | 594012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363820604 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.1363820604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/79.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.2614157904 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 10953317168 ps |
| CPU time | 100.63 seconds |
| Started | Sep 11 09:00:56 PM UTC 24 |
| Finished | Sep 11 09:02:39 PM UTC 24 |
| Peak memory | 593704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614157904 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.2614157904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/79.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.269054351 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 4197994434 ps |
| CPU time | 65.21 seconds |
| Started | Sep 11 09:01:00 PM UTC 24 |
| Finished | Sep 11 09:02:07 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269054351 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.269054351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.1768276627 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 46660929 ps |
| CPU time | 9.21 seconds |
| Started | Sep 11 09:00:54 PM UTC 24 |
| Finished | Sep 11 09:01:04 PM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768276627 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delays.1768276627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/79.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.741454684 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 1257723232 ps |
| CPU time | 98.33 seconds |
| Started | Sep 11 09:01:37 PM UTC 24 |
| Finished | Sep 11 09:03:18 PM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741454684 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.741454684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/79.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.1334091035 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 6341646701 ps |
| CPU time | 171.09 seconds |
| Started | Sep 11 09:01:39 PM UTC 24 |
| Finished | Sep 11 09:04:34 PM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334091035 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.1334091035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/79.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.2010812195 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 160965195 ps |
| CPU time | 91.62 seconds |
| Started | Sep 11 09:01:36 PM UTC 24 |
| Finished | Sep 11 09:03:10 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010812195 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_rand_reset.2010812195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.4167978971 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 1854467891 ps |
| CPU time | 358.42 seconds |
| Started | Sep 11 09:01:39 PM UTC 24 |
| Finished | Sep 11 09:07:43 PM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167978971 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_reset_error.4167978971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.164247874 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 1289633737 ps |
| CPU time | 45.95 seconds |
| Started | Sep 11 09:01:28 PM UTC 24 |
| Finished | Sep 11 09:02:16 PM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164247874 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.164247874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/79.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.2695963615 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 7338464384 ps |
| CPU time | 390.37 seconds |
| Started | Sep 11 07:11:51 PM UTC 24 |
| Finished | Sep 11 07:18:27 PM UTC 24 |
| Peak memory | 663964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2695963615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 8.chip_csr_mem_rw_with_rand_reset.2695963615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.2686948952 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 6008276148 ps |
| CPU time | 674.24 seconds |
| Started | Sep 11 07:11:45 PM UTC 24 |
| Finished | Sep 11 07:23:09 PM UTC 24 |
| Peak memory | 618960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686948952 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.2686948952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.2932573269 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 31556881472 ps |
| CPU time | 3375.26 seconds |
| Started | Sep 11 07:09:37 PM UTC 24 |
| Finished | Sep 11 08:06:33 PM UTC 24 |
| Peak memory | 611296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2932573269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.chip_same_csr_outstanding.2932573269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.3767798475 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 820742648 ps |
| CPU time | 74.29 seconds |
| Started | Sep 11 07:10:20 PM UTC 24 |
| Finished | Sep 11 07:11:37 PM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767798475 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.3767798475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.2445137031 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 98511629422 ps |
| CPU time | 1679.35 seconds |
| Started | Sep 11 07:10:26 PM UTC 24 |
| Finished | Sep 11 07:38:46 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445137031 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.2445137031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.1938354451 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 928415672 ps |
| CPU time | 45.26 seconds |
| Started | Sep 11 07:11:01 PM UTC 24 |
| Finished | Sep 11 07:11:48 PM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938354451 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1938354451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.1656595362 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 1940233388 ps |
| CPU time | 71.43 seconds |
| Started | Sep 11 07:10:35 PM UTC 24 |
| Finished | Sep 11 07:11:48 PM UTC 24 |
| Peak memory | 596072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656595362 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1656595362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.3726075331 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 1745678919 ps |
| CPU time | 98.14 seconds |
| Started | Sep 11 07:09:53 PM UTC 24 |
| Finished | Sep 11 07:11:33 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726075331 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.3726075331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.3190008152 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 68870689711 ps |
| CPU time | 731.76 seconds |
| Started | Sep 11 07:10:21 PM UTC 24 |
| Finished | Sep 11 07:22:41 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190008152 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3190008152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.2291629482 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 31145093602 ps |
| CPU time | 461.26 seconds |
| Started | Sep 11 07:10:21 PM UTC 24 |
| Finished | Sep 11 07:18:08 PM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291629482 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2291629482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.863739080 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 383218363 ps |
| CPU time | 47.72 seconds |
| Started | Sep 11 07:10:08 PM UTC 24 |
| Finished | Sep 11 07:10:58 PM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863739080 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.863739080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.3450388896 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 2224030302 ps |
| CPU time | 69.36 seconds |
| Started | Sep 11 07:10:33 PM UTC 24 |
| Finished | Sep 11 07:11:44 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450388896 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3450388896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.1746378429 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 230618014 ps |
| CPU time | 14.41 seconds |
| Started | Sep 11 07:09:41 PM UTC 24 |
| Finished | Sep 11 07:09:57 PM UTC 24 |
| Peak memory | 593844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746378429 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1746378429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.2638205605 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 10079924373 ps |
| CPU time | 131.86 seconds |
| Started | Sep 11 07:09:48 PM UTC 24 |
| Finished | Sep 11 07:12:03 PM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638205605 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2638205605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3247684379 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 5976283909 ps |
| CPU time | 85.59 seconds |
| Started | Sep 11 07:09:52 PM UTC 24 |
| Finished | Sep 11 07:11:20 PM UTC 24 |
| Peak memory | 593956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247684379 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3247684379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.1679882736 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 38643264 ps |
| CPU time | 8.4 seconds |
| Started | Sep 11 07:09:48 PM UTC 24 |
| Finished | Sep 11 07:09:57 PM UTC 24 |
| Peak memory | 594068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679882736 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.1679882736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.2306261311 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 2629090033 ps |
| CPU time | 250.58 seconds |
| Started | Sep 11 07:11:13 PM UTC 24 |
| Finished | Sep 11 07:15:27 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306261311 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2306261311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.1634167549 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 1092680858 ps |
| CPU time | 47.59 seconds |
| Started | Sep 11 07:11:30 PM UTC 24 |
| Finished | Sep 11 07:12:19 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634167549 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1634167549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1608299944 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 785575877 ps |
| CPU time | 412.8 seconds |
| Started | Sep 11 07:11:20 PM UTC 24 |
| Finished | Sep 11 07:18:18 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608299944 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.1608299944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.1904543900 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 1502858110 ps |
| CPU time | 81.93 seconds |
| Started | Sep 11 07:10:38 PM UTC 24 |
| Finished | Sep 11 07:12:02 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904543900 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1904543900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.3665426346 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 1384961309 ps |
| CPU time | 58.65 seconds |
| Started | Sep 11 09:02:17 PM UTC 24 |
| Finished | Sep 11 09:03:18 PM UTC 24 |
| Peak memory | 596060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665426346 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device.3665426346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/80.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.1754905376 |
| Short name | T2912 |
| Test name | |
| Test status | |
| Simulation time | 118090461344 ps |
| CPU time | 1703.2 seconds |
| Started | Sep 11 09:02:17 PM UTC 24 |
| Finished | Sep 11 09:30:59 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754905376 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device_slow_rsp.1754905376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.2451522485 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 752615998 ps |
| CPU time | 37.46 seconds |
| Started | Sep 11 09:02:33 PM UTC 24 |
| Finished | Sep 11 09:03:12 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451522485 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_addr.2451522485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.2858882514 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 1809240762 ps |
| CPU time | 64.68 seconds |
| Started | Sep 11 09:02:25 PM UTC 24 |
| Finished | Sep 11 09:03:31 PM UTC 24 |
| Peak memory | 596080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858882514 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.2858882514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/80.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.2114300658 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 1861831869 ps |
| CPU time | 57.26 seconds |
| Started | Sep 11 09:01:59 PM UTC 24 |
| Finished | Sep 11 09:02:58 PM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114300658 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.2114300658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/80.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_large_delays.474023097 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 48514474734 ps |
| CPU time | 556.23 seconds |
| Started | Sep 11 09:02:08 PM UTC 24 |
| Finished | Sep 11 09:11:32 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474023097 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.474023097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/80.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_slow_rsp.2595569877 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 58934592065 ps |
| CPU time | 852.81 seconds |
| Started | Sep 11 09:02:13 PM UTC 24 |
| Finished | Sep 11 09:16:36 PM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595569877 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.2595569877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/80.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.628853407 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 491915648 ps |
| CPU time | 38.72 seconds |
| Started | Sep 11 09:02:07 PM UTC 24 |
| Finished | Sep 11 09:02:47 PM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628853407 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_delays.628853407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/80.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.3162470185 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 531034093 ps |
| CPU time | 54.28 seconds |
| Started | Sep 11 09:02:18 PM UTC 24 |
| Finished | Sep 11 09:03:14 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162470185 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.3162470185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/80.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.1189542964 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 50432264 ps |
| CPU time | 6.02 seconds |
| Started | Sep 11 09:01:44 PM UTC 24 |
| Finished | Sep 11 09:01:51 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189542964 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.1189542964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/80.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.837670125 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 7057315929 ps |
| CPU time | 88.46 seconds |
| Started | Sep 11 09:01:55 PM UTC 24 |
| Finished | Sep 11 09:03:26 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837670125 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.837670125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/80.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.1453887277 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 3511395387 ps |
| CPU time | 54.85 seconds |
| Started | Sep 11 09:01:59 PM UTC 24 |
| Finished | Sep 11 09:02:55 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453887277 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.1453887277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.2424160486 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 37660578 ps |
| CPU time | 8.59 seconds |
| Started | Sep 11 09:01:53 PM UTC 24 |
| Finished | Sep 11 09:02:03 PM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424160486 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delays.2424160486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/80.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.2373972495 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 6095374215 ps |
| CPU time | 191.06 seconds |
| Started | Sep 11 09:02:37 PM UTC 24 |
| Finished | Sep 11 09:05:51 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373972495 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.2373972495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/80.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.4177294428 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 2367967569 ps |
| CPU time | 159.43 seconds |
| Started | Sep 11 09:02:43 PM UTC 24 |
| Finished | Sep 11 09:05:25 PM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177294428 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.4177294428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/80.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.948237495 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 7374272121 ps |
| CPU time | 527.6 seconds |
| Started | Sep 11 09:02:39 PM UTC 24 |
| Finished | Sep 11 09:11:34 PM UTC 24 |
| Peak memory | 596076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948237495 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_rand_reset.948237495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.3885871307 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 211611497 ps |
| CPU time | 51.55 seconds |
| Started | Sep 11 09:02:44 PM UTC 24 |
| Finished | Sep 11 09:03:38 PM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885871307 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_reset_error.3885871307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.4114145262 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 212570909 ps |
| CPU time | 32.53 seconds |
| Started | Sep 11 09:02:30 PM UTC 24 |
| Finished | Sep 11 09:03:04 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114145262 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.4114145262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/80.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.1338937253 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 384848952 ps |
| CPU time | 33.39 seconds |
| Started | Sep 11 09:03:36 PM UTC 24 |
| Finished | Sep 11 09:04:11 PM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338937253 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device.1338937253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/81.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.427920833 |
| Short name | T2908 |
| Test name | |
| Test status | |
| Simulation time | 94773516528 ps |
| CPU time | 1563.88 seconds |
| Started | Sep 11 09:03:39 PM UTC 24 |
| Finished | Sep 11 09:30:02 PM UTC 24 |
| Peak memory | 598928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427920833 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device_slow_rsp.427920833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.1492703949 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 777946615 ps |
| CPU time | 34.68 seconds |
| Started | Sep 11 09:03:44 PM UTC 24 |
| Finished | Sep 11 09:04:20 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492703949 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_addr.1492703949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.704956899 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 1330785687 ps |
| CPU time | 61.11 seconds |
| Started | Sep 11 09:03:40 PM UTC 24 |
| Finished | Sep 11 09:04:44 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704956899 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.704956899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/81.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.1131328971 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 923311349 ps |
| CPU time | 34.99 seconds |
| Started | Sep 11 09:03:19 PM UTC 24 |
| Finished | Sep 11 09:03:55 PM UTC 24 |
| Peak memory | 595984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131328971 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.1131328971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/81.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_large_delays.1975316873 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 14327134169 ps |
| CPU time | 127.78 seconds |
| Started | Sep 11 09:03:29 PM UTC 24 |
| Finished | Sep 11 09:05:39 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975316873 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.1975316873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/81.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_slow_rsp.4144472694 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 30653520069 ps |
| CPU time | 412.42 seconds |
| Started | Sep 11 09:03:35 PM UTC 24 |
| Finished | Sep 11 09:10:34 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144472694 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.4144472694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/81.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.726966841 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 126006891 ps |
| CPU time | 16.88 seconds |
| Started | Sep 11 09:03:23 PM UTC 24 |
| Finished | Sep 11 09:03:41 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726966841 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_delays.726966841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/81.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.3479013435 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 1906173011 ps |
| CPU time | 50.36 seconds |
| Started | Sep 11 09:03:38 PM UTC 24 |
| Finished | Sep 11 09:04:30 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479013435 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.3479013435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/81.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.238356238 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 43838215 ps |
| CPU time | 8.72 seconds |
| Started | Sep 11 09:03:05 PM UTC 24 |
| Finished | Sep 11 09:03:15 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238356238 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.238356238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/81.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.533894509 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 8583244720 ps |
| CPU time | 85.47 seconds |
| Started | Sep 11 09:03:09 PM UTC 24 |
| Finished | Sep 11 09:04:37 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533894509 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.533894509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/81.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.1519596578 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 4815079621 ps |
| CPU time | 69.12 seconds |
| Started | Sep 11 09:03:12 PM UTC 24 |
| Finished | Sep 11 09:04:23 PM UTC 24 |
| Peak memory | 593788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519596578 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.1519596578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.3986335451 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 57041993 ps |
| CPU time | 9.62 seconds |
| Started | Sep 11 09:03:06 PM UTC 24 |
| Finished | Sep 11 09:03:16 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986335451 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delays.3986335451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/81.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.3249949413 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 10008142803 ps |
| CPU time | 338.26 seconds |
| Started | Sep 11 09:03:50 PM UTC 24 |
| Finished | Sep 11 09:09:33 PM UTC 24 |
| Peak memory | 596152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249949413 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.3249949413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/81.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.1452195501 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 17862329211 ps |
| CPU time | 620.51 seconds |
| Started | Sep 11 09:03:52 PM UTC 24 |
| Finished | Sep 11 09:14:21 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452195501 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.1452195501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/81.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.3396709812 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 6475006501 ps |
| CPU time | 563.37 seconds |
| Started | Sep 11 09:03:48 PM UTC 24 |
| Finished | Sep 11 09:13:20 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396709812 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_rand_reset.3396709812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.3860228368 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 3772911543 ps |
| CPU time | 366.26 seconds |
| Started | Sep 11 09:04:01 PM UTC 24 |
| Finished | Sep 11 09:10:12 PM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860228368 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_reset_error.3860228368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.4088103785 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 308179582 ps |
| CPU time | 36.98 seconds |
| Started | Sep 11 09:03:39 PM UTC 24 |
| Finished | Sep 11 09:04:18 PM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088103785 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.4088103785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/81.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.189553641 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 928275034 ps |
| CPU time | 47.48 seconds |
| Started | Sep 11 09:04:38 PM UTC 24 |
| Finished | Sep 11 09:05:27 PM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189553641 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device.189553641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/82.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.2164393534 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 42128445515 ps |
| CPU time | 636.9 seconds |
| Started | Sep 11 09:04:41 PM UTC 24 |
| Finished | Sep 11 09:15:26 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164393534 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device_slow_rsp.2164393534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.2273617658 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 232407559 ps |
| CPU time | 26.39 seconds |
| Started | Sep 11 09:04:46 PM UTC 24 |
| Finished | Sep 11 09:05:14 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273617658 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_addr.2273617658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.3973244178 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 2384925479 ps |
| CPU time | 77.01 seconds |
| Started | Sep 11 09:04:44 PM UTC 24 |
| Finished | Sep 11 09:06:03 PM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973244178 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.3973244178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/82.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.2465606856 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 133948241 ps |
| CPU time | 13.85 seconds |
| Started | Sep 11 09:04:18 PM UTC 24 |
| Finished | Sep 11 09:04:33 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465606856 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.2465606856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/82.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_large_delays.713488608 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 92533290757 ps |
| CPU time | 1085.45 seconds |
| Started | Sep 11 09:04:36 PM UTC 24 |
| Finished | Sep 11 09:22:55 PM UTC 24 |
| Peak memory | 595756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713488608 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.713488608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/82.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_slow_rsp.805662793 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 5758244887 ps |
| CPU time | 127.11 seconds |
| Started | Sep 11 09:04:36 PM UTC 24 |
| Finished | Sep 11 09:06:46 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805662793 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.805662793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/82.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.483975044 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 268890552 ps |
| CPU time | 23.31 seconds |
| Started | Sep 11 09:04:26 PM UTC 24 |
| Finished | Sep 11 09:04:50 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483975044 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_delays.483975044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/82.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.1675049092 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 2123210503 ps |
| CPU time | 55.71 seconds |
| Started | Sep 11 09:04:38 PM UTC 24 |
| Finished | Sep 11 09:05:35 PM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675049092 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.1675049092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/82.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.521204326 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 256618878 ps |
| CPU time | 14.94 seconds |
| Started | Sep 11 09:03:59 PM UTC 24 |
| Finished | Sep 11 09:04:16 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521204326 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.521204326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/82.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.2605617514 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 9069692850 ps |
| CPU time | 84.67 seconds |
| Started | Sep 11 09:04:07 PM UTC 24 |
| Finished | Sep 11 09:05:34 PM UTC 24 |
| Peak memory | 593900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605617514 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.2605617514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/82.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.1497653973 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 6753491648 ps |
| CPU time | 93.74 seconds |
| Started | Sep 11 09:04:11 PM UTC 24 |
| Finished | Sep 11 09:05:47 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497653973 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.1497653973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.1254008641 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 54633372 ps |
| CPU time | 9.59 seconds |
| Started | Sep 11 09:04:06 PM UTC 24 |
| Finished | Sep 11 09:04:17 PM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254008641 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delays.1254008641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/82.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.2760767444 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 3043185431 ps |
| CPU time | 97.84 seconds |
| Started | Sep 11 09:04:54 PM UTC 24 |
| Finished | Sep 11 09:06:34 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760767444 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.2760767444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/82.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.3356118519 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 2922133020 ps |
| CPU time | 95.88 seconds |
| Started | Sep 11 09:04:55 PM UTC 24 |
| Finished | Sep 11 09:06:33 PM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356118519 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.3356118519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/82.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.2857354069 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 95799088 ps |
| CPU time | 26.17 seconds |
| Started | Sep 11 09:04:56 PM UTC 24 |
| Finished | Sep 11 09:05:24 PM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857354069 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_rand_reset.2857354069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.3057912443 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 352483433 ps |
| CPU time | 54.12 seconds |
| Started | Sep 11 09:05:02 PM UTC 24 |
| Finished | Sep 11 09:05:58 PM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057912443 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_reset_error.3057912443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.2098445608 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 1000323780 ps |
| CPU time | 34.8 seconds |
| Started | Sep 11 09:04:38 PM UTC 24 |
| Finished | Sep 11 09:05:14 PM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098445608 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.2098445608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/82.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.1135345329 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 1435860268 ps |
| CPU time | 70.22 seconds |
| Started | Sep 11 09:05:47 PM UTC 24 |
| Finished | Sep 11 09:07:00 PM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135345329 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device.1135345329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/83.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.3657562783 |
| Short name | T2916 |
| Test name | |
| Test status | |
| Simulation time | 121297358408 ps |
| CPU time | 1711.6 seconds |
| Started | Sep 11 09:05:46 PM UTC 24 |
| Finished | Sep 11 09:34:37 PM UTC 24 |
| Peak memory | 598936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657562783 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device_slow_rsp.3657562783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.4106755106 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 337222429 ps |
| CPU time | 32.56 seconds |
| Started | Sep 11 09:05:57 PM UTC 24 |
| Finished | Sep 11 09:06:31 PM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106755106 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_addr.4106755106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.3461018852 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 1852051794 ps |
| CPU time | 57.85 seconds |
| Started | Sep 11 09:05:50 PM UTC 24 |
| Finished | Sep 11 09:06:50 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461018852 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.3461018852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/83.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.3583951011 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 463240831 ps |
| CPU time | 16.57 seconds |
| Started | Sep 11 09:05:37 PM UTC 24 |
| Finished | Sep 11 09:05:55 PM UTC 24 |
| Peak memory | 595980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583951011 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.3583951011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/83.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_large_delays.1265801464 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 34915706878 ps |
| CPU time | 319.13 seconds |
| Started | Sep 11 09:05:38 PM UTC 24 |
| Finished | Sep 11 09:11:01 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265801464 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.1265801464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/83.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_slow_rsp.751736230 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 25113879542 ps |
| CPU time | 355.93 seconds |
| Started | Sep 11 09:05:41 PM UTC 24 |
| Finished | Sep 11 09:11:41 PM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751736230 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.751736230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/83.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.2444849543 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 558713458 ps |
| CPU time | 53.25 seconds |
| Started | Sep 11 09:05:36 PM UTC 24 |
| Finished | Sep 11 09:06:31 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444849543 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_delays.2444849543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/83.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.1303500065 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 69792010 ps |
| CPU time | 11.34 seconds |
| Started | Sep 11 09:05:50 PM UTC 24 |
| Finished | Sep 11 09:06:03 PM UTC 24 |
| Peak memory | 595884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303500065 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.1303500065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/83.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.1306522983 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 51521095 ps |
| CPU time | 9.13 seconds |
| Started | Sep 11 09:05:02 PM UTC 24 |
| Finished | Sep 11 09:05:12 PM UTC 24 |
| Peak memory | 593904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306522983 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.1306522983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/83.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.2708040496 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 8025663897 ps |
| CPU time | 83.35 seconds |
| Started | Sep 11 09:05:17 PM UTC 24 |
| Finished | Sep 11 09:06:42 PM UTC 24 |
| Peak memory | 593704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708040496 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.2708040496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/83.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.399139160 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 4929430006 ps |
| CPU time | 80.34 seconds |
| Started | Sep 11 09:05:31 PM UTC 24 |
| Finished | Sep 11 09:06:53 PM UTC 24 |
| Peak memory | 593956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399139160 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.399139160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.856803066 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 42602208 ps |
| CPU time | 8.82 seconds |
| Started | Sep 11 09:05:09 PM UTC 24 |
| Finished | Sep 11 09:05:19 PM UTC 24 |
| Peak memory | 593900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856803066 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delays.856803066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/83.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.3900422493 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 152177854 ps |
| CPU time | 20.55 seconds |
| Started | Sep 11 09:06:04 PM UTC 24 |
| Finished | Sep 11 09:06:26 PM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900422493 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.3900422493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/83.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.3935319353 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 12054073906 ps |
| CPU time | 390.69 seconds |
| Started | Sep 11 09:06:15 PM UTC 24 |
| Finished | Sep 11 09:12:52 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935319353 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.3935319353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/83.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.1514141966 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 657568712 ps |
| CPU time | 311.54 seconds |
| Started | Sep 11 09:06:13 PM UTC 24 |
| Finished | Sep 11 09:11:29 PM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514141966 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_rand_reset.1514141966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3277908938 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 99773987 ps |
| CPU time | 40.14 seconds |
| Started | Sep 11 09:06:21 PM UTC 24 |
| Finished | Sep 11 09:07:02 PM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277908938 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_reset_error.3277908938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.3823604138 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 194901775 ps |
| CPU time | 14.95 seconds |
| Started | Sep 11 09:05:58 PM UTC 24 |
| Finished | Sep 11 09:06:15 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823604138 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.3823604138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/83.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.3116638998 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 2663319917 ps |
| CPU time | 90.87 seconds |
| Started | Sep 11 09:06:56 PM UTC 24 |
| Finished | Sep 11 09:08:29 PM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116638998 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device.3116638998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/84.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.2075392336 |
| Short name | T2909 |
| Test name | |
| Test status | |
| Simulation time | 92050217636 ps |
| CPU time | 1375.47 seconds |
| Started | Sep 11 09:06:57 PM UTC 24 |
| Finished | Sep 11 09:30:09 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075392336 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device_slow_rsp.2075392336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.2386044320 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 624546316 ps |
| CPU time | 24.38 seconds |
| Started | Sep 11 09:07:04 PM UTC 24 |
| Finished | Sep 11 09:07:29 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386044320 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_addr.2386044320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.3260784203 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 171669294 ps |
| CPU time | 15.2 seconds |
| Started | Sep 11 09:07:00 PM UTC 24 |
| Finished | Sep 11 09:07:16 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260784203 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.3260784203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/84.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.322738272 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 1470462120 ps |
| CPU time | 63.5 seconds |
| Started | Sep 11 09:06:40 PM UTC 24 |
| Finished | Sep 11 09:07:45 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322738272 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.322738272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/84.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_large_delays.3617282402 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 46171906311 ps |
| CPU time | 463.77 seconds |
| Started | Sep 11 09:06:52 PM UTC 24 |
| Finished | Sep 11 09:14:41 PM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617282402 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.3617282402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/84.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_slow_rsp.4040806185 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 36343117648 ps |
| CPU time | 552.26 seconds |
| Started | Sep 11 09:06:55 PM UTC 24 |
| Finished | Sep 11 09:16:15 PM UTC 24 |
| Peak memory | 596180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040806185 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.4040806185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/84.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.2344738658 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 36953126 ps |
| CPU time | 7.73 seconds |
| Started | Sep 11 09:06:42 PM UTC 24 |
| Finished | Sep 11 09:06:51 PM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344738658 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_delays.2344738658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/84.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.2621623419 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 530444915 ps |
| CPU time | 34.7 seconds |
| Started | Sep 11 09:07:00 PM UTC 24 |
| Finished | Sep 11 09:07:36 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621623419 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.2621623419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/84.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.699222261 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 43649301 ps |
| CPU time | 8.58 seconds |
| Started | Sep 11 09:06:23 PM UTC 24 |
| Finished | Sep 11 09:06:33 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699222261 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.699222261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/84.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.2017230733 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 6025844095 ps |
| CPU time | 88.14 seconds |
| Started | Sep 11 09:06:30 PM UTC 24 |
| Finished | Sep 11 09:08:01 PM UTC 24 |
| Peak memory | 593704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017230733 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.2017230733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/84.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.2300280431 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 5342273535 ps |
| CPU time | 75 seconds |
| Started | Sep 11 09:06:40 PM UTC 24 |
| Finished | Sep 11 09:07:57 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300280431 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.2300280431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.1151482159 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 39269765 ps |
| CPU time | 8.39 seconds |
| Started | Sep 11 09:06:28 PM UTC 24 |
| Finished | Sep 11 09:06:37 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151482159 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delays.1151482159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/84.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.2849653197 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 9183818453 ps |
| CPU time | 302.99 seconds |
| Started | Sep 11 09:07:08 PM UTC 24 |
| Finished | Sep 11 09:12:15 PM UTC 24 |
| Peak memory | 596036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849653197 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.2849653197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/84.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.2721928723 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 3200167271 ps |
| CPU time | 112.29 seconds |
| Started | Sep 11 09:07:11 PM UTC 24 |
| Finished | Sep 11 09:09:06 PM UTC 24 |
| Peak memory | 596148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721928723 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.2721928723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/84.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.2612174242 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 7961886308 ps |
| CPU time | 294.21 seconds |
| Started | Sep 11 09:07:09 PM UTC 24 |
| Finished | Sep 11 09:12:08 PM UTC 24 |
| Peak memory | 596120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612174242 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_rand_reset.2612174242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.1910579639 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 5183766137 ps |
| CPU time | 433.45 seconds |
| Started | Sep 11 09:07:13 PM UTC 24 |
| Finished | Sep 11 09:14:32 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910579639 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_reset_error.1910579639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.45744514 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 1283120931 ps |
| CPU time | 47.01 seconds |
| Started | Sep 11 09:07:04 PM UTC 24 |
| Finished | Sep 11 09:07:53 PM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45744514 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.45744514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/84.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.4239391553 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 1080910775 ps |
| CPU time | 54.64 seconds |
| Started | Sep 11 09:07:50 PM UTC 24 |
| Finished | Sep 11 09:08:47 PM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239391553 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device.4239391553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/85.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.207673115 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 52390411322 ps |
| CPU time | 833.43 seconds |
| Started | Sep 11 09:07:55 PM UTC 24 |
| Finished | Sep 11 09:21:59 PM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207673115 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device_slow_rsp.207673115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.2068589579 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 76909606 ps |
| CPU time | 8.89 seconds |
| Started | Sep 11 09:08:14 PM UTC 24 |
| Finished | Sep 11 09:08:25 PM UTC 24 |
| Peak memory | 593804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068589579 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_addr.2068589579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.3348390281 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 418202859 ps |
| CPU time | 32.76 seconds |
| Started | Sep 11 09:08:06 PM UTC 24 |
| Finished | Sep 11 09:08:40 PM UTC 24 |
| Peak memory | 596136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348390281 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.3348390281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/85.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.4195467715 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 1067622836 ps |
| CPU time | 42.92 seconds |
| Started | Sep 11 09:07:25 PM UTC 24 |
| Finished | Sep 11 09:08:10 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195467715 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.4195467715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/85.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_large_delays.2480815418 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 30701358153 ps |
| CPU time | 269.14 seconds |
| Started | Sep 11 09:07:42 PM UTC 24 |
| Finished | Sep 11 09:12:15 PM UTC 24 |
| Peak memory | 595756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480815418 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.2480815418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/85.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_slow_rsp.1552453069 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 52769428695 ps |
| CPU time | 690.98 seconds |
| Started | Sep 11 09:07:46 PM UTC 24 |
| Finished | Sep 11 09:19:25 PM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552453069 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.1552453069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/85.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.384998224 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 219825139 ps |
| CPU time | 25.65 seconds |
| Started | Sep 11 09:07:28 PM UTC 24 |
| Finished | Sep 11 09:07:55 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384998224 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_delays.384998224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/85.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.3029471929 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 721323162 ps |
| CPU time | 21.68 seconds |
| Started | Sep 11 09:08:01 PM UTC 24 |
| Finished | Sep 11 09:08:24 PM UTC 24 |
| Peak memory | 596140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029471929 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.3029471929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/85.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.3491223365 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 47144924 ps |
| CPU time | 9.09 seconds |
| Started | Sep 11 09:07:14 PM UTC 24 |
| Finished | Sep 11 09:07:25 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491223365 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.3491223365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/85.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.2297691729 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 4904367518 ps |
| CPU time | 46.89 seconds |
| Started | Sep 11 09:07:19 PM UTC 24 |
| Finished | Sep 11 09:08:07 PM UTC 24 |
| Peak memory | 594140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297691729 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.2297691729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/85.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.844014313 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 5874857306 ps |
| CPU time | 78.02 seconds |
| Started | Sep 11 09:07:24 PM UTC 24 |
| Finished | Sep 11 09:08:44 PM UTC 24 |
| Peak memory | 593908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844014313 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.844014313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.3140706806 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 39864628 ps |
| CPU time | 5.59 seconds |
| Started | Sep 11 09:07:15 PM UTC 24 |
| Finished | Sep 11 09:07:21 PM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140706806 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delays.3140706806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/85.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all.4294707745 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 12318063506 ps |
| CPU time | 408.29 seconds |
| Started | Sep 11 09:08:17 PM UTC 24 |
| Finished | Sep 11 09:15:12 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294707745 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.4294707745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/85.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_error.273987304 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 8404620140 ps |
| CPU time | 251.2 seconds |
| Started | Sep 11 09:08:21 PM UTC 24 |
| Finished | Sep 11 09:12:36 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273987304 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.273987304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/85.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.2466273630 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 996848571 ps |
| CPU time | 268.75 seconds |
| Started | Sep 11 09:08:18 PM UTC 24 |
| Finished | Sep 11 09:12:51 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466273630 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_rand_reset.2466273630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.3570301457 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 15031846138 ps |
| CPU time | 770.54 seconds |
| Started | Sep 11 09:08:21 PM UTC 24 |
| Finished | Sep 11 09:21:22 PM UTC 24 |
| Peak memory | 599992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570301457 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_reset_error.3570301457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.3297032371 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 558339329 ps |
| CPU time | 28.34 seconds |
| Started | Sep 11 09:08:07 PM UTC 24 |
| Finished | Sep 11 09:08:37 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297032371 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.3297032371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/85.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.949152829 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 230616765 ps |
| CPU time | 13.72 seconds |
| Started | Sep 11 09:09:06 PM UTC 24 |
| Finished | Sep 11 09:09:21 PM UTC 24 |
| Peak memory | 593656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949152829 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device.949152829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/86.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.285300926 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 58668640050 ps |
| CPU time | 900.29 seconds |
| Started | Sep 11 09:09:05 PM UTC 24 |
| Finished | Sep 11 09:24:17 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285300926 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device_slow_rsp.285300926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.219618989 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 297892023 ps |
| CPU time | 39.07 seconds |
| Started | Sep 11 09:09:10 PM UTC 24 |
| Finished | Sep 11 09:09:51 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219618989 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_addr.219618989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.3609442432 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 405354692 ps |
| CPU time | 18.8 seconds |
| Started | Sep 11 09:09:07 PM UTC 24 |
| Finished | Sep 11 09:09:27 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609442432 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.3609442432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/86.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.3045966571 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 533898330 ps |
| CPU time | 43.21 seconds |
| Started | Sep 11 09:08:53 PM UTC 24 |
| Finished | Sep 11 09:09:37 PM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045966571 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.3045966571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/86.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_large_delays.2424969736 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 77515206327 ps |
| CPU time | 755.83 seconds |
| Started | Sep 11 09:09:00 PM UTC 24 |
| Finished | Sep 11 09:21:45 PM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424969736 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.2424969736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/86.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_slow_rsp.2988394681 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 64006507572 ps |
| CPU time | 1044.91 seconds |
| Started | Sep 11 09:09:00 PM UTC 24 |
| Finished | Sep 11 09:26:38 PM UTC 24 |
| Peak memory | 596136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988394681 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.2988394681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/86.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.1997177877 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 314022432 ps |
| CPU time | 33.62 seconds |
| Started | Sep 11 09:08:56 PM UTC 24 |
| Finished | Sep 11 09:09:31 PM UTC 24 |
| Peak memory | 596088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997177877 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_delays.1997177877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/86.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.1156690271 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 250019455 ps |
| CPU time | 20.43 seconds |
| Started | Sep 11 09:09:05 PM UTC 24 |
| Finished | Sep 11 09:09:27 PM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156690271 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.1156690271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/86.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.2149654341 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 163976529 ps |
| CPU time | 11.44 seconds |
| Started | Sep 11 09:08:31 PM UTC 24 |
| Finished | Sep 11 09:08:44 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149654341 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.2149654341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/86.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.3166764663 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 10204074340 ps |
| CPU time | 137.17 seconds |
| Started | Sep 11 09:08:51 PM UTC 24 |
| Finished | Sep 11 09:11:11 PM UTC 24 |
| Peak memory | 594164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166764663 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.3166764663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/86.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.2875491603 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 5398373076 ps |
| CPU time | 107.91 seconds |
| Started | Sep 11 09:08:49 PM UTC 24 |
| Finished | Sep 11 09:10:39 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875491603 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.2875491603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.1973151990 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 46930605 ps |
| CPU time | 7.01 seconds |
| Started | Sep 11 09:08:35 PM UTC 24 |
| Finished | Sep 11 09:08:43 PM UTC 24 |
| Peak memory | 593984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973151990 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delays.1973151990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/86.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.3184583299 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 8226061336 ps |
| CPU time | 286.65 seconds |
| Started | Sep 11 09:09:15 PM UTC 24 |
| Finished | Sep 11 09:14:06 PM UTC 24 |
| Peak memory | 596032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184583299 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.3184583299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/86.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_error.1947756200 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 17276941369 ps |
| CPU time | 575.66 seconds |
| Started | Sep 11 09:09:31 PM UTC 24 |
| Finished | Sep 11 09:19:15 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947756200 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.1947756200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/86.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.2709227786 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 4000525903 ps |
| CPU time | 301.24 seconds |
| Started | Sep 11 09:09:15 PM UTC 24 |
| Finished | Sep 11 09:14:21 PM UTC 24 |
| Peak memory | 595984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709227786 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_rand_reset.2709227786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.3975877363 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 222299860 ps |
| CPU time | 54.4 seconds |
| Started | Sep 11 09:09:43 PM UTC 24 |
| Finished | Sep 11 09:10:39 PM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975877363 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_reset_error.3975877363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.826579821 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 166404591 ps |
| CPU time | 14.96 seconds |
| Started | Sep 11 09:09:06 PM UTC 24 |
| Finished | Sep 11 09:09:22 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826579821 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.826579821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/86.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.1901018752 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 367536104 ps |
| CPU time | 39.32 seconds |
| Started | Sep 11 09:10:13 PM UTC 24 |
| Finished | Sep 11 09:10:53 PM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901018752 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device.1901018752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/87.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2135902609 |
| Short name | T2904 |
| Test name | |
| Test status | |
| Simulation time | 63978894665 ps |
| CPU time | 1084.89 seconds |
| Started | Sep 11 09:10:17 PM UTC 24 |
| Finished | Sep 11 09:28:35 PM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135902609 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device_slow_rsp.2135902609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.1412114890 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 381125241 ps |
| CPU time | 22.34 seconds |
| Started | Sep 11 09:10:39 PM UTC 24 |
| Finished | Sep 11 09:11:03 PM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412114890 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_addr.1412114890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.2027510230 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 485379404 ps |
| CPU time | 34.16 seconds |
| Started | Sep 11 09:10:22 PM UTC 24 |
| Finished | Sep 11 09:10:58 PM UTC 24 |
| Peak memory | 595940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027510230 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.2027510230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/87.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.3744605001 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 870088353 ps |
| CPU time | 28.22 seconds |
| Started | Sep 11 09:09:55 PM UTC 24 |
| Finished | Sep 11 09:10:24 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744605001 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.3744605001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/87.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_large_delays.3591653226 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 65380807746 ps |
| CPU time | 642.44 seconds |
| Started | Sep 11 09:10:02 PM UTC 24 |
| Finished | Sep 11 09:20:53 PM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591653226 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.3591653226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/87.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_slow_rsp.3839046165 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 69211098899 ps |
| CPU time | 933.1 seconds |
| Started | Sep 11 09:10:07 PM UTC 24 |
| Finished | Sep 11 09:25:51 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839046165 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.3839046165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/87.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.3540920723 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 226770505 ps |
| CPU time | 19.11 seconds |
| Started | Sep 11 09:09:59 PM UTC 24 |
| Finished | Sep 11 09:10:19 PM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540920723 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_delays.3540920723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/87.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.216746168 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 837222318 ps |
| CPU time | 36.05 seconds |
| Started | Sep 11 09:10:23 PM UTC 24 |
| Finished | Sep 11 09:11:00 PM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216746168 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.216746168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/87.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.2705820853 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 146281911 ps |
| CPU time | 11.02 seconds |
| Started | Sep 11 09:09:47 PM UTC 24 |
| Finished | Sep 11 09:10:00 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705820853 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.2705820853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/87.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.3198440631 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 7159099037 ps |
| CPU time | 99.62 seconds |
| Started | Sep 11 09:09:51 PM UTC 24 |
| Finished | Sep 11 09:11:32 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198440631 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.3198440631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/87.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.817508470 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 5104907803 ps |
| CPU time | 107.02 seconds |
| Started | Sep 11 09:09:55 PM UTC 24 |
| Finished | Sep 11 09:11:44 PM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817508470 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.817508470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.2355154335 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 40057200 ps |
| CPU time | 6.74 seconds |
| Started | Sep 11 09:09:49 PM UTC 24 |
| Finished | Sep 11 09:09:57 PM UTC 24 |
| Peak memory | 591752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355154335 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delays.2355154335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/87.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all.2724399429 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 1314915197 ps |
| CPU time | 115.13 seconds |
| Started | Sep 11 09:10:45 PM UTC 24 |
| Finished | Sep 11 09:12:43 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724399429 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.2724399429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/87.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_error.3982950409 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 15985107078 ps |
| CPU time | 517.15 seconds |
| Started | Sep 11 09:10:58 PM UTC 24 |
| Finished | Sep 11 09:19:42 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982950409 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.3982950409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/87.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.1421707542 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 703802320 ps |
| CPU time | 254.69 seconds |
| Started | Sep 11 09:10:47 PM UTC 24 |
| Finished | Sep 11 09:15:06 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421707542 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_rand_reset.1421707542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3960486962 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 9740098902 ps |
| CPU time | 399.24 seconds |
| Started | Sep 11 09:10:59 PM UTC 24 |
| Finished | Sep 11 09:17:44 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960486962 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_reset_error.3960486962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.1912293956 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 958953253 ps |
| CPU time | 55.18 seconds |
| Started | Sep 11 09:10:26 PM UTC 24 |
| Finished | Sep 11 09:11:23 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912293956 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.1912293956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/87.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.2627132639 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 2525406753 ps |
| CPU time | 94.44 seconds |
| Started | Sep 11 09:11:37 PM UTC 24 |
| Finished | Sep 11 09:13:14 PM UTC 24 |
| Peak memory | 596004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627132639 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device.2627132639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/88.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.469613321 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 47761078692 ps |
| CPU time | 684.38 seconds |
| Started | Sep 11 09:11:41 PM UTC 24 |
| Finished | Sep 11 09:23:14 PM UTC 24 |
| Peak memory | 596052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469613321 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device_slow_rsp.469613321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.3316764841 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 88934427 ps |
| CPU time | 11.58 seconds |
| Started | Sep 11 09:11:56 PM UTC 24 |
| Finished | Sep 11 09:12:09 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316764841 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_addr.3316764841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.1891141008 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 1264451036 ps |
| CPU time | 39.35 seconds |
| Started | Sep 11 09:11:48 PM UTC 24 |
| Finished | Sep 11 09:12:29 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891141008 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.1891141008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/88.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.112103095 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 2538869348 ps |
| CPU time | 82.74 seconds |
| Started | Sep 11 09:11:26 PM UTC 24 |
| Finished | Sep 11 09:12:51 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112103095 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.112103095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/88.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_large_delays.131819473 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 70342716367 ps |
| CPU time | 805 seconds |
| Started | Sep 11 09:11:30 PM UTC 24 |
| Finished | Sep 11 09:25:04 PM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131819473 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.131819473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/88.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_slow_rsp.4073645892 |
| Short name | T2903 |
| Test name | |
| Test status | |
| Simulation time | 67082195431 ps |
| CPU time | 1003.36 seconds |
| Started | Sep 11 09:11:36 PM UTC 24 |
| Finished | Sep 11 09:28:32 PM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073645892 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.4073645892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/88.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.31648832 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 611461639 ps |
| CPU time | 53.4 seconds |
| Started | Sep 11 09:11:25 PM UTC 24 |
| Finished | Sep 11 09:12:21 PM UTC 24 |
| Peak memory | 596056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31648832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_delays.31648832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/88.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.1259832953 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 366110553 ps |
| CPU time | 13.72 seconds |
| Started | Sep 11 09:11:41 PM UTC 24 |
| Finished | Sep 11 09:11:56 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259832953 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.1259832953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/88.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.3012037702 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 59729867 ps |
| CPU time | 10.02 seconds |
| Started | Sep 11 09:11:05 PM UTC 24 |
| Finished | Sep 11 09:11:16 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012037702 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.3012037702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/88.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.2107009239 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 6150942744 ps |
| CPU time | 66.35 seconds |
| Started | Sep 11 09:11:19 PM UTC 24 |
| Finished | Sep 11 09:12:27 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107009239 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.2107009239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/88.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.409185228 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 6492371348 ps |
| CPU time | 91.02 seconds |
| Started | Sep 11 09:11:24 PM UTC 24 |
| Finished | Sep 11 09:12:57 PM UTC 24 |
| Peak memory | 594144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409185228 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.409185228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.3910557030 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 41244719 ps |
| CPU time | 8.57 seconds |
| Started | Sep 11 09:11:05 PM UTC 24 |
| Finished | Sep 11 09:11:15 PM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910557030 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delays.3910557030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/88.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all.1398861392 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 6324797553 ps |
| CPU time | 228.25 seconds |
| Started | Sep 11 09:11:55 PM UTC 24 |
| Finished | Sep 11 09:15:46 PM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398861392 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.1398861392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/88.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_error.796207683 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 10746478407 ps |
| CPU time | 308.57 seconds |
| Started | Sep 11 09:12:05 PM UTC 24 |
| Finished | Sep 11 09:17:18 PM UTC 24 |
| Peak memory | 596000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796207683 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.796207683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/88.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.2179521632 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 2198404923 ps |
| CPU time | 407.56 seconds |
| Started | Sep 11 09:11:57 PM UTC 24 |
| Finished | Sep 11 09:18:50 PM UTC 24 |
| Peak memory | 595984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179521632 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_rand_reset.2179521632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.2161087453 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 48792458 ps |
| CPU time | 28.35 seconds |
| Started | Sep 11 09:12:06 PM UTC 24 |
| Finished | Sep 11 09:12:36 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161087453 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_reset_error.2161087453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.3344364855 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 216063061 ps |
| CPU time | 29.32 seconds |
| Started | Sep 11 09:11:54 PM UTC 24 |
| Finished | Sep 11 09:12:25 PM UTC 24 |
| Peak memory | 595964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344364855 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.3344364855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/88.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.955834346 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 709148572 ps |
| CPU time | 55.12 seconds |
| Started | Sep 11 09:12:49 PM UTC 24 |
| Finished | Sep 11 09:13:46 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955834346 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device.955834346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/89.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.1203917453 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 46407378083 ps |
| CPU time | 684.92 seconds |
| Started | Sep 11 09:12:52 PM UTC 24 |
| Finished | Sep 11 09:24:26 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203917453 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device_slow_rsp.1203917453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.1640168473 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 209877097 ps |
| CPU time | 29.16 seconds |
| Started | Sep 11 09:13:01 PM UTC 24 |
| Finished | Sep 11 09:13:32 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640168473 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_addr.1640168473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.1186725838 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 202533394 ps |
| CPU time | 18.61 seconds |
| Started | Sep 11 09:12:57 PM UTC 24 |
| Finished | Sep 11 09:13:17 PM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186725838 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.1186725838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/89.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.2930726900 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 306510360 ps |
| CPU time | 30.45 seconds |
| Started | Sep 11 09:12:37 PM UTC 24 |
| Finished | Sep 11 09:13:09 PM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930726900 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.2930726900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/89.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_large_delays.2860079366 |
| Short name | T2911 |
| Test name | |
| Test status | |
| Simulation time | 99872548803 ps |
| CPU time | 1062.96 seconds |
| Started | Sep 11 09:12:46 PM UTC 24 |
| Finished | Sep 11 09:30:41 PM UTC 24 |
| Peak memory | 596096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860079366 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.2860079366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/89.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_slow_rsp.2024995480 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 55986432630 ps |
| CPU time | 806.5 seconds |
| Started | Sep 11 09:12:47 PM UTC 24 |
| Finished | Sep 11 09:26:23 PM UTC 24 |
| Peak memory | 596168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024995480 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.2024995480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/89.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.2983023215 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 125724428 ps |
| CPU time | 11.55 seconds |
| Started | Sep 11 09:12:41 PM UTC 24 |
| Finished | Sep 11 09:12:53 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983023215 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_delays.2983023215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/89.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.3127599612 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 1766735792 ps |
| CPU time | 46.19 seconds |
| Started | Sep 11 09:12:55 PM UTC 24 |
| Finished | Sep 11 09:13:42 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127599612 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.3127599612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/89.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.997582305 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 39477180 ps |
| CPU time | 8.81 seconds |
| Started | Sep 11 09:12:09 PM UTC 24 |
| Finished | Sep 11 09:12:19 PM UTC 24 |
| Peak memory | 593636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997582305 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.997582305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/89.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.4254562439 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 9478062373 ps |
| CPU time | 101.72 seconds |
| Started | Sep 11 09:12:33 PM UTC 24 |
| Finished | Sep 11 09:14:17 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254562439 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.4254562439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/89.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.3230131313 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 4003818952 ps |
| CPU time | 83.39 seconds |
| Started | Sep 11 09:12:33 PM UTC 24 |
| Finished | Sep 11 09:13:59 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230131313 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.3230131313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.2707011076 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 52773031 ps |
| CPU time | 8.81 seconds |
| Started | Sep 11 09:12:22 PM UTC 24 |
| Finished | Sep 11 09:12:32 PM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707011076 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delays.2707011076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/89.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all.3421415849 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 4999497602 ps |
| CPU time | 147.37 seconds |
| Started | Sep 11 09:13:04 PM UTC 24 |
| Finished | Sep 11 09:15:35 PM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421415849 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.3421415849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/89.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_error.3763220019 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 11157486351 ps |
| CPU time | 310.43 seconds |
| Started | Sep 11 09:13:12 PM UTC 24 |
| Finished | Sep 11 09:18:27 PM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763220019 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.3763220019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/89.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.2969707106 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 564487248 ps |
| CPU time | 220.32 seconds |
| Started | Sep 11 09:13:14 PM UTC 24 |
| Finished | Sep 11 09:16:58 PM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969707106 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_rand_reset.2969707106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.2640572400 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 285499498 ps |
| CPU time | 116.43 seconds |
| Started | Sep 11 09:13:18 PM UTC 24 |
| Finished | Sep 11 09:15:17 PM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640572400 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_reset_error.2640572400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.3780259100 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 879216795 ps |
| CPU time | 46.49 seconds |
| Started | Sep 11 09:13:02 PM UTC 24 |
| Finished | Sep 11 09:13:50 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780259100 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.3780259100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/89.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.2078125600 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 13028273912 ps |
| CPU time | 1002.66 seconds |
| Started | Sep 11 07:13:56 PM UTC 24 |
| Finished | Sep 11 07:30:51 PM UTC 24 |
| Peak memory | 670448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2078125600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 9.chip_csr_mem_rw_with_rand_reset.2078125600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.1530302888 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 5594366710 ps |
| CPU time | 527.65 seconds |
| Started | Sep 11 07:13:51 PM UTC 24 |
| Finished | Sep 11 07:22:46 PM UTC 24 |
| Peak memory | 619008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530302888 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.1530302888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.200836481 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 3366145960 ps |
| CPU time | 147.38 seconds |
| Started | Sep 11 07:11:59 PM UTC 24 |
| Finished | Sep 11 07:14:29 PM UTC 24 |
| Peak memory | 616984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200836481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.200836481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.379341699 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 1426989076 ps |
| CPU time | 64.04 seconds |
| Started | Sep 11 07:12:37 PM UTC 24 |
| Finished | Sep 11 07:13:43 PM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379341699 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.379341699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2426348634 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 57435405889 ps |
| CPU time | 1052.14 seconds |
| Started | Sep 11 07:12:40 PM UTC 24 |
| Finished | Sep 11 07:30:26 PM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426348634 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.2426348634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.860198552 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 370291432 ps |
| CPU time | 23.75 seconds |
| Started | Sep 11 07:13:01 PM UTC 24 |
| Finished | Sep 11 07:13:26 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860198552 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.860198552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.2891784111 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 676435003 ps |
| CPU time | 28.59 seconds |
| Started | Sep 11 07:12:41 PM UTC 24 |
| Finished | Sep 11 07:13:12 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891784111 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2891784111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.1798677106 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 146022983 ps |
| CPU time | 7.7 seconds |
| Started | Sep 11 07:12:23 PM UTC 24 |
| Finished | Sep 11 07:12:32 PM UTC 24 |
| Peak memory | 593864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798677106 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.1798677106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.2240773342 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 18616111079 ps |
| CPU time | 197.63 seconds |
| Started | Sep 11 07:12:28 PM UTC 24 |
| Finished | Sep 11 07:15:49 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240773342 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.2240773342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.91687485 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 22688716201 ps |
| CPU time | 379.7 seconds |
| Started | Sep 11 07:12:28 PM UTC 24 |
| Finished | Sep 11 07:18:53 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91687485 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.91687485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.551955513 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 133923842 ps |
| CPU time | 13.84 seconds |
| Started | Sep 11 07:12:25 PM UTC 24 |
| Finished | Sep 11 07:12:40 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551955513 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.551955513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.296171562 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 1723144444 ps |
| CPU time | 73.79 seconds |
| Started | Sep 11 07:12:43 PM UTC 24 |
| Finished | Sep 11 07:13:59 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296171562 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.296171562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.2970888630 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 139631978 ps |
| CPU time | 10.22 seconds |
| Started | Sep 11 07:12:04 PM UTC 24 |
| Finished | Sep 11 07:12:15 PM UTC 24 |
| Peak memory | 593824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970888630 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2970888630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.3688780131 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 8142382864 ps |
| CPU time | 78.48 seconds |
| Started | Sep 11 07:12:11 PM UTC 24 |
| Finished | Sep 11 07:13:31 PM UTC 24 |
| Peak memory | 594076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688780131 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3688780131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.1923751151 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 4406528731 ps |
| CPU time | 93.88 seconds |
| Started | Sep 11 07:12:13 PM UTC 24 |
| Finished | Sep 11 07:13:49 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923751151 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1923751151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.995422009 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 40770275 ps |
| CPU time | 8.58 seconds |
| Started | Sep 11 07:12:10 PM UTC 24 |
| Finished | Sep 11 07:12:19 PM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995422009 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.995422009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.1489441161 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 5699414 ps |
| CPU time | 4.7 seconds |
| Started | Sep 11 07:13:37 PM UTC 24 |
| Finished | Sep 11 07:13:43 PM UTC 24 |
| Peak memory | 583536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489441161 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1489441161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.2126870476 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 218327331 ps |
| CPU time | 100.96 seconds |
| Started | Sep 11 07:13:21 PM UTC 24 |
| Finished | Sep 11 07:15:04 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126870476 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.2126870476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.1064722772 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 785688108 ps |
| CPU time | 387.71 seconds |
| Started | Sep 11 07:13:36 PM UTC 24 |
| Finished | Sep 11 07:20:10 PM UTC 24 |
| Peak memory | 595880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064722772 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.1064722772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.1592321132 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 306162633 ps |
| CPU time | 14.05 seconds |
| Started | Sep 11 07:12:57 PM UTC 24 |
| Finished | Sep 11 07:13:12 PM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592321132 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1592321132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.1852109580 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 3442810184 ps |
| CPU time | 132.25 seconds |
| Started | Sep 11 09:13:58 PM UTC 24 |
| Finished | Sep 11 09:16:13 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852109580 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device.1852109580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/90.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.1579885339 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 47642789546 ps |
| CPU time | 715 seconds |
| Started | Sep 11 09:14:04 PM UTC 24 |
| Finished | Sep 11 09:26:09 PM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579885339 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device_slow_rsp.1579885339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.2803920703 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 220675366 ps |
| CPU time | 13.69 seconds |
| Started | Sep 11 09:14:22 PM UTC 24 |
| Finished | Sep 11 09:14:37 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803920703 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_addr.2803920703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.2248719391 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 145311970 ps |
| CPU time | 15.14 seconds |
| Started | Sep 11 09:14:13 PM UTC 24 |
| Finished | Sep 11 09:14:29 PM UTC 24 |
| Peak memory | 596072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248719391 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.2248719391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/90.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.715228944 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 2450282739 ps |
| CPU time | 94.08 seconds |
| Started | Sep 11 09:13:43 PM UTC 24 |
| Finished | Sep 11 09:15:20 PM UTC 24 |
| Peak memory | 595984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715228944 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.715228944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/90.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_large_delays.3324355945 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 52921830040 ps |
| CPU time | 495.76 seconds |
| Started | Sep 11 09:13:54 PM UTC 24 |
| Finished | Sep 11 09:22:16 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324355945 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.3324355945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/90.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_slow_rsp.2936331437 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 4311365294 ps |
| CPU time | 71.71 seconds |
| Started | Sep 11 09:13:58 PM UTC 24 |
| Finished | Sep 11 09:15:12 PM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936331437 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.2936331437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/90.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.2956712609 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 325027242 ps |
| CPU time | 33.76 seconds |
| Started | Sep 11 09:13:46 PM UTC 24 |
| Finished | Sep 11 09:14:21 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956712609 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_delays.2956712609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/90.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.1808164060 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 429365525 ps |
| CPU time | 33.17 seconds |
| Started | Sep 11 09:14:06 PM UTC 24 |
| Finished | Sep 11 09:14:41 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808164060 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.1808164060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/90.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.2683045632 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 251095584 ps |
| CPU time | 11.89 seconds |
| Started | Sep 11 09:13:15 PM UTC 24 |
| Finished | Sep 11 09:13:28 PM UTC 24 |
| Peak memory | 593824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683045632 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.2683045632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/90.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.3972212152 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 8205253312 ps |
| CPU time | 97.65 seconds |
| Started | Sep 11 09:13:35 PM UTC 24 |
| Finished | Sep 11 09:15:15 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972212152 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.3972212152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/90.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.2083211851 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 5450969677 ps |
| CPU time | 79.2 seconds |
| Started | Sep 11 09:13:36 PM UTC 24 |
| Finished | Sep 11 09:14:57 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083211851 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.2083211851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.2653723937 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 54941314 ps |
| CPU time | 9.59 seconds |
| Started | Sep 11 09:13:22 PM UTC 24 |
| Finished | Sep 11 09:13:33 PM UTC 24 |
| Peak memory | 593652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653723937 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delays.2653723937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/90.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all.1573409523 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 3047557040 ps |
| CPU time | 251.15 seconds |
| Started | Sep 11 09:14:30 PM UTC 24 |
| Finished | Sep 11 09:18:45 PM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573409523 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.1573409523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/90.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_error.2674693579 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 984091373 ps |
| CPU time | 87.72 seconds |
| Started | Sep 11 09:14:43 PM UTC 24 |
| Finished | Sep 11 09:16:12 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674693579 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.2674693579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/90.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.627137334 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 7527832085 ps |
| CPU time | 497.2 seconds |
| Started | Sep 11 09:14:39 PM UTC 24 |
| Finished | Sep 11 09:23:02 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627137334 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_rand_reset.627137334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.1987045162 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 111534898 ps |
| CPU time | 43.62 seconds |
| Started | Sep 11 09:14:47 PM UTC 24 |
| Finished | Sep 11 09:15:32 PM UTC 24 |
| Peak memory | 596072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987045162 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_reset_error.1987045162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.2147465366 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 245482767 ps |
| CPU time | 13.58 seconds |
| Started | Sep 11 09:14:14 PM UTC 24 |
| Finished | Sep 11 09:14:29 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147465366 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.2147465366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/90.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.2484342008 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 738005503 ps |
| CPU time | 66.51 seconds |
| Started | Sep 11 09:15:17 PM UTC 24 |
| Finished | Sep 11 09:16:26 PM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484342008 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device.2484342008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/91.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.3673045917 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 43547570714 ps |
| CPU time | 603.16 seconds |
| Started | Sep 11 09:15:21 PM UTC 24 |
| Finished | Sep 11 09:25:32 PM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673045917 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device_slow_rsp.3673045917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.388863785 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 661222660 ps |
| CPU time | 34.36 seconds |
| Started | Sep 11 09:15:33 PM UTC 24 |
| Finished | Sep 11 09:16:10 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388863785 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_addr.388863785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.3129298931 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 598564554 ps |
| CPU time | 44.62 seconds |
| Started | Sep 11 09:15:31 PM UTC 24 |
| Finished | Sep 11 09:16:18 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129298931 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.3129298931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/91.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.3231622233 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 1592310654 ps |
| CPU time | 54.3 seconds |
| Started | Sep 11 09:15:00 PM UTC 24 |
| Finished | Sep 11 09:15:56 PM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231622233 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.3231622233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/91.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_large_delays.2266126611 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 28334696846 ps |
| CPU time | 240.05 seconds |
| Started | Sep 11 09:15:08 PM UTC 24 |
| Finished | Sep 11 09:19:11 PM UTC 24 |
| Peak memory | 596032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266126611 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.2266126611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/91.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_slow_rsp.223601890 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 46526852028 ps |
| CPU time | 767.9 seconds |
| Started | Sep 11 09:15:07 PM UTC 24 |
| Finished | Sep 11 09:28:04 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223601890 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.223601890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/91.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.1139383591 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 236502611 ps |
| CPU time | 23.48 seconds |
| Started | Sep 11 09:15:07 PM UTC 24 |
| Finished | Sep 11 09:15:31 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139383591 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_delays.1139383591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/91.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.1356023172 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 462641017 ps |
| CPU time | 17.83 seconds |
| Started | Sep 11 09:15:21 PM UTC 24 |
| Finished | Sep 11 09:15:41 PM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356023172 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.1356023172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/91.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.1731514206 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 37218251 ps |
| CPU time | 8.27 seconds |
| Started | Sep 11 09:14:43 PM UTC 24 |
| Finished | Sep 11 09:14:52 PM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731514206 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.1731514206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/91.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.2131891366 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 8504974030 ps |
| CPU time | 88.77 seconds |
| Started | Sep 11 09:14:54 PM UTC 24 |
| Finished | Sep 11 09:16:25 PM UTC 24 |
| Peak memory | 594076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131891366 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.2131891366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/91.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.459642836 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 5463537142 ps |
| CPU time | 94.94 seconds |
| Started | Sep 11 09:14:57 PM UTC 24 |
| Finished | Sep 11 09:16:34 PM UTC 24 |
| Peak memory | 594104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459642836 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.459642836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.3330415393 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 46450090 ps |
| CPU time | 8.82 seconds |
| Started | Sep 11 09:14:55 PM UTC 24 |
| Finished | Sep 11 09:15:05 PM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330415393 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delays.3330415393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/91.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all.202297951 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 1606682901 ps |
| CPU time | 132.47 seconds |
| Started | Sep 11 09:15:36 PM UTC 24 |
| Finished | Sep 11 09:17:51 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202297951 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.202297951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/91.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_error.2758827570 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 10154055456 ps |
| CPU time | 364.43 seconds |
| Started | Sep 11 09:15:36 PM UTC 24 |
| Finished | Sep 11 09:21:46 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758827570 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.2758827570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/91.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.2535133610 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 3487899354 ps |
| CPU time | 421.68 seconds |
| Started | Sep 11 09:15:38 PM UTC 24 |
| Finished | Sep 11 09:22:46 PM UTC 24 |
| Peak memory | 596120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535133610 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_rand_reset.2535133610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.570593872 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 647377051 ps |
| CPU time | 179.57 seconds |
| Started | Sep 11 09:15:42 PM UTC 24 |
| Finished | Sep 11 09:18:45 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570593872 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_reset_error.570593872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.1477076146 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 1422954834 ps |
| CPU time | 81.16 seconds |
| Started | Sep 11 09:15:32 PM UTC 24 |
| Finished | Sep 11 09:16:56 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477076146 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.1477076146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/91.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device.3831317965 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 431431551 ps |
| CPU time | 43.06 seconds |
| Started | Sep 11 09:16:19 PM UTC 24 |
| Finished | Sep 11 09:17:03 PM UTC 24 |
| Peak memory | 595720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831317965 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device.3831317965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/92.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.2031429220 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 2841989650 ps |
| CPU time | 58.4 seconds |
| Started | Sep 11 09:16:20 PM UTC 24 |
| Finished | Sep 11 09:17:20 PM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031429220 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device_slow_rsp.2031429220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.1769590907 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 926076028 ps |
| CPU time | 47.55 seconds |
| Started | Sep 11 09:16:37 PM UTC 24 |
| Finished | Sep 11 09:17:26 PM UTC 24 |
| Peak memory | 596048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769590907 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_addr.1769590907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.2864143158 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 591315477 ps |
| CPU time | 43.76 seconds |
| Started | Sep 11 09:16:34 PM UTC 24 |
| Finished | Sep 11 09:17:19 PM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864143158 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.2864143158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/92.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random.2662510046 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 28719984 ps |
| CPU time | 7.97 seconds |
| Started | Sep 11 09:15:59 PM UTC 24 |
| Finished | Sep 11 09:16:08 PM UTC 24 |
| Peak memory | 593812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662510046 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.2662510046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/92.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_large_delays.1915295749 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 5891125266 ps |
| CPU time | 61.32 seconds |
| Started | Sep 11 09:16:13 PM UTC 24 |
| Finished | Sep 11 09:17:16 PM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915295749 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.1915295749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/92.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_slow_rsp.3036813014 |
| Short name | T2914 |
| Test name | |
| Test status | |
| Simulation time | 67810330064 ps |
| CPU time | 983.11 seconds |
| Started | Sep 11 09:16:17 PM UTC 24 |
| Finished | Sep 11 09:32:51 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036813014 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.3036813014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/92.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_zero_delays.502453132 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 246143826 ps |
| CPU time | 25.06 seconds |
| Started | Sep 11 09:16:05 PM UTC 24 |
| Finished | Sep 11 09:16:32 PM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502453132 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_delays.502453132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/92.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_same_source.1391662580 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 492273998 ps |
| CPU time | 35.22 seconds |
| Started | Sep 11 09:16:27 PM UTC 24 |
| Finished | Sep 11 09:17:04 PM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391662580 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.1391662580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/92.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.2025675112 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 171985170 ps |
| CPU time | 11.83 seconds |
| Started | Sep 11 09:15:44 PM UTC 24 |
| Finished | Sep 11 09:15:57 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025675112 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.2025675112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/92.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_large_delays.4069008878 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 9600684359 ps |
| CPU time | 117.52 seconds |
| Started | Sep 11 09:15:56 PM UTC 24 |
| Finished | Sep 11 09:17:56 PM UTC 24 |
| Peak memory | 593952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069008878 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.4069008878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/92.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.647495927 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 5013374184 ps |
| CPU time | 65.92 seconds |
| Started | Sep 11 09:15:57 PM UTC 24 |
| Finished | Sep 11 09:17:04 PM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647495927 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.647495927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.1479724261 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 49813413 ps |
| CPU time | 9 seconds |
| Started | Sep 11 09:15:51 PM UTC 24 |
| Finished | Sep 11 09:16:01 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479724261 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delays.1479724261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/92.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all.2547969508 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 983853008 ps |
| CPU time | 92.28 seconds |
| Started | Sep 11 09:16:36 PM UTC 24 |
| Finished | Sep 11 09:18:10 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547969508 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.2547969508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/92.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_error.260592281 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 14345128863 ps |
| CPU time | 479.86 seconds |
| Started | Sep 11 09:16:44 PM UTC 24 |
| Finished | Sep 11 09:24:51 PM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260592281 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.260592281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/92.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.2299681394 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 709534684 ps |
| CPU time | 278.06 seconds |
| Started | Sep 11 09:16:41 PM UTC 24 |
| Finished | Sep 11 09:21:23 PM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299681394 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_rand_reset.2299681394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.1887377454 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 7088604365 ps |
| CPU time | 613.67 seconds |
| Started | Sep 11 09:16:49 PM UTC 24 |
| Finished | Sep 11 09:27:11 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887377454 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_reset_error.1887377454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_unmapped_addr.3518751245 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 268861514 ps |
| CPU time | 28.38 seconds |
| Started | Sep 11 09:16:34 PM UTC 24 |
| Finished | Sep 11 09:17:04 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518751245 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.3518751245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/92.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device.1966528698 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 226613121 ps |
| CPU time | 22.96 seconds |
| Started | Sep 11 09:17:25 PM UTC 24 |
| Finished | Sep 11 09:17:49 PM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966528698 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device.1966528698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/93.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.3625034024 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 5820455135 ps |
| CPU time | 98.03 seconds |
| Started | Sep 11 09:17:26 PM UTC 24 |
| Finished | Sep 11 09:19:06 PM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625034024 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device_slow_rsp.3625034024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.2310621965 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 304854877 ps |
| CPU time | 43.48 seconds |
| Started | Sep 11 09:17:31 PM UTC 24 |
| Finished | Sep 11 09:18:16 PM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310621965 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_addr.2310621965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_random.1543992264 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 618794447 ps |
| CPU time | 25.43 seconds |
| Started | Sep 11 09:17:29 PM UTC 24 |
| Finished | Sep 11 09:17:56 PM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543992264 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.1543992264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/93.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random.1769478647 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 141921608 ps |
| CPU time | 10.71 seconds |
| Started | Sep 11 09:17:02 PM UTC 24 |
| Finished | Sep 11 09:17:15 PM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769478647 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.1769478647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/93.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_large_delays.4238669051 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 33398508381 ps |
| CPU time | 387.47 seconds |
| Started | Sep 11 09:17:20 PM UTC 24 |
| Finished | Sep 11 09:23:53 PM UTC 24 |
| Peak memory | 596040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238669051 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.4238669051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/93.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_slow_rsp.3796365027 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 21066515284 ps |
| CPU time | 323.49 seconds |
| Started | Sep 11 09:17:22 PM UTC 24 |
| Finished | Sep 11 09:22:51 PM UTC 24 |
| Peak memory | 596008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796365027 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.3796365027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/93.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_zero_delays.962243748 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 504398936 ps |
| CPU time | 44.05 seconds |
| Started | Sep 11 09:17:05 PM UTC 24 |
| Finished | Sep 11 09:17:50 PM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962243748 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_delays.962243748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/93.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_same_source.2816988267 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 280393855 ps |
| CPU time | 23.15 seconds |
| Started | Sep 11 09:17:28 PM UTC 24 |
| Finished | Sep 11 09:17:53 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816988267 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.2816988267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/93.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.3429315934 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 201791552 ps |
| CPU time | 12.15 seconds |
| Started | Sep 11 09:16:52 PM UTC 24 |
| Finished | Sep 11 09:17:05 PM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429315934 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.3429315934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/93.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_large_delays.4055883948 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 7546648043 ps |
| CPU time | 68.95 seconds |
| Started | Sep 11 09:17:00 PM UTC 24 |
| Finished | Sep 11 09:18:11 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055883948 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.4055883948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/93.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.610715816 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 6440328052 ps |
| CPU time | 101.2 seconds |
| Started | Sep 11 09:16:57 PM UTC 24 |
| Finished | Sep 11 09:18:41 PM UTC 24 |
| Peak memory | 593956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610715816 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.610715816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_zero_delays.2224101229 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 43620215 ps |
| CPU time | 7.96 seconds |
| Started | Sep 11 09:16:56 PM UTC 24 |
| Finished | Sep 11 09:17:05 PM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224101229 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delays.2224101229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/93.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all.1874376868 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 1570706215 ps |
| CPU time | 125.33 seconds |
| Started | Sep 11 09:17:38 PM UTC 24 |
| Finished | Sep 11 09:19:45 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874376868 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.1874376868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/93.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_error.4276928346 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 5194617345 ps |
| CPU time | 186.14 seconds |
| Started | Sep 11 09:17:44 PM UTC 24 |
| Finished | Sep 11 09:20:53 PM UTC 24 |
| Peak memory | 595984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276928346 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.4276928346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/93.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.2494723955 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 5479987847 ps |
| CPU time | 635.33 seconds |
| Started | Sep 11 09:17:39 PM UTC 24 |
| Finished | Sep 11 09:28:22 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494723955 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_rand_reset.2494723955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.1841297392 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 491211890 ps |
| CPU time | 92.25 seconds |
| Started | Sep 11 09:17:43 PM UTC 24 |
| Finished | Sep 11 09:19:17 PM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841297392 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_reset_error.1841297392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_unmapped_addr.2062587392 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 299400102 ps |
| CPU time | 40.68 seconds |
| Started | Sep 11 09:17:30 PM UTC 24 |
| Finished | Sep 11 09:18:12 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062587392 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.2062587392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/93.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device.2095715728 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 164951855 ps |
| CPU time | 20.21 seconds |
| Started | Sep 11 09:18:21 PM UTC 24 |
| Finished | Sep 11 09:18:43 PM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095715728 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device.2095715728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/94.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.1053586776 |
| Short name | T2924 |
| Test name | |
| Test status | |
| Simulation time | 128253093276 ps |
| CPU time | 1841.36 seconds |
| Started | Sep 11 09:18:21 PM UTC 24 |
| Finished | Sep 11 09:49:24 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053586776 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device_slow_rsp.1053586776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.73814719 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 122705015 ps |
| CPU time | 19.09 seconds |
| Started | Sep 11 09:18:36 PM UTC 24 |
| Finished | Sep 11 09:18:56 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73814719 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_addr.73814719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_random.1054674440 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 2657268302 ps |
| CPU time | 109.52 seconds |
| Started | Sep 11 09:18:34 PM UTC 24 |
| Finished | Sep 11 09:20:26 PM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054674440 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.1054674440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/94.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random.2259949444 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 288069858 ps |
| CPU time | 36.52 seconds |
| Started | Sep 11 09:18:17 PM UTC 24 |
| Finished | Sep 11 09:18:55 PM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259949444 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.2259949444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/94.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_large_delays.1931355675 |
| Short name | T2906 |
| Test name | |
| Test status | |
| Simulation time | 71775484917 ps |
| CPU time | 636.42 seconds |
| Started | Sep 11 09:18:16 PM UTC 24 |
| Finished | Sep 11 09:29:00 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931355675 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.1931355675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/94.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_slow_rsp.1874510530 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 23456311523 ps |
| CPU time | 384.18 seconds |
| Started | Sep 11 09:18:19 PM UTC 24 |
| Finished | Sep 11 09:24:48 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874510530 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.1874510530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/94.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_zero_delays.3761242520 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 476598867 ps |
| CPU time | 44.56 seconds |
| Started | Sep 11 09:18:15 PM UTC 24 |
| Finished | Sep 11 09:19:01 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761242520 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_delays.3761242520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/94.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_same_source.3170754703 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 494792570 ps |
| CPU time | 47.83 seconds |
| Started | Sep 11 09:18:19 PM UTC 24 |
| Finished | Sep 11 09:19:08 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170754703 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.3170754703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/94.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke.1728198495 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 48112583 ps |
| CPU time | 8.92 seconds |
| Started | Sep 11 09:17:43 PM UTC 24 |
| Finished | Sep 11 09:17:53 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728198495 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.1728198495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/94.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_large_delays.1030377392 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 6632583407 ps |
| CPU time | 60.39 seconds |
| Started | Sep 11 09:18:04 PM UTC 24 |
| Finished | Sep 11 09:19:06 PM UTC 24 |
| Peak memory | 593704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030377392 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.1030377392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/94.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.335478648 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 3723735574 ps |
| CPU time | 74.14 seconds |
| Started | Sep 11 09:18:14 PM UTC 24 |
| Finished | Sep 11 09:19:30 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335478648 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.335478648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_zero_delays.3788053445 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 41961696 ps |
| CPU time | 8.22 seconds |
| Started | Sep 11 09:17:48 PM UTC 24 |
| Finished | Sep 11 09:17:58 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788053445 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delays.3788053445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/94.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all.2186005060 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 5686688007 ps |
| CPU time | 196 seconds |
| Started | Sep 11 09:18:40 PM UTC 24 |
| Finished | Sep 11 09:21:59 PM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186005060 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.2186005060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/94.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_error.4132361188 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 3969411655 ps |
| CPU time | 115.02 seconds |
| Started | Sep 11 09:19:05 PM UTC 24 |
| Finished | Sep 11 09:21:02 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132361188 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.4132361188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/94.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.2127709104 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 4495649734 ps |
| CPU time | 508.41 seconds |
| Started | Sep 11 09:18:52 PM UTC 24 |
| Finished | Sep 11 09:27:27 PM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127709104 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_rand_reset.2127709104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.1708507393 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 1075311017 ps |
| CPU time | 157.64 seconds |
| Started | Sep 11 09:19:09 PM UTC 24 |
| Finished | Sep 11 09:21:50 PM UTC 24 |
| Peak memory | 596064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708507393 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_reset_error.1708507393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_unmapped_addr.2553466924 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 929567430 ps |
| CPU time | 33.85 seconds |
| Started | Sep 11 09:18:37 PM UTC 24 |
| Finished | Sep 11 09:19:12 PM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553466924 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.2553466924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/94.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device.821970532 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 690372113 ps |
| CPU time | 55.35 seconds |
| Started | Sep 11 09:19:32 PM UTC 24 |
| Finished | Sep 11 09:20:29 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821970532 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device.821970532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/95.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.2322530137 |
| Short name | T2925 |
| Test name | |
| Test status | |
| Simulation time | 148357529329 ps |
| CPU time | 2049.48 seconds |
| Started | Sep 11 09:19:31 PM UTC 24 |
| Finished | Sep 11 09:54:05 PM UTC 24 |
| Peak memory | 598936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322530137 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device_slow_rsp.2322530137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.3870060466 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 149034214 ps |
| CPU time | 12.96 seconds |
| Started | Sep 11 09:19:36 PM UTC 24 |
| Finished | Sep 11 09:19:50 PM UTC 24 |
| Peak memory | 593660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870060466 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_addr.3870060466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_random.2151125273 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 1667731097 ps |
| CPU time | 66.79 seconds |
| Started | Sep 11 09:19:33 PM UTC 24 |
| Finished | Sep 11 09:20:42 PM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151125273 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.2151125273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/95.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random.1166362566 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 2099925952 ps |
| CPU time | 61.63 seconds |
| Started | Sep 11 09:19:19 PM UTC 24 |
| Finished | Sep 11 09:20:22 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166362566 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.1166362566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/95.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_large_delays.1859575286 |
| Short name | T2910 |
| Test name | |
| Test status | |
| Simulation time | 63680597812 ps |
| CPU time | 656.59 seconds |
| Started | Sep 11 09:19:25 PM UTC 24 |
| Finished | Sep 11 09:30:30 PM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859575286 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.1859575286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/95.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_slow_rsp.685450174 |
| Short name | T2905 |
| Test name | |
| Test status | |
| Simulation time | 36772088888 ps |
| CPU time | 551.48 seconds |
| Started | Sep 11 09:19:28 PM UTC 24 |
| Finished | Sep 11 09:28:47 PM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685450174 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.685450174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/95.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_zero_delays.2618219136 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 64141358 ps |
| CPU time | 8.86 seconds |
| Started | Sep 11 09:19:20 PM UTC 24 |
| Finished | Sep 11 09:19:30 PM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618219136 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_delays.2618219136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/95.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_same_source.2994121297 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 1332047492 ps |
| CPU time | 55.04 seconds |
| Started | Sep 11 09:19:37 PM UTC 24 |
| Finished | Sep 11 09:20:34 PM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994121297 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.2994121297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/95.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke.39201303 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 175576015 ps |
| CPU time | 12 seconds |
| Started | Sep 11 09:19:09 PM UTC 24 |
| Finished | Sep 11 09:19:22 PM UTC 24 |
| Peak memory | 593900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39201303 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.39201303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/95.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_large_delays.3971711909 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 6211613447 ps |
| CPU time | 59.11 seconds |
| Started | Sep 11 09:19:14 PM UTC 24 |
| Finished | Sep 11 09:20:15 PM UTC 24 |
| Peak memory | 593844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971711909 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.3971711909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/95.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.2621725786 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 3667646827 ps |
| CPU time | 47.24 seconds |
| Started | Sep 11 09:19:17 PM UTC 24 |
| Finished | Sep 11 09:20:06 PM UTC 24 |
| Peak memory | 594116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621725786 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.2621725786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_zero_delays.3075988988 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 48903220 ps |
| CPU time | 8.03 seconds |
| Started | Sep 11 09:19:06 PM UTC 24 |
| Finished | Sep 11 09:19:15 PM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075988988 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delays.3075988988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/95.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all.2818652940 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 5799631336 ps |
| CPU time | 253.6 seconds |
| Started | Sep 11 09:19:43 PM UTC 24 |
| Finished | Sep 11 09:24:01 PM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818652940 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.2818652940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/95.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_error.386356325 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 1096994794 ps |
| CPU time | 91.25 seconds |
| Started | Sep 11 09:19:50 PM UTC 24 |
| Finished | Sep 11 09:21:24 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386356325 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.386356325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/95.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.3099387176 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 64462210 ps |
| CPU time | 62.54 seconds |
| Started | Sep 11 09:19:47 PM UTC 24 |
| Finished | Sep 11 09:20:51 PM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099387176 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_rand_reset.3099387176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.2525732541 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 461173515 ps |
| CPU time | 139.83 seconds |
| Started | Sep 11 09:19:54 PM UTC 24 |
| Finished | Sep 11 09:22:16 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525732541 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_reset_error.2525732541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_unmapped_addr.2596001868 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 851643817 ps |
| CPU time | 48.15 seconds |
| Started | Sep 11 09:19:40 PM UTC 24 |
| Finished | Sep 11 09:20:30 PM UTC 24 |
| Peak memory | 596080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596001868 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.2596001868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/95.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device.1668928321 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 584716167 ps |
| CPU time | 30.22 seconds |
| Started | Sep 11 09:20:48 PM UTC 24 |
| Finished | Sep 11 09:21:20 PM UTC 24 |
| Peak memory | 595936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668928321 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device.1668928321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/96.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.130183481 |
| Short name | T2923 |
| Test name | |
| Test status | |
| Simulation time | 102850234631 ps |
| CPU time | 1369.93 seconds |
| Started | Sep 11 09:20:49 PM UTC 24 |
| Finished | Sep 11 09:43:56 PM UTC 24 |
| Peak memory | 598932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130183481 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device_slow_rsp.130183481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.3527740824 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 313221161 ps |
| CPU time | 13.98 seconds |
| Started | Sep 11 09:21:08 PM UTC 24 |
| Finished | Sep 11 09:21:24 PM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527740824 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_addr.3527740824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_random.3272544356 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 133848239 ps |
| CPU time | 16.16 seconds |
| Started | Sep 11 09:20:53 PM UTC 24 |
| Finished | Sep 11 09:21:10 PM UTC 24 |
| Peak memory | 595944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272544356 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.3272544356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/96.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random.1199768048 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 2211966763 ps |
| CPU time | 71.6 seconds |
| Started | Sep 11 09:20:31 PM UTC 24 |
| Finished | Sep 11 09:21:45 PM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199768048 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.1199768048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/96.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_large_delays.996397172 |
| Short name | T2913 |
| Test name | |
| Test status | |
| Simulation time | 73261430297 ps |
| CPU time | 669.1 seconds |
| Started | Sep 11 09:20:41 PM UTC 24 |
| Finished | Sep 11 09:31:58 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996397172 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.996397172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/96.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_slow_rsp.345898190 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 25740010763 ps |
| CPU time | 399.44 seconds |
| Started | Sep 11 09:20:44 PM UTC 24 |
| Finished | Sep 11 09:27:29 PM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345898190 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.345898190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/96.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_zero_delays.384871333 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 139284211 ps |
| CPU time | 17.51 seconds |
| Started | Sep 11 09:20:37 PM UTC 24 |
| Finished | Sep 11 09:20:56 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384871333 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_delays.384871333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/96.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_same_source.2151388068 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 1929690561 ps |
| CPU time | 50.25 seconds |
| Started | Sep 11 09:20:52 PM UTC 24 |
| Finished | Sep 11 09:21:44 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151388068 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.2151388068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/96.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke.1296443375 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 215506874 ps |
| CPU time | 12.95 seconds |
| Started | Sep 11 09:19:57 PM UTC 24 |
| Finished | Sep 11 09:20:11 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296443375 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.1296443375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/96.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_large_delays.2264295729 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 7468091246 ps |
| CPU time | 92.66 seconds |
| Started | Sep 11 09:20:12 PM UTC 24 |
| Finished | Sep 11 09:21:47 PM UTC 24 |
| Peak memory | 593944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264295729 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.2264295729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/96.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.238234941 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 4020870482 ps |
| CPU time | 60.26 seconds |
| Started | Sep 11 09:20:17 PM UTC 24 |
| Finished | Sep 11 09:21:18 PM UTC 24 |
| Peak memory | 593716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238234941 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.238234941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_zero_delays.2936969509 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 52589098 ps |
| CPU time | 9.06 seconds |
| Started | Sep 11 09:20:07 PM UTC 24 |
| Finished | Sep 11 09:20:17 PM UTC 24 |
| Peak memory | 593780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936969509 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delays.2936969509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/96.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all.2730647012 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 4113538967 ps |
| CPU time | 325.73 seconds |
| Started | Sep 11 09:21:11 PM UTC 24 |
| Finished | Sep 11 09:26:42 PM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730647012 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.2730647012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/96.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_error.1642008341 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 2814166956 ps |
| CPU time | 178.86 seconds |
| Started | Sep 11 09:21:19 PM UTC 24 |
| Finished | Sep 11 09:24:21 PM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642008341 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.1642008341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/96.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.448676898 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 279058411 ps |
| CPU time | 130.62 seconds |
| Started | Sep 11 09:21:18 PM UTC 24 |
| Finished | Sep 11 09:23:31 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448676898 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_rand_reset.448676898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.2715101066 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 1277750372 ps |
| CPU time | 244.47 seconds |
| Started | Sep 11 09:21:19 PM UTC 24 |
| Finished | Sep 11 09:25:28 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715101066 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_reset_error.2715101066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_unmapped_addr.727282417 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 139343503 ps |
| CPU time | 11.61 seconds |
| Started | Sep 11 09:21:00 PM UTC 24 |
| Finished | Sep 11 09:21:13 PM UTC 24 |
| Peak memory | 593776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727282417 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.727282417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/96.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device.3954318497 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 577448281 ps |
| CPU time | 39.67 seconds |
| Started | Sep 11 09:21:47 PM UTC 24 |
| Finished | Sep 11 09:22:28 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954318497 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device.3954318497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/97.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.265668704 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 13218343797 ps |
| CPU time | 178.64 seconds |
| Started | Sep 11 09:21:48 PM UTC 24 |
| Finished | Sep 11 09:24:50 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265668704 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device_slow_rsp.265668704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.3179974194 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 40605202 ps |
| CPU time | 9.63 seconds |
| Started | Sep 11 09:22:05 PM UTC 24 |
| Finished | Sep 11 09:22:16 PM UTC 24 |
| Peak memory | 593660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179974194 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_addr.3179974194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_random.1906938726 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 131797732 ps |
| CPU time | 14.85 seconds |
| Started | Sep 11 09:21:53 PM UTC 24 |
| Finished | Sep 11 09:22:09 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906938726 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.1906938726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/97.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random.1881701663 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 330776537 ps |
| CPU time | 28.12 seconds |
| Started | Sep 11 09:21:35 PM UTC 24 |
| Finished | Sep 11 09:22:04 PM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881701663 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.1881701663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/97.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_large_delays.4029779021 |
| Short name | T2919 |
| Test name | |
| Test status | |
| Simulation time | 91108682207 ps |
| CPU time | 943.41 seconds |
| Started | Sep 11 09:21:45 PM UTC 24 |
| Finished | Sep 11 09:37:39 PM UTC 24 |
| Peak memory | 596088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029779021 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.4029779021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/97.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_slow_rsp.1775869953 |
| Short name | T2921 |
| Test name | |
| Test status | |
| Simulation time | 69205775535 ps |
| CPU time | 953.53 seconds |
| Started | Sep 11 09:21:49 PM UTC 24 |
| Finished | Sep 11 09:37:54 PM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775869953 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.1775869953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/97.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_zero_delays.736698806 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 182585024 ps |
| CPU time | 24.04 seconds |
| Started | Sep 11 09:21:42 PM UTC 24 |
| Finished | Sep 11 09:22:08 PM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736698806 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_delays.736698806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/97.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_same_source.1588849486 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 2568490414 ps |
| CPU time | 74.28 seconds |
| Started | Sep 11 09:21:47 PM UTC 24 |
| Finished | Sep 11 09:23:03 PM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588849486 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.1588849486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/97.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke.18458835 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 55484666 ps |
| CPU time | 6.63 seconds |
| Started | Sep 11 09:21:20 PM UTC 24 |
| Finished | Sep 11 09:21:28 PM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18458835 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.18458835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/97.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_large_delays.646559715 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 9440836634 ps |
| CPU time | 120.59 seconds |
| Started | Sep 11 09:21:26 PM UTC 24 |
| Finished | Sep 11 09:23:29 PM UTC 24 |
| Peak memory | 593912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646559715 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.646559715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/97.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.3635919521 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 4664488493 ps |
| CPU time | 81.06 seconds |
| Started | Sep 11 09:21:36 PM UTC 24 |
| Finished | Sep 11 09:22:59 PM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635919521 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.3635919521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_zero_delays.2512001542 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 42280189 ps |
| CPU time | 8.27 seconds |
| Started | Sep 11 09:21:26 PM UTC 24 |
| Finished | Sep 11 09:21:35 PM UTC 24 |
| Peak memory | 593780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512001542 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delays.2512001542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/97.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all.903601532 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 6899324181 ps |
| CPU time | 252.65 seconds |
| Started | Sep 11 09:22:08 PM UTC 24 |
| Finished | Sep 11 09:26:25 PM UTC 24 |
| Peak memory | 596004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903601532 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.903601532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/97.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_error.2348619552 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 12125854169 ps |
| CPU time | 346.46 seconds |
| Started | Sep 11 09:22:09 PM UTC 24 |
| Finished | Sep 11 09:28:00 PM UTC 24 |
| Peak memory | 596148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348619552 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.2348619552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/97.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.4072771040 |
| Short name | T2922 |
| Test name | |
| Test status | |
| Simulation time | 11319108407 ps |
| CPU time | 1228.73 seconds |
| Started | Sep 11 09:22:07 PM UTC 24 |
| Finished | Sep 11 09:42:51 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072771040 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_rand_reset.4072771040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.89408154 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 23639234 ps |
| CPU time | 19.32 seconds |
| Started | Sep 11 09:22:10 PM UTC 24 |
| Finished | Sep 11 09:22:30 PM UTC 24 |
| Peak memory | 593640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89408154 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_reset_error.89408154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_unmapped_addr.1085617382 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 586432961 ps |
| CPU time | 22.55 seconds |
| Started | Sep 11 09:22:01 PM UTC 24 |
| Finished | Sep 11 09:22:25 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085617382 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.1085617382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/97.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device.3971133244 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 1007609586 ps |
| CPU time | 41.95 seconds |
| Started | Sep 11 09:22:39 PM UTC 24 |
| Finished | Sep 11 09:23:23 PM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971133244 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device.3971133244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/98.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.3984699048 |
| Short name | T2915 |
| Test name | |
| Test status | |
| Simulation time | 47975541696 ps |
| CPU time | 639.03 seconds |
| Started | Sep 11 09:22:50 PM UTC 24 |
| Finished | Sep 11 09:33:37 PM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984699048 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device_slow_rsp.3984699048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.390403476 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 148219797 ps |
| CPU time | 23.24 seconds |
| Started | Sep 11 09:22:57 PM UTC 24 |
| Finished | Sep 11 09:23:22 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390403476 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_addr.390403476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_random.1508876709 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 1879387534 ps |
| CPU time | 76.77 seconds |
| Started | Sep 11 09:22:51 PM UTC 24 |
| Finished | Sep 11 09:24:10 PM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508876709 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.1508876709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/98.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random.4207573672 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 180171353 ps |
| CPU time | 20.34 seconds |
| Started | Sep 11 09:22:33 PM UTC 24 |
| Finished | Sep 11 09:22:55 PM UTC 24 |
| Peak memory | 596044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207573672 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.4207573672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/98.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_large_delays.1574804867 |
| Short name | T2920 |
| Test name | |
| Test status | |
| Simulation time | 84784262583 ps |
| CPU time | 900.03 seconds |
| Started | Sep 11 09:22:41 PM UTC 24 |
| Finished | Sep 11 09:37:51 PM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574804867 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.1574804867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/98.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_slow_rsp.3242116380 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 7797947588 ps |
| CPU time | 119.02 seconds |
| Started | Sep 11 09:22:40 PM UTC 24 |
| Finished | Sep 11 09:24:42 PM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242116380 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.3242116380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/98.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_zero_delays.1077922410 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 63535364 ps |
| CPU time | 10.99 seconds |
| Started | Sep 11 09:22:32 PM UTC 24 |
| Finished | Sep 11 09:22:44 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077922410 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_delays.1077922410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/98.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_same_source.2510314624 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 853003963 ps |
| CPU time | 25.85 seconds |
| Started | Sep 11 09:22:51 PM UTC 24 |
| Finished | Sep 11 09:23:18 PM UTC 24 |
| Peak memory | 595824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510314624 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.2510314624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/98.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke.785688414 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 172006639 ps |
| CPU time | 11.45 seconds |
| Started | Sep 11 09:22:14 PM UTC 24 |
| Finished | Sep 11 09:22:27 PM UTC 24 |
| Peak memory | 593836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785688414 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.785688414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/98.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_large_delays.43114970 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 5535158034 ps |
| CPU time | 67.07 seconds |
| Started | Sep 11 09:22:24 PM UTC 24 |
| Finished | Sep 11 09:23:33 PM UTC 24 |
| Peak memory | 593708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43114970 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.43114970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/98.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.538063209 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 5970145958 ps |
| CPU time | 117.04 seconds |
| Started | Sep 11 09:22:29 PM UTC 24 |
| Finished | Sep 11 09:24:29 PM UTC 24 |
| Peak memory | 593952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538063209 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.538063209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_zero_delays.2042912999 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 48693493 ps |
| CPU time | 6.86 seconds |
| Started | Sep 11 09:22:24 PM UTC 24 |
| Finished | Sep 11 09:22:32 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042912999 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delays.2042912999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/98.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all.122888863 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 3796651768 ps |
| CPU time | 127.72 seconds |
| Started | Sep 11 09:23:11 PM UTC 24 |
| Finished | Sep 11 09:25:21 PM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122888863 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.122888863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/98.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_error.3656996633 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 2603185320 ps |
| CPU time | 62.15 seconds |
| Started | Sep 11 09:23:15 PM UTC 24 |
| Finished | Sep 11 09:24:19 PM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656996633 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.3656996633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/98.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.2796600862 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 123678515 ps |
| CPU time | 135.13 seconds |
| Started | Sep 11 09:23:10 PM UTC 24 |
| Finished | Sep 11 09:25:28 PM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796600862 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_rand_reset.2796600862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.4033994818 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 3856068942 ps |
| CPU time | 281.65 seconds |
| Started | Sep 11 09:23:18 PM UTC 24 |
| Finished | Sep 11 09:28:04 PM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033994818 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_reset_error.4033994818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_unmapped_addr.2446511562 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 610144453 ps |
| CPU time | 31.81 seconds |
| Started | Sep 11 09:22:52 PM UTC 24 |
| Finished | Sep 11 09:23:25 PM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446511562 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.2446511562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/98.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device.358421117 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 709162174 ps |
| CPU time | 66.12 seconds |
| Started | Sep 11 09:23:51 PM UTC 24 |
| Finished | Sep 11 09:24:59 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358421117 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device.358421117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/99.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.849941811 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 2602010015 ps |
| CPU time | 43.96 seconds |
| Started | Sep 11 09:23:54 PM UTC 24 |
| Finished | Sep 11 09:24:39 PM UTC 24 |
| Peak memory | 594100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849941811 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device_slow_rsp.849941811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.1630366173 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 689150324 ps |
| CPU time | 26.87 seconds |
| Started | Sep 11 09:24:01 PM UTC 24 |
| Finished | Sep 11 09:24:29 PM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630366173 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_addr.1630366173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_random.253191130 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 994589091 ps |
| CPU time | 41.12 seconds |
| Started | Sep 11 09:23:57 PM UTC 24 |
| Finished | Sep 11 09:24:39 PM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253191130 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.253191130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/99.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random.1912896097 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 312447175 ps |
| CPU time | 34.38 seconds |
| Started | Sep 11 09:23:38 PM UTC 24 |
| Finished | Sep 11 09:24:14 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912896097 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.1912896097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/99.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_large_delays.1862941141 |
| Short name | T2907 |
| Test name | |
| Test status | |
| Simulation time | 40372976776 ps |
| CPU time | 344.3 seconds |
| Started | Sep 11 09:23:48 PM UTC 24 |
| Finished | Sep 11 09:29:37 PM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862941141 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.1862941141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/99.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_slow_rsp.3213089837 |
| Short name | T2917 |
| Test name | |
| Test status | |
| Simulation time | 48544279793 ps |
| CPU time | 644.13 seconds |
| Started | Sep 11 09:23:48 PM UTC 24 |
| Finished | Sep 11 09:34:40 PM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213089837 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.3213089837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/99.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_zero_delays.3589527693 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 313251688 ps |
| CPU time | 36.67 seconds |
| Started | Sep 11 09:23:44 PM UTC 24 |
| Finished | Sep 11 09:24:22 PM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589527693 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_delays.3589527693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/99.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_same_source.1969420375 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 2040422598 ps |
| CPU time | 76.2 seconds |
| Started | Sep 11 09:23:54 PM UTC 24 |
| Finished | Sep 11 09:25:13 PM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969420375 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.1969420375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/99.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke.3577101261 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 146771123 ps |
| CPU time | 6.74 seconds |
| Started | Sep 11 09:23:21 PM UTC 24 |
| Finished | Sep 11 09:23:29 PM UTC 24 |
| Peak memory | 593644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577101261 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.3577101261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/99.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_large_delays.1237729895 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 7243614243 ps |
| CPU time | 88.3 seconds |
| Started | Sep 11 09:23:28 PM UTC 24 |
| Finished | Sep 11 09:24:58 PM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237729895 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.1237729895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/99.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.274129347 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 4956326803 ps |
| CPU time | 94.84 seconds |
| Started | Sep 11 09:23:26 PM UTC 24 |
| Finished | Sep 11 09:25:03 PM UTC 24 |
| Peak memory | 594144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274129347 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.274129347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_zero_delays.3558551554 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 45330720 ps |
| CPU time | 7.94 seconds |
| Started | Sep 11 09:23:25 PM UTC 24 |
| Finished | Sep 11 09:23:35 PM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558551554 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delays.3558551554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/99.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all.2825593695 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 7152947010 ps |
| CPU time | 221.51 seconds |
| Started | Sep 11 09:24:16 PM UTC 24 |
| Finished | Sep 11 09:28:01 PM UTC 24 |
| Peak memory | 596032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825593695 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.2825593695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/99.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_error.1361686592 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 4850901585 ps |
| CPU time | 139.85 seconds |
| Started | Sep 11 09:24:34 PM UTC 24 |
| Finished | Sep 11 09:26:57 PM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361686592 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.1361686592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/99.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.2170656945 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 758140635 ps |
| CPU time | 173.66 seconds |
| Started | Sep 11 09:24:27 PM UTC 24 |
| Finished | Sep 11 09:27:24 PM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170656945 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_rand_reset.2170656945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.1772047813 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 603058625 ps |
| CPU time | 155.58 seconds |
| Started | Sep 11 09:24:40 PM UTC 24 |
| Finished | Sep 11 09:27:19 PM UTC 24 |
| Peak memory | 595928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772047813 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_reset_error.1772047813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_unmapped_addr.2578387846 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 267912929 ps |
| CPU time | 31.63 seconds |
| Started | Sep 11 09:23:58 PM UTC 24 |
| Finished | Sep 11 09:24:31 PM UTC 24 |
| Peak memory | 595960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578387846 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.2578387846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/99.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.854832188 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 13866782190 ps |
| CPU time | 1310.48 seconds |
| Started | Sep 11 10:08:49 PM UTC 24 |
| Finished | Sep 11 10:30:57 PM UTC 24 |
| Peak memory | 623260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854832188 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.854832188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_jtag_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sival_flash_info_access.1876998369 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 2688958892 ps |
| CPU time | 208.49 seconds |
| Started | Sep 11 09:32:17 PM UTC 24 |
| Finished | Sep 11 09:35:49 PM UTC 24 |
| Peak memory | 625672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim _dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876998369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.1876998369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sival_flash_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc.3066096655 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 2727349456 ps |
| CPU time | 278.08 seconds |
| Started | Sep 11 09:46:10 PM UTC 24 |
| Finished | Sep 11 09:50:53 PM UTC 24 |
| Peak memory | 623628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_i mages=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066096655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.3066096655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en.1223273745 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 2901301558 ps |
| CPU time | 306.74 seconds |
| Started | Sep 11 09:46:16 PM UTC 24 |
| Finished | Sep 11 09:51:27 PM UTC 24 |
| Peak memory | 623728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223273745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.1223273745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.896065383 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 3474273187 ps |
| CPU time | 268.68 seconds |
| Started | Sep 11 10:16:45 PM UTC 24 |
| Finished | Sep 11 10:21:19 PM UTC 24 |
| Peak memory | 623664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896065383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.896065383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_entropy.645213761 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2965614200 ps |
| CPU time | 234.77 seconds |
| Started | Sep 11 09:50:50 PM UTC 24 |
| Finished | Sep 11 09:54:49 PM UTC 24 |
| Peak memory | 623580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645213761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_aes_entropy.645213761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_idle.4183039003 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 3040141600 ps |
| CPU time | 234.64 seconds |
| Started | Sep 11 09:46:31 PM UTC 24 |
| Finished | Sep 11 09:50:30 PM UTC 24 |
| Peak memory | 623452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183039003 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.4183039003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_masking_off.2767259329 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 3448069080 ps |
| CPU time | 278.58 seconds |
| Started | Sep 11 09:46:53 PM UTC 24 |
| Finished | Sep 11 09:51:36 PM UTC 24 |
| Peak memory | 623736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767259329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_aes_masking_off.2767259329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_masking_off/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_smoketest.1933677778 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 3289089014 ps |
| CPU time | 341.43 seconds |
| Started | Sep 11 11:12:14 PM UTC 24 |
| Finished | Sep 11 11:18:00 PM UTC 24 |
| Peak memory | 623700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1933677778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_a es_smoketest.1933677778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.4282458726 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 2825493984 ps |
| CPU time | 344.03 seconds |
| Started | Sep 11 09:50:47 PM UTC 24 |
| Finished | Sep 11 09:56:37 PM UTC 24 |
| Peak memory | 625720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282458726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.4282458726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_escalation.3830606751 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 5522790616 ps |
| CPU time | 538.79 seconds |
| Started | Sep 11 09:47:43 PM UTC 24 |
| Finished | Sep 11 09:56:50 PM UTC 24 |
| Peak memory | 636024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830606751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_ earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.3830606751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1370501608 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 7200302132 ps |
| CPU time | 1665.32 seconds |
| Started | Sep 11 09:50:16 PM UTC 24 |
| Finished | Sep 11 10:18:24 PM UTC 24 |
| Peak memory | 625796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370501608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_toggle.1370501608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.589153807 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 8098084186 ps |
| CPU time | 1298.01 seconds |
| Started | Sep 11 09:48:18 PM UTC 24 |
| Finished | Sep 11 10:10:13 PM UTC 24 |
| Peak memory | 623588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589153807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_bas e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.589153807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_timeout.2719532536 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 4961516400 ps |
| CPU time | 515.16 seconds |
| Started | Sep 11 09:47:43 PM UTC 24 |
| Finished | Sep 11 09:56:26 PM UTC 24 |
| Peak memory | 625640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719532536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.2719532536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_irq.1403062711 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 3539795248 ps |
| CPU time | 388.64 seconds |
| Started | Sep 11 09:44:43 PM UTC 24 |
| Finished | Sep 11 09:51:18 PM UTC 24 |
| Peak memory | 623592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403062711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.1403062711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.295208390 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 7753841946 ps |
| CPU time | 427.96 seconds |
| Started | Sep 11 09:45:21 PM UTC 24 |
| Finished | Sep 11 09:52:35 PM UTC 24 |
| Peak memory | 625832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295208390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.295208390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_smoketest.281650451 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 2936878424 ps |
| CPU time | 212.47 seconds |
| Started | Sep 11 11:16:17 PM UTC 24 |
| Finished | Sep 11 11:19:53 PM UTC 24 |
| Peak memory | 623528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281650451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_aon_timer_smoketest.281650451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3184492796 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 6783208250 ps |
| CPU time | 714.56 seconds |
| Started | Sep 11 09:45:27 PM UTC 24 |
| Finished | Sep 11 09:57:31 PM UTC 24 |
| Peak memory | 623828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184492796 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.3184492796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1658561161 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 5707294920 ps |
| CPU time | 547.63 seconds |
| Started | Sep 11 09:45:53 PM UTC 24 |
| Finished | Sep 11 09:55:09 PM UTC 24 |
| Peak memory | 625796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658561161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.1658561161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_outputs.323398353 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 8320510532 ps |
| CPU time | 988.14 seconds |
| Started | Sep 11 10:09:18 PM UTC 24 |
| Finished | Sep 11 10:25:59 PM UTC 24 |
| Peak memory | 632036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_ clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h w/dv/tools/sim.tcl +ntb_random_seed=323398353 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.323398353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3321097750 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 11827585268 ps |
| CPU time | 850.05 seconds |
| Started | Sep 11 10:03:54 PM UTC 24 |
| Finished | Sep 11 10:18:16 PM UTC 24 |
| Peak memory | 638112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_de vice=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321097750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.3321097750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2524336730 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 4776904138 ps |
| CPU time | 681.12 seconds |
| Started | Sep 11 10:06:22 PM UTC 24 |
| Finished | Sep 11 10:17:53 PM UTC 24 |
| Peak memory | 625604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524336730 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_rma.2524336730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2187187595 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 4856297728 ps |
| CPU time | 630.05 seconds |
| Started | Sep 11 10:04:04 PM UTC 24 |
| Finished | Sep 11 10:14:43 PM UTC 24 |
| Peak memory | 625628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218 7187595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_exter nal_clk_src_for_sw_fast_test_unlocked0.2187187595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4131811050 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 4836362408 ps |
| CPU time | 572.52 seconds |
| Started | Sep 11 10:05:36 PM UTC 24 |
| Finished | Sep 11 10:15:17 PM UTC 24 |
| Peak memory | 625944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131811050 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_dev.4131811050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3974409439 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 5628192968 ps |
| CPU time | 636.46 seconds |
| Started | Sep 11 10:07:11 PM UTC 24 |
| Finished | Sep 11 10:17:57 PM UTC 24 |
| Peak memory | 625844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974409439 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_rma.3974409439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3635456901 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 5569851148 ps |
| CPU time | 700.87 seconds |
| Started | Sep 11 10:04:08 PM UTC 24 |
| Finished | Sep 11 10:15:59 PM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363 5456901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_exter nal_clk_src_for_sw_slow_test_unlocked0.3635456901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter.2964766766 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 2464365094 ps |
| CPU time | 167.01 seconds |
| Started | Sep 11 10:07:55 PM UTC 24 |
| Finished | Sep 11 10:10:44 PM UTC 24 |
| Peak memory | 625756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2964766766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_clkmgr_jitter.2964766766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_frequency.4011853960 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 3285947114 ps |
| CPU time | 407.01 seconds |
| Started | Sep 11 10:07:12 PM UTC 24 |
| Finished | Sep 11 10:14:06 PM UTC 24 |
| Peak memory | 625516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=4011853960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_clkmgr_jitter_frequency.4011853960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.742978706 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 3469184274 ps |
| CPU time | 272.38 seconds |
| Started | Sep 11 10:15:52 PM UTC 24 |
| Finished | Sep 11 10:20:28 PM UTC 24 |
| Peak memory | 625716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkm gr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=742978706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.742978706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1933619242 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 3480191336 ps |
| CPU time | 294.19 seconds |
| Started | Sep 11 10:02:11 PM UTC 24 |
| Finished | Sep 11 10:07:09 PM UTC 24 |
| Peak memory | 625516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1933619242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.1933619242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.867490472 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 4491931432 ps |
| CPU time | 435.29 seconds |
| Started | Sep 11 10:02:58 PM UTC 24 |
| Finished | Sep 11 10:10:20 PM UTC 24 |
| Peak memory | 623524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=867490472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.867490472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1266395921 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 4478124026 ps |
| CPU time | 522.54 seconds |
| Started | Sep 11 10:03:54 PM UTC 24 |
| Finished | Sep 11 10:12:44 PM UTC 24 |
| Peak memory | 625924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1266395921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.chip_sw_clkmgr_off_otbn_trans.1266395921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_peri.1965254995 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 9210262340 ps |
| CPU time | 1290.03 seconds |
| Started | Sep 11 10:01:37 PM UTC 24 |
| Finished | Sep 11 10:23:24 PM UTC 24 |
| Peak memory | 625572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_i mages=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965254995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.1965254995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_reset_frequency.3938168957 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 3477698600 ps |
| CPU time | 340.18 seconds |
| Started | Sep 11 10:07:11 PM UTC 24 |
| Finished | Sep 11 10:12:56 PM UTC 24 |
| Peak memory | 625768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938168957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.3938168957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3836794986 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 4606735120 ps |
| CPU time | 554.9 seconds |
| Started | Sep 11 10:07:55 PM UTC 24 |
| Finished | Sep 11 10:17:18 PM UTC 24 |
| Peak memory | 625648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836794986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.3836794986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_smoketest.3253366886 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 2419024234 ps |
| CPU time | 328 seconds |
| Started | Sep 11 11:16:45 PM UTC 24 |
| Finished | Sep 11 11:22:18 PM UTC 24 |
| Peak memory | 623464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3253366886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_clkmgr_smoketest.3253366886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3688946541 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 4945232160 ps |
| CPU time | 518.97 seconds |
| Started | Sep 11 09:52:47 PM UTC 24 |
| Finished | Sep 11 10:01:34 PM UTC 24 |
| Peak memory | 625724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688946541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src _fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.3688946541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_kat_test.3717385372 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 3195140944 ps |
| CPU time | 369.62 seconds |
| Started | Sep 11 09:52:44 PM UTC 24 |
| Finished | Sep 11 09:59:00 PM UTC 24 |
| Peak memory | 623448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717385372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_csrng_kat_test.3717385372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_smoketest.2727600437 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 2872287748 ps |
| CPU time | 245.69 seconds |
| Started | Sep 11 11:19:00 PM UTC 24 |
| Finished | Sep 11 11:23:09 PM UTC 24 |
| Peak memory | 623556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2727600437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _csrng_smoketest.2727600437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.4137014811 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 6356953873 ps |
| CPU time | 1138.42 seconds |
| Started | Sep 11 09:54:26 PM UTC 24 |
| Finished | Sep 11 10:13:40 PM UTC 24 |
| Peak memory | 625908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137014811 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.4137014811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_kat.1487573471 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 3190647012 ps |
| CPU time | 608.32 seconds |
| Started | Sep 11 09:52:46 PM UTC 24 |
| Finished | Sep 11 10:03:04 PM UTC 24 |
| Peak memory | 631664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_a ssert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=1487573471 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_edn_kat.1487573471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_kat/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_sw_mode.2748171879 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 8557231984 ps |
| CPU time | 1629.91 seconds |
| Started | Sep 11 09:52:49 PM UTC 24 |
| Finished | Sep 11 10:20:20 PM UTC 24 |
| Peak memory | 623740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2748171879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_edn_sw_mode.2748171879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_ast_rng_req.4201865981 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 2576324056 ps |
| CPU time | 232.91 seconds |
| Started | Sep 11 09:53:36 PM UTC 24 |
| Finished | Sep 11 09:57:33 PM UTC 24 |
| Peak memory | 623612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201865981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.4201865981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_kat_test.1493586549 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 3066159600 ps |
| CPU time | 275.82 seconds |
| Started | Sep 11 09:51:17 PM UTC 24 |
| Finished | Sep 11 09:55:57 PM UTC 24 |
| Peak memory | 623460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493586549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.1493586549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_smoketest.3325971630 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 3703500832 ps |
| CPU time | 449.97 seconds |
| Started | Sep 11 11:19:00 PM UTC 24 |
| Finished | Sep 11 11:26:37 PM UTC 24 |
| Peak memory | 623668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_de vice=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325971630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.3325971630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.1593400015 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 2420617570 ps |
| CPU time | 209.68 seconds |
| Started | Sep 11 09:31:32 PM UTC 24 |
| Finished | Sep 11 09:35:05 PM UTC 24 |
| Peak memory | 623456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1593400015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_concurrency.1593400015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_flash.12963375 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 2688270772 ps |
| CPU time | 199.95 seconds |
| Started | Sep 11 09:30:09 PM UTC 24 |
| Finished | Sep 11 09:33:33 PM UTC 24 |
| Peak memory | 625512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=12963375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_sw_example_flash.12963375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_manufacturer.1635786819 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 2525866184 ps |
| CPU time | 162.21 seconds |
| Started | Sep 11 09:30:13 PM UTC 24 |
| Finished | Sep 11 09:32:58 PM UTC 24 |
| Peak memory | 625716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1635786819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ex ample_manufacturer.1635786819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_manufacturer/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_rom.2227862543 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 2332560550 ps |
| CPU time | 98.63 seconds |
| Started | Sep 11 09:28:28 PM UTC 24 |
| Finished | Sep 11 09:30:09 PM UTC 24 |
| Peak memory | 623280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:t est_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2227862543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_example_rom.2227862543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_crash_alert.3845411482 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 4769701148 ps |
| CPU time | 485.88 seconds |
| Started | Sep 11 10:16:06 PM UTC 24 |
| Finished | Sep 11 10:24:19 PM UTC 24 |
| Peak memory | 625912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check= 1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845411482 -assert nopostproc +UVM_TESTNAME=chip_base_test + UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.3845411482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access.1578889577 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 5908152120 ps |
| CPU time | 994.32 seconds |
| Started | Sep 11 09:32:08 PM UTC 24 |
| Finished | Sep 11 09:48:55 PM UTC 24 |
| Peak memory | 625640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1578889577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _flash_ctrl_access.1578889577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2045491695 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 6122529518 ps |
| CPU time | 859.4 seconds |
| Started | Sep 11 09:32:23 PM UTC 24 |
| Finished | Sep 11 09:46:54 PM UTC 24 |
| Peak memory | 623600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=2045491695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_flash_ctrl_access_jitter_en.2045491695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.226723492 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 7358949025 ps |
| CPU time | 922.67 seconds |
| Started | Sep 11 10:16:05 PM UTC 24 |
| Finished | Sep 11 10:31:40 PM UTC 24 |
| Peak memory | 623844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226723492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.226723492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3775173428 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 4952156384 ps |
| CPU time | 917.15 seconds |
| Started | Sep 11 09:32:11 PM UTC 24 |
| Finished | Sep 11 09:47:40 PM UTC 24 |
| Peak memory | 623688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=3775173428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_flash_ctrl_clock_freqs.3775173428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2072915528 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 3834111114 ps |
| CPU time | 392.33 seconds |
| Started | Sep 11 09:31:37 PM UTC 24 |
| Finished | Sep 11 09:38:16 PM UTC 24 |
| Peak memory | 625828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2072915528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_flash_ctrl_idle_low_power.2072915528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1312613790 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 5918354096 ps |
| CPU time | 1034.5 seconds |
| Started | Sep 11 10:22:54 PM UTC 24 |
| Finished | Sep 11 10:40:22 PM UTC 24 |
| Peak memory | 623588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1312613790 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_flash_ctrl_mem_protection.1312613790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.2759729272 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4478734600 ps |
| CPU time | 609.32 seconds |
| Started | Sep 11 09:31:13 PM UTC 24 |
| Finished | Sep 11 09:41:31 PM UTC 24 |
| Peak memory | 623732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759729272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.2759729272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2386360312 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 4714138428 ps |
| CPU time | 641.36 seconds |
| Started | Sep 11 09:31:50 PM UTC 24 |
| Finished | Sep 11 09:42:41 PM UTC 24 |
| Peak memory | 623520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386360312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.2386360312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_write_clear.803970425 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 3314042482 ps |
| CPU time | 261.78 seconds |
| Started | Sep 11 10:16:01 PM UTC 24 |
| Finished | Sep 11 10:20:27 PM UTC 24 |
| Peak memory | 623820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_image s=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803970425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.803970425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.2703488514 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 21855015048 ps |
| CPU time | 1580.02 seconds |
| Started | Sep 11 09:31:25 PM UTC 24 |
| Finished | Sep 11 09:58:06 PM UTC 24 |
| Peak memory | 627836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703488514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_flash_init.2703488514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_init/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_scrambling_smoketest.3598701466 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 2314005380 ps |
| CPU time | 177.88 seconds |
| Started | Sep 11 10:25:13 PM UTC 24 |
| Finished | Sep 11 10:28:14 PM UTC 24 |
| Peak memory | 623540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_ima ges=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoketest_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598701466 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chi p_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.3598701466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio_smoketest.815132847 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 3321658875 ps |
| CPU time | 326.45 seconds |
| Started | Sep 11 11:19:03 PM UTC 24 |
| Finished | Sep 11 11:24:35 PM UTC 24 |
| Peak memory | 623464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=815132847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_gpio_smoketest.815132847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc.769952520 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 2836167760 ps |
| CPU time | 286.92 seconds |
| Started | Sep 11 09:54:27 PM UTC 24 |
| Finished | Sep 11 09:59:19 PM UTC 24 |
| Peak memory | 625764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=769952520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hm ac_enc.769952520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.1263951643 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 2754252592 ps |
| CPU time | 270.95 seconds |
| Started | Sep 11 09:54:53 PM UTC 24 |
| Finished | Sep 11 09:59:29 PM UTC 24 |
| Peak memory | 623816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1263951643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_hmac_enc_idle.1263951643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.1273018372 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 2633094607 ps |
| CPU time | 277.95 seconds |
| Started | Sep 11 09:54:37 PM UTC 24 |
| Finished | Sep 11 09:59:20 PM UTC 24 |
| Peak memory | 623452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1273018372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.chip_sw_hmac_enc_jitter_en.1273018372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3392163527 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 3138446736 ps |
| CPU time | 243.18 seconds |
| Started | Sep 11 10:16:48 PM UTC 24 |
| Finished | Sep 11 10:20:55 PM UTC 24 |
| Peak memory | 623712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392163527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.3392163527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_multistream.1121793507 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 7161000368 ps |
| CPU time | 1527.06 seconds |
| Started | Sep 11 09:55:35 PM UTC 24 |
| Finished | Sep 11 10:21:23 PM UTC 24 |
| Peak memory | 623768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1121793507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_multistream.1121793507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_multistream/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_oneshot.4222135033 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 3172808400 ps |
| CPU time | 252.9 seconds |
| Started | Sep 11 09:55:12 PM UTC 24 |
| Finished | Sep 11 09:59:29 PM UTC 24 |
| Peak memory | 625656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4222135033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_h mac_oneshot.4222135033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_smoketest.1100209516 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 3745241598 ps |
| CPU time | 331.9 seconds |
| Started | Sep 11 11:19:20 PM UTC 24 |
| Finished | Sep 11 11:24:57 PM UTC 24 |
| Peak memory | 625508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=1100209516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ hmac_smoketest.1100209516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.1458923589 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 4808236354 ps |
| CPU time | 650.94 seconds |
| Started | Sep 11 09:32:24 PM UTC 24 |
| Finished | Sep 11 09:43:24 PM UTC 24 |
| Peak memory | 623736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1458923589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_i2c_host_tx_rx.1458923589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_inject_scramble_seed.263894146 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 68415013527 ps |
| CPU time | 15558 seconds |
| Started | Sep 11 09:30:25 PM UTC 24 |
| Finished | Sep 12 01:53:01 AM UTC 24 |
| Peak memory | 643284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=1 50_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263894146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.263894146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation.1766575435 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 8141957704 ps |
| CPU time | 1486.19 seconds |
| Started | Sep 11 09:55:59 PM UTC 24 |
| Finished | Sep 11 10:21:04 PM UTC 24 |
| Peak memory | 632012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766575435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key _derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.1766575435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.444095741 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 6823378619 ps |
| CPU time | 1000.16 seconds |
| Started | Sep 11 09:56:05 PM UTC 24 |
| Finished | Sep 11 10:12:59 PM UTC 24 |
| Peak memory | 631884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444095741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.444095741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4103050674 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 7682223852 ps |
| CPU time | 812.42 seconds |
| Started | Sep 11 10:17:16 PM UTC 24 |
| Finished | Sep 11 10:31:00 PM UTC 24 |
| Peak memory | 632128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103050674 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4103050674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1650221692 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 13469351540 ps |
| CPU time | 2864.93 seconds |
| Started | Sep 11 09:56:01 PM UTC 24 |
| Finished | Sep 11 10:44:22 PM UTC 24 |
| Peak memory | 634180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_devic e=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650221692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.1650221692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.306213571 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 13260513560 ps |
| CPU time | 2528.38 seconds |
| Started | Sep 11 09:56:06 PM UTC 24 |
| Finished | Sep 11 10:38:48 PM UTC 24 |
| Peak memory | 625856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306213571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sidel oad_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.306213571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_app_rom.324372462 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 2736207176 ps |
| CPU time | 316.98 seconds |
| Started | Sep 11 09:57:34 PM UTC 24 |
| Finished | Sep 11 10:02:57 PM UTC 24 |
| Peak memory | 625584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=324372462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_kmac_app_rom.324372462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_entropy.2968080354 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 3364888754 ps |
| CPU time | 282.57 seconds |
| Started | Sep 11 09:32:20 PM UTC 24 |
| Finished | Sep 11 09:37:07 PM UTC 24 |
| Peak memory | 625564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=2968080354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_kmac_entropy.2968080354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_idle.4253884747 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2465617852 ps |
| CPU time | 165.85 seconds |
| Started | Sep 11 09:57:41 PM UTC 24 |
| Finished | Sep 11 10:00:30 PM UTC 24 |
| Peak memory | 625744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=4253884747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ kmac_idle.4253884747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_cshake.1844502595 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 3242213616 ps |
| CPU time | 258.35 seconds |
| Started | Sep 11 09:56:32 PM UTC 24 |
| Finished | Sep 11 10:00:55 PM UTC 24 |
| Peak memory | 625796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1844502595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_sw_kmac_mode_cshake.1844502595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac.3996330642 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 3261647896 ps |
| CPU time | 324 seconds |
| Started | Sep 11 09:57:24 PM UTC 24 |
| Finished | Sep 11 10:02:54 PM UTC 24 |
| Peak memory | 625752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996330642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_kmac_mode_kmac.3996330642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2750695874 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 2528075346 ps |
| CPU time | 348.81 seconds |
| Started | Sep 11 09:57:35 PM UTC 24 |
| Finished | Sep 11 10:03:29 PM UTC 24 |
| Peak memory | 623692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_km ac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2750695874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.2750695874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2778119197 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 3642216906 ps |
| CPU time | 268.75 seconds |
| Started | Sep 11 10:17:35 PM UTC 24 |
| Finished | Sep 11 10:22:08 PM UTC 24 |
| Peak memory | 625904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778119197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2778119197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_smoketest.387803104 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 2605871180 ps |
| CPU time | 270.38 seconds |
| Started | Sep 11 11:20:29 PM UTC 24 |
| Finished | Sep 11 11:25:04 PM UTC 24 |
| Peak memory | 623600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=387803104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_k mac_smoketest.387803104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2230116578 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 3339903902 ps |
| CPU time | 335.91 seconds |
| Started | Sep 11 09:32:43 PM UTC 24 |
| Finished | Sep 11 09:38:24 PM UTC 24 |
| Peak memory | 623700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2230116578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.2230116578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2541709963 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 2848709181 ps |
| CPU time | 273.22 seconds |
| Started | Sep 11 09:36:58 PM UTC 24 |
| Finished | Sep 11 09:41:35 PM UTC 24 |
| Peak memory | 635820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541709963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.2541709963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.900151163 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3478169088 ps |
| CPU time | 140.75 seconds |
| Started | Sep 11 09:36:21 PM UTC 24 |
| Finished | Sep 11 09:38:44 PM UTC 24 |
| Peak memory | 635544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900151163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.900151163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.117968398 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 3336240750 ps |
| CPU time | 178.38 seconds |
| Started | Sep 11 09:37:27 PM UTC 24 |
| Finished | Sep 11 09:40:28 PM UTC 24 |
| Peak memory | 637400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTes tLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117968398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip _earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.117968398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3897266313 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2331664156 ps |
| CPU time | 138.57 seconds |
| Started | Sep 11 09:38:32 PM UTC 24 |
| Finished | Sep 11 09:40:54 PM UTC 24 |
| Peak memory | 633484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897266313 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.3897266313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.787395302 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 2441607575 ps |
| CPU time | 132.3 seconds |
| Started | Sep 11 09:39:19 PM UTC 24 |
| Finished | Sep 11 09:41:34 PM UTC 24 |
| Peak memory | 633424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSo urceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78739530 2 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ ctrl_volatile_raw_unlock_ext_clk_48mhz.787395302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_rma.2813045534 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 46658460863 ps |
| CPU time | 5955.52 seconds |
| Started | Sep 11 09:38:12 PM UTC 24 |
| Finished | Sep 11 11:18:42 PM UTC 24 |
| Peak memory | 643424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +fl ash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813045534 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_rma.2813045534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2983939706 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 24429140290 ps |
| CPU time | 1887.2 seconds |
| Started | Sep 11 09:38:55 PM UTC 24 |
| Finished | Sep 11 10:10:46 PM UTC 24 |
| Peak memory | 640252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnl ock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983939706 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testunlocks.2983939706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.559291905 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 16213940684 ps |
| CPU time | 3849 seconds |
| Started | Sep 11 09:45:07 PM UTC 24 |
| Finished | Sep 11 10:50:04 PM UTC 24 |
| Peak memory | 628956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559291905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.559291905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1826964 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 25335858637 ps |
| CPU time | 5036.67 seconds |
| Started | Sep 11 10:16:32 PM UTC 24 |
| Finished | Sep 11 11:41:31 PM UTC 24 |
| Peak memory | 628956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826964 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1826964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.763168718 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 3534758304 ps |
| CPU time | 473.27 seconds |
| Started | Sep 11 09:45:23 PM UTC 24 |
| Finished | Sep 11 09:53:23 PM UTC 24 |
| Peak memory | 625756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763168718 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.763168718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_randomness.326831725 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 5422098694 ps |
| CPU time | 876.95 seconds |
| Started | Sep 11 09:45:34 PM UTC 24 |
| Finished | Sep 11 10:00:23 PM UTC 24 |
| Peak memory | 625984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326831725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.326831725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_randomness/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_smoketest.301355981 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 8794821436 ps |
| CPU time | 1666.72 seconds |
| Started | Sep 11 11:20:34 PM UTC 24 |
| Finished | Sep 11 11:48:42 PM UTC 24 |
| Peak memory | 626016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=301355981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_o tbn_smoketest.301355981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_dai_lock.492033755 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 26060978490 ps |
| CPU time | 5914.25 seconds |
| Started | Sep 11 09:35:49 PM UTC 24 |
| Finished | Sep 11 11:15:37 PM UTC 24 |
| Peak memory | 628780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_i mages=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492033755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.492033755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.2179033171 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 3170775334 ps |
| CPU time | 284.85 seconds |
| Started | Sep 11 09:35:50 PM UTC 24 |
| Finished | Sep 11 09:40:40 PM UTC 24 |
| Peak memory | 625636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_ error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2179033171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.2179033171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1052876661 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 9043111534 ps |
| CPU time | 1140.49 seconds |
| Started | Sep 11 09:34:26 PM UTC 24 |
| Finished | Sep 11 09:53:42 PM UTC 24 |
| Peak memory | 625728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052876661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.1052876661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1231917382 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 9593478264 ps |
| CPU time | 1191.4 seconds |
| Started | Sep 11 09:34:30 PM UTC 24 |
| Finished | Sep 11 09:54:37 PM UTC 24 |
| Peak memory | 625700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_buil d_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231917382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.1231917382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3915980857 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 8134894718 ps |
| CPU time | 941.74 seconds |
| Started | Sep 11 09:34:35 PM UTC 24 |
| Finished | Sep 11 09:50:29 PM UTC 24 |
| Peak memory | 625648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915980857 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.3915980857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2120899591 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 4519210726 ps |
| CPU time | 691.14 seconds |
| Started | Sep 11 09:34:13 PM UTC 24 |
| Finished | Sep 11 09:45:54 PM UTC 24 |
| Peak memory | 623708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120899591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_ asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2120899591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_smoketest.3434423146 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 2699931180 ps |
| CPU time | 268.83 seconds |
| Started | Sep 11 11:20:34 PM UTC 24 |
| Finished | Sep 11 11:25:07 PM UTC 24 |
| Peak memory | 623452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3434423146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_otp_ctrl_smoketest.3434423146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.3490549301 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3054394762 ps |
| CPU time | 180.38 seconds |
| Started | Sep 11 09:30:05 PM UTC 24 |
| Finished | Sep 11 09:33:09 PM UTC 24 |
| Peak memory | 625780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_im ages=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490549301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.3490549301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pattgen_ios/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.1670814550 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 4693885470 ps |
| CPU time | 542.96 seconds |
| Started | Sep 11 10:22:52 PM UTC 24 |
| Finished | Sep 11 10:32:03 PM UTC 24 |
| Peak memory | 625560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670814550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_power_idle_load.1670814550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_sleep_load.1112719155 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 11158663216 ps |
| CPU time | 479.99 seconds |
| Started | Sep 11 10:20:33 PM UTC 24 |
| Finished | Sep 11 10:28:39 PM UTC 24 |
| Peak memory | 625700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1112719155 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.1112719155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.226996239 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 25927309294 ps |
| CPU time | 1756.52 seconds |
| Started | Sep 11 10:00:24 PM UTC 24 |
| Finished | Sep 11 10:30:03 PM UTC 24 |
| Peak memory | 625840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226996239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_res et_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.226996239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.403701411 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 15479547431 ps |
| CPU time | 1524.01 seconds |
| Started | Sep 11 09:40:35 PM UTC 24 |
| Finished | Sep 11 10:06:19 PM UTC 24 |
| Peak memory | 625784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403701411 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.403701411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3336968772 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 22969329928 ps |
| CPU time | 1798.71 seconds |
| Started | Sep 11 10:11:50 PM UTC 24 |
| Finished | Sep 11 10:42:13 PM UTC 24 |
| Peak memory | 625904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336968772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr _deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3336968772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1593555869 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 8031964776 ps |
| CPU time | 642.91 seconds |
| Started | Sep 11 09:40:36 PM UTC 24 |
| Finished | Sep 11 09:51:28 PM UTC 24 |
| Peak memory | 625704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_res et_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1593555869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.1593555869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1982535835 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 7077163368 ps |
| CPU time | 581.18 seconds |
| Started | Sep 11 09:45:26 PM UTC 24 |
| Finished | Sep 11 09:55:16 PM UTC 24 |
| Peak memory | 631816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982535835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1982535835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2876403169 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 6505928390 ps |
| CPU time | 287.78 seconds |
| Started | Sep 11 09:39:46 PM UTC 24 |
| Finished | Sep 11 09:44:39 PM UTC 24 |
| Peak memory | 625704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2876403169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.chip_sw_pwrmgr_full_aon_reset.2876403169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3039326133 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 11704430723 ps |
| CPU time | 1191.1 seconds |
| Started | Sep 11 09:40:35 PM UTC 24 |
| Finished | Sep 11 10:00:42 PM UTC 24 |
| Peak memory | 626028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_r eset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3039326133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3039326133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2730463811 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 7153992524 ps |
| CPU time | 623.57 seconds |
| Started | Sep 11 09:43:54 PM UTC 24 |
| Finished | Sep 11 09:54:26 PM UTC 24 |
| Peak memory | 625812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_r eset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2730463811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.2730463811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.427606226 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 23594388996 ps |
| CPU time | 2645.89 seconds |
| Started | Sep 11 09:39:46 PM UTC 24 |
| Finished | Sep 11 10:24:27 PM UTC 24 |
| Peak memory | 626024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427606226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_ asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.427606226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1058759190 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 2418176178 ps |
| CPU time | 173.67 seconds |
| Started | Sep 11 09:42:22 PM UTC 24 |
| Finished | Sep 11 09:45:19 PM UTC 24 |
| Peak memory | 623604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1058759190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.chip_sw_pwrmgr_sleep_disabled.1058759190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1374332729 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 5111232904 ps |
| CPU time | 395.05 seconds |
| Started | Sep 11 10:11:31 PM UTC 24 |
| Finished | Sep 11 10:18:12 PM UTC 24 |
| Peak memory | 625772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374332729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.1374332729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_smoketest.3688369306 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 6187907000 ps |
| CPU time | 427.98 seconds |
| Started | Sep 11 11:21:14 PM UTC 24 |
| Finished | Sep 11 11:28:28 PM UTC 24 |
| Peak memory | 625640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_ima ges=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688369306 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.3688369306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.582686723 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 7998813273 ps |
| CPU time | 941.06 seconds |
| Started | Sep 11 09:39:46 PM UTC 24 |
| Finished | Sep 11 09:55:41 PM UTC 24 |
| Peak memory | 625584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=582686723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.582686723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2419911445 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 3795310566 ps |
| CPU time | 343.18 seconds |
| Started | Sep 11 09:43:46 PM UTC 24 |
| Finished | Sep 11 09:49:35 PM UTC 24 |
| Peak memory | 625736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_w hen_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2419911445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2419911445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3780258723 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 5827000932 ps |
| CPU time | 471.98 seconds |
| Started | Sep 11 11:21:14 PM UTC 24 |
| Finished | Sep 11 11:29:13 PM UTC 24 |
| Peak memory | 625876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3780258723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_pwrmgr_usbdev_smoketest.3780258723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2891653696 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 3818349832 ps |
| CPU time | 505.78 seconds |
| Started | Sep 11 09:45:30 PM UTC 24 |
| Finished | Sep 11 09:54:02 PM UTC 24 |
| Peak memory | 623596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891653696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.2891653696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3048809716 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 9534407089 ps |
| CPU time | 506.23 seconds |
| Started | Sep 11 09:57:42 PM UTC 24 |
| Finished | Sep 11 10:06:15 PM UTC 24 |
| Peak memory | 625836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3048809716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.3048809716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.4113914447 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 5835929336 ps |
| CPU time | 721.68 seconds |
| Started | Sep 11 09:31:00 PM UTC 24 |
| Finished | Sep 11 09:43:12 PM UTC 24 |
| Peak memory | 670216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113914447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr _cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.4113914447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_smoketest.4176577519 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 3428743772 ps |
| CPU time | 266.56 seconds |
| Started | Sep 11 11:23:01 PM UTC 24 |
| Finished | Sep 11 11:27:31 PM UTC 24 |
| Peak memory | 623656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=4176577519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_rstmgr_smoketest.4176577519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_req.1269741253 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 4355296360 ps |
| CPU time | 381.33 seconds |
| Started | Sep 11 09:38:45 PM UTC 24 |
| Finished | Sep 11 09:45:12 PM UTC 24 |
| Peak memory | 623756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1269741253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_rstmgr_sw_req.1269741253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.1150811196 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 2904865400 ps |
| CPU time | 224.95 seconds |
| Started | Sep 11 09:39:10 PM UTC 24 |
| Finished | Sep 11 09:42:59 PM UTC 24 |
| Peak memory | 623704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1150811196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_rstmgr_sw_rst.1150811196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3847105099 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2988650647 ps |
| CPU time | 250.51 seconds |
| Started | Sep 11 10:14:44 PM UTC 24 |
| Finished | Sep 11 10:18:59 PM UTC 24 |
| Peak memory | 625640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_inval idate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3847105099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.3847105099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_rnd.199859888 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 5350099856 ps |
| CPU time | 938.82 seconds |
| Started | Sep 11 09:46:12 PM UTC 24 |
| Finished | Sep 11 10:02:03 PM UTC 24 |
| Peak memory | 623712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_b uild_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199859888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.199859888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1563464137 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 6438720198 ps |
| CPU time | 558.07 seconds |
| Started | Sep 11 10:12:00 PM UTC 24 |
| Finished | Sep 11 10:21:26 PM UTC 24 |
| Peak memory | 635964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_acc ess_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563464137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wak eup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.1563464137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2468877127 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 3886387922 ps |
| CPU time | 388.05 seconds |
| Started | Sep 11 10:12:01 PM UTC 24 |
| Finished | Sep 11 10:18:35 PM UTC 24 |
| Peak memory | 637932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm _reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468877127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_re set_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asi c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2468877127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_plic_smoketest.2802201401 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 3153001110 ps |
| CPU time | 274.09 seconds |
| Started | Sep 11 11:22:00 PM UTC 24 |
| Finished | Sep 11 11:26:38 PM UTC 24 |
| Peak memory | 625508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=2802201401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_rv_plic_smoketest.2802201401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_irq.2485652586 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 2601502306 ps |
| CPU time | 194.61 seconds |
| Started | Sep 11 09:43:20 PM UTC 24 |
| Finished | Sep 11 09:46:38 PM UTC 24 |
| Peak memory | 625684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2485652586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_rv_timer_irq.2485652586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_smoketest.4293986238 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 3460817206 ps |
| CPU time | 271.46 seconds |
| Started | Sep 11 11:23:00 PM UTC 24 |
| Finished | Sep 11 11:27:36 PM UTC 24 |
| Peak memory | 625672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=4293986238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_rv_timer_smoketest.4293986238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pwm_pulses.1548353930 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8886680696 ps |
| CPU time | 1263.82 seconds |
| Started | Sep 11 09:28:51 PM UTC 24 |
| Finished | Sep 11 09:50:12 PM UTC 24 |
| Peak memory | 628888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1548353930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_sleep_pwm_pulses.1548353930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.58163634 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 7054720472 ps |
| CPU time | 737.4 seconds |
| Started | Sep 11 09:58:42 PM UTC 24 |
| Finished | Sep 11 10:11:10 PM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58163634 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_sram_ret_contents_n o_scramble.58163634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1436340141 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 6637200992 ps |
| CPU time | 464.82 seconds |
| Started | Sep 11 09:59:35 PM UTC 24 |
| Finished | Sep 11 10:07:27 PM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436340141 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_sram_ret_contents_sc ramble.1436340141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through.75284153 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6150887848 ps |
| CPU time | 556.62 seconds |
| Started | Sep 11 09:32:37 PM UTC 24 |
| Finished | Sep 11 09:42:02 PM UTC 24 |
| Peak memory | 640176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75284153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 0.chip_sw_spi_device_pass_through.75284153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.3346106088 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4681108573 ps |
| CPU time | 518.29 seconds |
| Started | Sep 11 09:32:40 PM UTC 24 |
| Finished | Sep 11 09:41:25 PM UTC 24 |
| Peak memory | 640424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346106088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.3346106088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1108180983 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 5283921456 ps |
| CPU time | 691.73 seconds |
| Started | Sep 11 09:57:42 PM UTC 24 |
| Finished | Sep 11 10:09:24 PM UTC 24 |
| Peak memory | 625840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108180983 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_ access.1108180983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.648277959 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 4036029725 ps |
| CPU time | 406.57 seconds |
| Started | Sep 11 10:17:55 PM UTC 24 |
| Finished | Sep 11 10:24:48 PM UTC 24 |
| Peak memory | 625784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_r eady_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648277959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.648277959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_smoketest.3926786448 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 2402431858 ps |
| CPU time | 316.41 seconds |
| Started | Sep 11 11:23:49 PM UTC 24 |
| Finished | Sep 11 11:29:10 PM UTC 24 |
| Peak memory | 625508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926786448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_sram_ctrl_smoketest.3926786448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_inputs.209868842 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2890821278 ps |
| CPU time | 322.71 seconds |
| Started | Sep 11 09:43:31 PM UTC 24 |
| Finished | Sep 11 09:49:00 PM UTC 24 |
| Peak memory | 628036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=209868842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_sysrst_ctrl_inputs.209868842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.4280221088 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 2993149860 ps |
| CPU time | 302.31 seconds |
| Started | Sep 11 09:44:55 PM UTC 24 |
| Finished | Sep 11 09:50:03 PM UTC 24 |
| Peak memory | 625640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=4280221088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_sysrst_ctrl_outputs.4280221088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.1792514389 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 24247119132 ps |
| CPU time | 1950.99 seconds |
| Started | Sep 11 09:43:45 PM UTC 24 |
| Finished | Sep 11 10:16:41 PM UTC 24 |
| Peak memory | 629928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_i mages=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792514389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.1792514389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_rand_baudrate.2153832450 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 13721940000 ps |
| CPU time | 2434.2 seconds |
| Started | Sep 11 09:32:23 PM UTC 24 |
| Finished | Sep 11 10:13:28 PM UTC 24 |
| Peak memory | 639040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153832450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.2153832450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_smoketest.3614190500 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 3306338920 ps |
| CPU time | 306.94 seconds |
| Started | Sep 11 11:25:13 PM UTC 24 |
| Finished | Sep 11 11:30:24 PM UTC 24 |
| Peak memory | 623464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3614190500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch ip_sw_uart_smoketest.3614190500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3976031324 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 7558287812 ps |
| CPU time | 1384.62 seconds |
| Started | Sep 11 09:31:14 PM UTC 24 |
| Finished | Sep 11 09:54:37 PM UTC 24 |
| Peak memory | 636092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976031324 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_alt_clk_freq.3976031324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.4219735322 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 81199921156 ps |
| CPU time | 19028.6 seconds |
| Started | Sep 11 09:29:57 PM UTC 24 |
| Finished | Sep 12 02:51:03 AM UTC 24 |
| Peak memory | 655780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout _ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219735322 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.4219735322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.3982670363 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4071592862 ps |
| CPU time | 571.84 seconds |
| Started | Sep 11 09:32:17 PM UTC 24 |
| Finished | Sep 11 09:41:57 PM UTC 24 |
| Peak memory | 640180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982670363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.3982670363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usb_ast_clk_calib.618641868 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 3340443085 ps |
| CPU time | 336.31 seconds |
| Started | Sep 11 10:14:59 PM UTC 24 |
| Finished | Sep 11 10:20:41 PM UTC 24 |
| Peak memory | 625796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw _images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618641868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.618641868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.3785882176 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 7864935800 ps |
| CPU time | 1504.02 seconds |
| Started | Sep 11 09:31:22 PM UTC 24 |
| Finished | Sep 11 09:56:46 PM UTC 24 |
| Peak memory | 623528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785882176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.3785882176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_dpi.971862307 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11598731990 ps |
| CPU time | 2935.8 seconds |
| Started | Sep 11 09:32:01 PM UTC 24 |
| Finished | Sep 11 10:21:35 PM UTC 24 |
| Peak memory | 626656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_ 000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971862307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.971862307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pincfg.3725166548 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 31527463200 ps |
| CPU time | 8440.68 seconds |
| Started | Sep 11 09:31:41 PM UTC 24 |
| Finished | Sep 11 11:54:03 PM UTC 24 |
| Peak memory | 628584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000 _000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725166548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlg rey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.3725166548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.1228623099 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 2315534638 ps |
| CPU time | 260.66 seconds |
| Started | Sep 11 09:32:40 PM UTC 24 |
| Finished | Sep 11 09:37:05 PM UTC 24 |
| Peak memory | 623636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228623099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.1228623099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_stream.2071666930 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 19184420144 ps |
| CPU time | 4628.7 seconds |
| Started | Sep 11 09:32:38 PM UTC 24 |
| Finished | Sep 11 10:50:45 PM UTC 24 |
| Peak memory | 628572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_ 000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071666930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_ear lgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.2071666930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_stream/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_vbus.115977236 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3073696618 ps |
| CPU time | 250.73 seconds |
| Started | Sep 11 09:31:48 PM UTC 24 |
| Finished | Sep 11 09:36:03 PM UTC 24 |
| Peak memory | 623708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115977236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.115977236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.963025943 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 4180585461 ps |
| CPU time | 383.29 seconds |
| Started | Sep 11 10:12:59 PM UTC 24 |
| Finished | Sep 11 10:19:29 PM UTC 24 |
| Peak memory | 650472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963025943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.963025943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_prod.1053431474 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 18919660831 ps |
| CPU time | 1793.05 seconds |
| Started | Sep 11 10:13:32 PM UTC 24 |
| Finished | Sep 11 10:43:49 PM UTC 24 |
| Peak memory | 640436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053431474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.1053431474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.3619865428 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 5285839509 ps |
| CPU time | 453.63 seconds |
| Started | Sep 11 10:13:32 PM UTC 24 |
| Finished | Sep 11 10:21:13 PM UTC 24 |
| Peak memory | 640364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619865428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_tap_straps_rma.3619865428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_dev.3227854437 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 15370958572 ps |
| CPU time | 4891.86 seconds |
| Started | Sep 11 10:36:37 PM UTC 24 |
| Finished | Sep 11 11:59:10 PM UTC 24 |
| Peak memory | 623840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227854437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.3227854437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod.3441226969 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 15432340236 ps |
| CPU time | 4059.15 seconds |
| Started | Sep 11 10:37:23 PM UTC 24 |
| Finished | Sep 11 11:45:53 PM UTC 24 |
| Peak memory | 623832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441226969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.3441226969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod_end.742816516 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 15856502371 ps |
| CPU time | 4138.6 seconds |
| Started | Sep 11 10:39:35 PM UTC 24 |
| Finished | Sep 11 11:49:26 PM UTC 24 |
| Peak memory | 623844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742816 516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_ini t_prod_end.742816516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_rma.3547813646 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 15432392165 ps |
| CPU time | 4366.07 seconds |
| Started | Sep 11 10:41:08 PM UTC 24 |
| Finished | Sep 11 11:54:48 PM UTC 24 |
| Peak memory | 623836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547813646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.3547813646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_test_unlocked0.731813122 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 11445090632 ps |
| CPU time | 3234.91 seconds |
| Started | Sep 11 10:32:49 PM UTC 24 |
| Finished | Sep 11 11:27:25 PM UTC 24 |
| Peak memory | 623844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=731813122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2 e_asm_init_test_unlocked0.731813122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1836977558 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 24296337784 ps |
| CPU time | 7514.81 seconds |
| Started | Sep 11 10:25:30 PM UTC 24 |
| Finished | Sep 12 12:32:18 AM UTC 24 |
| Peak memory | 627032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836977558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1836977558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.734610620 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 24036273456 ps |
| CPU time | 7351.57 seconds |
| Started | Sep 11 10:27:50 PM UTC 24 |
| Finished | Sep 12 12:31:52 AM UTC 24 |
| Peak memory | 626908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734610620 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.734610620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2855106675 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 23174919704 ps |
| CPU time | 7652.51 seconds |
| Started | Sep 11 10:27:26 PM UTC 24 |
| Finished | Sep 12 12:36:33 AM UTC 24 |
| Peak memory | 627024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855106675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2855106675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.4023899917 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 18627528696 ps |
| CPU time | 5905.14 seconds |
| Started | Sep 11 10:26:37 PM UTC 24 |
| Finished | Sep 12 12:06:14 AM UTC 24 |
| Peak memory | 628844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023899917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.4023899917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1184655202 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 15703701400 ps |
| CPU time | 3988.39 seconds |
| Started | Sep 11 10:25:46 PM UTC 24 |
| Finished | Sep 11 11:33:02 PM UTC 24 |
| Peak memory | 625896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184655202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1184655202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2821798171 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 15718091620 ps |
| CPU time | 4315.03 seconds |
| Started | Sep 11 10:26:28 PM UTC 24 |
| Finished | Sep 11 11:39:15 PM UTC 24 |
| Peak memory | 623932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821798171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2821798171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.883939964 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 16089185632 ps |
| CPU time | 4330.58 seconds |
| Started | Sep 11 10:28:27 PM UTC 24 |
| Finished | Sep 11 11:41:32 PM UTC 24 |
| Peak memory | 623792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883939964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.883939964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3155142457 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 14761339550 ps |
| CPU time | 4035.74 seconds |
| Started | Sep 11 10:26:49 PM UTC 24 |
| Finished | Sep 11 11:34:55 PM UTC 24 |
| Peak memory | 623952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155142457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3155142457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2111536114 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 11545567000 ps |
| CPU time | 3498.9 seconds |
| Started | Sep 11 10:29:16 PM UTC 24 |
| Finished | Sep 11 11:28:20 PM UTC 24 |
| Peak memory | 623780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111536114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2111536114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1580480835 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 15664221272 ps |
| CPU time | 4271.37 seconds |
| Started | Sep 11 10:25:26 PM UTC 24 |
| Finished | Sep 11 11:37:31 PM UTC 24 |
| Peak memory | 626792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580480835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1580480835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.493160140 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 15983845560 ps |
| CPU time | 4274.5 seconds |
| Started | Sep 11 10:25:16 PM UTC 24 |
| Finished | Sep 11 11:37:22 PM UTC 24 |
| Peak memory | 626924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493160140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.493160140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1932523004 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 15433553620 ps |
| CPU time | 4644.27 seconds |
| Started | Sep 11 10:24:24 PM UTC 24 |
| Finished | Sep 11 11:42:48 PM UTC 24 |
| Peak memory | 628884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932523004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1932523004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1097272916 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 14583847440 ps |
| CPU time | 4089.23 seconds |
| Started | Sep 11 10:24:26 PM UTC 24 |
| Finished | Sep 11 11:33:26 PM UTC 24 |
| Peak memory | 628840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097272916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1097272916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.248453074 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 10979058138 ps |
| CPU time | 3222.78 seconds |
| Started | Sep 11 10:25:13 PM UTC 24 |
| Finished | Sep 11 11:19:36 PM UTC 24 |
| Peak memory | 625968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248453074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.248453074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_rma.316848663 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 11333787886 ps |
| CPU time | 2330.29 seconds |
| Started | Sep 11 10:42:49 PM UTC 24 |
| Finished | Sep 11 11:22:11 PM UTC 24 |
| Peak memory | 640280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_devic e=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316848663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag _debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.316848663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3827128655 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 12334391333 ps |
| CPU time | 2143.68 seconds |
| Started | Sep 11 10:41:53 PM UTC 24 |
| Finished | Sep 11 11:18:07 PM UTC 24 |
| Peak memory | 636180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_devic e=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827128655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.3827128655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_dev.3993479846 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 31798921398 ps |
| CPU time | 4337.35 seconds |
| Started | Sep 11 10:44:58 PM UTC 24 |
| Finished | Sep 11 11:58:11 PM UTC 24 |
| Peak memory | 635556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_imag e=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993479846 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.3993479846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_rma.1718469660 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 41844055699 ps |
| CPU time | 3299.79 seconds |
| Started | Sep 11 10:46:50 PM UTC 24 |
| Finished | Sep 11 11:42:31 PM UTC 24 |
| Peak memory | 635496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_imag e=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718469660 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.1718469660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.324329760 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 31979028376 ps |
| CPU time | 2864.81 seconds |
| Started | Sep 11 10:44:29 PM UTC 24 |
| Finished | Sep 11 11:32:48 PM UTC 24 |
| Peak memory | 635572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_imag e=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324329760 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_test_unlocked0.324329760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1644572209 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 14531609144 ps |
| CPU time | 4075.14 seconds |
| Started | Sep 11 11:00:36 PM UTC 24 |
| Finished | Sep 12 12:09:25 AM UTC 24 |
| Peak memory | 624756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644572209 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1644572209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1890919134 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 15506014720 ps |
| CPU time | 4124.91 seconds |
| Started | Sep 11 10:51:32 PM UTC 24 |
| Finished | Sep 12 12:01:08 AM UTC 24 |
| Peak memory | 623712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890919134 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.1890919134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.4160673543 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 14993392734 ps |
| CPU time | 4099.47 seconds |
| Started | Sep 11 10:57:11 PM UTC 24 |
| Finished | Sep 12 12:06:22 AM UTC 24 |
| Peak memory | 625988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160673543 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_no_meas.4160673543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_self_hash.40549759 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 26626933344 ps |
| CPU time | 7239.17 seconds |
| Started | Sep 11 11:10:20 PM UTC 24 |
| Finished | Sep 12 01:12:31 AM UTC 24 |
| Peak memory | 628756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_rules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40549759 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.40549759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_exception_c.349522210 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 14266908576 ps |
| CPU time | 4264.91 seconds |
| Started | Sep 11 10:25:19 PM UTC 24 |
| Finished | Sep 11 11:37:17 PM UTC 24 |
| Peak memory | 627000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349522210 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_exception_c.349522210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.449150207 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 23423857669 ps |
| CPU time | 6782.07 seconds |
| Started | Sep 11 10:26:21 PM UTC 24 |
| Finished | Sep 12 12:20:47 AM UTC 24 |
| Peak memory | 626776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_fla sh_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449150207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.449150207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1237143713 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 24146248580 ps |
| CPU time | 6823.58 seconds |
| Started | Sep 11 10:29:28 PM UTC 24 |
| Finished | Sep 12 12:24:34 AM UTC 24 |
| Peak memory | 627028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_fl ash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237143713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1237143713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2211008136 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 24399485560 ps |
| CPU time | 6561.53 seconds |
| Started | Sep 11 10:29:04 PM UTC 24 |
| Finished | Sep 12 12:19:44 AM UTC 24 |
| Peak memory | 626772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_fl ash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211008136 -assert nopostproc +UVM_TESTNAME=chip_base_test + UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2211008136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.4032417658 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 22641033590 ps |
| CPU time | 7036.32 seconds |
| Started | Sep 11 10:29:04 PM UTC 24 |
| Finished | Sep 12 12:27:48 AM UTC 24 |
| Peak memory | 627008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_fl ash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032417658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_rma.4032417658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.387563669 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 18153721040 ps |
| CPU time | 5763.79 seconds |
| Started | Sep 11 10:27:54 PM UTC 24 |
| Finished | Sep 12 12:05:09 AM UTC 24 |
| Peak memory | 627004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_fl ash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387563669 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.387563669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3623432858 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 14564340401 ps |
| CPU time | 3966.77 seconds |
| Started | Sep 11 10:28:38 PM UTC 24 |
| Finished | Sep 11 11:35:34 PM UTC 24 |
| Peak memory | 626076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3623432858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3623432858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3131105568 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 14595568869 ps |
| CPU time | 3987.18 seconds |
| Started | Sep 11 10:29:03 PM UTC 24 |
| Finished | Sep 11 11:36:19 PM UTC 24 |
| Peak memory | 623932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4 ,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3131105568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3131105568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2483079776 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 14251139672 ps |
| CPU time | 4141.67 seconds |
| Started | Sep 11 10:29:40 PM UTC 24 |
| Finished | Sep 11 11:39:32 PM UTC 24 |
| Peak memory | 623960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2483079776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2483079776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3441369894 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 11896178841 ps |
| CPU time | 3179.86 seconds |
| Started | Sep 11 10:27:40 PM UTC 24 |
| Finished | Sep 11 11:21:20 PM UTC 24 |
| Peak memory | 624092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_ test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3441369894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3441369894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.183063323 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 15562486830 ps |
| CPU time | 4280.06 seconds |
| Started | Sep 11 10:30:46 PM UTC 24 |
| Finished | Sep 11 11:43:01 PM UTC 24 |
| Peak memory | 623784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=183063323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.183063323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1480578565 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 15335876930 ps |
| CPU time | 3917.2 seconds |
| Started | Sep 11 10:31:55 PM UTC 24 |
| Finished | Sep 11 11:37:59 PM UTC 24 |
| Peak memory | 623924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mas k_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1480578565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1480578565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1768303086 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 14809482702 ps |
| CPU time | 3914.75 seconds |
| Started | Sep 11 10:31:55 PM UTC 24 |
| Finished | Sep 11 11:37:59 PM UTC 24 |
| Peak memory | 624032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4 ,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1768303086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1768303086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.380320973 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 14553148328 ps |
| CPU time | 4026.53 seconds |
| Started | Sep 11 10:32:24 PM UTC 24 |
| Finished | Sep 11 11:40:21 PM UTC 24 |
| Peak memory | 623784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=380320973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.380320973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.412386110 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 10917725185 ps |
| CPU time | 2950.92 seconds |
| Started | Sep 11 10:29:43 PM UTC 24 |
| Finished | Sep 11 11:19:30 PM UTC 24 |
| Peak memory | 623916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unloc ked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412386110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.412386110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_smoke.4009028309 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 14816140300 ps |
| CPU time | 3984.67 seconds |
| Started | Sep 11 10:22:29 PM UTC 24 |
| Finished | Sep 11 11:29:42 PM UTC 24 |
| Peak memory | 628756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009028309 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.4009028309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.880726032 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 17479835458 ps |
| CPU time | 5168.02 seconds |
| Started | Sep 11 10:50:50 PM UTC 24 |
| Finished | Sep 12 12:18:03 AM UTC 24 |
| Peak memory | 629064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880726032 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.880726032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_keymgr_functest.3820879991 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 5085102700 ps |
| CPU time | 596.17 seconds |
| Started | Sep 11 11:10:20 PM UTC 24 |
| Finished | Sep 11 11:20:25 PM UTC 24 |
| Peak memory | 625836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820879991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 0.rom_keymgr_functest.3820879991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_keymgr_functest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_raw_unlock.2499992891 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 4876783382 ps |
| CPU time | 347.19 seconds |
| Started | Sep 11 11:10:15 PM UTC 24 |
| Finished | Sep 11 11:16:08 PM UTC 24 |
| Peak memory | 637592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images =empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499992891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.2499992891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_volatile_raw_unlock.692179747 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 2769263241 ps |
| CPU time | 131.36 seconds |
| Started | Sep 11 11:09:20 PM UTC 24 |
| Finished | Sep 11 11:11:34 PM UTC 24 |
| Peak memory | 633504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRa w +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot _flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=692179747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.692179747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.4279136355 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 18758080728 ps |
| CPU time | 2168 seconds |
| Started | Sep 12 12:27:16 AM UTC 24 |
| Finished | Sep 12 01:03:51 AM UTC 24 |
| Peak memory | 623788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427913 6355 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_csr_rw.4279136355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.1837848674 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 13066343333 ps |
| CPU time | 1190.5 seconds |
| Started | Sep 12 12:27:28 AM UTC 24 |
| Finished | Sep 12 12:47:34 AM UTC 24 |
| Peak memory | 623148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837848674 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.1837848674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_jtag_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.3785772964 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 4587117992 ps |
| CPU time | 376.69 seconds |
| Started | Sep 12 12:30:50 AM UTC 24 |
| Finished | Sep 12 12:37:12 AM UTC 24 |
| Peak memory | 635904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785772964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_ reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.3785772964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sival_flash_info_access.2574558063 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 2617986552 ps |
| CPU time | 315.28 seconds |
| Started | Sep 11 11:27:28 PM UTC 24 |
| Finished | Sep 11 11:32:49 PM UTC 24 |
| Peak memory | 625588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim _dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574558063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.2574558063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sival_flash_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2799432810 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 18540241388 ps |
| CPU time | 436.23 seconds |
| Started | Sep 11 11:57:29 PM UTC 24 |
| Finished | Sep 12 12:04:52 AM UTC 24 |
| Peak memory | 635880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799432810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/c hip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2799432810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.1547894960 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 3103247080 ps |
| CPU time | 319.54 seconds |
| Started | Sep 12 12:00:08 AM UTC 24 |
| Finished | Sep 12 12:05:33 AM UTC 24 |
| Peak memory | 623704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_i mages=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547894960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.1547894960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.3141476296 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 2390810781 ps |
| CPU time | 198.54 seconds |
| Started | Sep 12 12:00:44 AM UTC 24 |
| Finished | Sep 12 12:04:06 AM UTC 24 |
| Peak memory | 623528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141476296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.3141476296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3938507679 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 2860598375 ps |
| CPU time | 212.73 seconds |
| Started | Sep 12 12:35:43 AM UTC 24 |
| Finished | Sep 12 12:39:19 AM UTC 24 |
| Peak memory | 623680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938507679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.3938507679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.1973198635 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 3191454470 ps |
| CPU time | 283.97 seconds |
| Started | Sep 12 12:06:12 AM UTC 24 |
| Finished | Sep 12 12:11:01 AM UTC 24 |
| Peak memory | 625772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973198635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_aes_entropy.1973198635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.795173819 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 2634916516 ps |
| CPU time | 229.45 seconds |
| Started | Sep 12 12:01:05 AM UTC 24 |
| Finished | Sep 12 12:05:00 AM UTC 24 |
| Peak memory | 625576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=795173819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.795173819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.3763580938 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 3297433223 ps |
| CPU time | 330.76 seconds |
| Started | Sep 12 12:02:17 AM UTC 24 |
| Finished | Sep 12 12:07:53 AM UTC 24 |
| Peak memory | 623572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763580938 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_aes_masking_off.3763580938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_masking_off/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.2230790839 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 2863967944 ps |
| CPU time | 343.51 seconds |
| Started | Sep 12 12:42:58 AM UTC 24 |
| Finished | Sep 12 12:48:47 AM UTC 24 |
| Peak memory | 623516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2230790839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_a es_smoketest.2230790839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.398823073 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 3415629698 ps |
| CPU time | 273.87 seconds |
| Started | Sep 12 12:05:12 AM UTC 24 |
| Finished | Sep 12 12:09:50 AM UTC 24 |
| Peak memory | 625648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398823073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.398823073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.1252061249 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 4412514280 ps |
| CPU time | 480.36 seconds |
| Started | Sep 12 12:02:35 AM UTC 24 |
| Finished | Sep 12 12:10:42 AM UTC 24 |
| Peak memory | 636132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252061249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_ earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.1252061249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2408099128 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 8793510872 ps |
| CPU time | 1648.58 seconds |
| Started | Sep 12 12:04:31 AM UTC 24 |
| Finished | Sep 12 12:32:21 AM UTC 24 |
| Peak memory | 625568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408099128 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_ea rlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.2408099128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.872708584 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 9144826920 ps |
| CPU time | 1691.03 seconds |
| Started | Sep 12 12:04:45 AM UTC 24 |
| Finished | Sep 12 12:33:19 AM UTC 24 |
| Peak memory | 625572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872708584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_toggle.872708584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2142935334 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 10239285376 ps |
| CPU time | 1004.94 seconds |
| Started | Sep 12 12:04:08 AM UTC 24 |
| Finished | Sep 12 12:21:07 AM UTC 24 |
| Peak memory | 625652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142935334 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_hand ler_lpg_sleep_mode_pings.2142935334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.3712729689 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 7958762380 ps |
| CPU time | 1444.7 seconds |
| Started | Sep 12 12:02:39 AM UTC 24 |
| Finished | Sep 12 12:27:03 AM UTC 24 |
| Peak memory | 623536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712729689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.3712729689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_timeout.966128033 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 4327775530 ps |
| CPU time | 405.57 seconds |
| Started | Sep 12 12:02:24 AM UTC 24 |
| Finished | Sep 12 12:09:16 AM UTC 24 |
| Peak memory | 625812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966128033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.966128033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.315553361 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 3228863288 ps |
| CPU time | 344.09 seconds |
| Started | Sep 12 12:02:19 AM UTC 24 |
| Finished | Sep 12 12:08:08 AM UTC 24 |
| Peak memory | 623604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand om_seed=315553361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert _test.315553361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.3289585033 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 3793631288 ps |
| CPU time | 364.8 seconds |
| Started | Sep 11 11:55:48 PM UTC 24 |
| Finished | Sep 12 12:01:59 AM UTC 24 |
| Peak memory | 625500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289585033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.3289585033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1613813919 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 7793454618 ps |
| CPU time | 513.68 seconds |
| Started | Sep 11 11:55:53 PM UTC 24 |
| Finished | Sep 12 12:04:34 AM UTC 24 |
| Peak memory | 623596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613813919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1613813919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.1044479816 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 3238963096 ps |
| CPU time | 331.22 seconds |
| Started | Sep 12 12:42:57 AM UTC 24 |
| Finished | Sep 12 12:48:33 AM UTC 24 |
| Peak memory | 623632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044479816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_aon_timer_smoketest.1044479816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1656480212 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 8848480280 ps |
| CPU time | 745.5 seconds |
| Started | Sep 11 11:57:24 PM UTC 24 |
| Finished | Sep 12 12:10:00 AM UTC 24 |
| Peak memory | 625916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656480212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.1656480212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1301573765 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 5107005490 ps |
| CPU time | 671.6 seconds |
| Started | Sep 11 11:57:30 PM UTC 24 |
| Finished | Sep 12 12:08:51 AM UTC 24 |
| Peak memory | 625652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301573765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.1301573765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.3227842114 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 8951280660 ps |
| CPU time | 837.88 seconds |
| Started | Sep 12 12:29:02 AM UTC 24 |
| Finished | Sep 12 12:43:11 AM UTC 24 |
| Peak memory | 630056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_ clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h w/dv/tools/sim.tcl +ntb_random_seed=3227842114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.3227842114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_rst_inputs.1479979216 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 18845770240 ps |
| CPU time | 2737.67 seconds |
| Started | Sep 12 12:39:27 AM UTC 24 |
| Finished | Sep 12 01:25:39 AM UTC 24 |
| Peak memory | 628632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_ images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479979216 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_input s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.1479979216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1822203065 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 7176425491 ps |
| CPU time | 536.96 seconds |
| Started | Sep 12 12:21:45 AM UTC 24 |
| Finished | Sep 12 12:30:49 AM UTC 24 |
| Peak memory | 638020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_de vice=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822203065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.1822203065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3447149632 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 4093256858 ps |
| CPU time | 565.73 seconds |
| Started | Sep 12 12:23:30 AM UTC 24 |
| Finished | Sep 12 12:33:04 AM UTC 24 |
| Peak memory | 625784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447149632 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_dev.3447149632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2744937279 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 4697453266 ps |
| CPU time | 665.06 seconds |
| Started | Sep 12 12:25:36 AM UTC 24 |
| Finished | Sep 12 12:36:50 AM UTC 24 |
| Peak memory | 625872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744937279 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_rma.2744937279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.892647147 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 4337966456 ps |
| CPU time | 679.93 seconds |
| Started | Sep 12 12:22:43 AM UTC 24 |
| Finished | Sep 12 12:34:12 AM UTC 24 |
| Peak memory | 627912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892 647147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_extern al_clk_src_for_sw_fast_test_unlocked0.892647147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3431321946 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 4747010122 ps |
| CPU time | 637.13 seconds |
| Started | Sep 12 12:25:12 AM UTC 24 |
| Finished | Sep 12 12:35:58 AM UTC 24 |
| Peak memory | 625636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431321946 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_dev.3431321946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3405647711 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 4028404250 ps |
| CPU time | 514.55 seconds |
| Started | Sep 12 12:26:22 AM UTC 24 |
| Finished | Sep 12 12:35:04 AM UTC 24 |
| Peak memory | 625916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405647711 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_rma.3405647711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3628564906 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 4918133712 ps |
| CPU time | 546.75 seconds |
| Started | Sep 12 12:23:02 AM UTC 24 |
| Finished | Sep 12 12:32:16 AM UTC 24 |
| Peak memory | 625836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362 8564906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_exter nal_clk_src_for_sw_slow_test_unlocked0.3628564906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.3959605759 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 3049469147 ps |
| CPU time | 209.51 seconds |
| Started | Sep 12 12:26:36 AM UTC 24 |
| Finished | Sep 12 12:30:09 AM UTC 24 |
| Peak memory | 623596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3959605759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_clkmgr_jitter.3959605759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.498328567 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 3756395252 ps |
| CPU time | 437.7 seconds |
| Started | Sep 12 12:26:23 AM UTC 24 |
| Finished | Sep 12 12:33:47 AM UTC 24 |
| Peak memory | 625708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=498328567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_clkmgr_jitter_frequency.498328567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2612988320 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 2964559930 ps |
| CPU time | 183.27 seconds |
| Started | Sep 12 12:34:07 AM UTC 24 |
| Finished | Sep 12 12:37:13 AM UTC 24 |
| Peak memory | 623704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkm gr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2612988320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.2612988320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1165146155 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 4984557632 ps |
| CPU time | 452.85 seconds |
| Started | Sep 12 12:19:37 AM UTC 24 |
| Finished | Sep 12 12:27:16 AM UTC 24 |
| Peak memory | 625576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1165146155 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.1165146155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.485766145 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 4050274750 ps |
| CPU time | 387.42 seconds |
| Started | Sep 12 12:20:32 AM UTC 24 |
| Finished | Sep 12 12:27:05 AM UTC 24 |
| Peak memory | 625512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=485766145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.485766145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3766605635 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 3508585070 ps |
| CPU time | 410.25 seconds |
| Started | Sep 12 12:20:33 AM UTC 24 |
| Finished | Sep 12 12:27:29 AM UTC 24 |
| Peak memory | 625656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3766605635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_clkmgr_off_kmac_trans.3766605635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2594597519 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 5761710520 ps |
| CPU time | 507.74 seconds |
| Started | Sep 12 12:21:27 AM UTC 24 |
| Finished | Sep 12 12:30:02 AM UTC 24 |
| Peak memory | 625640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2594597519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_clkmgr_off_otbn_trans.2594597519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.663435242 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 9212246184 ps |
| CPU time | 1224.77 seconds |
| Started | Sep 12 12:19:36 AM UTC 24 |
| Finished | Sep 12 12:40:16 AM UTC 24 |
| Peak memory | 625652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_i mages=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663435242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.663435242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_reset_frequency.2767326111 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 3532760480 ps |
| CPU time | 480 seconds |
| Started | Sep 12 12:26:19 AM UTC 24 |
| Finished | Sep 12 12:34:27 AM UTC 24 |
| Peak memory | 625660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767326111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.2767326111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.423182581 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 5141984384 ps |
| CPU time | 515.83 seconds |
| Started | Sep 12 12:26:39 AM UTC 24 |
| Finished | Sep 12 12:35:22 AM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423182581 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.423182581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.1762285092 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 2811871990 ps |
| CPU time | 267.44 seconds |
| Started | Sep 12 12:42:53 AM UTC 24 |
| Finished | Sep 12 12:47:25 AM UTC 24 |
| Peak memory | 623720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1762285092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_clkmgr_smoketest.1762285092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency.2039381003 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 26568446496 ps |
| CPU time | 7522.08 seconds |
| Started | Sep 12 12:07:24 AM UTC 24 |
| Finished | Sep 12 02:14:20 AM UTC 24 |
| Peak memory | 629024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2039381003 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_csrng_edn_concurrency.2039381003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.683593612 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 33261862894 ps |
| CPU time | 6924.06 seconds |
| Started | Sep 12 12:36:36 AM UTC 24 |
| Finished | Sep 12 02:33:26 AM UTC 24 |
| Peak memory | 628776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accele rate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683593612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.683593612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.869480685 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 4144853000 ps |
| CPU time | 421.65 seconds |
| Started | Sep 12 12:07:23 AM UTC 24 |
| Finished | Sep 12 12:14:31 AM UTC 24 |
| Peak memory | 623664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869480685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_ fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.869480685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_kat_test.3445510677 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 3238607684 ps |
| CPU time | 295.07 seconds |
| Started | Sep 12 12:07:23 AM UTC 24 |
| Finished | Sep 12 12:12:23 AM UTC 24 |
| Peak memory | 623456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445510677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_csrng_kat_test.3445510677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3482617216 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 7310088498 ps |
| CPU time | 543.38 seconds |
| Started | Sep 12 12:07:24 AM UTC 24 |
| Finished | Sep 12 12:16:36 AM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_ otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482617216 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_lc_hw_debug_en_test.3482617216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.3157135694 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 3003803740 ps |
| CPU time | 298.74 seconds |
| Started | Sep 12 12:44:00 AM UTC 24 |
| Finished | Sep 12 12:49:04 AM UTC 24 |
| Peak memory | 623676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3157135694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _csrng_smoketest.3157135694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.2791804722 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 5877213908 ps |
| CPU time | 583.26 seconds |
| Started | Sep 11 11:28:30 PM UTC 24 |
| Finished | Sep 11 11:38:22 PM UTC 24 |
| Peak memory | 625776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791804722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.2791804722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.3673719495 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 6498543408 ps |
| CPU time | 1472.39 seconds |
| Started | Sep 12 12:06:12 AM UTC 24 |
| Finished | Sep 12 12:31:04 AM UTC 24 |
| Peak memory | 626016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_ device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673719495 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_auto_mode.3673719495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.903044629 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 3163562872 ps |
| CPU time | 537.29 seconds |
| Started | Sep 12 12:06:17 AM UTC 24 |
| Finished | Sep 12 12:15:22 AM UTC 24 |
| Peak memory | 623896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_ device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903044629 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_boot_mode.903044629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs.887850639 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 7314631240 ps |
| CPU time | 1282.3 seconds |
| Started | Sep 12 12:09:11 AM UTC 24 |
| Finished | Sep 12 12:30:50 AM UTC 24 |
| Peak memory | 626004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887850639 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.887850639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.770391378 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 6413241874 ps |
| CPU time | 1196.91 seconds |
| Started | Sep 12 12:09:12 AM UTC 24 |
| Finished | Sep 12 12:29:24 AM UTC 24 |
| Peak memory | 625764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770391378 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.770391378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.1599809991 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 2895193160 ps |
| CPU time | 600.94 seconds |
| Started | Sep 12 12:06:18 AM UTC 24 |
| Finished | Sep 12 12:16:27 AM UTC 24 |
| Peak memory | 625520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_a ssert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=1599809991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_edn_kat.1599809991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_kat/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.2474972438 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 9543424102 ps |
| CPU time | 2163.04 seconds |
| Started | Sep 12 12:06:54 AM UTC 24 |
| Finished | Sep 12 12:43:25 AM UTC 24 |
| Peak memory | 625688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2474972438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_edn_sw_mode.2474972438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3412148823 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 2346751560 ps |
| CPU time | 277.8 seconds |
| Started | Sep 12 12:07:44 AM UTC 24 |
| Finished | Sep 12 12:12:26 AM UTC 24 |
| Peak memory | 623612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412148823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.3412148823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.1420420465 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 5648543176 ps |
| CPU time | 1085.09 seconds |
| Started | Sep 12 12:08:31 AM UTC 24 |
| Finished | Sep 12 12:26:51 AM UTC 24 |
| Peak memory | 623988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_ srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420420465 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.1420420465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.2015306669 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 2751594400 ps |
| CPU time | 254.62 seconds |
| Started | Sep 12 12:06:01 AM UTC 24 |
| Finished | Sep 12 12:10:20 AM UTC 24 |
| Peak memory | 625580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015306669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.2015306669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_smoketest.1696876180 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 3765816832 ps |
| CPU time | 445.29 seconds |
| Started | Sep 12 12:44:05 AM UTC 24 |
| Finished | Sep 12 12:51:37 AM UTC 24 |
| Peak memory | 623464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_de vice=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696876180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.1696876180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_concurrency.179991723 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 2976134736 ps |
| CPU time | 241.81 seconds |
| Started | Sep 11 11:27:28 PM UTC 24 |
| Finished | Sep 11 11:31:34 PM UTC 24 |
| Peak memory | 625712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=179991723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_example_concurrency.179991723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_flash.415458603 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 3250285576 ps |
| CPU time | 231.89 seconds |
| Started | Sep 11 11:25:50 PM UTC 24 |
| Finished | Sep 11 11:29:46 PM UTC 24 |
| Peak memory | 623672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=415458603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_example_flash.415458603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_manufacturer.3006579782 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 2407418346 ps |
| CPU time | 251.11 seconds |
| Started | Sep 11 11:25:53 PM UTC 24 |
| Finished | Sep 11 11:30:08 PM UTC 24 |
| Peak memory | 625508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3006579782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ex ample_manufacturer.3006579782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_manufacturer/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_rom.310049937 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 2049808000 ps |
| CPU time | 170.19 seconds |
| Started | Sep 11 11:25:38 PM UTC 24 |
| Finished | Sep 11 11:28:31 PM UTC 24 |
| Peak memory | 623148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:t est_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=310049937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_sw_example_rom.310049937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.3401392075 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 5014459920 ps |
| CPU time | 630.91 seconds |
| Started | Sep 12 12:34:05 AM UTC 24 |
| Finished | Sep 12 12:44:44 AM UTC 24 |
| Peak memory | 626056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check= 1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401392075 -assert nopostproc +UVM_TESTNAME=chip_base_test + UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.3401392075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.626739213 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 5710106000 ps |
| CPU time | 938.5 seconds |
| Started | Sep 11 11:39:07 PM UTC 24 |
| Finished | Sep 11 11:54:58 PM UTC 24 |
| Peak memory | 623840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=626739213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ flash_ctrl_access.626739213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.247291533 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 5619596548 ps |
| CPU time | 1001.39 seconds |
| Started | Sep 11 11:39:35 PM UTC 24 |
| Finished | Sep 11 11:56:30 PM UTC 24 |
| Peak memory | 625692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=247291533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_flash_ctrl_access_jitter_en.247291533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2004740154 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 7205470684 ps |
| CPU time | 1056.11 seconds |
| Started | Sep 12 12:35:31 AM UTC 24 |
| Finished | Sep 12 12:53:22 AM UTC 24 |
| Peak memory | 623536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004740154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2004740154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1058966718 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 5872063857 ps |
| CPU time | 890.34 seconds |
| Started | Sep 11 11:41:11 PM UTC 24 |
| Finished | Sep 11 11:56:14 PM UTC 24 |
| Peak memory | 623592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=1058966718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_flash_ctrl_clock_freqs.1058966718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3788332567 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 3209546372 ps |
| CPU time | 302.8 seconds |
| Started | Sep 11 11:39:54 PM UTC 24 |
| Finished | Sep 11 11:45:02 PM UTC 24 |
| Peak memory | 623660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3788332567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_flash_ctrl_idle_low_power.3788332567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.649645177 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 5071993144 ps |
| CPU time | 449.35 seconds |
| Started | Sep 11 11:39:04 PM UTC 24 |
| Finished | Sep 11 11:46:40 PM UTC 24 |
| Peak memory | 623704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649645177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctr l_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.649645177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1641723828 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 5340916026 ps |
| CPU time | 966 seconds |
| Started | Sep 12 12:39:54 AM UTC 24 |
| Finished | Sep 12 12:56:13 AM UTC 24 |
| Peak memory | 623588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1641723828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_flash_ctrl_mem_protection.1641723828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.1754741553 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 3843361936 ps |
| CPU time | 626.71 seconds |
| Started | Sep 11 11:38:44 PM UTC 24 |
| Finished | Sep 11 11:49:20 PM UTC 24 |
| Peak memory | 625760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754741553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.1754741553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3059081526 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 4216787031 ps |
| CPU time | 633.68 seconds |
| Started | Sep 11 11:39:03 PM UTC 24 |
| Finished | Sep 11 11:49:45 PM UTC 24 |
| Peak memory | 623700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059081526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.3059081526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.1972690861 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 3182633172 ps |
| CPU time | 286.25 seconds |
| Started | Sep 12 12:34:06 AM UTC 24 |
| Finished | Sep 12 12:38:56 AM UTC 24 |
| Peak memory | 623652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_image s=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972690861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.1972690861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.2282795956 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 23758641350 ps |
| CPU time | 2054.84 seconds |
| Started | Sep 11 11:40:04 PM UTC 24 |
| Finished | Sep 12 12:14:45 AM UTC 24 |
| Peak memory | 627880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282795956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_flash_init.2282795956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_init/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init_reduced_freq.2764850657 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 25267918289 ps |
| CPU time | 1982.57 seconds |
| Started | Sep 12 12:36:02 AM UTC 24 |
| Finished | Sep 12 01:09:31 AM UTC 24 |
| Peak memory | 630876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_buil d_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764850657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.2764850657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.1841485847 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 2602772724 ps |
| CPU time | 179.09 seconds |
| Started | Sep 12 12:42:29 AM UTC 24 |
| Finished | Sep 12 12:45:32 AM UTC 24 |
| Peak memory | 623676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_ima ges=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoketest_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841485847 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chi p_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.1841485847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.1358171920 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 2841027641 ps |
| CPU time | 307.5 seconds |
| Started | Sep 12 12:44:19 AM UTC 24 |
| Finished | Sep 12 12:49:32 AM UTC 24 |
| Peak memory | 623664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=1358171920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_sw_gpio_smoketest.1358171920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.549151020 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 2689689920 ps |
| CPU time | 252.19 seconds |
| Started | Sep 12 12:09:10 AM UTC 24 |
| Finished | Sep 12 12:13:26 AM UTC 24 |
| Peak memory | 623460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=549151020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hm ac_enc.549151020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.2580310973 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 2832854752 ps |
| CPU time | 228.62 seconds |
| Started | Sep 12 12:10:06 AM UTC 24 |
| Finished | Sep 12 12:13:58 AM UTC 24 |
| Peak memory | 623528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2580310973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_hmac_enc_idle.2580310973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en.1016899835 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 2638291195 ps |
| CPU time | 267.4 seconds |
| Started | Sep 12 12:09:28 AM UTC 24 |
| Finished | Sep 12 12:13:59 AM UTC 24 |
| Peak memory | 623468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1016899835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_hmac_enc_jitter_en.1016899835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3448768515 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 2425232965 ps |
| CPU time | 188.49 seconds |
| Started | Sep 12 12:35:30 AM UTC 24 |
| Finished | Sep 12 12:38:42 AM UTC 24 |
| Peak memory | 623756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448768515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.3448768515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.99245144 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 7133086210 ps |
| CPU time | 1532.75 seconds |
| Started | Sep 12 12:11:05 AM UTC 24 |
| Finished | Sep 12 12:36:58 AM UTC 24 |
| Peak memory | 625584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=99245144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_hmac_multistream.99245144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_multistream/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.47903030 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 3183942190 ps |
| CPU time | 366 seconds |
| Started | Sep 12 12:10:07 AM UTC 24 |
| Finished | Sep 12 12:16:19 AM UTC 24 |
| Peak memory | 623740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=47903030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hma c_oneshot.47903030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.2846969219 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 3863912112 ps |
| CPU time | 386.07 seconds |
| Started | Sep 12 12:45:06 AM UTC 24 |
| Finished | Sep 12 12:51:38 AM UTC 24 |
| Peak memory | 623524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2846969219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ hmac_smoketest.2846969219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.1499637646 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 4317892702 ps |
| CPU time | 661.48 seconds |
| Started | Sep 11 11:36:11 PM UTC 24 |
| Finished | Sep 11 11:47:22 PM UTC 24 |
| Peak memory | 625940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1499637646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.1499637646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.783915580 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 4890913492 ps |
| CPU time | 654.55 seconds |
| Started | Sep 11 11:34:55 PM UTC 24 |
| Finished | Sep 11 11:45:59 PM UTC 24 |
| Peak memory | 623828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=783915580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_i2c_host_tx_rx.783915580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.516646106 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 5178814790 ps |
| CPU time | 845.68 seconds |
| Started | Sep 11 11:35:55 PM UTC 24 |
| Finished | Sep 11 11:50:13 PM UTC 24 |
| Peak memory | 623588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=516646106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.516646106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1734782005 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 4682748562 ps |
| CPU time | 676.66 seconds |
| Started | Sep 11 11:36:11 PM UTC 24 |
| Finished | Sep 11 11:47:37 PM UTC 24 |
| Peak memory | 625784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1734782005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.1734782005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_inject_scramble_seed.2503349334 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 66006950979 ps |
| CPU time | 15513.7 seconds |
| Started | Sep 11 11:33:50 PM UTC 24 |
| Finished | Sep 12 03:55:36 AM UTC 24 |
| Peak memory | 643104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=1 50_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503349334 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.2503349334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation.183747124 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 6287847280 ps |
| CPU time | 1297.09 seconds |
| Started | Sep 12 12:11:19 AM UTC 24 |
| Finished | Sep 12 12:33:13 AM UTC 24 |
| Peak memory | 632064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183747124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_ derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.183747124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3773540175 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 8578638704 ps |
| CPU time | 1528.66 seconds |
| Started | Sep 12 12:11:16 AM UTC 24 |
| Finished | Sep 12 12:37:05 AM UTC 24 |
| Peak memory | 632072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773540175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.3773540175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2363304976 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 9447827685 ps |
| CPU time | 1237.12 seconds |
| Started | Sep 12 12:36:01 AM UTC 24 |
| Finished | Sep 12 12:56:54 AM UTC 24 |
| Peak memory | 632064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363304976 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2363304976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2556821776 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 9433945514 ps |
| CPU time | 1952.92 seconds |
| Started | Sep 12 12:11:18 AM UTC 24 |
| Finished | Sep 12 12:44:16 AM UTC 24 |
| Peak memory | 631940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_devic e=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556821776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.2556821776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_aes.791595344 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 11425995288 ps |
| CPU time | 2359.49 seconds |
| Started | Sep 12 12:11:38 AM UTC 24 |
| Finished | Sep 12 12:51:27 AM UTC 24 |
| Peak memory | 625920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791595344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sidelo ad_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.791595344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.1226224736 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 11676623050 ps |
| CPU time | 2187.14 seconds |
| Started | Sep 12 12:11:22 AM UTC 24 |
| Finished | Sep 12 12:48:17 AM UTC 24 |
| Peak memory | 625648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226224736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_side load_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.1226224736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_otbn.820254286 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 14632169800 ps |
| CPU time | 4215.24 seconds |
| Started | Sep 12 12:12:01 AM UTC 24 |
| Finished | Sep 12 01:23:10 AM UTC 24 |
| Peak memory | 628764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820254286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.820254286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_app_rom.2812762378 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 2832352048 ps |
| CPU time | 267.19 seconds |
| Started | Sep 12 12:14:00 AM UTC 24 |
| Finished | Sep 12 12:18:32 AM UTC 24 |
| Peak memory | 623676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=2812762378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_kmac_app_rom.2812762378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.3250512979 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 2903321350 ps |
| CPU time | 262.13 seconds |
| Started | Sep 11 11:43:33 PM UTC 24 |
| Finished | Sep 11 11:48:00 PM UTC 24 |
| Peak memory | 623672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=3250512979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_kmac_entropy.3250512979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.2969551686 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 3036816136 ps |
| CPU time | 243.85 seconds |
| Started | Sep 12 12:14:45 AM UTC 24 |
| Finished | Sep 12 12:18:53 AM UTC 24 |
| Peak memory | 623464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2969551686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ kmac_idle.2969551686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.3362630928 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 2454912368 ps |
| CPU time | 251.04 seconds |
| Started | Sep 12 12:12:15 AM UTC 24 |
| Finished | Sep 12 12:16:30 AM UTC 24 |
| Peak memory | 625504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3362630928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_sw_kmac_mode_cshake.3362630928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.149122611 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 3624781230 ps |
| CPU time | 325.8 seconds |
| Started | Sep 12 12:13:09 AM UTC 24 |
| Finished | Sep 12 12:18:40 AM UTC 24 |
| Peak memory | 625764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149122611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_kmac_mode_kmac.149122611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3681997770 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 3125352190 ps |
| CPU time | 305.41 seconds |
| Started | Sep 12 12:13:10 AM UTC 24 |
| Finished | Sep 12 12:18:20 AM UTC 24 |
| Peak memory | 625744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_km ac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3681997770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.3681997770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.4121665062 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 3768993650 ps |
| CPU time | 308.87 seconds |
| Started | Sep 12 12:36:06 AM UTC 24 |
| Finished | Sep 12 12:41:19 AM UTC 24 |
| Peak memory | 623844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121665062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.4121665062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.1959990374 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 3342343082 ps |
| CPU time | 280.31 seconds |
| Started | Sep 12 12:45:06 AM UTC 24 |
| Finished | Sep 12 12:49:51 AM UTC 24 |
| Peak memory | 625688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=1959990374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ kmac_smoketest.1959990374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3349639706 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 3146050856 ps |
| CPU time | 280.07 seconds |
| Started | Sep 11 11:43:55 PM UTC 24 |
| Finished | Sep 11 11:48:40 PM UTC 24 |
| Peak memory | 623456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3349639706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.3349639706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_program_error.1510768461 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 5729015820 ps |
| CPU time | 555.29 seconds |
| Started | Sep 12 12:29:00 AM UTC 24 |
| Finished | Sep 12 12:38:22 AM UTC 24 |
| Peak memory | 625864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510768461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_l c_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.1510768461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3516358244 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 3111409923 ps |
| CPU time | 144.96 seconds |
| Started | Sep 11 11:43:55 PM UTC 24 |
| Finished | Sep 11 11:46:23 PM UTC 24 |
| Peak memory | 635288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516358244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.3516358244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.1392362521 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 6388162573 ps |
| CPU time | 442 seconds |
| Started | Sep 11 11:44:16 PM UTC 24 |
| Finished | Sep 11 11:51:44 PM UTC 24 |
| Peak memory | 640232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1392362521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_lc_ctrl_transition.1392362521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1028369894 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 2152350446 ps |
| CPU time | 123.5 seconds |
| Started | Sep 11 11:45:40 PM UTC 24 |
| Finished | Sep 11 11:47:46 PM UTC 24 |
| Peak memory | 635232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028369894 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.1028369894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1847930588 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 2564994736 ps |
| CPU time | 133.41 seconds |
| Started | Sep 11 11:46:42 PM UTC 24 |
| Finished | Sep 11 11:48:58 PM UTC 24 |
| Peak memory | 633496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSo urceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18479305 88 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc _ctrl_volatile_raw_unlock_ext_clk_48mhz.1847930588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_dev.3126659455 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 47304539253 ps |
| CPU time | 6257.67 seconds |
| Started | Sep 11 11:44:16 PM UTC 24 |
| Finished | Sep 12 01:29:52 AM UTC 24 |
| Peak memory | 643392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126659455 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_dev.3126659455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prod.3021500738 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 47787579388 ps |
| CPU time | 5878.56 seconds |
| Started | Sep 11 11:44:14 PM UTC 24 |
| Finished | Sep 12 01:23:28 AM UTC 24 |
| Peak memory | 643176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021500738 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prod.3021500738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.1986004675 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 10225118650 ps |
| CPU time | 965.51 seconds |
| Started | Sep 11 11:45:17 PM UTC 24 |
| Finished | Sep 12 12:01:37 AM UTC 24 |
| Peak memory | 639980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986004675 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.1986004675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_rma.3307148634 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 46717962720 ps |
| CPU time | 6971.4 seconds |
| Started | Sep 11 11:46:43 PM UTC 24 |
| Finished | Sep 12 01:44:21 AM UTC 24 |
| Peak memory | 643396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +fl ash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307148634 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_rma.3307148634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2085613885 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 36644209868 ps |
| CPU time | 2804.45 seconds |
| Started | Sep 11 11:47:57 PM UTC 24 |
| Finished | Sep 12 12:35:18 AM UTC 24 |
| Peak memory | 640228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnl ock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085613885 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testunlocks.2085613885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.4056993852 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 17103929112 ps |
| CPU time | 4262.51 seconds |
| Started | Sep 11 11:58:18 PM UTC 24 |
| Finished | Sep 12 01:10:15 AM UTC 24 |
| Peak memory | 628836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056993852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.4056993852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1450079891 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 18862407687 ps |
| CPU time | 4275.32 seconds |
| Started | Sep 11 11:58:18 PM UTC 24 |
| Finished | Sep 12 01:10:29 AM UTC 24 |
| Peak memory | 628772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450079891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1450079891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2572005363 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 24526817709 ps |
| CPU time | 4723.8 seconds |
| Started | Sep 12 12:35:40 AM UTC 24 |
| Finished | Sep 12 01:55:26 AM UTC 24 |
| Peak memory | 628772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572005363 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2572005363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_mem_scramble.304162397 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 3242747800 ps |
| CPU time | 441.56 seconds |
| Started | Sep 11 11:58:50 PM UTC 24 |
| Finished | Sep 12 12:06:18 AM UTC 24 |
| Peak memory | 625828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304162397 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.304162397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_randomness.4172450459 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 5953869510 ps |
| CPU time | 1008.57 seconds |
| Started | Sep 11 11:57:46 PM UTC 24 |
| Finished | Sep 12 12:14:48 AM UTC 24 |
| Peak memory | 625932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172450459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.4172450459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_randomness/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_smoketest.2139620223 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 10412868782 ps |
| CPU time | 2635.52 seconds |
| Started | Sep 12 12:45:33 AM UTC 24 |
| Finished | Sep 12 01:30:03 AM UTC 24 |
| Peak memory | 623724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2139620223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ otbn_smoketest.2139620223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.393666458 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 2995284204 ps |
| CPU time | 236.66 seconds |
| Started | Sep 11 11:43:01 PM UTC 24 |
| Finished | Sep 11 11:47:02 PM UTC 24 |
| Peak memory | 623732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_ error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=393666458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.393666458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.396050516 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 9192314050 ps |
| CPU time | 1424.68 seconds |
| Started | Sep 11 11:44:08 PM UTC 24 |
| Finished | Sep 12 12:08:11 AM UTC 24 |
| Peak memory | 625764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396050516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.396050516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1261630183 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 7497179940 ps |
| CPU time | 1421.65 seconds |
| Started | Sep 11 11:44:06 PM UTC 24 |
| Finished | Sep 12 12:08:07 AM UTC 24 |
| Peak memory | 625932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_buil d_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261630183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.1261630183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2932527422 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 7460244866 ps |
| CPU time | 1270.89 seconds |
| Started | Sep 11 11:43:56 PM UTC 24 |
| Finished | Sep 12 12:05:24 AM UTC 24 |
| Peak memory | 625840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932527422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.2932527422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4189246129 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 4383891252 ps |
| CPU time | 637.39 seconds |
| Started | Sep 11 11:43:01 PM UTC 24 |
| Finished | Sep 11 11:53:48 PM UTC 24 |
| Peak memory | 625580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189246129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_ asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4189246129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.2474670858 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 2396530008 ps |
| CPU time | 237.63 seconds |
| Started | Sep 12 12:45:34 AM UTC 24 |
| Finished | Sep 12 12:49:36 AM UTC 24 |
| Peak memory | 625708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2474670858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_otp_ctrl_smoketest.2474670858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.3255417708 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 3245511928 ps |
| CPU time | 337.64 seconds |
| Started | Sep 12 12:19:30 AM UTC 24 |
| Finished | Sep 12 12:25:13 AM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3255417708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_plic_sw_irq.3255417708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.4170263680 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 4526007800 ps |
| CPU time | 535.22 seconds |
| Started | Sep 12 12:38:55 AM UTC 24 |
| Finished | Sep 12 12:47:57 AM UTC 24 |
| Peak memory | 625776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170263680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_power_idle_load.4170263680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_idle_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_virus.1277624754 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 5611739928 ps |
| CPU time | 1527.05 seconds |
| Started | Sep 12 12:40:21 AM UTC 24 |
| Finished | Sep 12 01:06:08 AM UTC 24 |
| Peak memory | 640660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_tim eout_ns=400_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_ img_rma:4,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277624754 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_virus.1277624754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.4221745229 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 13085257497 ps |
| CPU time | 1602.61 seconds |
| Started | Sep 11 11:48:39 PM UTC 24 |
| Finished | Sep 12 12:15:42 AM UTC 24 |
| Peak memory | 625716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221745229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep _all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.4221745229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3731576587 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 29660042048 ps |
| CPU time | 2334.86 seconds |
| Started | Sep 12 12:17:48 AM UTC 24 |
| Finished | Sep 12 12:57:12 AM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731576587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_re set_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.3731576587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1797842979 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 14935484504 ps |
| CPU time | 1289.22 seconds |
| Started | Sep 11 11:49:33 PM UTC 24 |
| Finished | Sep 12 12:11:20 AM UTC 24 |
| Peak memory | 626024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797842979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1797842979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3743302435 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 22179269030 ps |
| CPU time | 1512.81 seconds |
| Started | Sep 12 12:28:59 AM UTC 24 |
| Finished | Sep 12 12:54:32 AM UTC 24 |
| Peak memory | 625808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743302435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr _deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3743302435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3859381196 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 10322758220 ps |
| CPU time | 798.34 seconds |
| Started | Sep 11 11:50:22 PM UTC 24 |
| Finished | Sep 12 12:03:51 AM UTC 24 |
| Peak memory | 625860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_res et_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3859381196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.3859381196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.632226335 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 6803408864 ps |
| CPU time | 510.29 seconds |
| Started | Sep 11 11:50:25 PM UTC 24 |
| Finished | Sep 11 11:59:03 PM UTC 24 |
| Peak memory | 631812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632226335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asi c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.632226335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.666417888 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 6795343950 ps |
| CPU time | 559.62 seconds |
| Started | Sep 11 11:48:01 PM UTC 24 |
| Finished | Sep 11 11:57:29 PM UTC 24 |
| Peak memory | 625888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=666417888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.666417888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.4212658788 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 3849170334 ps |
| CPU time | 451.65 seconds |
| Started | Sep 11 11:48:43 PM UTC 24 |
| Finished | Sep 11 11:56:21 PM UTC 24 |
| Peak memory | 631680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212658788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_mai n_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.4212658788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.873524425 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 10211800696 ps |
| CPU time | 1010.65 seconds |
| Started | Sep 11 11:50:02 PM UTC 24 |
| Finished | Sep 12 12:07:06 AM UTC 24 |
| Peak memory | 626020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_r eset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=873524425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.873524425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3783787799 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 7822307578 ps |
| CPU time | 535.38 seconds |
| Started | Sep 12 12:29:00 AM UTC 24 |
| Finished | Sep 12 12:38:03 AM UTC 24 |
| Peak memory | 625828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_w ake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3783787799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3783787799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2036915317 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 6565193652 ps |
| CPU time | 674.71 seconds |
| Started | Sep 11 11:50:07 PM UTC 24 |
| Finished | Sep 12 12:01:31 AM UTC 24 |
| Peak memory | 625752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_r eset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2036915317 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.2036915317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3281433153 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 23878271460 ps |
| CPU time | 2571.91 seconds |
| Started | Sep 11 11:48:43 PM UTC 24 |
| Finished | Sep 12 12:32:08 AM UTC 24 |
| Peak memory | 625784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281433153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3281433153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2009375152 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 22646373832 ps |
| CPU time | 1366.77 seconds |
| Started | Sep 12 12:29:04 AM UTC 24 |
| Finished | Sep 12 12:52:07 AM UTC 24 |
| Peak memory | 625892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009375152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2009375152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3777684512 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 5029817728 ps |
| CPU time | 376.23 seconds |
| Started | Sep 12 12:30:05 AM UTC 24 |
| Finished | Sep 12 12:36:26 AM UTC 24 |
| Peak memory | 626012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777684512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3777684512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2001543921 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 3622716832 ps |
| CPU time | 359.01 seconds |
| Started | Sep 11 11:51:01 PM UTC 24 |
| Finished | Sep 11 11:57:06 PM UTC 24 |
| Peak memory | 623592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2001543921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_pwrmgr_sleep_disabled.2001543921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3385972997 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 5054419752 ps |
| CPU time | 431 seconds |
| Started | Sep 12 12:17:40 AM UTC 24 |
| Finished | Sep 12 12:24:57 AM UTC 24 |
| Peak memory | 625844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_im ages=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385972997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3385972997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1791756817 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 5814171928 ps |
| CPU time | 498.19 seconds |
| Started | Sep 12 12:28:58 AM UTC 24 |
| Finished | Sep 12 12:37:24 AM UTC 24 |
| Peak memory | 625636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791756817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.1791756817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.2291595441 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 6065129446 ps |
| CPU time | 529.53 seconds |
| Started | Sep 12 12:46:08 AM UTC 24 |
| Finished | Sep 12 12:55:05 AM UTC 24 |
| Peak memory | 625740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_ima ges=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291595441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.2291595441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2051782811 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 7284555462 ps |
| CPU time | 1039.89 seconds |
| Started | Sep 11 11:48:25 PM UTC 24 |
| Finished | Sep 12 12:05:59 AM UTC 24 |
| Peak memory | 625788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2051782811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.2051782811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2303273606 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 4161687868 ps |
| CPU time | 532.32 seconds |
| Started | Sep 11 11:51:02 PM UTC 24 |
| Finished | Sep 12 12:00:02 AM UTC 24 |
| Peak memory | 623756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_w hen_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2303273606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2303273606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2051164676 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 5870723736 ps |
| CPU time | 447.22 seconds |
| Started | Sep 12 12:46:12 AM UTC 24 |
| Finished | Sep 12 12:53:46 AM UTC 24 |
| Peak memory | 625876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2051164676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_pwrmgr_usbdev_smoketest.2051164676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2373318773 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 3884048104 ps |
| CPU time | 537.8 seconds |
| Started | Sep 11 11:57:25 PM UTC 24 |
| Finished | Sep 12 12:06:30 AM UTC 24 |
| Peak memory | 625640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373318773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.2373318773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2477189688 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 8534449004 ps |
| CPU time | 478.08 seconds |
| Started | Sep 12 12:14:46 AM UTC 24 |
| Finished | Sep 12 12:22:51 AM UTC 24 |
| Peak memory | 640040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2477189688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.2477189688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.2943867580 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 12705334324 ps |
| CPU time | 1849.47 seconds |
| Started | Sep 11 11:48:37 PM UTC 24 |
| Finished | Sep 12 12:19:50 AM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_buil d_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943867580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.2943867580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.989080698 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 5699298684 ps |
| CPU time | 669.78 seconds |
| Started | Sep 11 11:48:12 PM UTC 24 |
| Finished | Sep 11 11:59:31 PM UTC 24 |
| Peak memory | 623620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989080698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_rstmgr_cpu_info.989080698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.130588585 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 4643777444 ps |
| CPU time | 514.4 seconds |
| Started | Sep 11 11:28:27 PM UTC 24 |
| Finished | Sep 11 11:37:09 PM UTC 24 |
| Peak memory | 668092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130588585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_ cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.130588585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.2985353700 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 3378609232 ps |
| CPU time | 241.59 seconds |
| Started | Sep 12 12:48:15 AM UTC 24 |
| Finished | Sep 12 12:52:21 AM UTC 24 |
| Peak memory | 623712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2985353700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_rstmgr_smoketest.2985353700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.2426617836 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 4418384658 ps |
| CPU time | 429.64 seconds |
| Started | Sep 11 11:47:56 PM UTC 24 |
| Finished | Sep 11 11:55:12 PM UTC 24 |
| Peak memory | 625576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2426617836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_rstmgr_sw_req.2426617836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.3483400703 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 2749438872 ps |
| CPU time | 337.61 seconds |
| Started | Sep 11 11:48:24 PM UTC 24 |
| Finished | Sep 11 11:54:07 PM UTC 24 |
| Peak memory | 623724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3483400703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_rstmgr_sw_rst.3483400703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2214141499 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 2625280136 ps |
| CPU time | 233.57 seconds |
| Started | Sep 12 12:33:19 AM UTC 24 |
| Finished | Sep 12 12:37:17 AM UTC 24 |
| Peak memory | 623464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_im ages=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214141499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.2214141499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3467649063 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 2643564446 ps |
| CPU time | 262.8 seconds |
| Started | Sep 12 12:33:19 AM UTC 24 |
| Finished | Sep 12 12:37:46 AM UTC 24 |
| Peak memory | 623460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_inval idate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3467649063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.3467649063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1397803923 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 2488502480 ps |
| CPU time | 175.63 seconds |
| Started | Sep 12 12:33:20 AM UTC 24 |
| Finished | Sep 12 12:36:19 AM UTC 24 |
| Peak memory | 673516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_ima ges=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1397803923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_gli tch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.1397803923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3615747194 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 4712336804 ps |
| CPU time | 694.05 seconds |
| Started | Sep 11 11:59:53 PM UTC 24 |
| Finished | Sep 12 12:11:37 AM UTC 24 |
| Peak memory | 623524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615747194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.3615747194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.3819085730 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 5848897488 ps |
| CPU time | 978.34 seconds |
| Started | Sep 11 11:59:53 PM UTC 24 |
| Finished | Sep 12 12:16:25 AM UTC 24 |
| Peak memory | 623524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_b uild_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819085730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.3819085730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.37434656 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 6326835986 ps |
| CPU time | 599.32 seconds |
| Started | Sep 12 12:31:49 AM UTC 24 |
| Finished | Sep 12 12:41:57 AM UTC 24 |
| Peak memory | 640164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_han dler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=37434656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escal ation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.37434656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.2703013282 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 4894978060 ps |
| CPU time | 395.8 seconds |
| Started | Sep 12 12:31:49 AM UTC 24 |
| Finished | Sep 12 12:38:31 AM UTC 24 |
| Peak memory | 635820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_acc ess_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703013282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wak eup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.2703013282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1460230667 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 4985682456 ps |
| CPU time | 415.82 seconds |
| Started | Sep 12 12:30:50 AM UTC 24 |
| Finished | Sep 12 12:37:52 AM UTC 24 |
| Peak memory | 637932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm _reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460230667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_re set_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asi c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1460230667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_plic_smoketest.510085060 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 2672210424 ps |
| CPU time | 190.77 seconds |
| Started | Sep 12 12:47:11 AM UTC 24 |
| Finished | Sep 12 12:50:25 AM UTC 24 |
| Peak memory | 625512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=510085060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_rv_plic_smoketest.510085060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.1951527347 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 3158467478 ps |
| CPU time | 305.26 seconds |
| Started | Sep 11 11:51:15 PM UTC 24 |
| Finished | Sep 11 11:56:25 PM UTC 24 |
| Peak memory | 625496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1951527347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_rv_timer_irq.1951527347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.1805264155 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 3498283798 ps |
| CPU time | 250.6 seconds |
| Started | Sep 12 12:48:14 AM UTC 24 |
| Finished | Sep 12 12:52:29 AM UTC 24 |
| Peak memory | 623672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1805264155 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_rv_timer_smoketest.1805264155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.2764226925 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 2619637668 ps |
| CPU time | 250.83 seconds |
| Started | Sep 12 12:17:48 AM UTC 24 |
| Finished | Sep 12 12:22:03 AM UTC 24 |
| Peak memory | 623724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764226925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_s tatus_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.2764226925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.2137783135 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2854572968 ps |
| CPU time | 318.64 seconds |
| Started | Sep 11 11:29:21 PM UTC 24 |
| Finished | Sep 11 11:34:45 PM UTC 24 |
| Peak memory | 625580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137783135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.2137783135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.1781084968 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 8350618964 ps |
| CPU time | 1221.8 seconds |
| Started | Sep 11 11:29:59 PM UTC 24 |
| Finished | Sep 11 11:50:37 PM UTC 24 |
| Peak memory | 625736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1781084968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_sleep_pwm_pulses.1781084968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.978413020 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 6812403370 ps |
| CPU time | 578.29 seconds |
| Started | Sep 12 12:16:00 AM UTC 24 |
| Finished | Sep 12 12:25:47 AM UTC 24 |
| Peak memory | 625784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978413020 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_sram_ret_contents_ no_scramble.978413020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1446978685 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 8236766840 ps |
| CPU time | 633.83 seconds |
| Started | Sep 12 12:16:22 AM UTC 24 |
| Finished | Sep 12 12:27:05 AM UTC 24 |
| Peak memory | 625708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446978685 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_sram_ret_contents_sc ramble.1446978685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.3947666831 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 6994855761 ps |
| CPU time | 700.47 seconds |
| Started | Sep 11 11:38:23 PM UTC 24 |
| Finished | Sep 11 11:50:13 PM UTC 24 |
| Peak memory | 640440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947666831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_spi_device_pass_through.3947666831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through_collision.3115297534 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 4706006247 ps |
| CPU time | 477.72 seconds |
| Started | Sep 11 11:39:03 PM UTC 24 |
| Finished | Sep 11 11:47:08 PM UTC 24 |
| Peak memory | 640320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115297534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.3115297534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.3343668626 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 2885856577 ps |
| CPU time | 276.22 seconds |
| Started | Sep 11 11:36:59 PM UTC 24 |
| Finished | Sep 11 11:41:40 PM UTC 24 |
| Peak memory | 636196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3343668626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_device_pinmux_sleep_retention.3343668626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_tpm.3295727548 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3461203250 ps |
| CPU time | 314.96 seconds |
| Started | Sep 11 11:36:15 PM UTC 24 |
| Finished | Sep 11 11:41:34 PM UTC 24 |
| Peak memory | 636004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3295727548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_spi_device_tpm.3295727548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.2301325343 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2719558620 ps |
| CPU time | 305.32 seconds |
| Started | Sep 11 11:36:16 PM UTC 24 |
| Finished | Sep 11 11:41:26 PM UTC 24 |
| Peak memory | 623664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301325343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 1.chip_sw_spi_host_tx_rx.2301325343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.3679607146 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 9327067630 ps |
| CPU time | 589.58 seconds |
| Started | Sep 12 12:15:35 AM UTC 24 |
| Finished | Sep 12 12:25:33 AM UTC 24 |
| Peak memory | 625820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3679607146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.3679607146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1420073667 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 4798710414 ps |
| CPU time | 596.86 seconds |
| Started | Sep 12 12:15:10 AM UTC 24 |
| Finished | Sep 12 12:25:15 AM UTC 24 |
| Peak memory | 625824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420073667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_ access.1420073667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1585063044 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 6225864250 ps |
| CPU time | 688.18 seconds |
| Started | Sep 12 12:15:35 AM UTC 24 |
| Finished | Sep 12 12:27:12 AM UTC 24 |
| Peak memory | 625732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_ch eck=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585063044 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ct rl_scrambled_access_jitter_en.1585063044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3179491328 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 3995065315 ps |
| CPU time | 484.09 seconds |
| Started | Sep 12 12:36:07 AM UTC 24 |
| Finished | Sep 12 12:44:18 AM UTC 24 |
| Peak memory | 625768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_r eady_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179491328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3179491328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.2073981251 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 3095861336 ps |
| CPU time | 305.65 seconds |
| Started | Sep 12 12:48:35 AM UTC 24 |
| Finished | Sep 12 12:53:46 AM UTC 24 |
| Peak memory | 623528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073981251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_sram_ctrl_smoketest.2073981251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1854457481 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 20452651672 ps |
| CPU time | 3156.11 seconds |
| Started | Sep 11 11:55:38 PM UTC 24 |
| Finished | Sep 12 12:48:54 AM UTC 24 |
| Peak memory | 628884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1854457481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.1854457481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1068610206 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 5068619554 ps |
| CPU time | 533.57 seconds |
| Started | Sep 11 11:54:23 PM UTC 24 |
| Finished | Sep 12 12:03:26 AM UTC 24 |
| Peak memory | 628116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1068610206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_sysrst_ctrl_in_irq.1068610206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.69654166 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 2883971358 ps |
| CPU time | 296.49 seconds |
| Started | Sep 11 11:52:25 PM UTC 24 |
| Finished | Sep 11 11:57:28 PM UTC 24 |
| Peak memory | 627752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=69654166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_sysrst_ctrl_inputs.69654166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_outputs.4192182308 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 4132092360 ps |
| CPU time | 447.05 seconds |
| Started | Sep 11 11:54:54 PM UTC 24 |
| Finished | Sep 12 12:02:28 AM UTC 24 |
| Peak memory | 623692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=4192182308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_sysrst_ctrl_outputs.4192182308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.4231780216 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 23762692980 ps |
| CPU time | 1629.41 seconds |
| Started | Sep 11 11:54:53 PM UTC 24 |
| Finished | Sep 12 12:22:25 AM UTC 24 |
| Peak memory | 630188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_i mages=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231780216 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.4231780216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.821808777 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 5660809880 ps |
| CPU time | 399.16 seconds |
| Started | Sep 11 11:54:28 PM UTC 24 |
| Finished | Sep 12 12:01:13 AM UTC 24 |
| Peak memory | 625956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=821808777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.821808777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.1052328483 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 8041969502 ps |
| CPU time | 1550.42 seconds |
| Started | Sep 11 11:34:14 PM UTC 24 |
| Finished | Sep 12 12:00:25 AM UTC 24 |
| Peak memory | 636116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052328483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.1052328483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_smoketest.4253248969 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 3328701632 ps |
| CPU time | 245.52 seconds |
| Started | Sep 12 12:49:04 AM UTC 24 |
| Finished | Sep 12 12:53:14 AM UTC 24 |
| Peak memory | 623456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=4253248969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_sw_uart_smoketest.4253248969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx.1345936423 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 4224170998 ps |
| CPU time | 650.17 seconds |
| Started | Sep 11 11:30:46 PM UTC 24 |
| Finished | Sep 11 11:41:46 PM UTC 24 |
| Peak memory | 640116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345936423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.1345936423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2218271963 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 4093804362 ps |
| CPU time | 719.11 seconds |
| Started | Sep 11 11:34:21 PM UTC 24 |
| Finished | Sep 11 11:46:31 PM UTC 24 |
| Peak memory | 635952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218271963 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_alt_clk_freq.2218271963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4188051214 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 8996088049 ps |
| CPU time | 1018.45 seconds |
| Started | Sep 11 11:34:20 PM UTC 24 |
| Finished | Sep 11 11:51:33 PM UTC 24 |
| Peak memory | 635960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188051214 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4188051214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1220956524 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 80516916265 ps |
| CPU time | 16960.1 seconds |
| Started | Sep 11 11:32:14 PM UTC 24 |
| Finished | Sep 12 04:18:16 AM UTC 24 |
| Peak memory | 655532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout _ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220956524 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.1220956524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx1.4016070832 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 4586831930 ps |
| CPU time | 712.79 seconds |
| Started | Sep 11 11:30:46 PM UTC 24 |
| Finished | Sep 11 11:42:49 PM UTC 24 |
| Peak memory | 640208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016070832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.4016070832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx2.3612183188 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 4530361132 ps |
| CPU time | 565.41 seconds |
| Started | Sep 11 11:31:02 PM UTC 24 |
| Finished | Sep 11 11:40:35 PM UTC 24 |
| Peak memory | 639928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612183188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.3612183188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx3.1483433307 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 4649541148 ps |
| CPU time | 643.02 seconds |
| Started | Sep 11 11:31:05 PM UTC 24 |
| Finished | Sep 11 11:41:57 PM UTC 24 |
| Peak memory | 639992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483433307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.1483433307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.713340971 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 2640260354 ps |
| CPU time | 156.6 seconds |
| Started | Sep 12 12:31:27 AM UTC 24 |
| Finished | Sep 12 12:34:07 AM UTC 24 |
| Peak memory | 638004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713340971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.713340971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.2748954737 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 5986408785 ps |
| CPU time | 504.86 seconds |
| Started | Sep 12 12:32:41 AM UTC 24 |
| Finished | Sep 12 12:41:13 AM UTC 24 |
| Peak memory | 642672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748954737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.2748954737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.1837236684 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 2727571333 ps |
| CPU time | 153.45 seconds |
| Started | Sep 12 12:31:45 AM UTC 24 |
| Finished | Sep 12 12:34:21 AM UTC 24 |
| Peak memory | 640084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837236684 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.1837236684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_dev.1638648798 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 15698442550 ps |
| CPU time | 4379.68 seconds |
| Started | Sep 12 12:42:57 AM UTC 24 |
| Finished | Sep 12 01:56:53 AM UTC 24 |
| Peak memory | 626836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638648798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.1638648798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod.2142937529 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 16204298661 ps |
| CPU time | 4678.88 seconds |
| Started | Sep 12 12:42:56 AM UTC 24 |
| Finished | Sep 12 02:01:56 AM UTC 24 |
| Peak memory | 627028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142937529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.2142937529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod_end.1013893664 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 15746539427 ps |
| CPU time | 4303.71 seconds |
| Started | Sep 12 12:42:04 AM UTC 24 |
| Finished | Sep 12 01:54:42 AM UTC 24 |
| Peak memory | 626996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101389 3664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_in it_prod_end.1013893664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_rma.265877832 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 15495268648 ps |
| CPU time | 4260.56 seconds |
| Started | Sep 12 12:42:44 AM UTC 24 |
| Finished | Sep 12 01:54:38 AM UTC 24 |
| Peak memory | 629140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265877832 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.265877832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_test_unlocked0.870018415 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 11350399293 ps |
| CPU time | 3244.47 seconds |
| Started | Sep 12 12:42:31 AM UTC 24 |
| Finished | Sep 12 01:37:17 AM UTC 24 |
| Peak memory | 624020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=870018415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2 e_asm_init_test_unlocked0.870018415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3138887004 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 15091659100 ps |
| CPU time | 4128.97 seconds |
| Started | Sep 12 12:42:04 AM UTC 24 |
| Finished | Sep 12 01:51:44 AM UTC 24 |
| Peak memory | 626932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138887004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3138887004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.3417613649 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 15095488640 ps |
| CPU time | 4229.43 seconds |
| Started | Sep 12 12:41:29 AM UTC 24 |
| Finished | Sep 12 01:52:50 AM UTC 24 |
| Peak memory | 628760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417613649 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.3417613649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2188461954 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 15814981762 ps |
| CPU time | 4054.46 seconds |
| Started | Sep 12 12:42:30 AM UTC 24 |
| Finished | Sep 12 01:50:56 AM UTC 24 |
| Peak memory | 628916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188461954 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_no_meas.2188461954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_self_hash.709500279 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 26804139210 ps |
| CPU time | 7601.82 seconds |
| Started | Sep 12 12:42:18 AM UTC 24 |
| Finished | Sep 12 02:50:33 AM UTC 24 |
| Peak memory | 626708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_rules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709500279 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.709500279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_exception_c.345468576 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 14188248872 ps |
| CPU time | 3988.78 seconds |
| Started | Sep 12 12:41:45 AM UTC 24 |
| Finished | Sep 12 01:49:05 AM UTC 24 |
| Peak memory | 626768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345468576 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_exception_c.345468576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_output.2761152797 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 31611834192 ps |
| CPU time | 3988.56 seconds |
| Started | Sep 12 12:42:44 AM UTC 24 |
| Finished | Sep 12 01:50:04 AM UTC 24 |
| Peak memory | 628704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_flash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761152797 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.2761152797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_smoke.329485290 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 15578988360 ps |
| CPU time | 4484.54 seconds |
| Started | Sep 12 12:40:04 AM UTC 24 |
| Finished | Sep 12 01:55:47 AM UTC 24 |
| Peak memory | 626952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329485290 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.329485290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.rom_e2e_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_static_critical.1158863232 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 16628700826 ps |
| CPU time | 5062.28 seconds |
| Started | Sep 12 12:40:16 AM UTC 24 |
| Finished | Sep 12 02:05:41 AM UTC 24 |
| Peak memory | 626868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158863232 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.1158863232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.1037736071 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 4369107200 ps |
| CPU time | 461.23 seconds |
| Started | Sep 12 12:41:59 AM UTC 24 |
| Finished | Sep 12 12:49:47 AM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037736071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 1.rom_keymgr_functest.1037736071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.rom_keymgr_functest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_raw_unlock.530444419 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 5792664817 ps |
| CPU time | 268.9 seconds |
| Started | Sep 12 12:41:57 AM UTC 24 |
| Finished | Sep 12 12:46:31 AM UTC 24 |
| Peak memory | 637772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images =empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530444419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.530444419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_volatile_raw_unlock.3326427551 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 2754011608 ps |
| CPU time | 130.71 seconds |
| Started | Sep 12 12:41:28 AM UTC 24 |
| Finished | Sep 12 12:43:41 AM UTC 24 |
| Peak memory | 633252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRa w +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot _flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3326427551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.3326427551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.rom_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.38761125 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 7799446300 ps |
| CPU time | 549.82 seconds |
| Started | Sep 12 02:48:50 AM UTC 24 |
| Finished | Sep 12 02:58:08 AM UTC 24 |
| Peak memory | 635900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=38761125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 10.chip_sw_lc_ctrl_transition.38761125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.350266366 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 3777377744 ps |
| CPU time | 452.08 seconds |
| Started | Sep 12 02:48:37 AM UTC 24 |
| Finished | Sep 12 02:56:16 AM UTC 24 |
| Peak memory | 636084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350266366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.350266366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_lc_ctrl_transition.1110401320 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 8616004895 ps |
| CPU time | 1066.27 seconds |
| Started | Sep 12 02:50:56 AM UTC 24 |
| Finished | Sep 12 03:08:57 AM UTC 24 |
| Peak memory | 640252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1110401320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 11.chip_sw_lc_ctrl_transition.1110401320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.3603400790 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 3768584152 ps |
| CPU time | 533.51 seconds |
| Started | Sep 12 02:51:09 AM UTC 24 |
| Finished | Sep 12 03:00:10 AM UTC 24 |
| Peak memory | 636096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603400790 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.3603400790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.549284205 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 6596422912 ps |
| CPU time | 560.76 seconds |
| Started | Sep 12 02:51:27 AM UTC 24 |
| Finished | Sep 12 03:00:56 AM UTC 24 |
| Peak memory | 635892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=549284205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.chip_sw_lc_ctrl_transition.549284205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.3342670077 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 8937549388 ps |
| CPU time | 1679.72 seconds |
| Started | Sep 12 02:51:27 AM UTC 24 |
| Finished | Sep 12 03:19:49 AM UTC 24 |
| Peak memory | 636236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342670077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.3342670077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.3817801614 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 9865771571 ps |
| CPU time | 931.49 seconds |
| Started | Sep 12 02:53:32 AM UTC 24 |
| Finished | Sep 12 03:09:16 AM UTC 24 |
| Peak memory | 638152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3817801614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 13.chip_sw_lc_ctrl_transition.3817801614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.2323736113 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 4289084170 ps |
| CPU time | 570.13 seconds |
| Started | Sep 12 02:52:52 AM UTC 24 |
| Finished | Sep 12 03:02:31 AM UTC 24 |
| Peak memory | 636080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323736113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.2323736113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.2975397653 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 5359729654 ps |
| CPU time | 534.43 seconds |
| Started | Sep 12 02:55:10 AM UTC 24 |
| Finished | Sep 12 03:04:12 AM UTC 24 |
| Peak memory | 636036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2975397653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 14.chip_sw_lc_ctrl_transition.2975397653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.1987835256 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 4902886790 ps |
| CPU time | 698.78 seconds |
| Started | Sep 12 02:54:29 AM UTC 24 |
| Finished | Sep 12 03:06:18 AM UTC 24 |
| Peak memory | 635888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987835256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.1987835256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.688661727 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 13447996372 ps |
| CPU time | 2373.21 seconds |
| Started | Sep 12 02:56:22 AM UTC 24 |
| Finished | Sep 12 03:36:26 AM UTC 24 |
| Peak memory | 636148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688661727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.688661727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.2307496162 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 3884500790 ps |
| CPU time | 531.86 seconds |
| Started | Sep 12 02:58:04 AM UTC 24 |
| Finished | Sep 12 03:07:05 AM UTC 24 |
| Peak memory | 635964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307496162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.2307496162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.340330979 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 13488796004 ps |
| CPU time | 2423.21 seconds |
| Started | Sep 12 02:59:07 AM UTC 24 |
| Finished | Sep 12 03:40:01 AM UTC 24 |
| Peak memory | 636028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340330979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.340330979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.4209015478 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 7868786860 ps |
| CPU time | 1408.05 seconds |
| Started | Sep 12 03:00:11 AM UTC 24 |
| Finished | Sep 12 03:23:58 AM UTC 24 |
| Peak memory | 636100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209015478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.4209015478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2390384900 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 3879779048 ps |
| CPU time | 478.93 seconds |
| Started | Sep 12 03:00:51 AM UTC 24 |
| Finished | Sep 12 03:08:57 AM UTC 24 |
| Peak memory | 672176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390384900 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2390384900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.2710413913 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 8485011070 ps |
| CPU time | 1529.16 seconds |
| Started | Sep 12 03:00:47 AM UTC 24 |
| Finished | Sep 12 03:26:36 AM UTC 24 |
| Peak memory | 636036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710413913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.2710413913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.1416235819 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 11250162300 ps |
| CPU time | 1177.52 seconds |
| Started | Sep 12 02:00:29 AM UTC 24 |
| Finished | Sep 12 02:20:23 AM UTC 24 |
| Peak memory | 623240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141623 5819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_csr_rw.1416235819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_mem_access.2008154541 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 13996806504 ps |
| CPU time | 1294.56 seconds |
| Started | Sep 12 02:00:46 AM UTC 24 |
| Finished | Sep 12 02:22:37 AM UTC 24 |
| Peak memory | 623072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008154541 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.2008154541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_jtag_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.2730371697 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 3751060594 ps |
| CPU time | 427.54 seconds |
| Started | Sep 12 01:53:08 AM UTC 24 |
| Finished | Sep 12 02:00:21 AM UTC 24 |
| Peak memory | 623464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2730371697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_plic_all_irqs_10.2730371697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_plic_all_irqs_10/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_rv_dm_ndm_reset_req.1916839425 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 3776744834 ps |
| CPU time | 434.95 seconds |
| Started | Sep 12 02:05:01 AM UTC 24 |
| Finished | Sep 12 02:12:23 AM UTC 24 |
| Peak memory | 635852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916839425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_ reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.1916839425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.1826813604 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 3329391528 ps |
| CPU time | 341.38 seconds |
| Started | Sep 12 12:50:44 AM UTC 24 |
| Finished | Sep 12 12:56:31 AM UTC 24 |
| Peak memory | 625672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim _dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826813604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.1826813604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sival_flash_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1343740840 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 19167339264 ps |
| CPU time | 654.23 seconds |
| Started | Sep 12 01:27:21 AM UTC 24 |
| Finished | Sep 12 01:38:24 AM UTC 24 |
| Peak memory | 636052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343740840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/c hip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1343740840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc.2699994171 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 2930168580 ps |
| CPU time | 274.44 seconds |
| Started | Sep 12 01:30:04 AM UTC 24 |
| Finished | Sep 12 01:34:43 AM UTC 24 |
| Peak memory | 623676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_i mages=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699994171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.2699994171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en.1597294606 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 3301867259 ps |
| CPU time | 342.42 seconds |
| Started | Sep 12 01:30:55 AM UTC 24 |
| Finished | Sep 12 01:36:43 AM UTC 24 |
| Peak memory | 623720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597294606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.1597294606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3335557329 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 3203024442 ps |
| CPU time | 235.95 seconds |
| Started | Sep 12 02:08:26 AM UTC 24 |
| Finished | Sep 12 02:12:26 AM UTC 24 |
| Peak memory | 623672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335557329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.3335557329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_entropy.3325636504 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 3160159880 ps |
| CPU time | 229.4 seconds |
| Started | Sep 12 01:36:37 AM UTC 24 |
| Finished | Sep 12 01:40:30 AM UTC 24 |
| Peak memory | 625732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325636504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_aes_entropy.3325636504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_idle.2113342213 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 2853452936 ps |
| CPU time | 246.39 seconds |
| Started | Sep 12 01:30:53 AM UTC 24 |
| Finished | Sep 12 01:35:03 AM UTC 24 |
| Peak memory | 625764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113342213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.2113342213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_masking_off.163010875 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 2956163899 ps |
| CPU time | 289.53 seconds |
| Started | Sep 12 01:30:53 AM UTC 24 |
| Finished | Sep 12 01:35:47 AM UTC 24 |
| Peak memory | 625796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163010875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_aes_masking_off.163010875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_masking_off/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_smoketest.3176481010 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 3114790054 ps |
| CPU time | 215.21 seconds |
| Started | Sep 12 02:15:38 AM UTC 24 |
| Finished | Sep 12 02:19:17 AM UTC 24 |
| Peak memory | 625652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3176481010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_a es_smoketest.3176481010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_entropy.583872120 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 3116296814 ps |
| CPU time | 322.04 seconds |
| Started | Sep 12 01:36:36 AM UTC 24 |
| Finished | Sep 12 01:42:04 AM UTC 24 |
| Peak memory | 623460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583872120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.583872120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_escalation.2545639415 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 5395183420 ps |
| CPU time | 663.33 seconds |
| Started | Sep 12 01:31:57 AM UTC 24 |
| Finished | Sep 12 01:43:09 AM UTC 24 |
| Peak memory | 636052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545639415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_ earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.2545639415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2300257095 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 8073226390 ps |
| CPU time | 1681.32 seconds |
| Started | Sep 12 01:35:20 AM UTC 24 |
| Finished | Sep 12 02:03:42 AM UTC 24 |
| Peak memory | 625896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300257095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_ea rlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.2300257095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.4183590440 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 6835645420 ps |
| CPU time | 1368.52 seconds |
| Started | Sep 12 01:35:41 AM UTC 24 |
| Finished | Sep 12 01:58:47 AM UTC 24 |
| Peak memory | 625564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183590440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_toggle.4183590440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.18422366 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 3800992750 ps |
| CPU time | 428.31 seconds |
| Started | Sep 12 01:34:37 AM UTC 24 |
| Finished | Sep 12 01:41:51 AM UTC 24 |
| Peak memory | 672180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18422366 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sle ep_mode_alerts.18422366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1436777325 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 11087154688 ps |
| CPU time | 1056.52 seconds |
| Started | Sep 12 01:34:37 AM UTC 24 |
| Finished | Sep 12 01:52:28 AM UTC 24 |
| Peak memory | 625716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436777325 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_hand ler_lpg_sleep_mode_pings.1436777325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_ok.2848349392 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 7892391210 ps |
| CPU time | 1291.17 seconds |
| Started | Sep 12 01:33:50 AM UTC 24 |
| Finished | Sep 12 01:55:38 AM UTC 24 |
| Peak memory | 623588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848349392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.2848349392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_timeout.3383891684 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 3463965064 ps |
| CPU time | 296.83 seconds |
| Started | Sep 12 01:32:43 AM UTC 24 |
| Finished | Sep 12 01:37:45 AM UTC 24 |
| Peak memory | 623716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383891684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.3383891684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2338989490 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 256232431624 ps |
| CPU time | 13528.4 seconds |
| Started | Sep 12 01:33:50 AM UTC 24 |
| Finished | Sep 12 05:21:42 AM UTC 24 |
| Peak memory | 628856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=s im_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338989490 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2338989490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_test.2241111966 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 3353837314 ps |
| CPU time | 390.41 seconds |
| Started | Sep 12 01:30:55 AM UTC 24 |
| Finished | Sep 12 01:37:31 AM UTC 24 |
| Peak memory | 623608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand om_seed=2241111966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aler t_test.2241111966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.608465509 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 5802685830 ps |
| CPU time | 374.14 seconds |
| Started | Sep 12 01:25:44 AM UTC 24 |
| Finished | Sep 12 01:32:03 AM UTC 24 |
| Peak memory | 623748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608465509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.608465509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_smoketest.3814000294 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 3359419592 ps |
| CPU time | 426.62 seconds |
| Started | Sep 12 02:16:50 AM UTC 24 |
| Finished | Sep 12 02:24:03 AM UTC 24 |
| Peak memory | 625716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814000294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_aon_timer_smoketest.3814000294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1814256332 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 10120274356 ps |
| CPU time | 984.89 seconds |
| Started | Sep 12 01:26:18 AM UTC 24 |
| Finished | Sep 12 01:42:57 AM UTC 24 |
| Peak memory | 625696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814256332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.1814256332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3688049854 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 4264305320 ps |
| CPU time | 506.04 seconds |
| Started | Sep 12 01:27:21 AM UTC 24 |
| Finished | Sep 12 01:35:54 AM UTC 24 |
| Peak memory | 623604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688049854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.3688049854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_outputs.4036768710 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 8350927608 ps |
| CPU time | 928.84 seconds |
| Started | Sep 12 02:01:19 AM UTC 24 |
| Finished | Sep 12 02:17:00 AM UTC 24 |
| Peak memory | 632032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_ clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h w/dv/tools/sim.tcl +ntb_random_seed=4036768710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.4036768710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_rst_inputs.221001019 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 14713189119 ps |
| CPU time | 1644.35 seconds |
| Started | Sep 12 02:11:17 AM UTC 24 |
| Finished | Sep 12 02:39:02 AM UTC 24 |
| Peak memory | 625876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_ images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221001019 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.221001019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3366064188 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 6666828694 ps |
| CPU time | 504.13 seconds |
| Started | Sep 12 01:55:27 AM UTC 24 |
| Finished | Sep 12 02:03:58 AM UTC 24 |
| Peak memory | 635912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_de vice=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366064188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.3366064188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1674832843 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 3806840534 ps |
| CPU time | 600.21 seconds |
| Started | Sep 12 01:56:39 AM UTC 24 |
| Finished | Sep 12 02:06:48 AM UTC 24 |
| Peak memory | 625564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674832843 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_dev.1674832843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3909382365 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 4648544974 ps |
| CPU time | 569.31 seconds |
| Started | Sep 12 01:57:33 AM UTC 24 |
| Finished | Sep 12 02:07:10 AM UTC 24 |
| Peak memory | 625620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909382365 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_rma.3909382365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2074553588 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 4574610736 ps |
| CPU time | 617.79 seconds |
| Started | Sep 12 01:56:36 AM UTC 24 |
| Finished | Sep 12 02:07:02 AM UTC 24 |
| Peak memory | 625848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207 4553588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_exter nal_clk_src_for_sw_fast_test_unlocked0.2074553588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3469570119 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 4375554600 ps |
| CPU time | 511.69 seconds |
| Started | Sep 12 01:56:41 AM UTC 24 |
| Finished | Sep 12 02:05:19 AM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469570119 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_dev.3469570119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.436137107 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 5416118998 ps |
| CPU time | 632.97 seconds |
| Started | Sep 12 01:59:31 AM UTC 24 |
| Finished | Sep 12 02:10:13 AM UTC 24 |
| Peak memory | 625888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436137107 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src _for_sw_slow_rma.436137107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.741883050 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 4514679146 ps |
| CPU time | 632.53 seconds |
| Started | Sep 12 01:56:37 AM UTC 24 |
| Finished | Sep 12 02:07:18 AM UTC 24 |
| Peak memory | 625912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741 883050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_extern al_clk_src_for_sw_slow_test_unlocked0.741883050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter.2694149954 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 2438106882 ps |
| CPU time | 320.16 seconds |
| Started | Sep 12 01:59:38 AM UTC 24 |
| Finished | Sep 12 02:05:03 AM UTC 24 |
| Peak memory | 623720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2694149954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_clkmgr_jitter.2694149954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2637995733 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 3805422440 ps |
| CPU time | 456.99 seconds |
| Started | Sep 12 01:59:37 AM UTC 24 |
| Finished | Sep 12 02:07:21 AM UTC 24 |
| Peak memory | 623468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=2637995733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_clkmgr_jitter_frequency.2637995733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2902158704 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 2423584354 ps |
| CPU time | 240.77 seconds |
| Started | Sep 12 02:07:37 AM UTC 24 |
| Finished | Sep 12 02:11:42 AM UTC 24 |
| Peak memory | 623588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkm gr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2902158704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.2902158704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2723334467 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 5195961952 ps |
| CPU time | 486.23 seconds |
| Started | Sep 12 01:54:52 AM UTC 24 |
| Finished | Sep 12 02:03:05 AM UTC 24 |
| Peak memory | 623780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2723334467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.2723334467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3911319371 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 5135633852 ps |
| CPU time | 344.53 seconds |
| Started | Sep 12 01:54:52 AM UTC 24 |
| Finished | Sep 12 02:00:42 AM UTC 24 |
| Peak memory | 625836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3911319371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_clkmgr_off_hmac_trans.3911319371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1750424617 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 4730573480 ps |
| CPU time | 543.15 seconds |
| Started | Sep 12 01:54:56 AM UTC 24 |
| Finished | Sep 12 02:04:07 AM UTC 24 |
| Peak memory | 623888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1750424617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_clkmgr_off_kmac_trans.1750424617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.386429650 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 4706478200 ps |
| CPU time | 535 seconds |
| Started | Sep 12 01:55:26 AM UTC 24 |
| Finished | Sep 12 02:04:29 AM UTC 24 |
| Peak memory | 623528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=386429650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.386429650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_peri.2178687115 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 8937622640 ps |
| CPU time | 1140.19 seconds |
| Started | Sep 12 01:54:55 AM UTC 24 |
| Finished | Sep 12 02:14:11 AM UTC 24 |
| Peak memory | 625632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_i mages=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178687115 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.2178687115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_reset_frequency.3457886350 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 3291061820 ps |
| CPU time | 389.65 seconds |
| Started | Sep 12 01:59:33 AM UTC 24 |
| Finished | Sep 12 02:06:08 AM UTC 24 |
| Peak memory | 623780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457886350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.3457886350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_sleep_frequency.502764710 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 4802872400 ps |
| CPU time | 529.57 seconds |
| Started | Sep 12 02:00:27 AM UTC 24 |
| Finished | Sep 12 02:09:24 AM UTC 24 |
| Peak memory | 625636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502764710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.502764710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_smoketest.565673110 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 3113673396 ps |
| CPU time | 304.86 seconds |
| Started | Sep 12 02:16:45 AM UTC 24 |
| Finished | Sep 12 02:21:55 AM UTC 24 |
| Peak memory | 625636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=565673110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _clkmgr_smoketest.565673110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency.1388847822 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 9612026224 ps |
| CPU time | 2082.59 seconds |
| Started | Sep 12 01:38:35 AM UTC 24 |
| Finished | Sep 12 02:13:45 AM UTC 24 |
| Peak memory | 625780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1388847822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 2.chip_sw_csrng_edn_concurrency.1388847822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.744828529 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 4164756608 ps |
| CPU time | 500.25 seconds |
| Started | Sep 12 01:39:05 AM UTC 24 |
| Finished | Sep 12 01:47:33 AM UTC 24 |
| Peak memory | 623468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744828529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_ fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.744828529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_kat_test.1590534922 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 2890371950 ps |
| CPU time | 331.59 seconds |
| Started | Sep 12 01:39:05 AM UTC 24 |
| Finished | Sep 12 01:44:41 AM UTC 24 |
| Peak memory | 625496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590534922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_csrng_kat_test.1590534922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2922401282 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 5539505016 ps |
| CPU time | 729.24 seconds |
| Started | Sep 12 01:38:31 AM UTC 24 |
| Finished | Sep 12 01:50:51 AM UTC 24 |
| Peak memory | 625908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_ otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922401282 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_lc_hw_debug_en_test.2922401282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_smoketest.2704086390 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 2863475500 ps |
| CPU time | 266.89 seconds |
| Started | Sep 12 02:16:58 AM UTC 24 |
| Finished | Sep 12 02:21:29 AM UTC 24 |
| Peak memory | 623460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2704086390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _csrng_smoketest.2704086390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.3698730330 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 6159082326 ps |
| CPU time | 689.86 seconds |
| Started | Sep 12 12:51:01 AM UTC 24 |
| Finished | Sep 12 01:02:40 AM UTC 24 |
| Peak memory | 625768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698730330 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.3698730330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_auto_mode.2291682844 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 6188484356 ps |
| CPU time | 1485.51 seconds |
| Started | Sep 12 01:37:33 AM UTC 24 |
| Finished | Sep 12 02:02:37 AM UTC 24 |
| Peak memory | 626084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_ device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291682844 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_auto_mode.2291682844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_boot_mode.47137437 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 3331975428 ps |
| CPU time | 569.87 seconds |
| Started | Sep 12 01:37:33 AM UTC 24 |
| Finished | Sep 12 01:47:11 AM UTC 24 |
| Peak memory | 625936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_ device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47137437 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_boot_mode.47137437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs.1941579001 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 6491972760 ps |
| CPU time | 1070.24 seconds |
| Started | Sep 12 01:41:42 AM UTC 24 |
| Finished | Sep 12 01:59:46 AM UTC 24 |
| Peak memory | 625772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941579001 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.1941579001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1883076393 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 5211877752 ps |
| CPU time | 912.86 seconds |
| Started | Sep 12 01:43:00 AM UTC 24 |
| Finished | Sep 12 01:58:26 AM UTC 24 |
| Peak memory | 625868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883076393 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.1883076393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_kat.337359590 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 3404007350 ps |
| CPU time | 621.64 seconds |
| Started | Sep 12 01:38:31 AM UTC 24 |
| Finished | Sep 12 01:49:01 AM UTC 24 |
| Peak memory | 629908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_a ssert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=337359590 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_edn_kat.337359590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_kat/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_sw_mode.593588107 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 9226320664 ps |
| CPU time | 1797.89 seconds |
| Started | Sep 12 01:38:34 AM UTC 24 |
| Finished | Sep 12 02:08:56 AM UTC 24 |
| Peak memory | 623592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=593588107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_edn_sw_mode.593588107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3579378670 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 2586883522 ps |
| CPU time | 241.17 seconds |
| Started | Sep 12 01:39:54 AM UTC 24 |
| Finished | Sep 12 01:43:59 AM UTC 24 |
| Peak memory | 623672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579378670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.3579378670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_csrng.3838559598 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 7755732970 ps |
| CPU time | 1559.93 seconds |
| Started | Sep 12 01:41:12 AM UTC 24 |
| Finished | Sep 12 02:07:31 AM UTC 24 |
| Peak memory | 623720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_ srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838559598 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.3838559598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_kat_test.2911928328 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 2930622686 ps |
| CPU time | 235.66 seconds |
| Started | Sep 12 01:37:01 AM UTC 24 |
| Finished | Sep 12 01:41:00 AM UTC 24 |
| Peak memory | 623460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911928328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.2911928328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_smoketest.732707669 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 3574173880 ps |
| CPU time | 396.07 seconds |
| Started | Sep 12 02:17:50 AM UTC 24 |
| Finished | Sep 12 02:24:32 AM UTC 24 |
| Peak memory | 623768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_de vice=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732707669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.732707669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.193700518 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 2899495960 ps |
| CPU time | 318.56 seconds |
| Started | Sep 12 12:49:44 AM UTC 24 |
| Finished | Sep 12 12:55:08 AM UTC 24 |
| Peak memory | 625640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=193700518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_example_concurrency.193700518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_example_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.1707194164 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 2607739680 ps |
| CPU time | 180.58 seconds |
| Started | Sep 12 12:49:09 AM UTC 24 |
| Finished | Sep 12 12:52:13 AM UTC 24 |
| Peak memory | 623740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1707194164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_example_flash.1707194164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_example_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.2920945881 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 2664731740 ps |
| CPU time | 157.42 seconds |
| Started | Sep 12 12:49:43 AM UTC 24 |
| Finished | Sep 12 12:52:23 AM UTC 24 |
| Peak memory | 625508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2920945881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ex ample_manufacturer.2920945881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_example_manufacturer/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.2696966470 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 2708727340 ps |
| CPU time | 113 seconds |
| Started | Sep 12 12:49:17 AM UTC 24 |
| Finished | Sep 12 12:51:12 AM UTC 24 |
| Peak memory | 623292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:t est_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2696966470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2. chip_sw_example_rom.2696966470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_example_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.234390387 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 62246297406 ps |
| CPU time | 12395.7 seconds |
| Started | Sep 12 12:54:06 AM UTC 24 |
| Finished | Sep 12 04:23:12 AM UTC 24 |
| Peak memory | 643356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw _build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234390387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.234390387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_crash_alert.3128083123 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 4900813832 ps |
| CPU time | 451.04 seconds |
| Started | Sep 12 02:07:11 AM UTC 24 |
| Finished | Sep 12 02:14:49 AM UTC 24 |
| Peak memory | 626168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check= 1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128083123 -assert nopostproc +UVM_TESTNAME=chip_base_test + UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.3128083123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access.4018644478 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 5620575048 ps |
| CPU time | 1034.21 seconds |
| Started | Sep 12 01:03:56 AM UTC 24 |
| Finished | Sep 12 01:21:24 AM UTC 24 |
| Peak memory | 623660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=4018644478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _flash_ctrl_access.4018644478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.253849636 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 6156668759 ps |
| CPU time | 920.11 seconds |
| Started | Sep 12 01:04:15 AM UTC 24 |
| Finished | Sep 12 01:19:48 AM UTC 24 |
| Peak memory | 623768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=253849636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_flash_ctrl_access_jitter_en.253849636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3215278842 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 7617113823 ps |
| CPU time | 1079.88 seconds |
| Started | Sep 12 02:08:28 AM UTC 24 |
| Finished | Sep 12 02:26:42 AM UTC 24 |
| Peak memory | 625808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215278842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3215278842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2981061711 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 5406847681 ps |
| CPU time | 984.76 seconds |
| Started | Sep 12 01:04:50 AM UTC 24 |
| Finished | Sep 12 01:21:28 AM UTC 24 |
| Peak memory | 623776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=2981061711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_flash_ctrl_clock_freqs.2981061711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1278139829 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 3315366206 ps |
| CPU time | 319.73 seconds |
| Started | Sep 12 01:04:51 AM UTC 24 |
| Finished | Sep 12 01:10:16 AM UTC 24 |
| Peak memory | 625876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1278139829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_flash_ctrl_idle_low_power.1278139829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2231955715 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 4786477436 ps |
| CPU time | 446.24 seconds |
| Started | Sep 12 01:03:57 AM UTC 24 |
| Finished | Sep 12 01:11:29 AM UTC 24 |
| Peak memory | 623532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231955715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ct rl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.2231955715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2749352133 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 5591665170 ps |
| CPU time | 1015.94 seconds |
| Started | Sep 12 02:15:49 AM UTC 24 |
| Finished | Sep 12 02:32:58 AM UTC 24 |
| Peak memory | 623776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2749352133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_flash_ctrl_mem_protection.2749352133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops.32996760 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 4650912000 ps |
| CPU time | 645.86 seconds |
| Started | Sep 12 01:03:52 AM UTC 24 |
| Finished | Sep 12 01:14:47 AM UTC 24 |
| Peak memory | 625836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32996760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.32996760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3645532970 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 4150874480 ps |
| CPU time | 570.07 seconds |
| Started | Sep 12 01:03:50 AM UTC 24 |
| Finished | Sep 12 01:13:28 AM UTC 24 |
| Peak memory | 621704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645532970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.3645532970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2503028897 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 5229901185 ps |
| CPU time | 639.1 seconds |
| Started | Sep 12 02:07:58 AM UTC 24 |
| Finished | Sep 12 02:18:46 AM UTC 24 |
| Peak memory | 623536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503028897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2503028897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_write_clear.1462622051 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 3290152662 ps |
| CPU time | 365.67 seconds |
| Started | Sep 12 02:07:10 AM UTC 24 |
| Finished | Sep 12 02:13:21 AM UTC 24 |
| Peak memory | 623452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_image s=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462622051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.1462622051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init.3906186051 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 24042872907 ps |
| CPU time | 1868.24 seconds |
| Started | Sep 12 01:04:48 AM UTC 24 |
| Finished | Sep 12 01:36:22 AM UTC 24 |
| Peak memory | 627880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906186051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_flash_init.3906186051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_init/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.3554397788 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 22759361575 ps |
| CPU time | 2088.13 seconds |
| Started | Sep 12 02:09:37 AM UTC 24 |
| Finished | Sep 12 02:44:52 AM UTC 24 |
| Peak memory | 626540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_buil d_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554397788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.3554397788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_scrambling_smoketest.4221266845 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 2510392824 ps |
| CPU time | 180.39 seconds |
| Started | Sep 12 02:14:36 AM UTC 24 |
| Finished | Sep 12 02:17:39 AM UTC 24 |
| Peak memory | 623644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_ima ges=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoketest_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221266845 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chi p_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.4221266845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio_smoketest.798958071 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 2392241727 ps |
| CPU time | 258.7 seconds |
| Started | Sep 12 02:17:50 AM UTC 24 |
| Finished | Sep 12 02:22:14 AM UTC 24 |
| Peak memory | 623520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=798958071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_gpio_smoketest.798958071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc.3362436804 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 3176125264 ps |
| CPU time | 286.93 seconds |
| Started | Sep 12 01:43:03 AM UTC 24 |
| Finished | Sep 12 01:47:55 AM UTC 24 |
| Peak memory | 623460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3362436804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_h mac_enc.3362436804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_idle.2066302000 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 2841964326 ps |
| CPU time | 271.52 seconds |
| Started | Sep 12 01:43:04 AM UTC 24 |
| Finished | Sep 12 01:47:40 AM UTC 24 |
| Peak memory | 623464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2066302000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_hmac_enc_idle.2066302000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en.1437940401 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 2411906447 ps |
| CPU time | 220.99 seconds |
| Started | Sep 12 01:43:00 AM UTC 24 |
| Finished | Sep 12 01:46:44 AM UTC 24 |
| Peak memory | 625756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1437940401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_hmac_enc_jitter_en.1437940401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3072205347 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 3398949341 ps |
| CPU time | 205.57 seconds |
| Started | Sep 12 02:08:29 AM UTC 24 |
| Finished | Sep 12 02:11:58 AM UTC 24 |
| Peak memory | 623460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072205347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.3072205347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_multistream.1461236038 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 8129841374 ps |
| CPU time | 1690.9 seconds |
| Started | Sep 12 01:43:59 AM UTC 24 |
| Finished | Sep 12 02:12:32 AM UTC 24 |
| Peak memory | 623544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1461236038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_multistream.1461236038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_multistream/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_oneshot.2509599116 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 3469332846 ps |
| CPU time | 345.91 seconds |
| Started | Sep 12 01:43:54 AM UTC 24 |
| Finished | Sep 12 01:49:45 AM UTC 24 |
| Peak memory | 623460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2509599116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_h mac_oneshot.2509599116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_smoketest.146175083 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 3144660548 ps |
| CPU time | 319.93 seconds |
| Started | Sep 12 02:18:22 AM UTC 24 |
| Finished | Sep 12 02:23:46 AM UTC 24 |
| Peak memory | 625508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=146175083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_h mac_smoketest.146175083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.1154689662 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 4228230956 ps |
| CPU time | 559.12 seconds |
| Started | Sep 12 12:56:50 AM UTC 24 |
| Finished | Sep 12 01:06:18 AM UTC 24 |
| Peak memory | 623596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1154689662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.1154689662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx.2257884781 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 4846941392 ps |
| CPU time | 673.71 seconds |
| Started | Sep 12 12:56:09 AM UTC 24 |
| Finished | Sep 12 01:07:32 AM UTC 24 |
| Peak memory | 625864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2257884781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_i2c_host_tx_rx.2257884781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3772373548 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4470017476 ps |
| CPU time | 753.92 seconds |
| Started | Sep 12 12:56:06 AM UTC 24 |
| Finished | Sep 12 01:08:51 AM UTC 24 |
| Peak memory | 625916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3772373548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.3772373548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3694892424 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 5130561744 ps |
| CPU time | 748.73 seconds |
| Started | Sep 12 12:56:06 AM UTC 24 |
| Finished | Sep 12 01:08:45 AM UTC 24 |
| Peak memory | 623832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3694892424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.3694892424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.2454633831 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 68485663443 ps |
| CPU time | 13615.3 seconds |
| Started | Sep 12 12:54:06 AM UTC 24 |
| Finished | Sep 12 04:43:40 AM UTC 24 |
| Peak memory | 643340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=1 50_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454633831 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.2454633831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation.459586701 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 11178497120 ps |
| CPU time | 2340.25 seconds |
| Started | Sep 12 01:43:55 AM UTC 24 |
| Finished | Sep 12 02:23:25 AM UTC 24 |
| Peak memory | 632104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459586701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_ derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.459586701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.262173966 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 9510309027 ps |
| CPU time | 1561.22 seconds |
| Started | Sep 12 01:45:00 AM UTC 24 |
| Finished | Sep 12 02:11:21 AM UTC 24 |
| Peak memory | 632136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262173966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.262173966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3629332264 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 8787743411 ps |
| CPU time | 1163.94 seconds |
| Started | Sep 12 02:08:54 AM UTC 24 |
| Finished | Sep 12 02:28:33 AM UTC 24 |
| Peak memory | 632068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629332264 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3629332264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_prod.156849925 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 13716505134 ps |
| CPU time | 2810.91 seconds |
| Started | Sep 12 01:44:40 AM UTC 24 |
| Finished | Sep 12 02:32:07 AM UTC 24 |
| Peak memory | 633864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_devic e=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156849925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.156849925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_aes.1246542011 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 11811288324 ps |
| CPU time | 2217.86 seconds |
| Started | Sep 12 01:45:32 AM UTC 24 |
| Finished | Sep 12 02:22:58 AM UTC 24 |
| Peak memory | 625740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246542011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sidel oad_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.1246542011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_kmac.3453235261 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 7979869068 ps |
| CPU time | 1223.86 seconds |
| Started | Sep 12 01:45:31 AM UTC 24 |
| Finished | Sep 12 02:06:12 AM UTC 24 |
| Peak memory | 625852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453235261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_side load_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.3453235261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.2595455933 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 14726483994 ps |
| CPU time | 4069.62 seconds |
| Started | Sep 12 01:46:59 AM UTC 24 |
| Finished | Sep 12 02:55:42 AM UTC 24 |
| Peak memory | 628920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595455933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.2595455933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_app_rom.3521580862 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 3441923820 ps |
| CPU time | 303.46 seconds |
| Started | Sep 12 01:48:30 AM UTC 24 |
| Finished | Sep 12 01:53:39 AM UTC 24 |
| Peak memory | 625768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=3521580862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_kmac_app_rom.3521580862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_entropy.2351311800 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 2793193710 ps |
| CPU time | 238.94 seconds |
| Started | Sep 12 01:05:19 AM UTC 24 |
| Finished | Sep 12 01:09:22 AM UTC 24 |
| Peak memory | 623464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=2351311800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_kmac_entropy.2351311800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_idle.3891730966 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 3043544956 ps |
| CPU time | 311.73 seconds |
| Started | Sep 12 01:48:47 AM UTC 24 |
| Finished | Sep 12 01:54:04 AM UTC 24 |
| Peak memory | 625572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3891730966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ kmac_idle.3891730966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_cshake.3611845531 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 2816519996 ps |
| CPU time | 269.99 seconds |
| Started | Sep 12 01:47:22 AM UTC 24 |
| Finished | Sep 12 01:51:56 AM UTC 24 |
| Peak memory | 625496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3611845531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_sw_kmac_mode_cshake.3611845531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac.4099279391 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 2857829992 ps |
| CPU time | 346.81 seconds |
| Started | Sep 12 01:47:49 AM UTC 24 |
| Finished | Sep 12 01:53:41 AM UTC 24 |
| Peak memory | 625692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099279391 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_kmac_mode_kmac.4099279391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.464642037 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 2542681388 ps |
| CPU time | 292.28 seconds |
| Started | Sep 12 01:48:41 AM UTC 24 |
| Finished | Sep 12 01:53:38 AM UTC 24 |
| Peak memory | 625504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_km ac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=464642037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_kmac_mode_kmac_jitter_en.464642037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.766029025 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 3902988324 ps |
| CPU time | 315.11 seconds |
| Started | Sep 12 02:08:55 AM UTC 24 |
| Finished | Sep 12 02:14:15 AM UTC 24 |
| Peak memory | 623476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766029025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.766029025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_smoketest.1105717273 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 2608733338 ps |
| CPU time | 368.79 seconds |
| Started | Sep 12 02:18:22 AM UTC 24 |
| Finished | Sep 12 02:24:37 AM UTC 24 |
| Peak memory | 623704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=1105717273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ kmac_smoketest.1105717273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.958807520 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 2593051864 ps |
| CPU time | 267.12 seconds |
| Started | Sep 12 01:05:19 AM UTC 24 |
| Finished | Sep 12 01:09:50 AM UTC 24 |
| Peak memory | 625628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=958807520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_lc_ctrl_otp_hw_cfg0.958807520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_program_error.2003931607 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 5002134800 ps |
| CPU time | 438.26 seconds |
| Started | Sep 12 02:01:33 AM UTC 24 |
| Finished | Sep 12 02:08:58 AM UTC 24 |
| Peak memory | 625908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003931607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_l c_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.2003931607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2631480840 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 3865641755 ps |
| CPU time | 225.96 seconds |
| Started | Sep 12 01:10:40 AM UTC 24 |
| Finished | Sep 12 01:14:30 AM UTC 24 |
| Peak memory | 636096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631480840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.2631480840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_transition.1104410072 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 6648919219 ps |
| CPU time | 650.09 seconds |
| Started | Sep 12 01:08:40 AM UTC 24 |
| Finished | Sep 12 01:19:39 AM UTC 24 |
| Peak memory | 636100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1104410072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_lc_ctrl_transition.1104410072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3889554056 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 2770832885 ps |
| CPU time | 128.27 seconds |
| Started | Sep 12 01:10:18 AM UTC 24 |
| Finished | Sep 12 01:12:29 AM UTC 24 |
| Peak memory | 635228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889554056 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.3889554056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1622816716 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 2367684189 ps |
| CPU time | 129.34 seconds |
| Started | Sep 12 01:10:45 AM UTC 24 |
| Finished | Sep 12 01:12:57 AM UTC 24 |
| Peak memory | 633440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSo urceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16228167 16 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc _ctrl_volatile_raw_unlock_ext_clk_48mhz.1622816716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.263289535 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 48415164600 ps |
| CPU time | 6311.44 seconds |
| Started | Sep 12 01:10:07 AM UTC 24 |
| Finished | Sep 12 02:56:38 AM UTC 24 |
| Peak memory | 643408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263289535 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_dev.263289535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.588337364 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 51477699920 ps |
| CPU time | 5786.23 seconds |
| Started | Sep 12 01:10:18 AM UTC 24 |
| Finished | Sep 12 02:47:57 AM UTC 24 |
| Peak memory | 643560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588337364 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prod.588337364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prodend.2327330983 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 9432404550 ps |
| CPU time | 889.67 seconds |
| Started | Sep 12 01:10:02 AM UTC 24 |
| Finished | Sep 12 01:25:04 AM UTC 24 |
| Peak memory | 638104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327330983 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.2327330983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.1007489256 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 45285884884 ps |
| CPU time | 6018.24 seconds |
| Started | Sep 12 01:11:08 AM UTC 24 |
| Finished | Sep 12 02:52:42 AM UTC 24 |
| Peak memory | 643412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +fl ash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007489256 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_rma.1007489256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.521488351 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 34734867181 ps |
| CPU time | 1893.75 seconds |
| Started | Sep 12 01:10:54 AM UTC 24 |
| Finished | Sep 12 01:42:53 AM UTC 24 |
| Peak memory | 640120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnl ock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521488351 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testunlocks.521488351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3456270573 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 16990079938 ps |
| CPU time | 4318.74 seconds |
| Started | Sep 12 01:28:20 AM UTC 24 |
| Finished | Sep 12 02:41:12 AM UTC 24 |
| Peak memory | 628956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456270573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.3456270573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2894242759 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 18264253666 ps |
| CPU time | 4426.31 seconds |
| Started | Sep 12 01:28:20 AM UTC 24 |
| Finished | Sep 12 02:43:02 AM UTC 24 |
| Peak memory | 628764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894242759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2894242759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3639779430 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 25411820830 ps |
| CPU time | 4472.97 seconds |
| Started | Sep 12 02:08:30 AM UTC 24 |
| Finished | Sep 12 03:24:01 AM UTC 24 |
| Peak memory | 629068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639779430 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3639779430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_mem_scramble.1254470389 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 3420031128 ps |
| CPU time | 480.37 seconds |
| Started | Sep 12 01:28:43 AM UTC 24 |
| Finished | Sep 12 01:36:50 AM UTC 24 |
| Peak memory | 625564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254470389 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.1254470389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_randomness.1313648941 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 5930498980 ps |
| CPU time | 839.11 seconds |
| Started | Sep 12 01:27:38 AM UTC 24 |
| Finished | Sep 12 01:41:49 AM UTC 24 |
| Peak memory | 625788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313648941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.1313648941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_randomness/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_smoketest.2223676577 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 11187167728 ps |
| CPU time | 2511.41 seconds |
| Started | Sep 12 02:19:36 AM UTC 24 |
| Finished | Sep 12 03:02:01 AM UTC 24 |
| Peak memory | 623892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2223676577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ otbn_smoketest.2223676577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2614915694 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 2907480542 ps |
| CPU time | 327.24 seconds |
| Started | Sep 12 01:08:10 AM UTC 24 |
| Finished | Sep 12 01:13:42 AM UTC 24 |
| Peak memory | 625752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_ error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2614915694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.2614915694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.337003670 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 7778649976 ps |
| CPU time | 1268.17 seconds |
| Started | Sep 12 01:06:04 AM UTC 24 |
| Finished | Sep 12 01:27:29 AM UTC 24 |
| Peak memory | 625584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337003670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.337003670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3226424535 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 8270196190 ps |
| CPU time | 1130.82 seconds |
| Started | Sep 12 01:07:11 AM UTC 24 |
| Finished | Sep 12 01:26:18 AM UTC 24 |
| Peak memory | 623796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_buil d_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226424535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.3226424535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3259919417 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 7249445508 ps |
| CPU time | 1338.46 seconds |
| Started | Sep 12 01:07:12 AM UTC 24 |
| Finished | Sep 12 01:29:49 AM UTC 24 |
| Peak memory | 625588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259919417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.3259919417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2148140775 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 4754212038 ps |
| CPU time | 543.32 seconds |
| Started | Sep 12 01:05:38 AM UTC 24 |
| Finished | Sep 12 01:14:48 AM UTC 24 |
| Peak memory | 623520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148140775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_ asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2148140775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_smoketest.2157154973 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 2977235358 ps |
| CPU time | 271.1 seconds |
| Started | Sep 12 02:19:46 AM UTC 24 |
| Finished | Sep 12 02:24:21 AM UTC 24 |
| Peak memory | 625632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2157154973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_otp_ctrl_smoketest.2157154973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.1806855659 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 3199301034 ps |
| CPU time | 325.98 seconds |
| Started | Sep 12 12:52:33 AM UTC 24 |
| Finished | Sep 12 12:58:04 AM UTC 24 |
| Peak memory | 623768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_im ages=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806855659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.1806855659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pattgen_ios/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_plic_sw_irq.2305858533 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 3120453136 ps |
| CPU time | 290.78 seconds |
| Started | Sep 12 01:53:41 AM UTC 24 |
| Finished | Sep 12 01:58:37 AM UTC 24 |
| Peak memory | 623712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2305858533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_plic_sw_irq.2305858533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_idle_load.3900394483 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 3959305096 ps |
| CPU time | 521.46 seconds |
| Started | Sep 12 02:10:07 AM UTC 24 |
| Finished | Sep 12 02:18:56 AM UTC 24 |
| Peak memory | 625488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900394483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_power_idle_load.3900394483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_idle_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_sleep_load.1979949691 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 4856651888 ps |
| CPU time | 406.35 seconds |
| Started | Sep 12 02:10:07 AM UTC 24 |
| Finished | Sep 12 02:17:00 AM UTC 24 |
| Peak memory | 625848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1979949691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.1979949691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_sleep_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_virus.2193126062 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 5653948664 ps |
| CPU time | 1386.21 seconds |
| Started | Sep 12 02:11:21 AM UTC 24 |
| Finished | Sep 12 02:34:45 AM UTC 24 |
| Peak memory | 640612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_tim eout_ns=400_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_ img_rma:4,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193126062 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_virus.2193126062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.217489380 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 12008956564 ps |
| CPU time | 1149.44 seconds |
| Started | Sep 12 01:13:36 AM UTC 24 |
| Finished | Sep 12 01:33:00 AM UTC 24 |
| Peak memory | 625716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217489380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_ all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.217489380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1044172412 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 21982407180 ps |
| CPU time | 1973.85 seconds |
| Started | Sep 12 01:52:36 AM UTC 24 |
| Finished | Sep 12 02:25:56 AM UTC 24 |
| Peak memory | 625648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044172412 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_re set_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.1044172412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2447766811 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 13281176943 ps |
| CPU time | 1474.36 seconds |
| Started | Sep 12 01:14:22 AM UTC 24 |
| Finished | Sep 12 01:39:16 AM UTC 24 |
| Peak memory | 625784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447766811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2447766811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3345276424 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 24131481120 ps |
| CPU time | 1465.58 seconds |
| Started | Sep 12 02:02:16 AM UTC 24 |
| Finished | Sep 12 02:27:00 AM UTC 24 |
| Peak memory | 625716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345276424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr _deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3345276424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3588128849 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 10217467800 ps |
| CPU time | 775.57 seconds |
| Started | Sep 12 01:15:44 AM UTC 24 |
| Finished | Sep 12 01:28:50 AM UTC 24 |
| Peak memory | 625636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_res et_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3588128849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.3588128849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4081596319 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 5908443552 ps |
| CPU time | 491.7 seconds |
| Started | Sep 12 01:19:20 AM UTC 24 |
| Finished | Sep 12 01:27:39 AM UTC 24 |
| Peak memory | 632116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081596319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4081596319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2136776304 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 9087284606 ps |
| CPU time | 488.92 seconds |
| Started | Sep 12 01:12:19 AM UTC 24 |
| Finished | Sep 12 01:20:34 AM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2136776304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_pwrmgr_full_aon_reset.2136776304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2931215239 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 4490168656 ps |
| CPU time | 392.43 seconds |
| Started | Sep 12 02:01:59 AM UTC 24 |
| Finished | Sep 12 02:08:37 AM UTC 24 |
| Peak memory | 623588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=2931215239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_pwrmgr_lowpower_cancel.2931215239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2955186593 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 4962090424 ps |
| CPU time | 411.8 seconds |
| Started | Sep 12 01:13:17 AM UTC 24 |
| Finished | Sep 12 01:20:15 AM UTC 24 |
| Peak memory | 631744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955186593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_mai n_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.2955186593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1080718869 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 11908246601 ps |
| CPU time | 1369.01 seconds |
| Started | Sep 12 01:15:09 AM UTC 24 |
| Finished | Sep 12 01:38:16 AM UTC 24 |
| Peak memory | 625776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_r eset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1080718869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1080718869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.973907853 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 7054953548 ps |
| CPU time | 455.52 seconds |
| Started | Sep 12 02:01:36 AM UTC 24 |
| Finished | Sep 12 02:09:18 AM UTC 24 |
| Peak memory | 625952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_w ake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=973907853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.973907853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3005060101 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 7780326184 ps |
| CPU time | 787.22 seconds |
| Started | Sep 12 01:15:44 AM UTC 24 |
| Finished | Sep 12 01:29:02 AM UTC 24 |
| Peak memory | 625832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_r eset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3005060101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.3005060101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3001651797 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 23540445123 ps |
| CPU time | 2739.34 seconds |
| Started | Sep 12 01:14:18 AM UTC 24 |
| Finished | Sep 12 02:00:32 AM UTC 24 |
| Peak memory | 626028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001651797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3001651797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1731574560 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 25538471978 ps |
| CPU time | 1821.01 seconds |
| Started | Sep 12 02:02:35 AM UTC 24 |
| Finished | Sep 12 02:33:20 AM UTC 24 |
| Peak memory | 625704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731574560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1731574560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.676294513 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 5334062042 ps |
| CPU time | 588.25 seconds |
| Started | Sep 12 02:03:44 AM UTC 24 |
| Finished | Sep 12 02:13:41 AM UTC 24 |
| Peak memory | 625708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676294513 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.676294513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3337998059 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 2879401480 ps |
| CPU time | 374.44 seconds |
| Started | Sep 12 01:20:40 AM UTC 24 |
| Finished | Sep 12 01:27:00 AM UTC 24 |
| Peak memory | 623708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3337998059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_pwrmgr_sleep_disabled.3337998059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3268192278 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 5830986978 ps |
| CPU time | 495.64 seconds |
| Started | Sep 12 01:52:22 AM UTC 24 |
| Finished | Sep 12 02:00:45 AM UTC 24 |
| Peak memory | 625756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_im ages=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268192278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3268192278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1479748884 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 6418464104 ps |
| CPU time | 591.16 seconds |
| Started | Sep 12 02:03:18 AM UTC 24 |
| Finished | Sep 12 02:13:17 AM UTC 24 |
| Peak memory | 625788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479748884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.1479748884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_smoketest.2323010324 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 6037706750 ps |
| CPU time | 481.53 seconds |
| Started | Sep 12 02:20:01 AM UTC 24 |
| Finished | Sep 12 02:28:09 AM UTC 24 |
| Peak memory | 623840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_ima ges=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323010324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.2323010324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1057965447 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 8021182412 ps |
| CPU time | 1211.28 seconds |
| Started | Sep 12 01:13:17 AM UTC 24 |
| Finished | Sep 12 01:33:45 AM UTC 24 |
| Peak memory | 625580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1057965447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.1057965447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3931372498 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 4886552388 ps |
| CPU time | 613.49 seconds |
| Started | Sep 12 01:20:55 AM UTC 24 |
| Finished | Sep 12 01:31:17 AM UTC 24 |
| Peak memory | 625868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_w hen_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=3931372498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3931372498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.4209537366 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 5562010424 ps |
| CPU time | 392.44 seconds |
| Started | Sep 12 02:20:01 AM UTC 24 |
| Finished | Sep 12 02:26:39 AM UTC 24 |
| Peak memory | 625876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=4209537366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_pwrmgr_usbdev_smoketest.4209537366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1912042444 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 4518745352 ps |
| CPU time | 595.32 seconds |
| Started | Sep 12 01:27:16 AM UTC 24 |
| Finished | Sep 12 01:37:20 AM UTC 24 |
| Peak memory | 623688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912042444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.1912042444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2345756133 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 9878412767 ps |
| CPU time | 584.5 seconds |
| Started | Sep 12 01:48:48 AM UTC 24 |
| Finished | Sep 12 01:58:41 AM UTC 24 |
| Peak memory | 625828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2345756133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.2345756133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_cpu_info.3862325474 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 5441161242 ps |
| CPU time | 691.01 seconds |
| Started | Sep 12 01:12:14 AM UTC 24 |
| Finished | Sep 12 01:23:55 AM UTC 24 |
| Peak memory | 625824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862325474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_sw_rstmgr_cpu_info.3862325474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1426235169 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 6336868792 ps |
| CPU time | 760.92 seconds |
| Started | Sep 12 12:51:04 AM UTC 24 |
| Finished | Sep 12 01:03:55 AM UTC 24 |
| Peak memory | 668052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426235169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr _cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.1426235169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_smoketest.1306013252 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 2380155360 ps |
| CPU time | 195.31 seconds |
| Started | Sep 12 02:22:33 AM UTC 24 |
| Finished | Sep 12 02:25:51 AM UTC 24 |
| Peak memory | 625660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1306013252 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_rstmgr_smoketest.1306013252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_req.1461989572 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 4603272516 ps |
| CPU time | 429.35 seconds |
| Started | Sep 12 01:11:25 AM UTC 24 |
| Finished | Sep 12 01:18:40 AM UTC 24 |
| Peak memory | 625580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1461989572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_rstmgr_sw_req.1461989572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_rst.2559539365 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 2611177244 ps |
| CPU time | 235.72 seconds |
| Started | Sep 12 01:11:10 AM UTC 24 |
| Finished | Sep 12 01:15:09 AM UTC 24 |
| Peak memory | 623632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2559539365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_rstmgr_sw_rst.2559539365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2696368345 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 3329369748 ps |
| CPU time | 302.63 seconds |
| Started | Sep 12 02:06:30 AM UTC 24 |
| Finished | Sep 12 02:11:37 AM UTC 24 |
| Peak memory | 625740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_im ages=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696368345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.2696368345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2457324594 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 2825223876 ps |
| CPU time | 243.62 seconds |
| Started | Sep 12 02:07:12 AM UTC 24 |
| Finished | Sep 12 02:11:19 AM UTC 24 |
| Peak memory | 625512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_inval idate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2457324594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.2457324594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2815539673 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 4509382272 ps |
| CPU time | 885.96 seconds |
| Started | Sep 12 01:29:42 AM UTC 24 |
| Finished | Sep 12 01:44:40 AM UTC 24 |
| Peak memory | 625816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815539673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.2815539673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_rnd.445734351 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 4909514668 ps |
| CPU time | 985.14 seconds |
| Started | Sep 12 01:29:39 AM UTC 24 |
| Finished | Sep 12 01:46:18 AM UTC 24 |
| Peak memory | 623708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_b uild_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445734351 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.445734351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.85332209 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 5700421400 ps |
| CPU time | 601.28 seconds |
| Started | Sep 12 02:04:54 AM UTC 24 |
| Finished | Sep 12 02:15:03 AM UTC 24 |
| Peak memory | 640088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_han dler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=85332209 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escal ation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.85332209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.1939505309 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 6111930080 ps |
| CPU time | 480.77 seconds |
| Started | Sep 12 02:04:54 AM UTC 24 |
| Finished | Sep 12 02:13:02 AM UTC 24 |
| Peak memory | 636088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_acc ess_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939505309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wak eup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.1939505309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.11771293 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 5175456960 ps |
| CPU time | 470.6 seconds |
| Started | Sep 12 02:04:53 AM UTC 24 |
| Finished | Sep 12 02:12:50 AM UTC 24 |
| Peak memory | 638060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm _reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11771293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_rese t_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.11771293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_plic_smoketest.2021711186 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 3407667396 ps |
| CPU time | 257.7 seconds |
| Started | Sep 12 02:21:02 AM UTC 24 |
| Finished | Sep 12 02:25:24 AM UTC 24 |
| Peak memory | 623452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=2021711186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_rv_plic_smoketest.2021711186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_irq.1759673630 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 2737582872 ps |
| CPU time | 325.63 seconds |
| Started | Sep 12 01:20:56 AM UTC 24 |
| Finished | Sep 12 01:26:26 AM UTC 24 |
| Peak memory | 625720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1759673630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_rv_timer_irq.1759673630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_smoketest.1215199989 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 2514619052 ps |
| CPU time | 273.4 seconds |
| Started | Sep 12 02:22:32 AM UTC 24 |
| Finished | Sep 12 02:27:10 AM UTC 24 |
| Peak memory | 625812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1215199989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_rv_timer_smoketest.1215199989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_status.1819818181 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 2753638160 ps |
| CPU time | 233.07 seconds |
| Started | Sep 12 01:51:41 AM UTC 24 |
| Finished | Sep 12 01:55:38 AM UTC 24 |
| Peak memory | 623720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819818181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_s tatus_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.1819818181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.109118070 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 4446762788 ps |
| CPU time | 316.36 seconds |
| Started | Sep 12 12:52:27 AM UTC 24 |
| Finished | Sep 12 12:57:49 AM UTC 24 |
| Peak memory | 625640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=109118070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_sleep_pin_retention.109118070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pwm_pulses.2140250758 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 8493937000 ps |
| CPU time | 1134.73 seconds |
| Started | Sep 12 12:52:32 AM UTC 24 |
| Finished | Sep 12 01:11:41 AM UTC 24 |
| Peak memory | 625900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2140250758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_sleep_pwm_pulses.2140250758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1671171830 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 7422115750 ps |
| CPU time | 657.44 seconds |
| Started | Sep 12 01:50:29 AM UTC 24 |
| Finished | Sep 12 02:01:35 AM UTC 24 |
| Peak memory | 625828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671171830 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_sram_ret_contents _no_scramble.1671171830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.641394713 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 8541745942 ps |
| CPU time | 842.7 seconds |
| Started | Sep 12 01:50:44 AM UTC 24 |
| Finished | Sep 12 02:04:59 AM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641394713 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_sram_ret_contents_scramble.641394713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through.850863494 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 7132274690 ps |
| CPU time | 693.9 seconds |
| Started | Sep 12 12:57:59 AM UTC 24 |
| Finished | Sep 12 01:09:43 AM UTC 24 |
| Peak memory | 640180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850863494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_spi_device_pass_through.850863494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through_collision.1951277000 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 3938591588 ps |
| CPU time | 612.19 seconds |
| Started | Sep 12 12:58:28 AM UTC 24 |
| Finished | Sep 12 01:08:48 AM UTC 24 |
| Peak memory | 640428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951277000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.1951277000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.3367538440 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 3893631063 ps |
| CPU time | 292.48 seconds |
| Started | Sep 12 12:57:56 AM UTC 24 |
| Finished | Sep 12 01:02:53 AM UTC 24 |
| Peak memory | 636068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3367538440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_device_pinmux_sleep_retention.3367538440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_tpm.3760659591 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3352338473 ps |
| CPU time | 348.43 seconds |
| Started | Sep 12 12:57:09 AM UTC 24 |
| Finished | Sep 12 01:03:03 AM UTC 24 |
| Peak memory | 636228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3760659591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_spi_device_tpm.3760659591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_execution_main.3467074439 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 9148273009 ps |
| CPU time | 787.95 seconds |
| Started | Sep 12 01:50:29 AM UTC 24 |
| Finished | Sep 12 02:03:47 AM UTC 24 |
| Peak memory | 625840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3467074439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.3467074439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.10185314 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 5503796250 ps |
| CPU time | 604.05 seconds |
| Started | Sep 12 01:49:52 AM UTC 24 |
| Finished | Sep 12 02:00:04 AM UTC 24 |
| Peak memory | 625740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10185314 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access.10185314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1323611188 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 4310607350 ps |
| CPU time | 679.96 seconds |
| Started | Sep 12 01:49:53 AM UTC 24 |
| Finished | Sep 12 02:01:22 AM UTC 24 |
| Peak memory | 625768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_ch eck=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323611188 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ct rl_scrambled_access_jitter_en.1323611188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.8197941 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 4707870969 ps |
| CPU time | 487.63 seconds |
| Started | Sep 12 02:09:17 AM UTC 24 |
| Finished | Sep 12 02:17:31 AM UTC 24 |
| Peak memory | 625828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_r eady_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8197941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.8197941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_smoketest.647281567 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 3574700726 ps |
| CPU time | 340.37 seconds |
| Started | Sep 12 02:22:39 AM UTC 24 |
| Finished | Sep 12 02:28:25 AM UTC 24 |
| Peak memory | 623608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647281567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_sram_ctrl_smoketest.647281567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3003850246 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 20591768260 ps |
| CPU time | 3399.1 seconds |
| Started | Sep 12 01:24:04 AM UTC 24 |
| Finished | Sep 12 02:21:27 AM UTC 24 |
| Peak memory | 625868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3003850246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.3003850246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2780011750 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 4527896434 ps |
| CPU time | 679.04 seconds |
| Started | Sep 12 01:22:23 AM UTC 24 |
| Finished | Sep 12 01:33:54 AM UTC 24 |
| Peak memory | 630096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2780011750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_sysrst_ctrl_in_irq.2780011750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1247410463 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 3002588328 ps |
| CPU time | 291.98 seconds |
| Started | Sep 12 01:21:35 AM UTC 24 |
| Finished | Sep 12 01:26:32 AM UTC 24 |
| Peak memory | 628060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1247410463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_sysrst_ctrl_inputs.1247410463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3599728991 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 3405653976 ps |
| CPU time | 330.84 seconds |
| Started | Sep 12 01:23:50 AM UTC 24 |
| Finished | Sep 12 01:29:26 AM UTC 24 |
| Peak memory | 625564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3599728991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_sysrst_ctrl_outputs.3599728991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_reset.2161255946 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 22890153400 ps |
| CPU time | 1611.14 seconds |
| Started | Sep 12 01:22:27 AM UTC 24 |
| Finished | Sep 12 01:49:38 AM UTC 24 |
| Peak memory | 630060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_i mages=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161255946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.2161255946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3612562511 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 5826644500 ps |
| CPU time | 427.58 seconds |
| Started | Sep 12 01:22:26 AM UTC 24 |
| Finished | Sep 12 01:29:40 AM UTC 24 |
| Peak memory | 625844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3612562511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3612562511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_rand_baudrate.3776610581 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 8369158380 ps |
| CPU time | 1599.26 seconds |
| Started | Sep 12 12:54:36 AM UTC 24 |
| Finished | Sep 12 01:21:36 AM UTC 24 |
| Peak memory | 636076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776610581 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.3776610581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_smoketest.3596969963 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 3250830000 ps |
| CPU time | 275.89 seconds |
| Started | Sep 12 02:22:51 AM UTC 24 |
| Finished | Sep 12 02:27:31 AM UTC 24 |
| Peak memory | 623604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3596969963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_sw_uart_smoketest.3596969963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx.3696452004 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 4483075384 ps |
| CPU time | 657.55 seconds |
| Started | Sep 12 12:53:22 AM UTC 24 |
| Finished | Sep 12 01:04:29 AM UTC 24 |
| Peak memory | 640056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696452004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.3696452004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1000419530 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 4440978102 ps |
| CPU time | 549.75 seconds |
| Started | Sep 12 12:54:36 AM UTC 24 |
| Finished | Sep 12 01:03:54 AM UTC 24 |
| Peak memory | 634148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000419530 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_alt_clk_freq.1000419530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2940712139 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 3914456476 ps |
| CPU time | 445.02 seconds |
| Started | Sep 12 12:55:12 AM UTC 24 |
| Finished | Sep 12 01:02:43 AM UTC 24 |
| Peak memory | 633848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940712139 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2940712139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1717362405 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 81105940182 ps |
| CPU time | 15318.1 seconds |
| Started | Sep 12 12:53:38 AM UTC 24 |
| Finished | Sep 12 05:11:47 AM UTC 24 |
| Peak memory | 657680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout _ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717362405 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.1717362405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx1.2008436762 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 3949250292 ps |
| CPU time | 689.51 seconds |
| Started | Sep 12 12:53:19 AM UTC 24 |
| Finished | Sep 12 01:04:59 AM UTC 24 |
| Peak memory | 640052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008436762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.2008436762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx2.3242298028 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 4189402560 ps |
| CPU time | 626.14 seconds |
| Started | Sep 12 12:54:00 AM UTC 24 |
| Finished | Sep 12 01:04:36 AM UTC 24 |
| Peak memory | 639924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242298028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.3242298028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx3.3605106481 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 4407731876 ps |
| CPU time | 671.57 seconds |
| Started | Sep 12 12:54:04 AM UTC 24 |
| Finished | Sep 12 01:05:25 AM UTC 24 |
| Peak memory | 640144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605106481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.3605106481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_dev.2716832616 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 2671440870 ps |
| CPU time | 189.32 seconds |
| Started | Sep 12 02:05:02 AM UTC 24 |
| Finished | Sep 12 02:08:15 AM UTC 24 |
| Peak memory | 640108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716832616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.2716832616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_prod.1088904533 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 2800466521 ps |
| CPU time | 132.53 seconds |
| Started | Sep 12 02:05:50 AM UTC 24 |
| Finished | Sep 12 02:08:05 AM UTC 24 |
| Peak memory | 639468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088904533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.1088904533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_rma.1276698360 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 5572359786 ps |
| CPU time | 481.68 seconds |
| Started | Sep 12 02:05:36 AM UTC 24 |
| Finished | Sep 12 02:13:44 AM UTC 24 |
| Peak memory | 640368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276698360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_tap_straps_rma.1276698360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_testunlock0.3382697648 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 5222421177 ps |
| CPU time | 451.64 seconds |
| Started | Sep 12 02:05:35 AM UTC 24 |
| Finished | Sep 12 02:13:14 AM UTC 24 |
| Peak memory | 650672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382697648 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.3382697648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_dev.1387060925 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 15892274883 ps |
| CPU time | 3989.41 seconds |
| Started | Sep 12 02:16:40 AM UTC 24 |
| Finished | Sep 12 03:24:00 AM UTC 24 |
| Peak memory | 629004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387060925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.1387060925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod.367676440 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 15966492581 ps |
| CPU time | 4013.3 seconds |
| Started | Sep 12 02:16:45 AM UTC 24 |
| Finished | Sep 12 03:24:27 AM UTC 24 |
| Peak memory | 627048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367676440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.367676440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod_end.2823669346 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 15412128472 ps |
| CPU time | 4245.92 seconds |
| Started | Sep 12 02:16:59 AM UTC 24 |
| Finished | Sep 12 03:28:38 AM UTC 24 |
| Peak memory | 623912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282366 9346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_in it_prod_end.2823669346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_rma.2164344030 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 14849239439 ps |
| CPU time | 3951.14 seconds |
| Started | Sep 12 02:16:40 AM UTC 24 |
| Finished | Sep 12 03:23:20 AM UTC 24 |
| Peak memory | 626884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164344030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.2164344030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2946053170 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 11359683710 ps |
| CPU time | 3303.65 seconds |
| Started | Sep 12 02:16:24 AM UTC 24 |
| Finished | Sep 12 03:12:10 AM UTC 24 |
| Peak memory | 627072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2946053170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e 2e_asm_init_test_unlocked0.2946053170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3680285151 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 15127558820 ps |
| CPU time | 4046.83 seconds |
| Started | Sep 12 02:16:57 AM UTC 24 |
| Finished | Sep 12 03:25:16 AM UTC 24 |
| Peak memory | 626728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680285151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3680285151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2494962893 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 15712831432 ps |
| CPU time | 4196.02 seconds |
| Started | Sep 12 02:16:13 AM UTC 24 |
| Finished | Sep 12 03:27:03 AM UTC 24 |
| Peak memory | 628888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494962893 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.2494962893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.724009231 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 14576367240 ps |
| CPU time | 3954.75 seconds |
| Started | Sep 12 02:16:05 AM UTC 24 |
| Finished | Sep 12 03:22:49 AM UTC 24 |
| Peak memory | 626852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724009231 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_no_meas.724009231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.764482133 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 26163861640 ps |
| CPU time | 6574.17 seconds |
| Started | Sep 12 02:16:59 AM UTC 24 |
| Finished | Sep 12 04:07:52 AM UTC 24 |
| Peak memory | 628756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_rules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764482133 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.764482133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.rom_e2e_self_hash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.1295751810 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 15196565307 ps |
| CPU time | 4120.65 seconds |
| Started | Sep 12 02:15:50 AM UTC 24 |
| Finished | Sep 12 03:25:22 AM UTC 24 |
| Peak memory | 628960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295751810 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_exception_c.1295751810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.2580563586 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 23580661944 ps |
| CPU time | 3976.24 seconds |
| Started | Sep 12 02:16:46 AM UTC 24 |
| Finished | Sep 12 03:23:51 AM UTC 24 |
| Peak memory | 628620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_flash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580563586 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.2580563586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.rom_e2e_shutdown_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.3382750355 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 15214721544 ps |
| CPU time | 4197.81 seconds |
| Started | Sep 12 02:15:36 AM UTC 24 |
| Finished | Sep 12 03:26:26 AM UTC 24 |
| Peak memory | 629012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382750355 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.3382750355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.rom_e2e_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.2922684436 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 16893384064 ps |
| CPU time | 4393.71 seconds |
| Started | Sep 12 02:16:52 AM UTC 24 |
| Finished | Sep 12 03:31:01 AM UTC 24 |
| Peak memory | 626968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922684436 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.2922684436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.rom_e2e_static_critical/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_keymgr_functest.2417630763 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 5818967380 ps |
| CPU time | 794.16 seconds |
| Started | Sep 12 02:16:43 AM UTC 24 |
| Finished | Sep 12 02:30:08 AM UTC 24 |
| Peak memory | 625836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417630763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 2.rom_keymgr_functest.2417630763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.rom_keymgr_functest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_raw_unlock.1747402244 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 6514480917 ps |
| CPU time | 296.11 seconds |
| Started | Sep 12 02:16:48 AM UTC 24 |
| Finished | Sep 12 02:21:48 AM UTC 24 |
| Peak memory | 637692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images =empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747402244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.1747402244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.rom_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_volatile_raw_unlock.591782745 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 2498689548 ps |
| CPU time | 135.9 seconds |
| Started | Sep 12 02:16:51 AM UTC 24 |
| Finished | Sep 12 02:19:10 AM UTC 24 |
| Peak memory | 633184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRa w +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot _flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=591782745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.591782745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.rom_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.181988210 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 3090463140 ps |
| CPU time | 453.61 seconds |
| Started | Sep 12 03:03:29 AM UTC 24 |
| Finished | Sep 12 03:11:10 AM UTC 24 |
| Peak memory | 672304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181988210 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_alert_handler_lpg_s leep_mode_alerts.181988210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.3450093161 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 5284785520 ps |
| CPU time | 733.45 seconds |
| Started | Sep 12 03:03:25 AM UTC 24 |
| Finished | Sep 12 03:15:48 AM UTC 24 |
| Peak memory | 674420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450093161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.3450093161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.395078025 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 3746078682 ps |
| CPU time | 339.17 seconds |
| Started | Sep 12 02:26:40 AM UTC 24 |
| Finished | Sep 12 02:32:24 AM UTC 24 |
| Peak memory | 672376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395078025 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_alert_handler_lpg_sl eep_mode_alerts.395078025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_all_escalation_resets.2582189163 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 5722019360 ps |
| CPU time | 680.84 seconds |
| Started | Sep 12 02:22:55 AM UTC 24 |
| Finished | Sep 12 02:34:26 AM UTC 24 |
| Peak memory | 625712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582189163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.2582189163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2652143699 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 5785105840 ps |
| CPU time | 287.03 seconds |
| Started | Sep 12 02:26:40 AM UTC 24 |
| Finished | Sep 12 02:31:31 AM UTC 24 |
| Peak memory | 623736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652143699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2652143699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.781183861 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 26999771022 ps |
| CPU time | 6473.95 seconds |
| Started | Sep 12 02:27:42 AM UTC 24 |
| Finished | Sep 12 04:16:51 AM UTC 24 |
| Peak memory | 626864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=781183861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 3.chip_sw_csrng_edn_concurrency.781183861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_data_integrity_escalation.572431259 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 4821896524 ps |
| CPU time | 583.94 seconds |
| Started | Sep 12 02:23:17 AM UTC 24 |
| Finished | Sep 12 02:33:09 AM UTC 24 |
| Peak memory | 625708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572431259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.572431259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_lc_ctrl_transition.2343940021 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 12821021229 ps |
| CPU time | 813.8 seconds |
| Started | Sep 12 02:26:02 AM UTC 24 |
| Finished | Sep 12 02:39:47 AM UTC 24 |
| Peak memory | 638084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2343940021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 3.chip_sw_lc_ctrl_transition.2343940021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.847701498 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 8428618190 ps |
| CPU time | 1488.96 seconds |
| Started | Sep 12 02:25:20 AM UTC 24 |
| Finished | Sep 12 02:50:29 AM UTC 24 |
| Peak memory | 635968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847701498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.847701498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx.4245830378 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 4854412956 ps |
| CPU time | 644.98 seconds |
| Started | Sep 12 02:23:37 AM UTC 24 |
| Finished | Sep 12 02:34:31 AM UTC 24 |
| Peak memory | 639920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245830378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.4245830378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1878036544 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 4054083656 ps |
| CPU time | 438.21 seconds |
| Started | Sep 12 02:25:25 AM UTC 24 |
| Finished | Sep 12 02:32:50 AM UTC 24 |
| Peak memory | 635948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878036544 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_alt_clk_freq.1878036544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1461460960 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 4876254072 ps |
| CPU time | 612.33 seconds |
| Started | Sep 12 02:25:26 AM UTC 24 |
| Finished | Sep 12 02:35:48 AM UTC 24 |
| Peak memory | 636100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461460960 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1461460960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx1.3093757549 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 4654144000 ps |
| CPU time | 576.4 seconds |
| Started | Sep 12 02:24:04 AM UTC 24 |
| Finished | Sep 12 02:33:48 AM UTC 24 |
| Peak memory | 640112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093757549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.3093757549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx2.1002567990 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 4227664264 ps |
| CPU time | 560.46 seconds |
| Started | Sep 12 02:24:26 AM UTC 24 |
| Finished | Sep 12 02:33:55 AM UTC 24 |
| Peak memory | 639864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002567990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.1002567990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx3.1666772215 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 5083647052 ps |
| CPU time | 754.86 seconds |
| Started | Sep 12 02:24:43 AM UTC 24 |
| Finished | Sep 12 02:37:28 AM UTC 24 |
| Peak memory | 640148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666772215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.1666772215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_prod.59947243 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 2739585336 ps |
| CPU time | 205.34 seconds |
| Started | Sep 12 02:28:41 AM UTC 24 |
| Finished | Sep 12 02:32:10 AM UTC 24 |
| Peak memory | 637612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59947243 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.59947243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_rma.2930694301 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 4688136045 ps |
| CPU time | 313.34 seconds |
| Started | Sep 12 02:28:04 AM UTC 24 |
| Finished | Sep 12 02:33:22 AM UTC 24 |
| Peak memory | 648772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930694301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 3.chip_tap_straps_rma.2930694301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_testunlock0.1644098267 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 5926279866 ps |
| CPU time | 514.67 seconds |
| Started | Sep 12 02:27:43 AM UTC 24 |
| Finished | Sep 12 02:36:24 AM UTC 24 |
| Peak memory | 642668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644098267 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.1644098267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.123643283 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 6070635816 ps |
| CPU time | 717 seconds |
| Started | Sep 12 03:10:38 AM UTC 24 |
| Finished | Sep 12 03:22:45 AM UTC 24 |
| Peak memory | 674536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123643283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.123643283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.65088426 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 4716367624 ps |
| CPU time | 569.55 seconds |
| Started | Sep 12 03:11:26 AM UTC 24 |
| Finished | Sep 12 03:21:03 AM UTC 24 |
| Peak memory | 674500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65088426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esca lation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.65088426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.3951731364 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 4625694424 ps |
| CPU time | 526.85 seconds |
| Started | Sep 12 03:11:50 AM UTC 24 |
| Finished | Sep 12 03:20:44 AM UTC 24 |
| Peak memory | 674544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951731364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.3951731364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1282189253 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 4265543316 ps |
| CPU time | 440.68 seconds |
| Started | Sep 12 03:13:58 AM UTC 24 |
| Finished | Sep 12 03:21:25 AM UTC 24 |
| Peak memory | 636224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282189253 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1282189253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2556810458 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 3697133320 ps |
| CPU time | 430.3 seconds |
| Started | Sep 12 03:14:14 AM UTC 24 |
| Finished | Sep 12 03:21:30 AM UTC 24 |
| Peak memory | 672176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556810458 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2556810458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.2906494844 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 4186202676 ps |
| CPU time | 546.02 seconds |
| Started | Sep 12 03:14:44 AM UTC 24 |
| Finished | Sep 12 03:23:58 AM UTC 24 |
| Peak memory | 672384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906494844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.2906494844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2148136532 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 3987647280 ps |
| CPU time | 392.65 seconds |
| Started | Sep 12 03:16:09 AM UTC 24 |
| Finished | Sep 12 03:22:48 AM UTC 24 |
| Peak memory | 672428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148136532 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2148136532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1821721203 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 3856297416 ps |
| CPU time | 456.88 seconds |
| Started | Sep 12 02:34:34 AM UTC 24 |
| Finished | Sep 12 02:42:17 AM UTC 24 |
| Peak memory | 672412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821721203 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_alert_handler_lpg_s leep_mode_alerts.1821721203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.945382235 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 6895705076 ps |
| CPU time | 381.92 seconds |
| Started | Sep 12 02:34:34 AM UTC 24 |
| Finished | Sep 12 02:41:01 AM UTC 24 |
| Peak memory | 623732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945382235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.945382235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.4189603318 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 22915567436 ps |
| CPU time | 5603.15 seconds |
| Started | Sep 12 02:35:09 AM UTC 24 |
| Finished | Sep 12 04:09:38 AM UTC 24 |
| Peak memory | 629024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=4189603318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 4.chip_sw_csrng_edn_concurrency.4189603318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.1142060358 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 4838939128 ps |
| CPU time | 656.85 seconds |
| Started | Sep 12 02:29:18 AM UTC 24 |
| Finished | Sep 12 02:40:24 AM UTC 24 |
| Peak memory | 625840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142060358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.1142060358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.3659303719 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 12158672946 ps |
| CPU time | 797.09 seconds |
| Started | Sep 12 02:34:44 AM UTC 24 |
| Finished | Sep 12 02:48:12 AM UTC 24 |
| Peak memory | 638004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3659303719 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 4.chip_sw_lc_ctrl_transition.3659303719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.220292268 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 8152491416 ps |
| CPU time | 701.86 seconds |
| Started | Sep 12 02:35:08 AM UTC 24 |
| Finished | Sep 12 02:46:59 AM UTC 24 |
| Peak memory | 625568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220292268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.220292268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.3455044107 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 12719234066 ps |
| CPU time | 2843.42 seconds |
| Started | Sep 12 02:33:07 AM UTC 24 |
| Finished | Sep 12 03:21:08 AM UTC 24 |
| Peak memory | 635896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455044107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.3455044107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx.689338149 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 3595282000 ps |
| CPU time | 577.85 seconds |
| Started | Sep 12 02:30:49 AM UTC 24 |
| Finished | Sep 12 02:40:35 AM UTC 24 |
| Peak memory | 639860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689338149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.689338149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.854892796 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 12897588949 ps |
| CPU time | 2854.81 seconds |
| Started | Sep 12 02:34:45 AM UTC 24 |
| Finished | Sep 12 03:22:57 AM UTC 24 |
| Peak memory | 636132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854892796 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_alt_clk_freq.854892796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2134387165 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 13639149151 ps |
| CPU time | 1830.68 seconds |
| Started | Sep 12 02:34:07 AM UTC 24 |
| Finished | Sep 12 03:05:02 AM UTC 24 |
| Peak memory | 634152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134387165 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2134387165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx1.3637019742 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 4229437308 ps |
| CPU time | 561.03 seconds |
| Started | Sep 12 02:32:12 AM UTC 24 |
| Finished | Sep 12 02:41:41 AM UTC 24 |
| Peak memory | 639864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637019742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.3637019742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx2.1379875964 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 4447938626 ps |
| CPU time | 604.4 seconds |
| Started | Sep 12 02:33:08 AM UTC 24 |
| Finished | Sep 12 02:43:21 AM UTC 24 |
| Peak memory | 640140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379875964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.1379875964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx3.1042003799 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 4974176572 ps |
| CPU time | 667.9 seconds |
| Started | Sep 12 02:33:10 AM UTC 24 |
| Finished | Sep 12 02:44:28 AM UTC 24 |
| Peak memory | 639928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042003799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.1042003799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.4157340657 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 7275190204 ps |
| CPU time | 751.36 seconds |
| Started | Sep 12 02:34:46 AM UTC 24 |
| Finished | Sep 12 02:47:27 AM UTC 24 |
| Peak memory | 642604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157340657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.4157340657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.539073292 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 11706628880 ps |
| CPU time | 1051.84 seconds |
| Started | Sep 12 02:35:09 AM UTC 24 |
| Finished | Sep 12 02:52:54 AM UTC 24 |
| Peak memory | 640524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539073292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.539073292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_rma.2418648570 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 2637616409 ps |
| CPU time | 187.33 seconds |
| Started | Sep 12 02:35:11 AM UTC 24 |
| Finished | Sep 12 02:38:21 AM UTC 24 |
| Peak memory | 642176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418648570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 4.chip_tap_straps_rma.2418648570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_testunlock0.3547863913 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 2923913301 ps |
| CPU time | 147.69 seconds |
| Started | Sep 12 02:35:11 AM UTC 24 |
| Finished | Sep 12 02:37:42 AM UTC 24 |
| Peak memory | 638444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547863913 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.3547863913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.3604610004 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 5016756384 ps |
| CPU time | 591.56 seconds |
| Started | Sep 12 03:18:41 AM UTC 24 |
| Finished | Sep 12 03:28:41 AM UTC 24 |
| Peak memory | 674524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604610004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.3604610004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3342575617 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 3835808884 ps |
| CPU time | 369.42 seconds |
| Started | Sep 12 03:18:45 AM UTC 24 |
| Finished | Sep 12 03:25:00 AM UTC 24 |
| Peak memory | 672428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342575617 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3342575617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.1187373837 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 4612068940 ps |
| CPU time | 454.51 seconds |
| Started | Sep 12 03:18:51 AM UTC 24 |
| Finished | Sep 12 03:26:32 AM UTC 24 |
| Peak memory | 636400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187373837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.1187373837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.894114000 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 3361017448 ps |
| CPU time | 348.15 seconds |
| Started | Sep 12 03:18:52 AM UTC 24 |
| Finished | Sep 12 03:24:45 AM UTC 24 |
| Peak memory | 672428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894114000 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_alert_handler_lpg_s leep_mode_alerts.894114000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2584887074 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 3596094488 ps |
| CPU time | 354.54 seconds |
| Started | Sep 12 03:20:01 AM UTC 24 |
| Finished | Sep 12 03:26:00 AM UTC 24 |
| Peak memory | 672172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584887074 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2584887074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.1929880149 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 5556944960 ps |
| CPU time | 494.97 seconds |
| Started | Sep 12 03:19:27 AM UTC 24 |
| Finished | Sep 12 03:27:49 AM UTC 24 |
| Peak memory | 674516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929880149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.1929880149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2498666784 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 4190790504 ps |
| CPU time | 385.42 seconds |
| Started | Sep 12 03:20:55 AM UTC 24 |
| Finished | Sep 12 03:27:27 AM UTC 24 |
| Peak memory | 672428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498666784 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2498666784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.1315700940 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 5483035928 ps |
| CPU time | 575.4 seconds |
| Started | Sep 12 03:20:30 AM UTC 24 |
| Finished | Sep 12 03:30:13 AM UTC 24 |
| Peak memory | 674284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315700940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.1315700940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2650714623 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 4127642320 ps |
| CPU time | 286.64 seconds |
| Started | Sep 12 03:24:45 AM UTC 24 |
| Finished | Sep 12 03:29:37 AM UTC 24 |
| Peak memory | 672244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650714623 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2650714623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.867851366 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 5767200504 ps |
| CPU time | 612.39 seconds |
| Started | Sep 12 03:22:11 AM UTC 24 |
| Finished | Sep 12 03:32:32 AM UTC 24 |
| Peak memory | 674536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867851366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.867851366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1724585525 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 3450437288 ps |
| CPU time | 335.34 seconds |
| Started | Sep 12 03:26:38 AM UTC 24 |
| Finished | Sep 12 03:32:19 AM UTC 24 |
| Peak memory | 672448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724585525 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1724585525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.613533457 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 6018780210 ps |
| CPU time | 656.64 seconds |
| Started | Sep 12 03:22:15 AM UTC 24 |
| Finished | Sep 12 03:33:20 AM UTC 24 |
| Peak memory | 674536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613533457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.613533457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.2506892781 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 5559049286 ps |
| CPU time | 525.56 seconds |
| Started | Sep 12 03:23:37 AM UTC 24 |
| Finished | Sep 12 03:32:30 AM UTC 24 |
| Peak memory | 674604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506892781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.2506892781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3950031838 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 3186912600 ps |
| CPU time | 391.03 seconds |
| Started | Sep 12 02:38:21 AM UTC 24 |
| Finished | Sep 12 02:44:58 AM UTC 24 |
| Peak memory | 672400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950031838 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_alert_handler_lpg_s leep_mode_alerts.3950031838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.50041197 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 21528380622 ps |
| CPU time | 4751.44 seconds |
| Started | Sep 12 02:39:01 AM UTC 24 |
| Finished | Sep 12 03:59:10 AM UTC 24 |
| Peak memory | 628764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=50041197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 5.chip_sw_csrng_edn_concurrency.50041197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.837993225 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 5005498770 ps |
| CPU time | 785.89 seconds |
| Started | Sep 12 02:36:27 AM UTC 24 |
| Finished | Sep 12 02:49:43 AM UTC 24 |
| Peak memory | 625780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837993225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.837993225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_lc_ctrl_transition.251030654 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 7068568703 ps |
| CPU time | 516.75 seconds |
| Started | Sep 12 02:38:06 AM UTC 24 |
| Finished | Sep 12 02:46:50 AM UTC 24 |
| Peak memory | 636100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=251030654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.chip_sw_lc_ctrl_transition.251030654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.647843148 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 3871717540 ps |
| CPU time | 474.86 seconds |
| Started | Sep 12 02:37:02 AM UTC 24 |
| Finished | Sep 12 02:45:04 AM UTC 24 |
| Peak memory | 635892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647843148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.647843148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2631788571 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 3581471320 ps |
| CPU time | 293.06 seconds |
| Started | Sep 12 03:25:45 AM UTC 24 |
| Finished | Sep 12 03:30:42 AM UTC 24 |
| Peak memory | 636216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631788571 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2631788571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_all_escalation_resets.2181948879 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 5034200900 ps |
| CPU time | 614.55 seconds |
| Started | Sep 12 03:24:03 AM UTC 24 |
| Finished | Sep 12 03:34:26 AM UTC 24 |
| Peak memory | 674500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181948879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.2181948879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.58813036 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 3951629570 ps |
| CPU time | 296.21 seconds |
| Started | Sep 12 03:26:16 AM UTC 24 |
| Finished | Sep 12 03:31:18 AM UTC 24 |
| Peak memory | 672184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58813036 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_alert_handler_lpg_sl eep_mode_alerts.58813036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.822187573 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 4838469370 ps |
| CPU time | 572.31 seconds |
| Started | Sep 12 03:25:14 AM UTC 24 |
| Finished | Sep 12 03:34:54 AM UTC 24 |
| Peak memory | 674280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822187573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.822187573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1459992247 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 4517254248 ps |
| CPU time | 379.08 seconds |
| Started | Sep 12 03:25:29 AM UTC 24 |
| Finished | Sep 12 03:31:54 AM UTC 24 |
| Peak memory | 672228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459992247 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1459992247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.1226945824 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 6077971652 ps |
| CPU time | 582.31 seconds |
| Started | Sep 12 03:25:54 AM UTC 24 |
| Finished | Sep 12 03:35:44 AM UTC 24 |
| Peak memory | 674532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226945824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.1226945824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1804749865 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 3880663130 ps |
| CPU time | 394.9 seconds |
| Started | Sep 12 03:26:49 AM UTC 24 |
| Finished | Sep 12 03:33:30 AM UTC 24 |
| Peak memory | 672168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804749865 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1804749865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.1134068589 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 5002753636 ps |
| CPU time | 561.97 seconds |
| Started | Sep 12 03:26:38 AM UTC 24 |
| Finished | Sep 12 03:36:07 AM UTC 24 |
| Peak memory | 674492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134068589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.1134068589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1064859144 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 4316634848 ps |
| CPU time | 385.65 seconds |
| Started | Sep 12 03:26:39 AM UTC 24 |
| Finished | Sep 12 03:33:10 AM UTC 24 |
| Peak memory | 672396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064859144 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1064859144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1428367301 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 4098397440 ps |
| CPU time | 421.65 seconds |
| Started | Sep 12 03:28:48 AM UTC 24 |
| Finished | Sep 12 03:35:56 AM UTC 24 |
| Peak memory | 636404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428367301 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1428367301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_all_escalation_resets.1450885623 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 5414136160 ps |
| CPU time | 460.44 seconds |
| Started | Sep 12 03:26:03 AM UTC 24 |
| Finished | Sep 12 03:33:50 AM UTC 24 |
| Peak memory | 636216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450885623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.1450885623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.174730326 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 4011980428 ps |
| CPU time | 359.4 seconds |
| Started | Sep 12 03:27:23 AM UTC 24 |
| Finished | Sep 12 03:33:28 AM UTC 24 |
| Peak memory | 672360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174730326 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_alert_handler_lpg_s leep_mode_alerts.174730326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1387227327 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 3112701060 ps |
| CPU time | 372.56 seconds |
| Started | Sep 12 03:27:24 AM UTC 24 |
| Finished | Sep 12 03:33:42 AM UTC 24 |
| Peak memory | 672240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387227327 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1387227327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3711370206 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 4022922576 ps |
| CPU time | 492.86 seconds |
| Started | Sep 12 02:41:26 AM UTC 24 |
| Finished | Sep 12 02:49:46 AM UTC 24 |
| Peak memory | 672420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711370206 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_alert_handler_lpg_s leep_mode_alerts.3711370206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.2913840403 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 5795665860 ps |
| CPU time | 578 seconds |
| Started | Sep 12 02:39:44 AM UTC 24 |
| Finished | Sep 12 02:49:29 AM UTC 24 |
| Peak memory | 674516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913840403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.2913840403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.852732259 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 22739290716 ps |
| CPU time | 5129.7 seconds |
| Started | Sep 12 02:41:57 AM UTC 24 |
| Finished | Sep 12 04:08:28 AM UTC 24 |
| Peak memory | 628912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=852732259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 6.chip_sw_csrng_edn_concurrency.852732259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.1862929291 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 9968277938 ps |
| CPU time | 1072.17 seconds |
| Started | Sep 12 02:41:25 AM UTC 24 |
| Finished | Sep 12 02:59:32 AM UTC 24 |
| Peak memory | 638004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1862929291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 6.chip_sw_lc_ctrl_transition.1862929291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.2791191222 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 4643885030 ps |
| CPU time | 696.68 seconds |
| Started | Sep 12 02:40:27 AM UTC 24 |
| Finished | Sep 12 02:52:13 AM UTC 24 |
| Peak memory | 636128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791191222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.2791191222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3362754804 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 4278280544 ps |
| CPU time | 329.2 seconds |
| Started | Sep 12 03:28:02 AM UTC 24 |
| Finished | Sep 12 03:33:36 AM UTC 24 |
| Peak memory | 636372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362754804 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3362754804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.3360396024 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 6140113320 ps |
| CPU time | 522.98 seconds |
| Started | Sep 12 03:28:31 AM UTC 24 |
| Finished | Sep 12 03:37:22 AM UTC 24 |
| Peak memory | 674444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360396024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.3360396024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3021666114 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 4600357984 ps |
| CPU time | 421.93 seconds |
| Started | Sep 12 03:27:31 AM UTC 24 |
| Finished | Sep 12 03:34:39 AM UTC 24 |
| Peak memory | 672536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021666114 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3021666114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2832204319 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 3911760134 ps |
| CPU time | 364.54 seconds |
| Started | Sep 12 03:28:29 AM UTC 24 |
| Finished | Sep 12 03:34:39 AM UTC 24 |
| Peak memory | 672256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832204319 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2832204319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_all_escalation_resets.1323118985 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 5805291400 ps |
| CPU time | 537.88 seconds |
| Started | Sep 12 03:28:25 AM UTC 24 |
| Finished | Sep 12 03:37:31 AM UTC 24 |
| Peak memory | 674348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323118985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.1323118985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_all_escalation_resets.3199843398 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 5567200592 ps |
| CPU time | 504.64 seconds |
| Started | Sep 12 03:28:32 AM UTC 24 |
| Finished | Sep 12 03:37:04 AM UTC 24 |
| Peak memory | 674284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199843398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.3199843398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2229733888 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 4485408400 ps |
| CPU time | 359.93 seconds |
| Started | Sep 12 03:28:50 AM UTC 24 |
| Finished | Sep 12 03:34:55 AM UTC 24 |
| Peak memory | 672384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229733888 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2229733888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.2231535211 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 5762613362 ps |
| CPU time | 658.91 seconds |
| Started | Sep 12 03:28:30 AM UTC 24 |
| Finished | Sep 12 03:39:38 AM UTC 24 |
| Peak memory | 674428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231535211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.2231535211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3463234152 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 3811153336 ps |
| CPU time | 341.89 seconds |
| Started | Sep 12 03:28:31 AM UTC 24 |
| Finished | Sep 12 03:34:18 AM UTC 24 |
| Peak memory | 672428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463234152 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3463234152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.461550592 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 5943426200 ps |
| CPU time | 561.95 seconds |
| Started | Sep 12 03:27:53 AM UTC 24 |
| Finished | Sep 12 03:37:23 AM UTC 24 |
| Peak memory | 674516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461550592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.461550592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1158649453 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 3822479728 ps |
| CPU time | 378.43 seconds |
| Started | Sep 12 03:28:55 AM UTC 24 |
| Finished | Sep 12 03:35:19 AM UTC 24 |
| Peak memory | 672384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158649453 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1158649453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3239296769 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 3636443916 ps |
| CPU time | 382.33 seconds |
| Started | Sep 12 03:29:32 AM UTC 24 |
| Finished | Sep 12 03:36:00 AM UTC 24 |
| Peak memory | 672320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239296769 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3239296769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1411548910 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 3948780632 ps |
| CPU time | 331.46 seconds |
| Started | Sep 12 03:30:17 AM UTC 24 |
| Finished | Sep 12 03:35:54 AM UTC 24 |
| Peak memory | 672436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411548910 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1411548910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.564239181 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 5532436260 ps |
| CPU time | 543.45 seconds |
| Started | Sep 12 03:29:32 AM UTC 24 |
| Finished | Sep 12 03:38:43 AM UTC 24 |
| Peak memory | 674296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564239181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.564239181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2120627861 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 3858271428 ps |
| CPU time | 329.49 seconds |
| Started | Sep 12 03:30:54 AM UTC 24 |
| Finished | Sep 12 03:36:28 AM UTC 24 |
| Peak memory | 672240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120627861 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2120627861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.599689726 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 3774472200 ps |
| CPU time | 406.54 seconds |
| Started | Sep 12 02:42:34 AM UTC 24 |
| Finished | Sep 12 02:49:26 AM UTC 24 |
| Peak memory | 672180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599689726 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_alert_handler_lpg_sl eep_mode_alerts.599689726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.2024323530 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 20913865406 ps |
| CPU time | 4824.16 seconds |
| Started | Sep 12 02:42:56 AM UTC 24 |
| Finished | Sep 12 04:04:17 AM UTC 24 |
| Peak memory | 626720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2024323530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 7.chip_sw_csrng_edn_concurrency.2024323530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_lc_ctrl_transition.1580196976 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 6009876117 ps |
| CPU time | 435.24 seconds |
| Started | Sep 12 02:42:18 AM UTC 24 |
| Finished | Sep 12 02:49:39 AM UTC 24 |
| Peak memory | 638084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1580196976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 7.chip_sw_lc_ctrl_transition.1580196976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.836981302 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 3007428638 ps |
| CPU time | 434.25 seconds |
| Started | Sep 12 02:41:58 AM UTC 24 |
| Finished | Sep 12 02:49:18 AM UTC 24 |
| Peak memory | 636052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836981302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.836981302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.63234335 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 3635530268 ps |
| CPU time | 355.24 seconds |
| Started | Sep 12 03:31:42 AM UTC 24 |
| Finished | Sep 12 03:37:43 AM UTC 24 |
| Peak memory | 672172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63234335 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_alert_handler_lpg_sl eep_mode_alerts.63234335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.1865572162 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 5827610336 ps |
| CPU time | 537.95 seconds |
| Started | Sep 12 03:31:21 AM UTC 24 |
| Finished | Sep 12 03:40:27 AM UTC 24 |
| Peak memory | 674528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865572162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.1865572162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.757944644 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 3845861800 ps |
| CPU time | 253.92 seconds |
| Started | Sep 12 03:36:05 AM UTC 24 |
| Finished | Sep 12 03:40:22 AM UTC 24 |
| Peak memory | 672176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757944644 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_alert_handler_lpg_s leep_mode_alerts.757944644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.2864240685 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 6065176200 ps |
| CPU time | 478.24 seconds |
| Started | Sep 12 03:31:57 AM UTC 24 |
| Finished | Sep 12 03:40:02 AM UTC 24 |
| Peak memory | 674284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864240685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.2864240685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.949081559 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 3951455000 ps |
| CPU time | 264.1 seconds |
| Started | Sep 12 03:33:25 AM UTC 24 |
| Finished | Sep 12 03:37:54 AM UTC 24 |
| Peak memory | 672492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949081559 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_alert_handler_lpg_s leep_mode_alerts.949081559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.205062192 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 5096470984 ps |
| CPU time | 510.36 seconds |
| Started | Sep 12 03:33:51 AM UTC 24 |
| Finished | Sep 12 03:42:28 AM UTC 24 |
| Peak memory | 674496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205062192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.205062192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3709908907 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 4304910762 ps |
| CPU time | 389.25 seconds |
| Started | Sep 12 03:33:40 AM UTC 24 |
| Finished | Sep 12 03:40:15 AM UTC 24 |
| Peak memory | 672380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709908907 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3709908907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.2180453922 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 4361396288 ps |
| CPU time | 493.1 seconds |
| Started | Sep 12 03:35:15 AM UTC 24 |
| Finished | Sep 12 03:43:35 AM UTC 24 |
| Peak memory | 674456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180453922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.2180453922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1150481 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 3590275040 ps |
| CPU time | 287.52 seconds |
| Started | Sep 12 03:39:24 AM UTC 24 |
| Finished | Sep 12 03:44:15 AM UTC 24 |
| Peak memory | 672196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150481 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_alert_handler_lpg_sle ep_mode_alerts.1150481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1442685929 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 3278820294 ps |
| CPU time | 352.67 seconds |
| Started | Sep 12 03:36:00 AM UTC 24 |
| Finished | Sep 12 03:41:58 AM UTC 24 |
| Peak memory | 672480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442685929 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1442685929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.4186098537 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 6283003552 ps |
| CPU time | 524.38 seconds |
| Started | Sep 12 03:37:14 AM UTC 24 |
| Finished | Sep 12 03:46:05 AM UTC 24 |
| Peak memory | 674368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186098537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.4186098537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2978146861 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 3398305080 ps |
| CPU time | 384.21 seconds |
| Started | Sep 12 03:37:40 AM UTC 24 |
| Finished | Sep 12 03:44:10 AM UTC 24 |
| Peak memory | 672332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978146861 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2978146861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3134731642 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 3429113278 ps |
| CPU time | 304.28 seconds |
| Started | Sep 12 03:36:57 AM UTC 24 |
| Finished | Sep 12 03:42:06 AM UTC 24 |
| Peak memory | 672460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134731642 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3134731642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.3740384881 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 5828046920 ps |
| CPU time | 554.44 seconds |
| Started | Sep 12 03:35:49 AM UTC 24 |
| Finished | Sep 12 03:45:11 AM UTC 24 |
| Peak memory | 674360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740384881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.3740384881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1917038933 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 3953883346 ps |
| CPU time | 297.75 seconds |
| Started | Sep 12 03:35:42 AM UTC 24 |
| Finished | Sep 12 03:40:44 AM UTC 24 |
| Peak memory | 672228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917038933 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1917038933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.186622483 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 3830371456 ps |
| CPU time | 514.23 seconds |
| Started | Sep 12 03:37:13 AM UTC 24 |
| Finished | Sep 12 03:45:55 AM UTC 24 |
| Peak memory | 674472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186622483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.186622483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.4287733099 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 3431783304 ps |
| CPU time | 272.63 seconds |
| Started | Sep 12 03:38:23 AM UTC 24 |
| Finished | Sep 12 03:42:59 AM UTC 24 |
| Peak memory | 672476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287733099 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_alert_handler_lpg_ sleep_mode_alerts.4287733099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.1985365153 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 4756345892 ps |
| CPU time | 540.72 seconds |
| Started | Sep 12 03:40:15 AM UTC 24 |
| Finished | Sep 12 03:49:23 AM UTC 24 |
| Peak memory | 674284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985365153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.1985365153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.3474795053 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 5903239002 ps |
| CPU time | 667.09 seconds |
| Started | Sep 12 02:43:40 AM UTC 24 |
| Finished | Sep 12 02:54:57 AM UTC 24 |
| Peak memory | 674284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474795053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.3474795053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.1563509126 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 8821584154 ps |
| CPU time | 2199.88 seconds |
| Started | Sep 12 02:45:59 AM UTC 24 |
| Finished | Sep 12 03:23:09 AM UTC 24 |
| Peak memory | 625776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1563509126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 8.chip_sw_csrng_edn_concurrency.1563509126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.3488570917 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 6153041075 ps |
| CPU time | 492.48 seconds |
| Started | Sep 12 02:45:27 AM UTC 24 |
| Finished | Sep 12 02:53:47 AM UTC 24 |
| Peak memory | 638172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3488570917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 8.chip_sw_lc_ctrl_transition.3488570917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.2976047165 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 8180301160 ps |
| CPU time | 1681.4 seconds |
| Started | Sep 12 02:44:00 AM UTC 24 |
| Finished | Sep 12 03:12:24 AM UTC 24 |
| Peak memory | 635960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976047165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.2976047165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.442574447 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 3818605252 ps |
| CPU time | 371.72 seconds |
| Started | Sep 12 03:38:19 AM UTC 24 |
| Finished | Sep 12 03:44:36 AM UTC 24 |
| Peak memory | 672432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442574447 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_alert_handler_lpg_s leep_mode_alerts.442574447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_all_escalation_resets.1706515565 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 5650105802 ps |
| CPU time | 636.03 seconds |
| Started | Sep 12 03:37:49 AM UTC 24 |
| Finished | Sep 12 03:48:33 AM UTC 24 |
| Peak memory | 674492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706515565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.1706515565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2436606647 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 4153200848 ps |
| CPU time | 348.39 seconds |
| Started | Sep 12 03:38:11 AM UTC 24 |
| Finished | Sep 12 03:44:05 AM UTC 24 |
| Peak memory | 672428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436606647 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2436606647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.2609237184 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 4931226160 ps |
| CPU time | 482.07 seconds |
| Started | Sep 12 03:39:05 AM UTC 24 |
| Finished | Sep 12 03:47:13 AM UTC 24 |
| Peak memory | 674524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609237184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.2609237184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1001176231 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 3415863062 ps |
| CPU time | 333.4 seconds |
| Started | Sep 12 03:38:24 AM UTC 24 |
| Finished | Sep 12 03:44:02 AM UTC 24 |
| Peak memory | 672328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001176231 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1001176231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.2546116765 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 5895921128 ps |
| CPU time | 425.52 seconds |
| Started | Sep 12 03:39:05 AM UTC 24 |
| Finished | Sep 12 03:46:16 AM UTC 24 |
| Peak memory | 674516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546116765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.2546116765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.749163437 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 4170303292 ps |
| CPU time | 350.4 seconds |
| Started | Sep 12 03:39:56 AM UTC 24 |
| Finished | Sep 12 03:45:52 AM UTC 24 |
| Peak memory | 672520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749163437 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_alert_handler_lpg_s leep_mode_alerts.749163437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.4056571210 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 4319310528 ps |
| CPU time | 484.91 seconds |
| Started | Sep 12 03:36:56 AM UTC 24 |
| Finished | Sep 12 03:45:08 AM UTC 24 |
| Peak memory | 674276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056571210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.4056571210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1324610842 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 4200585960 ps |
| CPU time | 318.4 seconds |
| Started | Sep 12 03:39:04 AM UTC 24 |
| Finished | Sep 12 03:44:28 AM UTC 24 |
| Peak memory | 672176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324610842 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1324610842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.2714064408 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 5425270370 ps |
| CPU time | 434.2 seconds |
| Started | Sep 12 03:39:15 AM UTC 24 |
| Finished | Sep 12 03:46:35 AM UTC 24 |
| Peak memory | 674512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714064408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.2714064408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3882395173 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 4441957728 ps |
| CPU time | 385.54 seconds |
| Started | Sep 12 03:40:12 AM UTC 24 |
| Finished | Sep 12 03:46:43 AM UTC 24 |
| Peak memory | 672320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882395173 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3882395173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.1988299052 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 4517452648 ps |
| CPU time | 497.01 seconds |
| Started | Sep 12 03:40:20 AM UTC 24 |
| Finished | Sep 12 03:48:44 AM UTC 24 |
| Peak memory | 674452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988299052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.1988299052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2086450887 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 3576988720 ps |
| CPU time | 343.61 seconds |
| Started | Sep 12 03:40:14 AM UTC 24 |
| Finished | Sep 12 03:46:02 AM UTC 24 |
| Peak memory | 672280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086450887 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2086450887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.1632906486 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 5125473164 ps |
| CPU time | 453.2 seconds |
| Started | Sep 12 03:39:53 AM UTC 24 |
| Finished | Sep 12 03:47:32 AM UTC 24 |
| Peak memory | 674516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632906486 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.1632906486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2056138095 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 3571474746 ps |
| CPU time | 303.97 seconds |
| Started | Sep 12 03:39:52 AM UTC 24 |
| Finished | Sep 12 03:45:01 AM UTC 24 |
| Peak memory | 672428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056138095 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2056138095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.75766496 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 5231746074 ps |
| CPU time | 558.28 seconds |
| Started | Sep 12 03:38:04 AM UTC 24 |
| Finished | Sep 12 03:47:29 AM UTC 24 |
| Peak memory | 636348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75766496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esca lation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.75766496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2960909329 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 3909953186 ps |
| CPU time | 338.15 seconds |
| Started | Sep 12 03:39:37 AM UTC 24 |
| Finished | Sep 12 03:45:20 AM UTC 24 |
| Peak memory | 672168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960909329 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2960909329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.1517269493 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 5082275420 ps |
| CPU time | 534.28 seconds |
| Started | Sep 12 03:40:38 AM UTC 24 |
| Finished | Sep 12 03:49:39 AM UTC 24 |
| Peak memory | 674352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517269493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.1517269493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2956946983 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 3415686384 ps |
| CPU time | 298.76 seconds |
| Started | Sep 12 03:40:12 AM UTC 24 |
| Finished | Sep 12 03:45:15 AM UTC 24 |
| Peak memory | 672492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956946983 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2956946983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_all_escalation_resets.1605286447 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 5909606154 ps |
| CPU time | 514.65 seconds |
| Started | Sep 12 03:40:13 AM UTC 24 |
| Finished | Sep 12 03:48:54 AM UTC 24 |
| Peak memory | 674424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605286447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.1605286447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1302117984 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 3469606812 ps |
| CPU time | 421.88 seconds |
| Started | Sep 12 02:47:43 AM UTC 24 |
| Finished | Sep 12 02:54:51 AM UTC 24 |
| Peak memory | 672400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302117984 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_alert_handler_lpg_s leep_mode_alerts.1302117984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.1196777567 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 4796996392 ps |
| CPU time | 736.42 seconds |
| Started | Sep 12 02:46:00 AM UTC 24 |
| Finished | Sep 12 02:58:27 AM UTC 24 |
| Peak memory | 674284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196777567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.1196777567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.346217980 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 26504700874 ps |
| CPU time | 5573.85 seconds |
| Started | Sep 12 02:47:43 AM UTC 24 |
| Finished | Sep 12 04:21:39 AM UTC 24 |
| Peak memory | 628832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=346217980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 9.chip_sw_csrng_edn_concurrency.346217980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_lc_ctrl_transition.1367929813 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 5611760684 ps |
| CPU time | 472.51 seconds |
| Started | Sep 12 02:46:31 AM UTC 24 |
| Finished | Sep 12 02:54:30 AM UTC 24 |
| Peak memory | 635892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1367929813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 9.chip_sw_lc_ctrl_transition.1367929813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.2544295650 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 7798862300 ps |
| CPU time | 1449.13 seconds |
| Started | Sep 12 02:45:59 AM UTC 24 |
| Finished | Sep 12 03:10:28 AM UTC 24 |
| Peak memory | 636168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544295650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.2544295650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.3528761272 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 5697169592 ps |
| CPU time | 600.24 seconds |
| Started | Sep 12 03:39:55 AM UTC 24 |
| Finished | Sep 12 03:50:03 AM UTC 24 |
| Peak memory | 675212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528761272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.3528761272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/91.chip_sw_all_escalation_resets.2295212782 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 5308085686 ps |
| CPU time | 485.37 seconds |
| Started | Sep 12 03:39:50 AM UTC 24 |
| Finished | Sep 12 03:48:02 AM UTC 24 |
| Peak memory | 674356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295212782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.2295212782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.3958460935 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 5095751464 ps |
| CPU time | 488.48 seconds |
| Started | Sep 12 03:39:24 AM UTC 24 |
| Finished | Sep 12 03:47:39 AM UTC 24 |
| Peak memory | 674284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958460935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.3958460935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.3364973580 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 5561860600 ps |
| CPU time | 382.98 seconds |
| Started | Sep 12 03:40:11 AM UTC 24 |
| Finished | Sep 12 03:46:39 AM UTC 24 |
| Peak memory | 674524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364973580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.3364973580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.1275635951 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 5249819554 ps |
| CPU time | 537.56 seconds |
| Started | Sep 12 03:39:36 AM UTC 24 |
| Finished | Sep 12 03:48:41 AM UTC 24 |
| Peak memory | 674296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275635951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.1275635951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.1481166617 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 5168583042 ps |
| CPU time | 561.01 seconds |
| Started | Sep 12 03:40:42 AM UTC 24 |
| Finished | Sep 12 03:50:10 AM UTC 24 |
| Peak memory | 626352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481166617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.1481166617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.364392411 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 5093807376 ps |
| CPU time | 437.44 seconds |
| Started | Sep 12 03:40:37 AM UTC 24 |
| Finished | Sep 12 03:48:00 AM UTC 24 |
| Peak memory | 674376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364392411 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.364392411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.1148484424 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 4361843432 ps |
| CPU time | 434.1 seconds |
| Started | Sep 12 03:40:42 AM UTC 24 |
| Finished | Sep 12 03:48:02 AM UTC 24 |
| Peak memory | 674468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148484424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.1148484424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.211206799 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 4725675250 ps |
| CPU time | 424.58 seconds |
| Started | Sep 12 03:40:24 AM UTC 24 |
| Finished | Sep 12 03:47:34 AM UTC 24 |
| Peak memory | 674420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211206799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.211206799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1636856402 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 4742693332 ps |
| CPU time | 256.17 seconds |
| Started | Sep 11 09:24:40 PM UTC 24 |
| Finished | Sep 11 09:28:59 PM UTC 24 |
| Peak memory | 666212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636856 402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 0.chip_ padctrl_attributes.1636856402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2345014238 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4881879860 ps |
| CPU time | 200.74 seconds |
| Started | Sep 11 09:24:42 PM UTC 24 |
| Finished | Sep 11 09:28:06 PM UTC 24 |
| Peak memory | 666464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345014 238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 1.chip_ padctrl_attributes.2345014238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.100060340 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 4997991016 ps |
| CPU time | 198.92 seconds |
| Started | Sep 11 09:24:47 PM UTC 24 |
| Finished | Sep 11 09:28:09 PM UTC 24 |
| Peak memory | 668504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000603 40 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 2.chip_p adctrl_attributes.100060340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3471829689 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 5407608600 ps |
| CPU time | 208.89 seconds |
| Started | Sep 11 09:24:46 PM UTC 24 |
| Finished | Sep 11 09:28:19 PM UTC 24 |
| Peak memory | 658020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471829 689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 3.chip_ padctrl_attributes.3471829689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/3.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2106207182 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 5726491072 ps |
| CPU time | 209.89 seconds |
| Started | Sep 11 09:24:50 PM UTC 24 |
| Finished | Sep 11 09:28:23 PM UTC 24 |
| Peak memory | 666340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106207 182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 4.chip_ padctrl_attributes.2106207182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/4.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.42490000 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 5295506305 ps |
| CPU time | 182.01 seconds |
| Started | Sep 11 09:24:50 PM UTC 24 |
| Finished | Sep 11 09:27:55 PM UTC 24 |
| Peak memory | 656104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249000 0 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 6.chip_pa dctrl_attributes.42490000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/6.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2946204658 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 4231784376 ps |
| CPU time | 191.66 seconds |
| Started | Sep 11 09:25:02 PM UTC 24 |
| Finished | Sep 11 09:28:17 PM UTC 24 |
| Peak memory | 666340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946204 658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 8.chip_ padctrl_attributes.2946204658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/8.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1878718164 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 4245700670 ps |
| CPU time | 190.63 seconds |
| Started | Sep 11 09:25:04 PM UTC 24 |
| Finished | Sep 11 09:28:18 PM UTC 24 |
| Peak memory | 672364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878718 164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 9.chip_ padctrl_attributes.1878718164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/9.chip_padctrl_attributes/latest |
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