Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.97 95.43 93.69 95.30 94.46 97.35 99.55


Total test records in report: 2925
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html | tests61.html
T1354 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.234390387 Sep 12 12:54:06 AM UTC 24 Sep 12 04:23:12 AM UTC 24 62246297406 ps
T1355 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.2454633831 Sep 12 12:54:06 AM UTC 24 Sep 12 04:43:40 AM UTC 24 68485663443 ps
T1356 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1717362405 Sep 12 12:53:38 AM UTC 24 Sep 12 05:11:47 AM UTC 24 81105940182 ps
T1357 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2338989490 Sep 12 01:33:50 AM UTC 24 Sep 12 05:21:42 AM UTC 24 256232431624 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1989833712 Sep 11 06:54:13 PM UTC 24 Sep 11 06:54:23 PM UTC 24 48757872 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.2930070906 Sep 11 06:54:15 PM UTC 24 Sep 11 06:54:26 PM UTC 24 158951347 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.84376732 Sep 11 06:54:17 PM UTC 24 Sep 11 06:54:31 PM UTC 24 89225765 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.3247871316 Sep 11 06:54:20 PM UTC 24 Sep 11 06:54:39 PM UTC 24 207944669 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2420399445 Sep 11 06:54:20 PM UTC 24 Sep 11 06:54:41 PM UTC 24 151966390 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.2999316973 Sep 11 06:54:22 PM UTC 24 Sep 11 06:54:47 PM UTC 24 361174543 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1278738303 Sep 11 06:54:53 PM UTC 24 Sep 11 06:55:03 PM UTC 24 48186970 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1530334569 Sep 11 06:54:16 PM UTC 24 Sep 11 06:55:06 PM UTC 24 3143233823 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.3725597504 Sep 11 06:54:19 PM UTC 24 Sep 11 06:55:06 PM UTC 24 466037819 ps
T573 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.1478793014 Sep 11 06:54:52 PM UTC 24 Sep 11 06:55:07 PM UTC 24 217743541 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1686967284 Sep 11 06:54:29 PM UTC 24 Sep 11 06:55:11 PM UTC 24 142451631 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.3689397848 Sep 11 06:54:19 PM UTC 24 Sep 11 06:55:15 PM UTC 24 1947969629 ps
T556 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.484454880 Sep 11 06:54:59 PM UTC 24 Sep 11 06:55:18 PM UTC 24 145709074 ps
T572 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.1263850415 Sep 11 06:54:14 PM UTC 24 Sep 11 06:55:22 PM UTC 24 6464658435 ps
T574 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.2667672222 Sep 11 06:55:08 PM UTC 24 Sep 11 06:55:23 PM UTC 24 190883979 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.2884597962 Sep 11 06:54:59 PM UTC 24 Sep 11 06:55:25 PM UTC 24 212708000 ps
T562 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.3676249871 Sep 11 06:55:09 PM UTC 24 Sep 11 06:55:42 PM UTC 24 611413900 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.2188544417 Sep 11 06:54:16 PM UTC 24 Sep 11 06:55:48 PM UTC 24 2444118708 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.2339072587 Sep 11 06:55:13 PM UTC 24 Sep 11 06:55:48 PM UTC 24 236174526 ps
T564 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1455526238 Sep 11 06:55:28 PM UTC 24 Sep 11 06:56:05 PM UTC 24 796593012 ps
T561 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3756185822 Sep 11 06:54:57 PM UTC 24 Sep 11 06:56:11 PM UTC 24 4760768169 ps
T568 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.226615675 Sep 11 06:56:06 PM UTC 24 Sep 11 06:56:16 PM UTC 24 47896459 ps
T567 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.1998037310 Sep 11 06:56:05 PM UTC 24 Sep 11 06:56:16 PM UTC 24 199874257 ps
T565 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.1707802047 Sep 11 06:56:15 PM UTC 24 Sep 11 06:56:46 PM UTC 24 356417896 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.3926988701 Sep 11 06:55:03 PM UTC 24 Sep 11 06:56:52 PM UTC 24 2694579972 ps
T563 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.2429054614 Sep 11 06:56:42 PM UTC 24 Sep 11 06:56:57 PM UTC 24 83384466 ps
T557 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.2308792437 Sep 11 06:56:11 PM UTC 24 Sep 11 06:57:08 PM UTC 24 521183438 ps
T558 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.1710146532 Sep 11 06:57:00 PM UTC 24 Sep 11 06:57:25 PM UTC 24 631939023 ps
T575 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.1957958112 Sep 11 06:56:10 PM UTC 24 Sep 11 06:57:25 PM UTC 24 4646468831 ps
T576 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.360452449 Sep 11 06:57:17 PM UTC 24 Sep 11 06:57:35 PM UTC 24 193988610 ps
T566 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.1019435153 Sep 11 06:54:30 PM UTC 24 Sep 11 06:57:36 PM UTC 24 2367719138 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.2097245910 Sep 11 06:54:12 PM UTC 24 Sep 11 06:57:37 PM UTC 24 3444689029 ps
T577 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.3477633976 Sep 11 06:54:58 PM UTC 24 Sep 11 06:57:47 PM UTC 24 10414808005 ps
T559 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.1925101871 Sep 11 06:57:10 PM UTC 24 Sep 11 06:57:57 PM UTC 24 290876630 ps
T698 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.282770451 Sep 11 06:56:36 PM UTC 24 Sep 11 06:58:01 PM UTC 24 1446178138 ps
T896 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.1221066444 Sep 11 06:54:49 PM UTC 24 Sep 11 06:58:04 PM UTC 24 3764778322 ps
T828 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.298587621 Sep 11 06:56:11 PM UTC 24 Sep 11 06:58:05 PM UTC 24 7042209786 ps
T560 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.4092173773 Sep 11 06:57:34 PM UTC 24 Sep 11 06:58:05 PM UTC 24 71818896 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.995202937 Sep 11 06:57:16 PM UTC 24 Sep 11 06:58:20 PM UTC 24 1689387049 ps
T570 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.496342011 Sep 11 06:55:26 PM UTC 24 Sep 11 06:58:23 PM UTC 24 4427191661 ps
T569 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.2362526763 Sep 11 06:57:28 PM UTC 24 Sep 11 06:58:26 PM UTC 24 706848211 ps
T571 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.801944869 Sep 11 06:55:31 PM UTC 24 Sep 11 06:58:27 PM UTC 24 3966237204 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.302508255 Sep 11 06:54:48 PM UTC 24 Sep 11 06:58:28 PM UTC 24 3472988702 ps
T625 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.793995497 Sep 11 06:58:21 PM UTC 24 Sep 11 06:58:30 PM UTC 24 44842828 ps
T592 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.86312635 Sep 11 06:55:00 PM UTC 24 Sep 11 06:58:31 PM UTC 24 12809914707 ps
T488 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.4218343831 Sep 11 06:54:26 PM UTC 24 Sep 11 06:58:36 PM UTC 24 1117757728 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.1841834051 Sep 11 06:58:27 PM UTC 24 Sep 11 06:58:38 PM UTC 24 55626093 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.583367649 Sep 11 06:55:47 PM UTC 24 Sep 11 06:58:41 PM UTC 24 3004194184 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.2487825146 Sep 11 06:58:31 PM UTC 24 Sep 11 06:58:45 PM UTC 24 273531517 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.2145846974 Sep 11 06:58:41 PM UTC 24 Sep 11 06:59:00 PM UTC 24 205636582 ps
T1358 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.293656640 Sep 11 06:58:54 PM UTC 24 Sep 11 06:59:03 PM UTC 24 23907488 ps
T1359 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.4272326104 Sep 11 06:58:57 PM UTC 24 Sep 11 06:59:11 PM UTC 24 145240411 ps
T879 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.798630873 Sep 11 06:59:03 PM UTC 24 Sep 11 06:59:11 PM UTC 24 8167930 ps
T859 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.580273013 Sep 11 06:58:54 PM UTC 24 Sep 11 06:59:18 PM UTC 24 247677525 ps
T843 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.3402410305 Sep 11 06:59:09 PM UTC 24 Sep 11 06:59:35 PM UTC 24 185360864 ps
T811 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.4079612554 Sep 11 06:58:30 PM UTC 24 Sep 11 06:59:42 PM UTC 24 4761791847 ps
T1360 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.4170589431 Sep 11 06:55:48 PM UTC 24 Sep 11 06:59:50 PM UTC 24 6286486330 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.2323069731 Sep 11 06:55:36 PM UTC 24 Sep 11 06:59:52 PM UTC 24 5359367672 ps
T1361 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.782905279 Sep 11 06:58:30 PM UTC 24 Sep 11 07:00:05 PM UTC 24 8678754171 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.4173762030 Sep 11 06:54:18 PM UTC 24 Sep 11 07:00:07 PM UTC 24 11269970221 ps
T685 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.899700811 Sep 11 06:55:30 PM UTC 24 Sep 11 07:00:08 PM UTC 24 9031258697 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.1366195712 Sep 11 06:54:30 PM UTC 24 Sep 11 07:00:16 PM UTC 24 6006121102 ps
T1362 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.3204405540 Sep 11 06:54:12 PM UTC 24 Sep 11 07:00:17 PM UTC 24 7613157550 ps
T609 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.994141882 Sep 11 06:58:47 PM UTC 24 Sep 11 07:00:22 PM UTC 24 2536221988 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.512150406 Sep 11 06:55:35 PM UTC 24 Sep 11 07:00:23 PM UTC 24 5004618816 ps
T1363 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.2881374250 Sep 11 07:00:14 PM UTC 24 Sep 11 07:00:26 PM UTC 24 133235662 ps
T1364 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.132802300 Sep 11 07:00:16 PM UTC 24 Sep 11 07:00:27 PM UTC 24 53640214 ps
T665 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.2494806009 Sep 11 06:58:43 PM UTC 24 Sep 11 07:00:44 PM UTC 24 2453024254 ps
T500 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.872057925 Sep 11 07:00:31 PM UTC 24 Sep 11 07:01:21 PM UTC 24 476345556 ps
T680 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.1128345919 Sep 11 07:00:49 PM UTC 24 Sep 11 07:01:26 PM UTC 24 774225308 ps
T1365 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.3003534611 Sep 11 07:00:52 PM UTC 24 Sep 11 07:01:29 PM UTC 24 274556040 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.2546885324 Sep 11 06:57:50 PM UTC 24 Sep 11 07:01:40 PM UTC 24 4484476150 ps
T492 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.46094752 Sep 11 06:57:21 PM UTC 24 Sep 11 07:01:41 PM UTC 24 1226722950 ps
T681 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.3974248308 Sep 11 07:00:46 PM UTC 24 Sep 11 07:01:43 PM UTC 24 958364167 ps
T612 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.3522397906 Sep 11 07:00:29 PM UTC 24 Sep 11 07:01:47 PM UTC 24 1648106704 ps
T580 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.4068853731 Sep 11 06:58:17 PM UTC 24 Sep 11 07:01:50 PM UTC 24 2814823074 ps
T597 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.1738469618 Sep 11 07:01:09 PM UTC 24 Sep 11 07:01:56 PM UTC 24 280981528 ps
T1366 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.3048179338 Sep 11 07:00:29 PM UTC 24 Sep 11 07:01:57 PM UTC 24 4019952024 ps
T639 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.3273813437 Sep 11 07:00:24 PM UTC 24 Sep 11 07:02:02 PM UTC 24 8213979381 ps
T588 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.3248200472 Sep 11 06:54:16 PM UTC 24 Sep 11 07:02:08 PM UTC 24 41708803547 ps
T817 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.128718841 Sep 11 06:55:31 PM UTC 24 Sep 11 07:02:24 PM UTC 24 6418661459 ps
T536 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.1263484062 Sep 11 07:02:18 PM UTC 24 Sep 11 07:02:28 PM UTC 24 42930366 ps
T1367 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.3417334751 Sep 11 07:01:46 PM UTC 24 Sep 11 07:02:29 PM UTC 24 284690713 ps
T819 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.1970228362 Sep 11 06:59:20 PM UTC 24 Sep 11 07:02:30 PM UTC 24 776418530 ps
T590 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.2849014019 Sep 11 07:02:18 PM UTC 24 Sep 11 07:02:31 PM UTC 24 186533576 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.1735785335 Sep 11 06:54:33 PM UTC 24 Sep 11 07:02:37 PM UTC 24 5601852759 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3277233634 Sep 11 06:55:40 PM UTC 24 Sep 11 07:02:45 PM UTC 24 5709937640 ps
T589 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.959376551 Sep 11 07:00:06 PM UTC 24 Sep 11 07:02:51 PM UTC 24 3853121667 ps
T1368 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2584609761 Sep 11 06:54:49 PM UTC 24 Sep 11 07:02:52 PM UTC 24 9088500338 ps
T581 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.3415841367 Sep 11 07:01:50 PM UTC 24 Sep 11 07:03:06 PM UTC 24 2152142043 ps
T1369 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.2883606270 Sep 11 06:56:06 PM UTC 24 Sep 11 07:03:34 PM UTC 24 10331689587 ps
T620 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.4106401116 Sep 11 07:03:09 PM UTC 24 Sep 11 07:03:34 PM UTC 24 554750010 ps
T1370 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.895166507 Sep 11 07:03:19 PM UTC 24 Sep 11 07:03:38 PM UTC 24 73344714 ps
T604 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.4188657423 Sep 11 07:02:54 PM UTC 24 Sep 11 07:03:40 PM UTC 24 372887304 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.2986473906 Sep 11 06:59:25 PM UTC 24 Sep 11 07:03:43 PM UTC 24 5651573204 ps
T1371 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.3243188061 Sep 11 07:03:17 PM UTC 24 Sep 11 07:03:47 PM UTC 24 649806721 ps
T1372 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.1830066862 Sep 11 07:03:30 PM UTC 24 Sep 11 07:04:10 PM UTC 24 256348591 ps
T632 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.2992505341 Sep 11 07:02:24 PM UTC 24 Sep 11 07:04:25 PM UTC 24 8913076342 ps
T1373 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3997115854 Sep 11 06:54:15 PM UTC 24 Sep 11 07:04:30 PM UTC 24 12066664153 ps
T594 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.4242487632 Sep 11 07:02:50 PM UTC 24 Sep 11 07:04:30 PM UTC 24 2144793830 ps
T822 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.3317366633 Sep 11 07:02:56 PM UTC 24 Sep 11 07:04:32 PM UTC 24 2655808609 ps
T848 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.4253474238 Sep 11 07:02:30 PM UTC 24 Sep 11 07:04:35 PM UTC 24 6419901188 ps
T1374 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.361812853 Sep 11 07:04:51 PM UTC 24 Sep 11 07:05:01 PM UTC 24 47943770 ps
T616 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.407303971 Sep 11 06:58:45 PM UTC 24 Sep 11 07:05:03 PM UTC 24 25022904147 ps
T586 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.2739934163 Sep 11 07:04:55 PM UTC 24 Sep 11 07:05:05 PM UTC 24 47946740 ps
T635 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.4041923862 Sep 11 07:04:59 PM UTC 24 Sep 11 07:05:24 PM UTC 24 175087133 ps
T649 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.2565322076 Sep 11 07:03:57 PM UTC 24 Sep 11 07:05:45 PM UTC 24 1704467855 ps
T503 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.1964960606 Sep 11 07:05:26 PM UTC 24 Sep 11 07:06:00 PM UTC 24 258556394 ps
T605 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.215486393 Sep 11 06:54:18 PM UTC 24 Sep 11 07:06:02 PM UTC 24 48758747430 ps
T1375 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.2590389354 Sep 11 07:04:58 PM UTC 24 Sep 11 07:06:20 PM UTC 24 5215910315 ps
T854 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.2099221585 Sep 11 07:04:54 PM UTC 24 Sep 11 07:06:28 PM UTC 24 5709041801 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.2449390502 Sep 11 06:59:02 PM UTC 24 Sep 11 07:06:48 PM UTC 24 13425404287 ps
T1376 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.1700711856 Sep 11 07:06:25 PM UTC 24 Sep 11 07:06:48 PM UTC 24 179901636 ps
T806 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.1511526860 Sep 11 07:05:49 PM UTC 24 Sep 11 07:07:04 PM UTC 24 549748865 ps
T598 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.1161423716 Sep 11 07:06:46 PM UTC 24 Sep 11 07:07:08 PM UTC 24 131134068 ps
T505 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.4094178340 Sep 11 07:01:49 PM UTC 24 Sep 11 07:07:12 PM UTC 24 5902460147 ps
T583 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.3992057246 Sep 11 07:02:11 PM UTC 24 Sep 11 07:07:18 PM UTC 24 3679436545 ps
T481 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.3323904717 Sep 11 06:55:01 PM UTC 24 Sep 11 07:07:25 PM UTC 24 82377534993 ps
T656 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.192116447 Sep 11 07:06:53 PM UTC 24 Sep 11 07:07:28 PM UTC 24 552857373 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.2406508408 Sep 11 06:57:49 PM UTC 24 Sep 11 07:07:31 PM UTC 24 6603473250 ps
T682 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.3331166945 Sep 11 07:00:49 PM UTC 24 Sep 11 07:07:31 PM UTC 24 28319119286 ps
T633 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.3771269828 Sep 11 07:06:24 PM UTC 24 Sep 11 07:07:42 PM UTC 24 1919701882 ps
T537 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.2277460739 Sep 11 06:56:15 PM UTC 24 Sep 11 07:07:44 PM UTC 24 66265752391 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.3039827195 Sep 11 07:02:05 PM UTC 24 Sep 11 07:07:46 PM UTC 24 5002694740 ps
T829 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.2799999588 Sep 11 06:58:50 PM UTC 24 Sep 11 07:07:55 PM UTC 24 39109395375 ps
T1377 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.831198495 Sep 11 07:07:56 PM UTC 24 Sep 11 07:08:05 PM UTC 24 47211352 ps
T593 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.3083711159 Sep 11 07:04:36 PM UTC 24 Sep 11 07:08:07 PM UTC 24 3378102530 ps
T544 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.3187486222 Sep 11 07:07:57 PM UTC 24 Sep 11 07:08:09 PM UTC 24 228054903 ps
T653 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.3739012873 Sep 11 07:04:03 PM UTC 24 Sep 11 07:08:19 PM UTC 24 3072513199 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.3148179812 Sep 11 07:02:04 PM UTC 24 Sep 11 07:08:21 PM UTC 24 7350388818 ps
T602 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.875000378 Sep 11 07:08:11 PM UTC 24 Sep 11 07:08:25 PM UTC 24 170820260 ps
T654 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.4198807499 Sep 11 07:01:53 PM UTC 24 Sep 11 07:08:29 PM UTC 24 11447805011 ps
T623 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.452078318 Sep 11 07:08:20 PM UTC 24 Sep 11 07:08:38 PM UTC 24 170364001 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.3427677563 Sep 11 07:04:00 PM UTC 24 Sep 11 07:08:42 PM UTC 24 3589871620 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3874627985 Sep 11 06:54:40 PM UTC 24 Sep 11 07:08:52 PM UTC 24 9186354616 ps
T614 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.3498768936 Sep 11 06:56:29 PM UTC 24 Sep 11 07:09:09 PM UTC 24 45202281389 ps
T872 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.454044352 Sep 11 07:07:13 PM UTC 24 Sep 11 07:09:09 PM UTC 24 161929459 ps
T1378 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.1054751751 Sep 11 07:08:51 PM UTC 24 Sep 11 07:09:10 PM UTC 24 137277325 ps
T1379 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.3179591444 Sep 11 06:58:42 PM UTC 24 Sep 11 07:09:13 PM UTC 24 54519663493 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.630746060 Sep 11 07:02:01 PM UTC 24 Sep 11 07:09:13 PM UTC 24 6061732610 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.666332940 Sep 11 06:59:27 PM UTC 24 Sep 11 07:09:17 PM UTC 24 6153497899 ps
T506 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.1591996403 Sep 11 07:08:46 PM UTC 24 Sep 11 07:09:17 PM UTC 24 399080780 ps
T621 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.3463507241 Sep 11 07:02:53 PM UTC 24 Sep 11 07:09:22 PM UTC 24 35654075497 ps
T844 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.1180949398 Sep 11 07:08:32 PM UTC 24 Sep 11 07:09:23 PM UTC 24 412037341 ps
T1380 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.1313656374 Sep 11 07:09:04 PM UTC 24 Sep 11 07:09:28 PM UTC 24 190477082 ps
T524 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.2239439162 Sep 11 07:08:55 PM UTC 24 Sep 11 07:09:29 PM UTC 24 178218036 ps
T1381 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.666612953 Sep 11 07:08:07 PM UTC 24 Sep 11 07:09:43 PM UTC 24 8880157151 ps
T893 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.958341682 Sep 11 07:09:34 PM UTC 24 Sep 11 07:09:56 PM UTC 24 100124589 ps
T1382 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.1746378429 Sep 11 07:09:41 PM UTC 24 Sep 11 07:09:57 PM UTC 24 230618014 ps
T651 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.1656595362 Sep 11 07:10:35 PM UTC 24 Sep 11 07:11:48 PM UTC 24 1940233388 ps
T1383 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.1679882736 Sep 11 07:09:48 PM UTC 24 Sep 11 07:09:57 PM UTC 24 38643264 ps
T479 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.856693275 Sep 11 07:03:58 PM UTC 24 Sep 11 07:10:03 PM UTC 24 8689769794 ps
T1384 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.274244751 Sep 11 07:08:10 PM UTC 24 Sep 11 07:10:08 PM UTC 24 6307193971 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.2286675493 Sep 11 07:07:13 PM UTC 24 Sep 11 07:10:10 PM UTC 24 1891727306 ps
T637 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.2206767541 Sep 11 07:02:56 PM UTC 24 Sep 11 07:10:14 PM UTC 24 25832525739 ps
T1385 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.3452244124 Sep 11 07:09:32 PM UTC 24 Sep 11 07:10:37 PM UTC 24 591661201 ps
T587 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.371362628 Sep 11 07:07:53 PM UTC 24 Sep 11 07:10:47 PM UTC 24 3845723712 ps
T507 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.863739080 Sep 11 07:10:08 PM UTC 24 Sep 11 07:10:58 PM UTC 24 383218363 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.2502084613 Sep 11 07:09:07 PM UTC 24 Sep 11 07:11:04 PM UTC 24 1206639467 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_bit_bash.2969410123 Sep 11 06:55:43 PM UTC 24 Sep 11 07:11:07 PM UTC 24 8772289634 ps
T1386 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3247684379 Sep 11 07:09:52 PM UTC 24 Sep 11 07:11:20 PM UTC 24 5976283909 ps
T830 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.29869044 Sep 11 06:54:21 PM UTC 24 Sep 11 07:11:26 PM UTC 24 67651754423 ps
T502 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.3726075331 Sep 11 07:09:53 PM UTC 24 Sep 11 07:11:33 PM UTC 24 1745678919 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.3767798475 Sep 11 07:10:20 PM UTC 24 Sep 11 07:11:37 PM UTC 24 820742648 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.2979561548 Sep 11 07:03:52 PM UTC 24 Sep 11 07:11:39 PM UTC 24 9449151868 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.3450388896 Sep 11 07:10:33 PM UTC 24 Sep 11 07:11:44 PM UTC 24 2224030302 ps
T1387 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.1938354451 Sep 11 07:11:01 PM UTC 24 Sep 11 07:11:48 PM UTC 24 928415672 ps
T831 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1035460207 Sep 11 07:03:02 PM UTC 24 Sep 11 07:11:59 PM UTC 24 25785172457 ps
T874 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3500489995 Sep 11 07:07:34 PM UTC 24 Sep 11 07:12:00 PM UTC 24 1033708594 ps
T1388 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.1904543900 Sep 11 07:10:38 PM UTC 24 Sep 11 07:12:02 PM UTC 24 1502858110 ps
T1389 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.2638205605 Sep 11 07:09:48 PM UTC 24 Sep 11 07:12:03 PM UTC 24 10079924373 ps
T860 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.4109637456 Sep 11 07:09:17 PM UTC 24 Sep 11 07:12:12 PM UTC 24 285494615 ps
T1390 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.2970888630 Sep 11 07:12:04 PM UTC 24 Sep 11 07:12:15 PM UTC 24 139631978 ps
T812 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.1634167549 Sep 11 07:11:30 PM UTC 24 Sep 11 07:12:19 PM UTC 24 1092680858 ps
T1391 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.995422009 Sep 11 07:12:10 PM UTC 24 Sep 11 07:12:19 PM UTC 24 40770275 ps
T1392 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.1798677106 Sep 11 07:12:23 PM UTC 24 Sep 11 07:12:32 PM UTC 24 146022983 ps
T1393 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.551955513 Sep 11 07:12:25 PM UTC 24 Sep 11 07:12:40 PM UTC 24 133923842 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.2844943565 Sep 11 06:57:59 PM UTC 24 Sep 11 07:12:47 PM UTC 24 10887633998 ps
T610 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.1184331176 Sep 11 07:00:38 PM UTC 24 Sep 11 07:12:58 PM UTC 24 51106903651 ps
T1394 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.2891784111 Sep 11 07:12:41 PM UTC 24 Sep 11 07:13:12 PM UTC 24 676435003 ps
T1395 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.1592321132 Sep 11 07:12:57 PM UTC 24 Sep 11 07:13:12 PM UTC 24 306162633 ps
T1396 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.860198552 Sep 11 07:13:01 PM UTC 24 Sep 11 07:13:26 PM UTC 24 370291432 ps
T1397 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.3688780131 Sep 11 07:12:11 PM UTC 24 Sep 11 07:13:31 PM UTC 24 8142382864 ps
T1398 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.1489441161 Sep 11 07:13:37 PM UTC 24 Sep 11 07:13:43 PM UTC 24 5699414 ps
T813 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.379341699 Sep 11 07:12:37 PM UTC 24 Sep 11 07:13:43 PM UTC 24 1426989076 ps
T627 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.1923751151 Sep 11 07:12:13 PM UTC 24 Sep 11 07:13:49 PM UTC 24 4406528731 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.296171562 Sep 11 07:12:43 PM UTC 24 Sep 11 07:13:59 PM UTC 24 1723144444 ps
T578 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.704966496 Sep 11 07:09:39 PM UTC 24 Sep 11 07:14:07 PM UTC 24 3018299344 ps
T686 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.199480339 Sep 11 07:07:29 PM UTC 24 Sep 11 07:14:07 PM UTC 24 11872895157 ps
T1399 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.2583176847 Sep 11 07:14:14 PM UTC 24 Sep 11 07:14:24 PM UTC 24 46633889 ps
T595 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.200836481 Sep 11 07:11:59 PM UTC 24 Sep 11 07:14:29 PM UTC 24 3366145960 ps
T1400 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2576294553 Sep 11 07:14:24 PM UTC 24 Sep 11 07:14:34 PM UTC 24 35047093 ps
T1401 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.3460423024 Sep 11 06:58:02 PM UTC 24 Sep 11 07:14:51 PM UTC 24 10221024925 ps
T553 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.3407454028 Sep 11 07:09:35 PM UTC 24 Sep 11 07:14:59 PM UTC 24 4717861354 ps
T832 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.2126870476 Sep 11 07:13:21 PM UTC 24 Sep 11 07:15:04 PM UTC 24 218327331 ps
T1402 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.2685778436 Sep 11 07:14:50 PM UTC 24 Sep 11 07:15:05 PM UTC 24 227841336 ps
T493 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.3724813326 Sep 11 07:14:54 PM UTC 24 Sep 11 07:15:22 PM UTC 24 214688568 ps
T617 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.2306261311 Sep 11 07:11:13 PM UTC 24 Sep 11 07:15:27 PM UTC 24 2629090033 ps
T628 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.3141507886 Sep 11 07:01:52 PM UTC 24 Sep 11 07:15:30 PM UTC 24 15150653203 ps
T542 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.3384656258 Sep 11 07:05:27 PM UTC 24 Sep 11 07:21:48 PM UTC 24 81336582419 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.2012891587 Sep 11 07:04:07 PM UTC 24 Sep 11 07:15:33 PM UTC 24 9828202135 ps
T1403 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.2240773342 Sep 11 07:12:28 PM UTC 24 Sep 11 07:15:49 PM UTC 24 18616111079 ps
T1404 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.2851436033 Sep 11 07:14:32 PM UTC 24 Sep 11 07:15:50 PM UTC 24 9023875212 ps
T622 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.224449765 Sep 11 07:14:31 PM UTC 24 Sep 11 07:16:22 PM UTC 24 4895098398 ps
T1405 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.4216579821 Sep 11 07:15:53 PM UTC 24 Sep 11 07:16:29 PM UTC 24 217205438 ps
T1406 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3104250841 Sep 11 07:15:55 PM UTC 24 Sep 11 07:16:30 PM UTC 24 571275460 ps
T644 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.2607680191 Sep 11 07:15:32 PM UTC 24 Sep 11 07:16:33 PM UTC 24 2281759654 ps
T1407 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2489954512 Sep 11 07:16:14 PM UTC 24 Sep 11 07:16:35 PM UTC 24 93867793 ps
T596 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.2767067168 Sep 11 07:08:31 PM UTC 24 Sep 11 07:16:47 PM UTC 24 32727175814 ps
T837 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.1157407946 Sep 11 07:15:24 PM UTC 24 Sep 11 07:16:49 PM UTC 24 1002880228 ps
T684 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.643444813 Sep 11 07:15:45 PM UTC 24 Sep 11 07:16:52 PM UTC 24 2043040204 ps
T613 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.3340246874 Sep 11 07:15:58 PM UTC 24 Sep 11 07:17:06 PM UTC 24 480839242 ps
T552 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.2279643501 Sep 11 06:59:35 PM UTC 24 Sep 11 07:17:09 PM UTC 24 12288643698 ps
T643 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.4174781439 Sep 11 07:17:02 PM UTC 24 Sep 11 07:17:12 PM UTC 24 46617720 ps
T1408 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2296960003 Sep 11 07:17:11 PM UTC 24 Sep 11 07:17:20 PM UTC 24 39386085 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.2836942972 Sep 11 07:09:38 PM UTC 24 Sep 11 07:17:40 PM UTC 24 7174530708 ps
T579 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.468336393 Sep 11 07:14:07 PM UTC 24 Sep 11 07:17:41 PM UTC 24 2835136392 ps
T551 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.481562042 Sep 11 07:07:38 PM UTC 24 Sep 11 07:17:49 PM UTC 24 5781027934 ps
T1409 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.985052530 Sep 11 07:17:31 PM UTC 24 Sep 11 07:17:50 PM UTC 24 156826068 ps
T1410 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.4271277644 Sep 11 07:15:16 PM UTC 24 Sep 11 07:17:51 PM UTC 24 8166488812 ps
T1411 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.3131433686 Sep 11 07:17:32 PM UTC 24 Sep 11 07:18:07 PM UTC 24 554605419 ps
T603 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.2291629482 Sep 11 07:10:21 PM UTC 24 Sep 11 07:18:08 PM UTC 24 31145093602 ps
T538 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1608299944 Sep 11 07:11:20 PM UTC 24 Sep 11 07:18:18 PM UTC 24 785575877 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.2695963615 Sep 11 07:11:51 PM UTC 24 Sep 11 07:18:27 PM UTC 24 7338464384 ps
T1412 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2653978399 Sep 11 07:17:18 PM UTC 24 Sep 11 07:18:39 PM UTC 24 4784750553 ps
T1413 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.1930997191 Sep 11 07:18:15 PM UTC 24 Sep 11 07:18:45 PM UTC 24 513874271 ps
T655 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.2236518838 Sep 11 07:16:16 PM UTC 24 Sep 11 07:18:46 PM UTC 24 3008289902 ps
T858 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.91687485 Sep 11 07:12:28 PM UTC 24 Sep 11 07:18:53 PM UTC 24 22688716201 ps
T601 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.412894243 Sep 11 07:00:41 PM UTC 24 Sep 11 07:18:58 PM UTC 24 97584383894 ps
T1414 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.2930489784 Sep 11 07:17:14 PM UTC 24 Sep 11 07:19:04 PM UTC 24 9345723627 ps
T1415 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1247180183 Sep 11 07:18:32 PM UTC 24 Sep 11 07:19:04 PM UTC 24 256775708 ps
T641 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.2173059162 Sep 11 07:18:10 PM UTC 24 Sep 11 07:19:05 PM UTC 24 1718997180 ps
T878 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3348892717 Sep 11 07:16:48 PM UTC 24 Sep 11 07:19:20 PM UTC 24 1322452340 ps
T1416 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.3006306728 Sep 11 07:18:15 PM UTC 24 Sep 11 07:19:35 PM UTC 24 1842958326 ps
T1417 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.3331171309 Sep 11 07:19:27 PM UTC 24 Sep 11 07:19:38 PM UTC 24 50809421 ps
T606 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1342101731 Sep 11 07:19:29 PM UTC 24 Sep 11 07:19:39 PM UTC 24 53815508 ps
T640 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.3547580913 Sep 11 07:19:46 PM UTC 24 Sep 11 07:20:05 PM UTC 24 110063854 ps
T864 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.1064722772 Sep 11 07:13:36 PM UTC 24 Sep 11 07:20:10 PM UTC 24 785688108 ps
T807 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.3781620137 Sep 11 07:18:04 PM UTC 24 Sep 11 07:20:28 PM UTC 24 2597653557 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.2566653238 Sep 11 07:13:12 PM UTC 24 Sep 11 07:20:41 PM UTC 24 12379285375 ps
T504 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.3777092402 Sep 11 07:19:56 PM UTC 24 Sep 11 07:20:54 PM UTC 24 456680935 ps
T1418 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3867684861 Sep 11 07:19:42 PM UTC 24 Sep 11 07:21:20 PM UTC 24 4270905713 ps
T629 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.2854025832 Sep 11 07:05:28 PM UTC 24 Sep 11 07:21:29 PM UTC 24 64595953001 ps
T1419 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.4144501190 Sep 11 07:19:30 PM UTC 24 Sep 11 07:21:40 PM UTC 24 8380207145 ps
T1420 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.1809525086 Sep 11 07:21:07 PM UTC 24 Sep 11 07:21:45 PM UTC 24 474688467 ps
T546 /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.1846973514 Sep 11 07:20:53 PM UTC 24 Sep 11 07:21:48 PM UTC 24 1380628550 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%