| T2514 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.1189542964 |
|
|
Sep 11 09:01:44 PM UTC 24 |
Sep 11 09:01:51 PM UTC 24 |
50432264 ps |
| T2515 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.2678725037 |
|
|
Sep 11 09:01:25 PM UTC 24 |
Sep 11 09:01:53 PM UTC 24 |
750018500 ps |
| T2516 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.2106897200 |
|
|
Sep 11 08:56:30 PM UTC 24 |
Sep 11 09:01:55 PM UTC 24 |
10172334415 ps |
| T2517 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.2118659926 |
|
|
Sep 11 09:00:17 PM UTC 24 |
Sep 11 09:01:58 PM UTC 24 |
2370090330 ps |
| T2518 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.2424160486 |
|
|
Sep 11 09:01:53 PM UTC 24 |
Sep 11 09:02:03 PM UTC 24 |
37660578 ps |
| T2519 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.269054351 |
|
|
Sep 11 09:01:00 PM UTC 24 |
Sep 11 09:02:07 PM UTC 24 |
4197994434 ps |
| T2520 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.286138293 |
|
|
Sep 11 08:59:51 PM UTC 24 |
Sep 11 09:02:11 PM UTC 24 |
386457816 ps |
| T2521 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.164247874 |
|
|
Sep 11 09:01:28 PM UTC 24 |
Sep 11 09:02:16 PM UTC 24 |
1289633737 ps |
| T2522 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.1750177923 |
|
|
Sep 11 08:58:45 PM UTC 24 |
Sep 11 09:02:17 PM UTC 24 |
6513307178 ps |
| T2523 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.3754174190 |
|
|
Sep 11 09:01:03 PM UTC 24 |
Sep 11 09:02:18 PM UTC 24 |
1746110196 ps |
| T2524 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.2614157904 |
|
|
Sep 11 09:00:56 PM UTC 24 |
Sep 11 09:02:39 PM UTC 24 |
10953317168 ps |
| T2525 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.3038487656 |
|
|
Sep 11 09:01:22 PM UTC 24 |
Sep 11 09:02:41 PM UTC 24 |
1632357594 ps |
| T2526 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.402214007 |
|
|
Sep 11 08:49:01 PM UTC 24 |
Sep 11 09:02:43 PM UTC 24 |
53877148988 ps |
| T2527 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.628853407 |
|
|
Sep 11 09:02:07 PM UTC 24 |
Sep 11 09:02:47 PM UTC 24 |
491915648 ps |
| T2528 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.1453887277 |
|
|
Sep 11 09:01:59 PM UTC 24 |
Sep 11 09:02:55 PM UTC 24 |
3511395387 ps |
| T2529 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.2114300658 |
|
|
Sep 11 09:01:59 PM UTC 24 |
Sep 11 09:02:58 PM UTC 24 |
1861831869 ps |
| T2530 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.4114145262 |
|
|
Sep 11 09:02:30 PM UTC 24 |
Sep 11 09:03:04 PM UTC 24 |
212570909 ps |
| T2531 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.2010812195 |
|
|
Sep 11 09:01:36 PM UTC 24 |
Sep 11 09:03:10 PM UTC 24 |
160965195 ps |
| T2532 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.2451522485 |
|
|
Sep 11 09:02:33 PM UTC 24 |
Sep 11 09:03:12 PM UTC 24 |
752615998 ps |
| T2533 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.3162470185 |
|
|
Sep 11 09:02:18 PM UTC 24 |
Sep 11 09:03:14 PM UTC 24 |
531034093 ps |
| T2534 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.238356238 |
|
|
Sep 11 09:03:05 PM UTC 24 |
Sep 11 09:03:15 PM UTC 24 |
43838215 ps |
| T2535 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.3986335451 |
|
|
Sep 11 09:03:06 PM UTC 24 |
Sep 11 09:03:16 PM UTC 24 |
57041993 ps |
| T2536 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.3665426346 |
|
|
Sep 11 09:02:17 PM UTC 24 |
Sep 11 09:03:18 PM UTC 24 |
1384961309 ps |
| T2537 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.741454684 |
|
|
Sep 11 09:01:37 PM UTC 24 |
Sep 11 09:03:18 PM UTC 24 |
1257723232 ps |
| T2538 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.837670125 |
|
|
Sep 11 09:01:55 PM UTC 24 |
Sep 11 09:03:26 PM UTC 24 |
7057315929 ps |
| T2539 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.4024375563 |
|
|
Sep 11 08:59:43 PM UTC 24 |
Sep 11 09:03:26 PM UTC 24 |
3526215389 ps |
| T2540 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.2858882514 |
|
|
Sep 11 09:02:25 PM UTC 24 |
Sep 11 09:03:31 PM UTC 24 |
1809240762 ps |
| T2541 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.534172123 |
|
|
Sep 11 09:00:29 PM UTC 24 |
Sep 11 09:03:36 PM UTC 24 |
2165615966 ps |
| T2542 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.3885871307 |
|
|
Sep 11 09:02:44 PM UTC 24 |
Sep 11 09:03:38 PM UTC 24 |
211611497 ps |
| T2543 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.726966841 |
|
|
Sep 11 09:03:23 PM UTC 24 |
Sep 11 09:03:41 PM UTC 24 |
126006891 ps |
| T2544 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.3777247017 |
|
|
Sep 11 08:58:55 PM UTC 24 |
Sep 11 09:03:46 PM UTC 24 |
9291887529 ps |
| T2545 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.1954415791 |
|
|
Sep 11 08:56:46 PM UTC 24 |
Sep 11 09:03:48 PM UTC 24 |
13138069315 ps |
| T2546 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.1131328971 |
|
|
Sep 11 09:03:19 PM UTC 24 |
Sep 11 09:03:55 PM UTC 24 |
923311349 ps |
| T2547 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.3271240117 |
|
|
Sep 11 08:32:39 PM UTC 24 |
Sep 11 09:04:02 PM UTC 24 |
119991897748 ps |
| T2548 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.887219163 |
|
|
Sep 11 08:38:58 PM UTC 24 |
Sep 11 09:04:11 PM UTC 24 |
110070383367 ps |
| T2549 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.1338937253 |
|
|
Sep 11 09:03:36 PM UTC 24 |
Sep 11 09:04:11 PM UTC 24 |
384848952 ps |
| T2550 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.1280752632 |
|
|
Sep 11 08:54:43 PM UTC 24 |
Sep 11 09:04:15 PM UTC 24 |
35368995803 ps |
| T2551 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.521204326 |
|
|
Sep 11 09:03:59 PM UTC 24 |
Sep 11 09:04:16 PM UTC 24 |
256618878 ps |
| T2552 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.1254008641 |
|
|
Sep 11 09:04:06 PM UTC 24 |
Sep 11 09:04:17 PM UTC 24 |
54633372 ps |
| T2553 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.4088103785 |
|
|
Sep 11 09:03:39 PM UTC 24 |
Sep 11 09:04:18 PM UTC 24 |
308179582 ps |
| T2554 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.1492703949 |
|
|
Sep 11 09:03:44 PM UTC 24 |
Sep 11 09:04:20 PM UTC 24 |
777946615 ps |
| T2555 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.1519596578 |
|
|
Sep 11 09:03:12 PM UTC 24 |
Sep 11 09:04:23 PM UTC 24 |
4815079621 ps |
| T2556 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.3479013435 |
|
|
Sep 11 09:03:38 PM UTC 24 |
Sep 11 09:04:30 PM UTC 24 |
1906173011 ps |
| T2557 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.2465606856 |
|
|
Sep 11 09:04:18 PM UTC 24 |
Sep 11 09:04:33 PM UTC 24 |
133948241 ps |
| T2558 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.1334091035 |
|
|
Sep 11 09:01:39 PM UTC 24 |
Sep 11 09:04:34 PM UTC 24 |
6341646701 ps |
| T2559 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.533894509 |
|
|
Sep 11 09:03:09 PM UTC 24 |
Sep 11 09:04:37 PM UTC 24 |
8583244720 ps |
| T2560 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.704956899 |
|
|
Sep 11 09:03:40 PM UTC 24 |
Sep 11 09:04:44 PM UTC 24 |
1330785687 ps |
| T2561 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.1798218078 |
|
|
Sep 11 08:53:14 PM UTC 24 |
Sep 11 09:04:44 PM UTC 24 |
62131700644 ps |
| T2562 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.483975044 |
|
|
Sep 11 09:04:26 PM UTC 24 |
Sep 11 09:04:50 PM UTC 24 |
268890552 ps |
| T2563 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.2798612986 |
|
|
Sep 11 09:00:31 PM UTC 24 |
Sep 11 09:05:06 PM UTC 24 |
850615148 ps |
| T2564 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.1306522983 |
|
|
Sep 11 09:05:02 PM UTC 24 |
Sep 11 09:05:12 PM UTC 24 |
51521095 ps |
| T2565 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.2273617658 |
|
|
Sep 11 09:04:46 PM UTC 24 |
Sep 11 09:05:14 PM UTC 24 |
232407559 ps |
| T2566 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.2098445608 |
|
|
Sep 11 09:04:38 PM UTC 24 |
Sep 11 09:05:14 PM UTC 24 |
1000323780 ps |
| T2567 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.856803066 |
|
|
Sep 11 09:05:09 PM UTC 24 |
Sep 11 09:05:19 PM UTC 24 |
42602208 ps |
| T2568 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.1792783676 |
|
|
Sep 11 08:53:18 PM UTC 24 |
Sep 11 09:05:22 PM UTC 24 |
50911454969 ps |
| T2569 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.2857354069 |
|
|
Sep 11 09:04:56 PM UTC 24 |
Sep 11 09:05:24 PM UTC 24 |
95799088 ps |
| T2570 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.4177294428 |
|
|
Sep 11 09:02:43 PM UTC 24 |
Sep 11 09:05:25 PM UTC 24 |
2367967569 ps |
| T2571 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.189553641 |
|
|
Sep 11 09:04:38 PM UTC 24 |
Sep 11 09:05:27 PM UTC 24 |
928275034 ps |
| T2572 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.2605617514 |
|
|
Sep 11 09:04:07 PM UTC 24 |
Sep 11 09:05:34 PM UTC 24 |
9069692850 ps |
| T2573 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.1675049092 |
|
|
Sep 11 09:04:38 PM UTC 24 |
Sep 11 09:05:35 PM UTC 24 |
2123210503 ps |
| T2574 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_large_delays.1975316873 |
|
|
Sep 11 09:03:29 PM UTC 24 |
Sep 11 09:05:39 PM UTC 24 |
14327134169 ps |
| T2575 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.1497653973 |
|
|
Sep 11 09:04:11 PM UTC 24 |
Sep 11 09:05:47 PM UTC 24 |
6753491648 ps |
| T2576 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.4106755106 |
|
|
Sep 11 09:05:57 PM UTC 24 |
Sep 11 09:06:31 PM UTC 24 |
337222429 ps |
| T2577 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.2373972495 |
|
|
Sep 11 09:02:37 PM UTC 24 |
Sep 11 09:05:51 PM UTC 24 |
6095374215 ps |
| T2578 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.3583951011 |
|
|
Sep 11 09:05:37 PM UTC 24 |
Sep 11 09:05:55 PM UTC 24 |
463240831 ps |
| T2579 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.3057912443 |
|
|
Sep 11 09:05:02 PM UTC 24 |
Sep 11 09:05:58 PM UTC 24 |
352483433 ps |
| T2580 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.1303500065 |
|
|
Sep 11 09:05:50 PM UTC 24 |
Sep 11 09:06:03 PM UTC 24 |
69792010 ps |
| T2581 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.3973244178 |
|
|
Sep 11 09:04:44 PM UTC 24 |
Sep 11 09:06:03 PM UTC 24 |
2384925479 ps |
| T2582 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.1387981804 |
|
|
Sep 11 08:59:19 PM UTC 24 |
Sep 11 09:06:14 PM UTC 24 |
27169416980 ps |
| T2583 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.3823604138 |
|
|
Sep 11 09:05:58 PM UTC 24 |
Sep 11 09:06:15 PM UTC 24 |
194901775 ps |
| T2584 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.2133754029 |
|
|
Sep 11 08:52:32 PM UTC 24 |
Sep 11 09:06:16 PM UTC 24 |
9491368073 ps |
| T2585 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.3900422493 |
|
|
Sep 11 09:06:04 PM UTC 24 |
Sep 11 09:06:26 PM UTC 24 |
152177854 ps |
| T2586 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.2444849543 |
|
|
Sep 11 09:05:36 PM UTC 24 |
Sep 11 09:06:31 PM UTC 24 |
558713458 ps |
| T2587 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.3356118519 |
|
|
Sep 11 09:04:55 PM UTC 24 |
Sep 11 09:06:33 PM UTC 24 |
2922133020 ps |
| T2588 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.2760767444 |
|
|
Sep 11 09:04:54 PM UTC 24 |
Sep 11 09:06:34 PM UTC 24 |
3043185431 ps |
| T2589 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.1151482159 |
|
|
Sep 11 09:06:28 PM UTC 24 |
Sep 11 09:06:37 PM UTC 24 |
39269765 ps |
| T2590 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.3735419691 |
|
|
Sep 11 08:56:00 PM UTC 24 |
Sep 11 09:06:38 PM UTC 24 |
45005267633 ps |
| T2591 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.2708040496 |
|
|
Sep 11 09:05:17 PM UTC 24 |
Sep 11 09:06:42 PM UTC 24 |
8025663897 ps |
| T2592 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.3499408613 |
|
|
Sep 11 09:00:36 PM UTC 24 |
Sep 11 09:06:45 PM UTC 24 |
9802355995 ps |
| T2593 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_slow_rsp.805662793 |
|
|
Sep 11 09:04:36 PM UTC 24 |
Sep 11 09:06:46 PM UTC 24 |
5758244887 ps |
| T2594 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.1644773786 |
|
|
Sep 11 08:44:10 PM UTC 24 |
Sep 11 09:06:48 PM UTC 24 |
95763882476 ps |
| T2595 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.3461018852 |
|
|
Sep 11 09:05:50 PM UTC 24 |
Sep 11 09:06:50 PM UTC 24 |
1852051794 ps |
| T2596 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.2344738658 |
|
|
Sep 11 09:06:42 PM UTC 24 |
Sep 11 09:06:51 PM UTC 24 |
36953126 ps |
| T2597 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.399139160 |
|
|
Sep 11 09:05:31 PM UTC 24 |
Sep 11 09:06:53 PM UTC 24 |
4929430006 ps |
| T2598 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.1135345329 |
|
|
Sep 11 09:05:47 PM UTC 24 |
Sep 11 09:07:00 PM UTC 24 |
1435860268 ps |
| T2599 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3277908938 |
|
|
Sep 11 09:06:21 PM UTC 24 |
Sep 11 09:07:02 PM UTC 24 |
99773987 ps |
| T2600 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.1543336769 |
|
|
Sep 11 08:51:51 PM UTC 24 |
Sep 11 09:07:04 PM UTC 24 |
88919040347 ps |
| T2601 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.3260784203 |
|
|
Sep 11 09:07:00 PM UTC 24 |
Sep 11 09:07:16 PM UTC 24 |
171669294 ps |
| T2602 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.3140706806 |
|
|
Sep 11 09:07:15 PM UTC 24 |
Sep 11 09:07:21 PM UTC 24 |
39864628 ps |
| T2603 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.3491223365 |
|
|
Sep 11 09:07:14 PM UTC 24 |
Sep 11 09:07:25 PM UTC 24 |
47144924 ps |
| T2604 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.2386044320 |
|
|
Sep 11 09:07:04 PM UTC 24 |
Sep 11 09:07:29 PM UTC 24 |
624546316 ps |
| T2605 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.2621623419 |
|
|
Sep 11 09:07:00 PM UTC 24 |
Sep 11 09:07:36 PM UTC 24 |
530444915 ps |
| T2606 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.4167978971 |
|
|
Sep 11 09:01:39 PM UTC 24 |
Sep 11 09:07:43 PM UTC 24 |
1854467891 ps |
| T2607 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.322738272 |
|
|
Sep 11 09:06:40 PM UTC 24 |
Sep 11 09:07:45 PM UTC 24 |
1470462120 ps |
| T2608 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.45744514 |
|
|
Sep 11 09:07:04 PM UTC 24 |
Sep 11 09:07:53 PM UTC 24 |
1283120931 ps |
| T2609 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.38522595 |
|
|
Sep 11 08:51:52 PM UTC 24 |
Sep 11 09:07:54 PM UTC 24 |
56544355765 ps |
| T2610 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.384998224 |
|
|
Sep 11 09:07:28 PM UTC 24 |
Sep 11 09:07:55 PM UTC 24 |
219825139 ps |
| T2611 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.2300280431 |
|
|
Sep 11 09:06:40 PM UTC 24 |
Sep 11 09:07:57 PM UTC 24 |
5342273535 ps |
| T2612 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.2017230733 |
|
|
Sep 11 09:06:30 PM UTC 24 |
Sep 11 09:08:01 PM UTC 24 |
6025844095 ps |
| T2613 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.2297691729 |
|
|
Sep 11 09:07:19 PM UTC 24 |
Sep 11 09:08:07 PM UTC 24 |
4904367518 ps |
| T2614 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.4195467715 |
|
|
Sep 11 09:07:25 PM UTC 24 |
Sep 11 09:08:10 PM UTC 24 |
1067622836 ps |
| T2615 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.3029471929 |
|
|
Sep 11 09:08:01 PM UTC 24 |
Sep 11 09:08:24 PM UTC 24 |
721323162 ps |
| T2616 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.2068589579 |
|
|
Sep 11 09:08:14 PM UTC 24 |
Sep 11 09:08:25 PM UTC 24 |
76909606 ps |
| T2617 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.3116638998 |
|
|
Sep 11 09:06:56 PM UTC 24 |
Sep 11 09:08:29 PM UTC 24 |
2663319917 ps |
| T2618 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_large_delays.3910411804 |
|
|
Sep 11 09:00:13 PM UTC 24 |
Sep 11 09:08:33 PM UTC 24 |
53588387938 ps |
| T2619 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.3586922696 |
|
|
Sep 11 08:29:33 PM UTC 24 |
Sep 11 09:08:37 PM UTC 24 |
148303049929 ps |
| T2620 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.3297032371 |
|
|
Sep 11 09:08:07 PM UTC 24 |
Sep 11 09:08:37 PM UTC 24 |
558339329 ps |
| T2621 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.3348390281 |
|
|
Sep 11 09:08:06 PM UTC 24 |
Sep 11 09:08:40 PM UTC 24 |
418202859 ps |
| T2622 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.3596640749 |
|
|
Sep 11 08:55:11 PM UTC 24 |
Sep 11 09:08:43 PM UTC 24 |
18990924456 ps |
| T2623 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.1973151990 |
|
|
Sep 11 09:08:35 PM UTC 24 |
Sep 11 09:08:43 PM UTC 24 |
46930605 ps |
| T2624 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.844014313 |
|
|
Sep 11 09:07:24 PM UTC 24 |
Sep 11 09:08:44 PM UTC 24 |
5874857306 ps |
| T2625 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.2149654341 |
|
|
Sep 11 09:08:31 PM UTC 24 |
Sep 11 09:08:44 PM UTC 24 |
163976529 ps |
| T2626 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.4239391553 |
|
|
Sep 11 09:07:50 PM UTC 24 |
Sep 11 09:08:47 PM UTC 24 |
1080910775 ps |
| T2627 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.2907031353 |
|
|
Sep 11 08:33:35 PM UTC 24 |
Sep 11 09:08:51 PM UTC 24 |
136148987716 ps |
| T2628 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.513609776 |
|
|
Sep 11 08:36:24 PM UTC 24 |
Sep 11 09:08:51 PM UTC 24 |
131862500563 ps |
| T2629 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.2721928723 |
|
|
Sep 11 09:07:11 PM UTC 24 |
Sep 11 09:09:06 PM UTC 24 |
3200167271 ps |
| T2630 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.949152829 |
|
|
Sep 11 09:09:06 PM UTC 24 |
Sep 11 09:09:21 PM UTC 24 |
230616765 ps |
| T2631 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.826579821 |
|
|
Sep 11 09:09:06 PM UTC 24 |
Sep 11 09:09:22 PM UTC 24 |
166404591 ps |
| T2632 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.1156690271 |
|
|
Sep 11 09:09:05 PM UTC 24 |
Sep 11 09:09:27 PM UTC 24 |
250019455 ps |
| T2633 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.3609442432 |
|
|
Sep 11 09:09:07 PM UTC 24 |
Sep 11 09:09:27 PM UTC 24 |
405354692 ps |
| T2634 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.1997177877 |
|
|
Sep 11 09:08:56 PM UTC 24 |
Sep 11 09:09:31 PM UTC 24 |
314022432 ps |
| T2635 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.3249949413 |
|
|
Sep 11 09:03:50 PM UTC 24 |
Sep 11 09:09:33 PM UTC 24 |
10008142803 ps |
| T2636 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_slow_rsp.1855508803 |
|
|
Sep 11 09:01:22 PM UTC 24 |
Sep 11 09:09:34 PM UTC 24 |
27733872877 ps |
| T2637 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.3045966571 |
|
|
Sep 11 09:08:53 PM UTC 24 |
Sep 11 09:09:37 PM UTC 24 |
533898330 ps |
| T2638 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.693023536 |
|
|
Sep 11 08:54:39 PM UTC 24 |
Sep 11 09:09:43 PM UTC 24 |
79349156253 ps |
| T2639 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.4206002506 |
|
|
Sep 11 08:57:50 PM UTC 24 |
Sep 11 09:09:48 PM UTC 24 |
5088323441 ps |
| T2640 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.219618989 |
|
|
Sep 11 09:09:10 PM UTC 24 |
Sep 11 09:09:51 PM UTC 24 |
297892023 ps |
| T2641 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.3234022188 |
|
|
Sep 11 08:58:54 PM UTC 24 |
Sep 11 09:09:57 PM UTC 24 |
6575351110 ps |
| T2642 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.2355154335 |
|
|
Sep 11 09:09:49 PM UTC 24 |
Sep 11 09:09:57 PM UTC 24 |
40057200 ps |
| T2643 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.2705820853 |
|
|
Sep 11 09:09:47 PM UTC 24 |
Sep 11 09:10:00 PM UTC 24 |
146281911 ps |
| T2644 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.3860228368 |
|
|
Sep 11 09:04:01 PM UTC 24 |
Sep 11 09:10:12 PM UTC 24 |
3772911543 ps |
| T2645 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.3540920723 |
|
|
Sep 11 09:09:59 PM UTC 24 |
Sep 11 09:10:19 PM UTC 24 |
226770505 ps |
| T2646 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.3744605001 |
|
|
Sep 11 09:09:55 PM UTC 24 |
Sep 11 09:10:24 PM UTC 24 |
870088353 ps |
| T2647 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.3072840926 |
|
|
Sep 11 09:01:24 PM UTC 24 |
Sep 11 09:10:32 PM UTC 24 |
30739515660 ps |
| T2648 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_slow_rsp.4144472694 |
|
|
Sep 11 09:03:35 PM UTC 24 |
Sep 11 09:10:34 PM UTC 24 |
30653520069 ps |
| T2649 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.3975877363 |
|
|
Sep 11 09:09:43 PM UTC 24 |
Sep 11 09:10:39 PM UTC 24 |
222299860 ps |
| T2650 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.2875491603 |
|
|
Sep 11 09:08:49 PM UTC 24 |
Sep 11 09:10:39 PM UTC 24 |
5398373076 ps |
| T2651 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.1901018752 |
|
|
Sep 11 09:10:13 PM UTC 24 |
Sep 11 09:10:53 PM UTC 24 |
367536104 ps |
| T2652 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.2027510230 |
|
|
Sep 11 09:10:22 PM UTC 24 |
Sep 11 09:10:58 PM UTC 24 |
485379404 ps |
| T2653 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.216746168 |
|
|
Sep 11 09:10:23 PM UTC 24 |
Sep 11 09:11:00 PM UTC 24 |
837222318 ps |
| T2654 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_large_delays.1265801464 |
|
|
Sep 11 09:05:38 PM UTC 24 |
Sep 11 09:11:01 PM UTC 24 |
34915706878 ps |
| T2655 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.1412114890 |
|
|
Sep 11 09:10:39 PM UTC 24 |
Sep 11 09:11:03 PM UTC 24 |
381125241 ps |
| T2656 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.3166764663 |
|
|
Sep 11 09:08:51 PM UTC 24 |
Sep 11 09:11:11 PM UTC 24 |
10204074340 ps |
| T2657 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.2183536784 |
|
|
Sep 11 08:59:14 PM UTC 24 |
Sep 11 09:11:11 PM UTC 24 |
75912461773 ps |
| T2658 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.3910557030 |
|
|
Sep 11 09:11:05 PM UTC 24 |
Sep 11 09:11:15 PM UTC 24 |
41244719 ps |
| T2659 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.3012037702 |
|
|
Sep 11 09:11:05 PM UTC 24 |
Sep 11 09:11:16 PM UTC 24 |
59729867 ps |
| T2660 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.1912293956 |
|
|
Sep 11 09:10:26 PM UTC 24 |
Sep 11 09:11:23 PM UTC 24 |
958953253 ps |
| T2661 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.1514141966 |
|
|
Sep 11 09:06:13 PM UTC 24 |
Sep 11 09:11:29 PM UTC 24 |
657568712 ps |
| T2662 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_large_delays.474023097 |
|
|
Sep 11 09:02:08 PM UTC 24 |
Sep 11 09:11:32 PM UTC 24 |
48514474734 ps |
| T2663 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.3198440631 |
|
|
Sep 11 09:09:51 PM UTC 24 |
Sep 11 09:11:32 PM UTC 24 |
7159099037 ps |
| T2664 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.948237495 |
|
|
Sep 11 09:02:39 PM UTC 24 |
Sep 11 09:11:34 PM UTC 24 |
7374272121 ps |
| T2665 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_large_delays.2654098942 |
|
|
Sep 11 09:01:15 PM UTC 24 |
Sep 11 09:11:40 PM UTC 24 |
65954327872 ps |
| T2666 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_slow_rsp.751736230 |
|
|
Sep 11 09:05:41 PM UTC 24 |
Sep 11 09:11:41 PM UTC 24 |
25113879542 ps |
| T2667 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.817508470 |
|
|
Sep 11 09:09:55 PM UTC 24 |
Sep 11 09:11:44 PM UTC 24 |
5104907803 ps |
| T2668 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.1259832953 |
|
|
Sep 11 09:11:41 PM UTC 24 |
Sep 11 09:11:56 PM UTC 24 |
366110553 ps |
| T2669 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.2612174242 |
|
|
Sep 11 09:07:09 PM UTC 24 |
Sep 11 09:12:08 PM UTC 24 |
7961886308 ps |
| T2670 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.3316764841 |
|
|
Sep 11 09:11:56 PM UTC 24 |
Sep 11 09:12:09 PM UTC 24 |
88934427 ps |
| T2671 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_large_delays.2480815418 |
|
|
Sep 11 09:07:42 PM UTC 24 |
Sep 11 09:12:15 PM UTC 24 |
30701358153 ps |
| T2672 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.2849653197 |
|
|
Sep 11 09:07:08 PM UTC 24 |
Sep 11 09:12:15 PM UTC 24 |
9183818453 ps |
| T2673 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.997582305 |
|
|
Sep 11 09:12:09 PM UTC 24 |
Sep 11 09:12:19 PM UTC 24 |
39477180 ps |
| T2674 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.31648832 |
|
|
Sep 11 09:11:25 PM UTC 24 |
Sep 11 09:12:21 PM UTC 24 |
611461639 ps |
| T2675 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.3344364855 |
|
|
Sep 11 09:11:54 PM UTC 24 |
Sep 11 09:12:25 PM UTC 24 |
216063061 ps |
| T2676 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.2107009239 |
|
|
Sep 11 09:11:19 PM UTC 24 |
Sep 11 09:12:27 PM UTC 24 |
6150942744 ps |
| T2677 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.1891141008 |
|
|
Sep 11 09:11:48 PM UTC 24 |
Sep 11 09:12:29 PM UTC 24 |
1264451036 ps |
| T2678 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.2707011076 |
|
|
Sep 11 09:12:22 PM UTC 24 |
Sep 11 09:12:32 PM UTC 24 |
52773031 ps |
| T2679 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.2161087453 |
|
|
Sep 11 09:12:06 PM UTC 24 |
Sep 11 09:12:36 PM UTC 24 |
48792458 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_error.273987304 |
|
|
Sep 11 09:08:21 PM UTC 24 |
Sep 11 09:12:36 PM UTC 24 |
8404620140 ps |
| T2680 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all.2724399429 |
|
|
Sep 11 09:10:45 PM UTC 24 |
Sep 11 09:12:43 PM UTC 24 |
1314915197 ps |
| T2681 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.112103095 |
|
|
Sep 11 09:11:26 PM UTC 24 |
Sep 11 09:12:51 PM UTC 24 |
2538869348 ps |
| T2682 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.2466273630 |
|
|
Sep 11 09:08:18 PM UTC 24 |
Sep 11 09:12:51 PM UTC 24 |
996848571 ps |
| T2683 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.3935319353 |
|
|
Sep 11 09:06:15 PM UTC 24 |
Sep 11 09:12:52 PM UTC 24 |
12054073906 ps |
| T2684 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.2983023215 |
|
|
Sep 11 09:12:41 PM UTC 24 |
Sep 11 09:12:53 PM UTC 24 |
125724428 ps |
| T2685 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.409185228 |
|
|
Sep 11 09:11:24 PM UTC 24 |
Sep 11 09:12:57 PM UTC 24 |
6492371348 ps |
| T2686 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.2930726900 |
|
|
Sep 11 09:12:37 PM UTC 24 |
Sep 11 09:13:09 PM UTC 24 |
306510360 ps |
| T2687 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.2627132639 |
|
|
Sep 11 09:11:37 PM UTC 24 |
Sep 11 09:13:14 PM UTC 24 |
2525406753 ps |
| T2688 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.2484342008 |
|
|
Sep 11 09:15:17 PM UTC 24 |
Sep 11 09:16:26 PM UTC 24 |
738005503 ps |
| T2689 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.1186725838 |
|
|
Sep 11 09:12:57 PM UTC 24 |
Sep 11 09:13:17 PM UTC 24 |
202533394 ps |
| T2690 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.3396709812 |
|
|
Sep 11 09:03:48 PM UTC 24 |
Sep 11 09:13:20 PM UTC 24 |
6475006501 ps |
| T2691 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.2683045632 |
|
|
Sep 11 09:13:15 PM UTC 24 |
Sep 11 09:13:28 PM UTC 24 |
251095584 ps |
| T2692 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.1640168473 |
|
|
Sep 11 09:13:01 PM UTC 24 |
Sep 11 09:13:32 PM UTC 24 |
209877097 ps |
| T2693 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.2653723937 |
|
|
Sep 11 09:13:22 PM UTC 24 |
Sep 11 09:13:33 PM UTC 24 |
54941314 ps |
| T2694 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.1293209673 |
|
|
Sep 11 08:56:11 PM UTC 24 |
Sep 11 09:13:38 PM UTC 24 |
67055714607 ps |
| T2695 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.3127599612 |
|
|
Sep 11 09:12:55 PM UTC 24 |
Sep 11 09:13:42 PM UTC 24 |
1766735792 ps |
| T2696 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.955834346 |
|
|
Sep 11 09:12:49 PM UTC 24 |
Sep 11 09:13:46 PM UTC 24 |
709148572 ps |
| T2697 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.3780259100 |
|
|
Sep 11 09:13:02 PM UTC 24 |
Sep 11 09:13:50 PM UTC 24 |
879216795 ps |
| T2698 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.3230131313 |
|
|
Sep 11 09:12:33 PM UTC 24 |
Sep 11 09:13:59 PM UTC 24 |
4003818952 ps |
| T2699 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.3184583299 |
|
|
Sep 11 09:09:15 PM UTC 24 |
Sep 11 09:14:06 PM UTC 24 |
8226061336 ps |
| T2700 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.4254562439 |
|
|
Sep 11 09:12:33 PM UTC 24 |
Sep 11 09:14:17 PM UTC 24 |
9478062373 ps |
| T2701 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.2709227786 |
|
|
Sep 11 09:09:15 PM UTC 24 |
Sep 11 09:14:21 PM UTC 24 |
4000525903 ps |
| T2702 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.1452195501 |
|
|
Sep 11 09:03:52 PM UTC 24 |
Sep 11 09:14:21 PM UTC 24 |
17862329211 ps |
| T2703 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.2956712609 |
|
|
Sep 11 09:13:46 PM UTC 24 |
Sep 11 09:14:21 PM UTC 24 |
325027242 ps |
| T2704 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.2147465366 |
|
|
Sep 11 09:14:14 PM UTC 24 |
Sep 11 09:14:29 PM UTC 24 |
245482767 ps |
| T2705 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.2248719391 |
|
|
Sep 11 09:14:13 PM UTC 24 |
Sep 11 09:14:29 PM UTC 24 |
145311970 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.1910579639 |
|
|
Sep 11 09:07:13 PM UTC 24 |
Sep 11 09:14:32 PM UTC 24 |
5183766137 ps |
| T2706 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.2803920703 |
|
|
Sep 11 09:14:22 PM UTC 24 |
Sep 11 09:14:37 PM UTC 24 |
220675366 ps |
| T2707 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.1808164060 |
|
|
Sep 11 09:14:06 PM UTC 24 |
Sep 11 09:14:41 PM UTC 24 |
429365525 ps |
| T2708 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_large_delays.3617282402 |
|
|
Sep 11 09:06:52 PM UTC 24 |
Sep 11 09:14:41 PM UTC 24 |
46171906311 ps |
| T2709 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.2333577879 |
|
|
Sep 11 08:57:15 PM UTC 24 |
Sep 11 09:14:43 PM UTC 24 |
101244832780 ps |
| T2710 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.1731514206 |
|
|
Sep 11 09:14:43 PM UTC 24 |
Sep 11 09:14:52 PM UTC 24 |
37218251 ps |
| T2711 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.806482035 |
|
|
Sep 11 08:59:26 PM UTC 24 |
Sep 11 09:14:55 PM UTC 24 |
60657166477 ps |
| T2712 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.2083211851 |
|
|
Sep 11 09:13:36 PM UTC 24 |
Sep 11 09:14:57 PM UTC 24 |
5450969677 ps |
| T2713 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.3330415393 |
|
|
Sep 11 09:14:55 PM UTC 24 |
Sep 11 09:15:05 PM UTC 24 |
46450090 ps |
| T2714 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.1421707542 |
|
|
Sep 11 09:10:47 PM UTC 24 |
Sep 11 09:15:06 PM UTC 24 |
703802320 ps |
| T2715 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.486864317 |
|
|
Sep 11 08:58:32 PM UTC 24 |
Sep 11 09:15:07 PM UTC 24 |
53345449921 ps |
| T2716 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_slow_rsp.2936331437 |
|
|
Sep 11 09:13:58 PM UTC 24 |
Sep 11 09:15:12 PM UTC 24 |
4311365294 ps |
| T2717 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.2131891366 |
|
|
Sep 11 09:14:54 PM UTC 24 |
Sep 11 09:16:25 PM UTC 24 |
8504974030 ps |
| T2718 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all.4294707745 |
|
|
Sep 11 09:08:17 PM UTC 24 |
Sep 11 09:15:12 PM UTC 24 |
12318063506 ps |
| T2719 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.3972212152 |
|
|
Sep 11 09:13:35 PM UTC 24 |
Sep 11 09:15:15 PM UTC 24 |
8205253312 ps |
| T2720 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.2640572400 |
|
|
Sep 11 09:13:18 PM UTC 24 |
Sep 11 09:15:17 PM UTC 24 |
285499498 ps |
| T2721 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.715228944 |
|
|
Sep 11 09:13:43 PM UTC 24 |
Sep 11 09:15:20 PM UTC 24 |
2450282739 ps |
| T2722 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.2164393534 |
|
|
Sep 11 09:04:41 PM UTC 24 |
Sep 11 09:15:26 PM UTC 24 |
42128445515 ps |
| T2723 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.1139383591 |
|
|
Sep 11 09:15:07 PM UTC 24 |
Sep 11 09:15:31 PM UTC 24 |
236502611 ps |
| T2724 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.1987045162 |
|
|
Sep 11 09:14:47 PM UTC 24 |
Sep 11 09:15:32 PM UTC 24 |
111534898 ps |
| T2725 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all.3421415849 |
|
|
Sep 11 09:13:04 PM UTC 24 |
Sep 11 09:15:35 PM UTC 24 |
4999497602 ps |
| T2726 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.1356023172 |
|
|
Sep 11 09:15:21 PM UTC 24 |
Sep 11 09:15:41 PM UTC 24 |
462641017 ps |
| T2727 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all.1398861392 |
|
|
Sep 11 09:11:55 PM UTC 24 |
Sep 11 09:15:46 PM UTC 24 |
6324797553 ps |
| T2728 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.3164095580 |
|
|
Sep 11 08:58:28 PM UTC 24 |
Sep 11 09:15:53 PM UTC 24 |
108884386460 ps |
| T2729 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.3231622233 |
|
|
Sep 11 09:15:00 PM UTC 24 |
Sep 11 09:15:56 PM UTC 24 |
1592310654 ps |
| T2730 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.2025675112 |
|
|
Sep 11 09:15:44 PM UTC 24 |
Sep 11 09:15:57 PM UTC 24 |
171985170 ps |
| T2731 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.1479724261 |
|
|
Sep 11 09:15:51 PM UTC 24 |
Sep 11 09:16:01 PM UTC 24 |
49813413 ps |
| T2732 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random.2662510046 |
|
|
Sep 11 09:15:59 PM UTC 24 |
Sep 11 09:16:08 PM UTC 24 |
28719984 ps |
| T2733 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.388863785 |
|
|
Sep 11 09:15:33 PM UTC 24 |
Sep 11 09:16:10 PM UTC 24 |
661222660 ps |
| T2734 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_error.2674693579 |
|
|
Sep 11 09:14:43 PM UTC 24 |
Sep 11 09:16:12 PM UTC 24 |
984091373 ps |
| T2735 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.1852109580 |
|
|
Sep 11 09:13:58 PM UTC 24 |
Sep 11 09:16:13 PM UTC 24 |
3442810184 ps |
| T2736 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_slow_rsp.4040806185 |
|
|
Sep 11 09:06:55 PM UTC 24 |
Sep 11 09:16:15 PM UTC 24 |
36343117648 ps |
| T2737 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.3129298931 |
|
|
Sep 11 09:15:31 PM UTC 24 |
Sep 11 09:16:18 PM UTC 24 |
598564554 ps |
| T2738 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_zero_delays.502453132 |
|
|
Sep 11 09:16:05 PM UTC 24 |
Sep 11 09:16:32 PM UTC 24 |
246143826 ps |
| T2739 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.459642836 |
|
|
Sep 11 09:14:57 PM UTC 24 |
Sep 11 09:16:34 PM UTC 24 |
5463537142 ps |
| T2740 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.829039911 |
|
|
Sep 11 09:00:15 PM UTC 24 |
Sep 11 09:16:36 PM UTC 24 |
66487498047 ps |
| T2741 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_slow_rsp.2595569877 |
|
|
Sep 11 09:02:13 PM UTC 24 |
Sep 11 09:16:36 PM UTC 24 |
58934592065 ps |
| T2742 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.572950871 |
|
|
Sep 11 08:46:32 PM UTC 24 |
Sep 11 09:16:41 PM UTC 24 |
126104027822 ps |
| T2743 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.1477076146 |
|
|
Sep 11 09:15:32 PM UTC 24 |
Sep 11 09:16:56 PM UTC 24 |
1422954834 ps |
| T2744 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.2969707106 |
|
|
Sep 11 09:13:14 PM UTC 24 |
Sep 11 09:16:58 PM UTC 24 |
564487248 ps |
| T2745 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device.3831317965 |
|
|
Sep 11 09:16:19 PM UTC 24 |
Sep 11 09:17:03 PM UTC 24 |
431431551 ps |
| T2746 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_unmapped_addr.3518751245 |
|
|
Sep 11 09:16:34 PM UTC 24 |
Sep 11 09:17:04 PM UTC 24 |
268861514 ps |
| T2747 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_same_source.1391662580 |
|
|
Sep 11 09:16:27 PM UTC 24 |
Sep 11 09:17:04 PM UTC 24 |
492273998 ps |
| T2748 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.647495927 |
|
|
Sep 11 09:15:57 PM UTC 24 |
Sep 11 09:17:04 PM UTC 24 |
5013374184 ps |
| T2749 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_zero_delays.2224101229 |
|
|
Sep 11 09:16:56 PM UTC 24 |
Sep 11 09:17:05 PM UTC 24 |
43620215 ps |
| T2750 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.3429315934 |
|
|
Sep 11 09:16:52 PM UTC 24 |
Sep 11 09:17:05 PM UTC 24 |
201791552 ps |
| T2751 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random.1769478647 |
|
|
Sep 11 09:17:02 PM UTC 24 |
Sep 11 09:17:15 PM UTC 24 |
141921608 ps |
| T2752 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_large_delays.1915295749 |
|
|
Sep 11 09:16:13 PM UTC 24 |
Sep 11 09:17:16 PM UTC 24 |
5891125266 ps |
| T2753 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_error.796207683 |
|
|
Sep 11 09:12:05 PM UTC 24 |
Sep 11 09:17:18 PM UTC 24 |
10746478407 ps |
| T2754 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.2864143158 |
|
|
Sep 11 09:16:34 PM UTC 24 |
Sep 11 09:17:19 PM UTC 24 |
591315477 ps |
| T2755 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.2031429220 |
|
|
Sep 11 09:16:20 PM UTC 24 |
Sep 11 09:17:20 PM UTC 24 |
2841989650 ps |
| T2756 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.1769590907 |
|
|
Sep 11 09:16:37 PM UTC 24 |
Sep 11 09:17:26 PM UTC 24 |
926076028 ps |
| T2757 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3960486962 |
|
|
Sep 11 09:10:59 PM UTC 24 |
Sep 11 09:17:44 PM UTC 24 |
9740098902 ps |
| T2758 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device.1966528698 |
|
|
Sep 11 09:17:25 PM UTC 24 |
Sep 11 09:17:49 PM UTC 24 |
226613121 ps |
| T2759 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_zero_delays.962243748 |
|
|
Sep 11 09:17:05 PM UTC 24 |
Sep 11 09:17:50 PM UTC 24 |
504398936 ps |
| T2760 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all.202297951 |
|
|
Sep 11 09:15:36 PM UTC 24 |
Sep 11 09:17:51 PM UTC 24 |
1606682901 ps |
| T2761 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_same_source.2816988267 |
|
|
Sep 11 09:17:28 PM UTC 24 |
Sep 11 09:17:53 PM UTC 24 |
280393855 ps |