| T1268 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_lc_ctrl_transition.2343940021 |
|
|
Sep 12 02:26:02 AM UTC 24 |
Sep 12 02:39:47 AM UTC 24 |
12821021229 ps |
| T1269 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.1142060358 |
|
|
Sep 12 02:29:18 AM UTC 24 |
Sep 12 02:40:24 AM UTC 24 |
4838939128 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.3617563057 |
|
|
Sep 12 02:29:18 AM UTC 24 |
Sep 12 02:40:33 AM UTC 24 |
6416838240 ps |
| T1270 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx.689338149 |
|
|
Sep 12 02:30:49 AM UTC 24 |
Sep 12 02:40:35 AM UTC 24 |
3595282000 ps |
| T1271 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.945382235 |
|
|
Sep 12 02:34:34 AM UTC 24 |
Sep 12 02:41:01 AM UTC 24 |
6895705076 ps |
| T1272 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3456270573 |
|
|
Sep 12 01:28:20 AM UTC 24 |
Sep 12 02:41:12 AM UTC 24 |
16990079938 ps |
| T1273 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx1.3637019742 |
|
|
Sep 12 02:32:12 AM UTC 24 |
Sep 12 02:41:41 AM UTC 24 |
4229437308 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.1600988141 |
|
|
Sep 12 02:27:42 AM UTC 24 |
Sep 12 02:41:55 AM UTC 24 |
8388332502 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.1929880149 |
|
|
Sep 12 03:19:27 AM UTC 24 |
Sep 12 03:27:49 AM UTC 24 |
5556944960 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1821721203 |
|
|
Sep 12 02:34:34 AM UTC 24 |
Sep 12 02:42:17 AM UTC 24 |
3856297416 ps |
| T1274 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2894242759 |
|
|
Sep 12 01:28:20 AM UTC 24 |
Sep 12 02:43:02 AM UTC 24 |
18264253666 ps |
| T1275 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx2.1379875964 |
|
|
Sep 12 02:33:08 AM UTC 24 |
Sep 12 02:43:21 AM UTC 24 |
4447938626 ps |
| T1276 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx3.1042003799 |
|
|
Sep 12 02:33:10 AM UTC 24 |
Sep 12 02:44:28 AM UTC 24 |
4974176572 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.1164833815 |
|
|
Sep 12 02:27:41 AM UTC 24 |
Sep 12 02:44:32 AM UTC 24 |
10713176963 ps |
| T1277 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.3554397788 |
|
|
Sep 12 02:09:37 AM UTC 24 |
Sep 12 02:44:52 AM UTC 24 |
22759361575 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3950031838 |
|
|
Sep 12 02:38:21 AM UTC 24 |
Sep 12 02:44:58 AM UTC 24 |
3186912600 ps |
| T1278 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.647843148 |
|
|
Sep 12 02:37:02 AM UTC 24 |
Sep 12 02:45:04 AM UTC 24 |
3871717540 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.1807689539 |
|
|
Sep 12 02:35:27 AM UTC 24 |
Sep 12 02:45:54 AM UTC 24 |
5080106904 ps |
| T1279 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_lc_ctrl_transition.251030654 |
|
|
Sep 12 02:38:06 AM UTC 24 |
Sep 12 02:46:50 AM UTC 24 |
7068568703 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.220292268 |
|
|
Sep 12 02:35:08 AM UTC 24 |
Sep 12 02:46:59 AM UTC 24 |
8152491416 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.4157340657 |
|
|
Sep 12 02:34:46 AM UTC 24 |
Sep 12 02:47:27 AM UTC 24 |
7275190204 ps |
| T1280 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.588337364 |
|
|
Sep 12 01:10:18 AM UTC 24 |
Sep 12 02:47:57 AM UTC 24 |
51477699920 ps |
| T1281 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.3659303719 |
|
|
Sep 12 02:34:44 AM UTC 24 |
Sep 12 02:48:12 AM UTC 24 |
12158672946 ps |
| T1282 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.836981302 |
|
|
Sep 12 02:41:58 AM UTC 24 |
Sep 12 02:49:18 AM UTC 24 |
3007428638 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.599689726 |
|
|
Sep 12 02:42:34 AM UTC 24 |
Sep 12 02:49:26 AM UTC 24 |
3774472200 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.2913840403 |
|
|
Sep 12 02:39:44 AM UTC 24 |
Sep 12 02:49:29 AM UTC 24 |
5795665860 ps |
| T1283 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_lc_ctrl_transition.1580196976 |
|
|
Sep 12 02:42:18 AM UTC 24 |
Sep 12 02:49:39 AM UTC 24 |
6009876117 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.837993225 |
|
|
Sep 12 02:36:27 AM UTC 24 |
Sep 12 02:49:43 AM UTC 24 |
5005498770 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3711370206 |
|
|
Sep 12 02:41:26 AM UTC 24 |
Sep 12 02:49:46 AM UTC 24 |
4022922576 ps |
| T1284 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.847701498 |
|
|
Sep 12 02:25:20 AM UTC 24 |
Sep 12 02:50:29 AM UTC 24 |
8428618190 ps |
| T1285 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_self_hash.709500279 |
|
|
Sep 12 12:42:18 AM UTC 24 |
Sep 12 02:50:33 AM UTC 24 |
26804139210 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.4219735322 |
|
|
Sep 11 09:29:57 PM UTC 24 |
Sep 12 02:51:03 AM UTC 24 |
81199921156 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.23676054 |
|
|
Sep 12 02:41:58 AM UTC 24 |
Sep 12 02:51:06 AM UTC 24 |
4371412400 ps |
| T1286 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.2791191222 |
|
|
Sep 12 02:40:27 AM UTC 24 |
Sep 12 02:52:13 AM UTC 24 |
4643885030 ps |
| T1287 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.1007489256 |
|
|
Sep 12 01:11:08 AM UTC 24 |
Sep 12 02:52:42 AM UTC 24 |
45285884884 ps |
| T1288 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.539073292 |
|
|
Sep 12 02:35:09 AM UTC 24 |
Sep 12 02:52:54 AM UTC 24 |
11706628880 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.655879464 |
|
|
Sep 12 02:45:52 AM UTC 24 |
Sep 12 02:53:32 AM UTC 24 |
3585854950 ps |
| T1289 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.3488570917 |
|
|
Sep 12 02:45:27 AM UTC 24 |
Sep 12 02:53:47 AM UTC 24 |
6153041075 ps |
| T1290 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_lc_ctrl_transition.1367929813 |
|
|
Sep 12 02:46:31 AM UTC 24 |
Sep 12 02:54:30 AM UTC 24 |
5611760684 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1302117984 |
|
|
Sep 12 02:47:43 AM UTC 24 |
Sep 12 02:54:51 AM UTC 24 |
3469606812 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.3474795053 |
|
|
Sep 12 02:43:40 AM UTC 24 |
Sep 12 02:54:57 AM UTC 24 |
5903239002 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.2595455933 |
|
|
Sep 12 01:46:59 AM UTC 24 |
Sep 12 02:55:42 AM UTC 24 |
14726483994 ps |
| T1291 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.350266366 |
|
|
Sep 12 02:48:37 AM UTC 24 |
Sep 12 02:56:16 AM UTC 24 |
3777377744 ps |
| T1292 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.263289535 |
|
|
Sep 12 01:10:07 AM UTC 24 |
Sep 12 02:56:38 AM UTC 24 |
48415164600 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2675723930 |
|
|
Sep 12 02:51:09 AM UTC 24 |
Sep 12 02:57:16 AM UTC 24 |
3697906440 ps |
| T1293 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.38761125 |
|
|
Sep 12 02:48:50 AM UTC 24 |
Sep 12 02:58:08 AM UTC 24 |
7799446300 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.1196777567 |
|
|
Sep 12 02:46:00 AM UTC 24 |
Sep 12 02:58:27 AM UTC 24 |
4796996392 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.4216625995 |
|
|
Sep 12 02:48:09 AM UTC 24 |
Sep 12 02:58:50 AM UTC 24 |
4542672984 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.462223641 |
|
|
Sep 12 02:50:38 AM UTC 24 |
Sep 12 02:59:16 AM UTC 24 |
3872043116 ps |
| T1294 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.1862929291 |
|
|
Sep 12 02:41:25 AM UTC 24 |
Sep 12 02:59:32 AM UTC 24 |
9968277938 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.922593685 |
|
|
Sep 12 02:53:36 AM UTC 24 |
Sep 12 02:59:55 AM UTC 24 |
3758651180 ps |
| T1295 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.3603400790 |
|
|
Sep 12 02:51:09 AM UTC 24 |
Sep 12 03:00:10 AM UTC 24 |
3768584152 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.3327705739 |
|
|
Sep 12 02:50:50 AM UTC 24 |
Sep 12 03:00:54 AM UTC 24 |
4776017900 ps |
| T1296 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.549284205 |
|
|
Sep 12 02:51:27 AM UTC 24 |
Sep 12 03:00:56 AM UTC 24 |
6596422912 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.1339604676 |
|
|
Sep 12 02:50:59 AM UTC 24 |
Sep 12 03:01:52 AM UTC 24 |
6211023560 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2489027387 |
|
|
Sep 12 02:55:42 AM UTC 24 |
Sep 12 03:02:01 AM UTC 24 |
3775788750 ps |
| T1297 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_smoketest.2223676577 |
|
|
Sep 12 02:19:36 AM UTC 24 |
Sep 12 03:02:01 AM UTC 24 |
11187167728 ps |
| T1298 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.2323736113 |
|
|
Sep 12 02:52:52 AM UTC 24 |
Sep 12 03:02:31 AM UTC 24 |
4289084170 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2832213610 |
|
|
Sep 12 02:56:57 AM UTC 24 |
Sep 12 03:02:44 AM UTC 24 |
3668669760 ps |
| T1299 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.2975397653 |
|
|
Sep 12 02:55:10 AM UTC 24 |
Sep 12 03:04:12 AM UTC 24 |
5359729654 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.1728362932 |
|
|
Sep 12 02:54:12 AM UTC 24 |
Sep 12 03:04:41 AM UTC 24 |
4985888700 ps |
| T1300 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2134387165 |
|
|
Sep 12 02:34:07 AM UTC 24 |
Sep 12 03:05:02 AM UTC 24 |
13639149151 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3133402158 |
|
|
Sep 12 02:58:05 AM UTC 24 |
Sep 12 03:05:13 AM UTC 24 |
3741686944 ps |
| T1301 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.1987835256 |
|
|
Sep 12 02:54:29 AM UTC 24 |
Sep 12 03:06:18 AM UTC 24 |
4902886790 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1476482001 |
|
|
Sep 12 02:59:36 AM UTC 24 |
Sep 12 03:06:23 AM UTC 24 |
4101619440 ps |
| T1302 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.2307496162 |
|
|
Sep 12 02:58:04 AM UTC 24 |
Sep 12 03:07:05 AM UTC 24 |
3884500790 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.520865886 |
|
|
Sep 12 02:55:43 AM UTC 24 |
Sep 12 03:07:41 AM UTC 24 |
5618806824 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.56529458 |
|
|
Sep 12 03:00:18 AM UTC 24 |
Sep 12 03:07:59 AM UTC 24 |
3373785416 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3585173679 |
|
|
Sep 12 03:01:50 AM UTC 24 |
Sep 12 03:08:18 AM UTC 24 |
4492998428 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.3553695702 |
|
|
Sep 12 02:57:19 AM UTC 24 |
Sep 12 03:08:48 AM UTC 24 |
5570163056 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_lc_ctrl_transition.1110401320 |
|
|
Sep 12 02:50:56 AM UTC 24 |
Sep 12 03:08:57 AM UTC 24 |
8616004895 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2390384900 |
|
|
Sep 12 03:00:51 AM UTC 24 |
Sep 12 03:08:57 AM UTC 24 |
3879779048 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2724548515 |
|
|
Sep 12 03:03:27 AM UTC 24 |
Sep 12 03:09:14 AM UTC 24 |
3188311490 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.3817801614 |
|
|
Sep 12 02:53:32 AM UTC 24 |
Sep 12 03:09:16 AM UTC 24 |
9865771571 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.1896237557 |
|
|
Sep 12 02:59:36 AM UTC 24 |
Sep 12 03:09:32 AM UTC 24 |
5485088332 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.2544295650 |
|
|
Sep 12 02:45:59 AM UTC 24 |
Sep 12 03:10:28 AM UTC 24 |
7798862300 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3443442800 |
|
|
Sep 12 03:04:52 AM UTC 24 |
Sep 12 03:10:34 AM UTC 24 |
3793268750 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.2440816116 |
|
|
Sep 12 02:58:45 AM UTC 24 |
Sep 12 03:10:47 AM UTC 24 |
6278085170 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.181988210 |
|
|
Sep 12 03:03:29 AM UTC 24 |
Sep 12 03:11:10 AM UTC 24 |
3090463140 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2946053170 |
|
|
Sep 12 02:16:24 AM UTC 24 |
Sep 12 03:12:10 AM UTC 24 |
11359683710 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.2293938442 |
|
|
Sep 12 03:00:17 AM UTC 24 |
Sep 12 03:12:11 AM UTC 24 |
6005786226 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.2976047165 |
|
|
Sep 12 02:44:00 AM UTC 24 |
Sep 12 03:12:24 AM UTC 24 |
8180301160 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2463402370 |
|
|
Sep 12 03:05:56 AM UTC 24 |
Sep 12 03:12:37 AM UTC 24 |
3733097500 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.1069337514 |
|
|
Sep 12 03:03:12 AM UTC 24 |
Sep 12 03:12:55 AM UTC 24 |
4889120146 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2113514899 |
|
|
Sep 12 03:07:13 AM UTC 24 |
Sep 12 03:14:05 AM UTC 24 |
3491149144 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.1320057176 |
|
|
Sep 12 03:05:20 AM UTC 24 |
Sep 12 03:14:18 AM UTC 24 |
6072987864 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.4041041649 |
|
|
Sep 12 03:08:40 AM UTC 24 |
Sep 12 03:14:35 AM UTC 24 |
3769885800 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2498666784 |
|
|
Sep 12 03:20:55 AM UTC 24 |
Sep 12 03:27:27 AM UTC 24 |
4190790504 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1845337622 |
|
|
Sep 12 03:07:44 AM UTC 24 |
Sep 12 03:14:46 AM UTC 24 |
3683643644 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.4164338258 |
|
|
Sep 12 03:01:49 AM UTC 24 |
Sep 12 03:15:05 AM UTC 24 |
6213148536 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.437025010 |
|
|
Sep 12 03:03:31 AM UTC 24 |
Sep 12 03:15:18 AM UTC 24 |
5496627882 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.3450093161 |
|
|
Sep 12 03:03:25 AM UTC 24 |
Sep 12 03:15:48 AM UTC 24 |
5284785520 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2425189958 |
|
|
Sep 12 03:10:28 AM UTC 24 |
Sep 12 03:17:04 AM UTC 24 |
3462736374 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.3251925478 |
|
|
Sep 12 03:08:23 AM UTC 24 |
Sep 12 03:17:06 AM UTC 24 |
5358407724 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3441832429 |
|
|
Sep 12 03:10:12 AM UTC 24 |
Sep 12 03:17:07 AM UTC 24 |
3754495304 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1397607545 |
|
|
Sep 12 03:10:38 AM UTC 24 |
Sep 12 03:17:32 AM UTC 24 |
3763083980 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.4161849105 |
|
|
Sep 12 03:11:29 AM UTC 24 |
Sep 12 03:17:40 AM UTC 24 |
3652043640 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.209345015 |
|
|
Sep 12 03:08:59 AM UTC 24 |
Sep 12 03:17:44 AM UTC 24 |
5152429020 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3497184241 |
|
|
Sep 12 03:11:23 AM UTC 24 |
Sep 12 03:18:46 AM UTC 24 |
3276202512 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.3904897670 |
|
|
Sep 12 03:05:57 AM UTC 24 |
Sep 12 03:19:20 AM UTC 24 |
5603886454 ps |
| T1303 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.3342670077 |
|
|
Sep 12 02:51:27 AM UTC 24 |
Sep 12 03:19:49 AM UTC 24 |
8937549388 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.1757210850 |
|
|
Sep 12 03:10:39 AM UTC 24 |
Sep 12 03:20:16 AM UTC 24 |
5244264820 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.3951731364 |
|
|
Sep 12 03:11:50 AM UTC 24 |
Sep 12 03:20:44 AM UTC 24 |
4625694424 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.324818015 |
|
|
Sep 12 03:15:00 AM UTC 24 |
Sep 12 03:20:53 AM UTC 24 |
3713848722 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.65088426 |
|
|
Sep 12 03:11:26 AM UTC 24 |
Sep 12 03:21:03 AM UTC 24 |
4716367624 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3896125447 |
|
|
Sep 12 03:14:05 AM UTC 24 |
Sep 12 03:21:06 AM UTC 24 |
3850417004 ps |
| T1304 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.3455044107 |
|
|
Sep 12 02:33:07 AM UTC 24 |
Sep 12 03:21:08 AM UTC 24 |
12719234066 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.2800423324 |
|
|
Sep 12 03:10:33 AM UTC 24 |
Sep 12 03:21:09 AM UTC 24 |
5741666582 ps |
| T1305 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1282189253 |
|
|
Sep 12 03:13:58 AM UTC 24 |
Sep 12 03:21:25 AM UTC 24 |
4265543316 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2556810458 |
|
|
Sep 12 03:14:14 AM UTC 24 |
Sep 12 03:21:30 AM UTC 24 |
3697133320 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2076164104 |
|
|
Sep 12 03:16:28 AM UTC 24 |
Sep 12 03:22:26 AM UTC 24 |
3855140548 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.123643283 |
|
|
Sep 12 03:10:38 AM UTC 24 |
Sep 12 03:22:45 AM UTC 24 |
6070635816 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2148136532 |
|
|
Sep 12 03:16:09 AM UTC 24 |
Sep 12 03:22:48 AM UTC 24 |
3987647280 ps |
| T1306 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.724009231 |
|
|
Sep 12 02:16:05 AM UTC 24 |
Sep 12 03:22:49 AM UTC 24 |
14576367240 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3452509024 |
|
|
Sep 12 03:16:08 AM UTC 24 |
Sep 12 03:22:50 AM UTC 24 |
4377745844 ps |
| T1307 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.854892796 |
|
|
Sep 12 02:34:45 AM UTC 24 |
Sep 12 03:22:57 AM UTC 24 |
12897588949 ps |
| T1308 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.1563509126 |
|
|
Sep 12 02:45:59 AM UTC 24 |
Sep 12 03:23:09 AM UTC 24 |
8821584154 ps |
| T1309 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_rma.2164344030 |
|
|
Sep 12 02:16:40 AM UTC 24 |
Sep 12 03:23:20 AM UTC 24 |
14849239439 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.620236670 |
|
|
Sep 12 03:14:07 AM UTC 24 |
Sep 12 03:23:37 AM UTC 24 |
4545855550 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.1544554598 |
|
|
Sep 12 03:14:05 AM UTC 24 |
Sep 12 03:23:43 AM UTC 24 |
5584403000 ps |
| T1310 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.2580563586 |
|
|
Sep 12 02:16:46 AM UTC 24 |
Sep 12 03:23:51 AM UTC 24 |
23580661944 ps |
| T1311 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.4209015478 |
|
|
Sep 12 03:00:11 AM UTC 24 |
Sep 12 03:23:58 AM UTC 24 |
7868786860 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.2906494844 |
|
|
Sep 12 03:14:44 AM UTC 24 |
Sep 12 03:23:58 AM UTC 24 |
4186202676 ps |
| T1312 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_dev.1387060925 |
|
|
Sep 12 02:16:40 AM UTC 24 |
Sep 12 03:24:00 AM UTC 24 |
15892274883 ps |
| T1313 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3639779430 |
|
|
Sep 12 02:08:30 AM UTC 24 |
Sep 12 03:24:01 AM UTC 24 |
25411820830 ps |
| T1314 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod.367676440 |
|
|
Sep 12 02:16:45 AM UTC 24 |
Sep 12 03:24:27 AM UTC 24 |
15966492581 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.894114000 |
|
|
Sep 12 03:18:52 AM UTC 24 |
Sep 12 03:24:45 AM UTC 24 |
3361017448 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3342575617 |
|
|
Sep 12 03:18:45 AM UTC 24 |
Sep 12 03:25:00 AM UTC 24 |
3835808884 ps |
| T1315 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3680285151 |
|
|
Sep 12 02:16:57 AM UTC 24 |
Sep 12 03:25:16 AM UTC 24 |
15127558820 ps |
| T1316 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.1295751810 |
|
|
Sep 12 02:15:50 AM UTC 24 |
Sep 12 03:25:22 AM UTC 24 |
15196565307 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.2546134937 |
|
|
Sep 12 03:14:11 AM UTC 24 |
Sep 12 03:25:33 AM UTC 24 |
6091417968 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.2874225320 |
|
|
Sep 12 03:16:12 AM UTC 24 |
Sep 12 03:25:43 AM UTC 24 |
5937844970 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.549313516 |
|
|
Sep 12 03:18:43 AM UTC 24 |
Sep 12 03:25:52 AM UTC 24 |
3902657934 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2584887074 |
|
|
Sep 12 03:20:01 AM UTC 24 |
Sep 12 03:26:00 AM UTC 24 |
3596094488 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.1067347306 |
|
|
Sep 12 03:16:05 AM UTC 24 |
Sep 12 03:26:01 AM UTC 24 |
4807634452 ps |
| T1317 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.3382750355 |
|
|
Sep 12 02:15:36 AM UTC 24 |
Sep 12 03:26:26 AM UTC 24 |
15214721544 ps |
| T1318 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.1187373837 |
|
|
Sep 12 03:18:51 AM UTC 24 |
Sep 12 03:26:32 AM UTC 24 |
4612068940 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.4137651289 |
|
|
Sep 12 03:18:51 AM UTC 24 |
Sep 12 03:26:36 AM UTC 24 |
5521075708 ps |
| T1319 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.2710413913 |
|
|
Sep 12 03:00:47 AM UTC 24 |
Sep 12 03:26:36 AM UTC 24 |
8485011070 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.1429375099 |
|
|
Sep 12 03:15:51 AM UTC 24 |
Sep 12 03:26:56 AM UTC 24 |
5970804764 ps |
| T1320 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2494962893 |
|
|
Sep 12 02:16:13 AM UTC 24 |
Sep 12 03:27:03 AM UTC 24 |
15712831432 ps |
| T1321 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod_end.2823669346 |
|
|
Sep 12 02:16:59 AM UTC 24 |
Sep 12 03:28:38 AM UTC 24 |
15412128472 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.3604610004 |
|
|
Sep 12 03:18:41 AM UTC 24 |
Sep 12 03:28:41 AM UTC 24 |
5016756384 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2650714623 |
|
|
Sep 12 03:24:45 AM UTC 24 |
Sep 12 03:29:37 AM UTC 24 |
4127642320 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2022085074 |
|
|
Sep 12 03:23:36 AM UTC 24 |
Sep 12 03:29:57 AM UTC 24 |
3542697470 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.1315700940 |
|
|
Sep 12 03:20:30 AM UTC 24 |
Sep 12 03:30:13 AM UTC 24 |
5483035928 ps |
| T1322 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2631788571 |
|
|
Sep 12 03:25:45 AM UTC 24 |
Sep 12 03:30:42 AM UTC 24 |
3581471320 ps |
| T1323 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.2922684436 |
|
|
Sep 12 02:16:52 AM UTC 24 |
Sep 12 03:31:01 AM UTC 24 |
16893384064 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.58813036 |
|
|
Sep 12 03:26:16 AM UTC 24 |
Sep 12 03:31:18 AM UTC 24 |
3951629570 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1459992247 |
|
|
Sep 12 03:25:29 AM UTC 24 |
Sep 12 03:31:54 AM UTC 24 |
4517254248 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1724585525 |
|
|
Sep 12 03:26:38 AM UTC 24 |
Sep 12 03:32:19 AM UTC 24 |
3450437288 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.2506892781 |
|
|
Sep 12 03:23:37 AM UTC 24 |
Sep 12 03:32:30 AM UTC 24 |
5559049286 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.867851366 |
|
|
Sep 12 03:22:11 AM UTC 24 |
Sep 12 03:32:32 AM UTC 24 |
5767200504 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1064859144 |
|
|
Sep 12 03:26:39 AM UTC 24 |
Sep 12 03:33:10 AM UTC 24 |
4316634848 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.613533457 |
|
|
Sep 12 03:22:15 AM UTC 24 |
Sep 12 03:33:20 AM UTC 24 |
6018780210 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.174730326 |
|
|
Sep 12 03:27:23 AM UTC 24 |
Sep 12 03:33:28 AM UTC 24 |
4011980428 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1804749865 |
|
|
Sep 12 03:26:49 AM UTC 24 |
Sep 12 03:33:30 AM UTC 24 |
3880663130 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1777683648 |
|
|
Sep 12 03:26:35 AM UTC 24 |
Sep 12 03:33:35 AM UTC 24 |
4488721306 ps |
| T1324 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3362754804 |
|
|
Sep 12 03:28:02 AM UTC 24 |
Sep 12 03:33:36 AM UTC 24 |
4278280544 ps |
| T1325 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1387227327 |
|
|
Sep 12 03:27:24 AM UTC 24 |
Sep 12 03:33:42 AM UTC 24 |
3112701060 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.924099141 |
|
|
Sep 12 03:26:33 AM UTC 24 |
Sep 12 03:33:43 AM UTC 24 |
4553137720 ps |
| T1326 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_all_escalation_resets.1450885623 |
|
|
Sep 12 03:26:03 AM UTC 24 |
Sep 12 03:33:50 AM UTC 24 |
5414136160 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3463234152 |
|
|
Sep 12 03:28:31 AM UTC 24 |
Sep 12 03:34:18 AM UTC 24 |
3811153336 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_all_escalation_resets.2181948879 |
|
|
Sep 12 03:24:03 AM UTC 24 |
Sep 12 03:34:26 AM UTC 24 |
5034200900 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2832204319 |
|
|
Sep 12 03:28:29 AM UTC 24 |
Sep 12 03:34:39 AM UTC 24 |
3911760134 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3021666114 |
|
|
Sep 12 03:27:31 AM UTC 24 |
Sep 12 03:34:39 AM UTC 24 |
4600357984 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.822187573 |
|
|
Sep 12 03:25:14 AM UTC 24 |
Sep 12 03:34:54 AM UTC 24 |
4838469370 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2229733888 |
|
|
Sep 12 03:28:50 AM UTC 24 |
Sep 12 03:34:55 AM UTC 24 |
4485408400 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1828864339 |
|
|
Sep 12 03:28:56 AM UTC 24 |
Sep 12 03:34:56 AM UTC 24 |
3754174318 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1158649453 |
|
|
Sep 12 03:28:55 AM UTC 24 |
Sep 12 03:35:19 AM UTC 24 |
3822479728 ps |
| T1327 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.1226945824 |
|
|
Sep 12 03:25:54 AM UTC 24 |
Sep 12 03:35:44 AM UTC 24 |
6077971652 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1411548910 |
|
|
Sep 12 03:30:17 AM UTC 24 |
Sep 12 03:35:54 AM UTC 24 |
3948780632 ps |
| T1328 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1428367301 |
|
|
Sep 12 03:28:48 AM UTC 24 |
Sep 12 03:35:56 AM UTC 24 |
4098397440 ps |
| T1329 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3239296769 |
|
|
Sep 12 03:29:32 AM UTC 24 |
Sep 12 03:36:00 AM UTC 24 |
3636443916 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_all_escalation_resets.2855525424 |
|
|
Sep 12 03:26:34 AM UTC 24 |
Sep 12 03:36:05 AM UTC 24 |
5231060696 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.1134068589 |
|
|
Sep 12 03:26:38 AM UTC 24 |
Sep 12 03:36:07 AM UTC 24 |
5002753636 ps |
| T1330 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.688661727 |
|
|
Sep 12 02:56:22 AM UTC 24 |
Sep 12 03:36:26 AM UTC 24 |
13447996372 ps |
| T1331 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2120627861 |
|
|
Sep 12 03:30:54 AM UTC 24 |
Sep 12 03:36:28 AM UTC 24 |
3858271428 ps |
| T1332 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_all_escalation_resets.3199843398 |
|
|
Sep 12 03:28:32 AM UTC 24 |
Sep 12 03:37:04 AM UTC 24 |
5567200592 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.1012464093 |
|
|
Sep 12 03:28:56 AM UTC 24 |
Sep 12 03:37:13 AM UTC 24 |
4794749842 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.3360396024 |
|
|
Sep 12 03:28:31 AM UTC 24 |
Sep 12 03:37:22 AM UTC 24 |
6140113320 ps |
| T1333 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.461550592 |
|
|
Sep 12 03:27:53 AM UTC 24 |
Sep 12 03:37:23 AM UTC 24 |
5943426200 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.4034021463 |
|
|
Sep 12 03:28:28 AM UTC 24 |
Sep 12 03:37:27 AM UTC 24 |
5634524462 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_all_escalation_resets.1323118985 |
|
|
Sep 12 03:28:25 AM UTC 24 |
Sep 12 03:37:31 AM UTC 24 |
5805291400 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.2132244047 |
|
|
Sep 12 03:27:53 AM UTC 24 |
Sep 12 03:37:42 AM UTC 24 |
4902398840 ps |
| T1334 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.63234335 |
|
|
Sep 12 03:31:42 AM UTC 24 |
Sep 12 03:37:43 AM UTC 24 |
3635530268 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.949081559 |
|
|
Sep 12 03:33:25 AM UTC 24 |
Sep 12 03:37:54 AM UTC 24 |
3951455000 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.551114867 |
|
|
Sep 12 03:30:39 AM UTC 24 |
Sep 12 03:38:12 AM UTC 24 |
5354248052 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.1066043934 |
|
|
Sep 12 03:27:28 AM UTC 24 |
Sep 12 03:38:23 AM UTC 24 |
6727287220 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.564239181 |
|
|
Sep 12 03:29:32 AM UTC 24 |
Sep 12 03:38:43 AM UTC 24 |
5532436260 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.499977552 |
|
|
Sep 12 03:28:03 AM UTC 24 |
Sep 12 03:38:45 AM UTC 24 |
4848090752 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.696970500 |
|
|
Sep 12 03:28:34 AM UTC 24 |
Sep 12 03:39:29 AM UTC 24 |
5572352160 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.2231535211 |
|
|
Sep 12 03:28:30 AM UTC 24 |
Sep 12 03:39:38 AM UTC 24 |
5762613362 ps |
| T1335 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.340330979 |
|
|
Sep 12 02:59:07 AM UTC 24 |
Sep 12 03:40:01 AM UTC 24 |
13488796004 ps |
| T1336 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.2180453922 |
|
|
Sep 12 03:35:15 AM UTC 24 |
Sep 12 03:43:35 AM UTC 24 |
4361396288 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.2864240685 |
|
|
Sep 12 03:31:57 AM UTC 24 |
Sep 12 03:40:02 AM UTC 24 |
6065176200 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3709908907 |
|
|
Sep 12 03:33:40 AM UTC 24 |
Sep 12 03:40:15 AM UTC 24 |
4304910762 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.757944644 |
|
|
Sep 12 03:36:05 AM UTC 24 |
Sep 12 03:40:22 AM UTC 24 |
3845861800 ps |
| T1337 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.1865572162 |
|
|
Sep 12 03:31:21 AM UTC 24 |
Sep 12 03:40:27 AM UTC 24 |
5827610336 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1917038933 |
|
|
Sep 12 03:35:42 AM UTC 24 |
Sep 12 03:40:44 AM UTC 24 |
3953883346 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1442685929 |
|
|
Sep 12 03:36:00 AM UTC 24 |
Sep 12 03:41:58 AM UTC 24 |
3278820294 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3134731642 |
|
|
Sep 12 03:36:57 AM UTC 24 |
Sep 12 03:42:06 AM UTC 24 |
3429113278 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.205062192 |
|
|
Sep 12 03:33:51 AM UTC 24 |
Sep 12 03:42:28 AM UTC 24 |
5096470984 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.4287733099 |
|
|
Sep 12 03:38:23 AM UTC 24 |
Sep 12 03:42:59 AM UTC 24 |
3431783304 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1001176231 |
|
|
Sep 12 03:38:24 AM UTC 24 |
Sep 12 03:44:02 AM UTC 24 |
3415863062 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2436606647 |
|
|
Sep 12 03:38:11 AM UTC 24 |
Sep 12 03:44:05 AM UTC 24 |
4153200848 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2978146861 |
|
|
Sep 12 03:37:40 AM UTC 24 |
Sep 12 03:44:10 AM UTC 24 |
3398305080 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1150481 |
|
|
Sep 12 03:39:24 AM UTC 24 |
Sep 12 03:44:15 AM UTC 24 |
3590275040 ps |
| T1338 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1324610842 |
|
|
Sep 12 03:39:04 AM UTC 24 |
Sep 12 03:44:28 AM UTC 24 |
4200585960 ps |
| T1339 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.442574447 |
|
|
Sep 12 03:38:19 AM UTC 24 |
Sep 12 03:44:36 AM UTC 24 |
3818605252 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.4277443543 |
|
|
Sep 12 03:36:11 AM UTC 24 |
Sep 12 03:44:45 AM UTC 24 |
4409021296 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2056138095 |
|
|
Sep 12 03:39:52 AM UTC 24 |
Sep 12 03:45:01 AM UTC 24 |
3571474746 ps |
| T1340 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.4056571210 |
|
|
Sep 12 03:36:56 AM UTC 24 |
Sep 12 03:45:08 AM UTC 24 |
4319310528 ps |
| T1341 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.3740384881 |
|
|
Sep 12 03:35:49 AM UTC 24 |
Sep 12 03:45:11 AM UTC 24 |
5828046920 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2956946983 |
|
|
Sep 12 03:40:12 AM UTC 24 |
Sep 12 03:45:15 AM UTC 24 |
3415686384 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2960909329 |
|
|
Sep 12 03:39:37 AM UTC 24 |
Sep 12 03:45:20 AM UTC 24 |
3909953186 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.749163437 |
|
|
Sep 12 03:39:56 AM UTC 24 |
Sep 12 03:45:52 AM UTC 24 |
4170303292 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.186622483 |
|
|
Sep 12 03:37:13 AM UTC 24 |
Sep 12 03:45:55 AM UTC 24 |
3830371456 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2086450887 |
|
|
Sep 12 03:40:14 AM UTC 24 |
Sep 12 03:46:02 AM UTC 24 |
3576988720 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.4186098537 |
|
|
Sep 12 03:37:14 AM UTC 24 |
Sep 12 03:46:05 AM UTC 24 |
6283003552 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.2546116765 |
|
|
Sep 12 03:39:05 AM UTC 24 |
Sep 12 03:46:16 AM UTC 24 |
5895921128 ps |
| T1342 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.2714064408 |
|
|
Sep 12 03:39:15 AM UTC 24 |
Sep 12 03:46:35 AM UTC 24 |
5425270370 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.3364973580 |
|
|
Sep 12 03:40:11 AM UTC 24 |
Sep 12 03:46:39 AM UTC 24 |
5561860600 ps |
| T1343 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3882395173 |
|
|
Sep 12 03:40:12 AM UTC 24 |
Sep 12 03:46:43 AM UTC 24 |
4441957728 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.2609237184 |
|
|
Sep 12 03:39:05 AM UTC 24 |
Sep 12 03:47:13 AM UTC 24 |
4931226160 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.75766496 |
|
|
Sep 12 03:38:04 AM UTC 24 |
Sep 12 03:47:29 AM UTC 24 |
5231746074 ps |
| T1344 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.1632906486 |
|
|
Sep 12 03:39:53 AM UTC 24 |
Sep 12 03:47:32 AM UTC 24 |
5125473164 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.123915410 |
|
|
Sep 12 03:39:06 AM UTC 24 |
Sep 12 03:47:34 AM UTC 24 |
4661930460 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.211206799 |
|
|
Sep 12 03:40:24 AM UTC 24 |
Sep 12 03:47:34 AM UTC 24 |
4725675250 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.3958460935 |
|
|
Sep 12 03:39:24 AM UTC 24 |
Sep 12 03:47:39 AM UTC 24 |
5095751464 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.364392411 |
|
|
Sep 12 03:40:37 AM UTC 24 |
Sep 12 03:48:00 AM UTC 24 |
5093807376 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.1148484424 |
|
|
Sep 12 03:40:42 AM UTC 24 |
Sep 12 03:48:02 AM UTC 24 |
4361843432 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/91.chip_sw_all_escalation_resets.2295212782 |
|
|
Sep 12 03:39:50 AM UTC 24 |
Sep 12 03:48:02 AM UTC 24 |
5308085686 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_all_escalation_resets.1706515565 |
|
|
Sep 12 03:37:49 AM UTC 24 |
Sep 12 03:48:33 AM UTC 24 |
5650105802 ps |
| T1345 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.1275635951 |
|
|
Sep 12 03:39:36 AM UTC 24 |
Sep 12 03:48:41 AM UTC 24 |
5249819554 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.1988299052 |
|
|
Sep 12 03:40:20 AM UTC 24 |
Sep 12 03:48:44 AM UTC 24 |
4517452648 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_all_escalation_resets.1605286447 |
|
|
Sep 12 03:40:13 AM UTC 24 |
Sep 12 03:48:54 AM UTC 24 |
5909606154 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.1985365153 |
|
|
Sep 12 03:40:15 AM UTC 24 |
Sep 12 03:49:23 AM UTC 24 |
4756345892 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.1517269493 |
|
|
Sep 12 03:40:38 AM UTC 24 |
Sep 12 03:49:39 AM UTC 24 |
5082275420 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.3528761272 |
|
|
Sep 12 03:39:55 AM UTC 24 |
Sep 12 03:50:03 AM UTC 24 |
5697169592 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.1481166617 |
|
|
Sep 12 03:40:42 AM UTC 24 |
Sep 12 03:50:10 AM UTC 24 |
5168583042 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_inject_scramble_seed.2503349334 |
|
|
Sep 11 11:33:50 PM UTC 24 |
Sep 12 03:55:36 AM UTC 24 |
66006950979 ps |
| T1346 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.50041197 |
|
|
Sep 12 02:39:01 AM UTC 24 |
Sep 12 03:59:10 AM UTC 24 |
21528380622 ps |
| T1347 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.2024323530 |
|
|
Sep 12 02:42:56 AM UTC 24 |
Sep 12 04:04:17 AM UTC 24 |
20913865406 ps |
| T1348 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.764482133 |
|
|
Sep 12 02:16:59 AM UTC 24 |
Sep 12 04:07:52 AM UTC 24 |
26163861640 ps |
| T1349 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.852732259 |
|
|
Sep 12 02:41:57 AM UTC 24 |
Sep 12 04:08:28 AM UTC 24 |
22739290716 ps |
| T1350 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.4189603318 |
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|
Sep 12 02:35:09 AM UTC 24 |
Sep 12 04:09:38 AM UTC 24 |
22915567436 ps |
| T1351 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.781183861 |
|
|
Sep 12 02:27:42 AM UTC 24 |
Sep 12 04:16:51 AM UTC 24 |
26999771022 ps |
| T1352 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1220956524 |
|
|
Sep 11 11:32:14 PM UTC 24 |
Sep 12 04:18:16 AM UTC 24 |
80516916265 ps |
| T1353 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.346217980 |
|
|
Sep 12 02:47:43 AM UTC 24 |
Sep 12 04:21:39 AM UTC 24 |
26504700874 ps |