| T534 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.3731904201 |
|
|
Sep 11 07:40:18 PM UTC 24 |
Sep 11 07:51:51 PM UTC 24 |
46174491147 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.822952080 |
|
|
Sep 11 07:51:33 PM UTC 24 |
Sep 11 07:52:12 PM UTC 24 |
616408963 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.1244388922 |
|
|
Sep 11 07:50:34 PM UTC 24 |
Sep 11 07:52:13 PM UTC 24 |
5167885810 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.4080164680 |
|
|
Sep 11 07:52:09 PM UTC 24 |
Sep 11 07:52:21 PM UTC 24 |
204817298 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.4274859209 |
|
|
Sep 11 07:52:11 PM UTC 24 |
Sep 11 07:52:21 PM UTC 24 |
47602599 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.1799548606 |
|
|
Sep 11 07:50:57 PM UTC 24 |
Sep 11 07:52:31 PM UTC 24 |
1139281795 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.861444782 |
|
|
Sep 11 07:51:15 PM UTC 24 |
Sep 11 07:52:33 PM UTC 24 |
2193223102 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.984075726 |
|
|
Sep 11 07:43:12 PM UTC 24 |
Sep 11 07:52:50 PM UTC 24 |
44108535982 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.793246846 |
|
|
Sep 11 07:52:39 PM UTC 24 |
Sep 11 07:52:57 PM UTC 24 |
116990789 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.2612767535 |
|
|
Sep 11 07:06:09 PM UTC 24 |
Sep 11 07:53:04 PM UTC 24 |
146339154382 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.2144833252 |
|
|
Sep 11 07:32:13 PM UTC 24 |
Sep 11 07:53:10 PM UTC 24 |
93998513838 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.3394543980 |
|
|
Sep 11 07:22:23 PM UTC 24 |
Sep 11 07:53:11 PM UTC 24 |
17339624539 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.3335718082 |
|
|
Sep 11 07:52:13 PM UTC 24 |
Sep 11 07:53:23 PM UTC 24 |
5551366490 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.3078226228 |
|
|
Sep 11 07:52:36 PM UTC 24 |
Sep 11 07:53:25 PM UTC 24 |
1219569341 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.1577144584 |
|
|
Sep 11 07:52:17 PM UTC 24 |
Sep 11 07:53:32 PM UTC 24 |
3576390184 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.219149260 |
|
|
Sep 11 07:53:16 PM UTC 24 |
Sep 11 07:53:33 PM UTC 24 |
148951651 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.2236123808 |
|
|
Sep 11 07:44:35 PM UTC 24 |
Sep 11 07:53:47 PM UTC 24 |
13022693984 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.3468163825 |
|
|
Sep 11 07:45:46 PM UTC 24 |
Sep 11 07:53:48 PM UTC 24 |
3233503734 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.1767572298 |
|
|
Sep 11 07:51:51 PM UTC 24 |
Sep 11 07:53:51 PM UTC 24 |
1093510917 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.2325342024 |
|
|
Sep 11 07:51:55 PM UTC 24 |
Sep 11 07:53:53 PM UTC 24 |
2453896774 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.2544408329 |
|
|
Sep 11 07:40:10 PM UTC 24 |
Sep 11 07:53:54 PM UTC 24 |
81045068887 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.3571507728 |
|
|
Sep 11 07:53:34 PM UTC 24 |
Sep 11 07:53:55 PM UTC 24 |
276764529 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.4053776850 |
|
|
Sep 11 07:53:48 PM UTC 24 |
Sep 11 07:54:02 PM UTC 24 |
27968847 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.2075873065 |
|
|
Sep 11 07:53:23 PM UTC 24 |
Sep 11 07:54:10 PM UTC 24 |
942011009 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.1257237238 |
|
|
Sep 11 07:54:12 PM UTC 24 |
Sep 11 07:54:22 PM UTC 24 |
47332775 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.3658610803 |
|
|
Sep 11 07:54:10 PM UTC 24 |
Sep 11 07:54:23 PM UTC 24 |
187041270 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.3707767684 |
|
|
Sep 11 07:49:38 PM UTC 24 |
Sep 11 07:54:28 PM UTC 24 |
8699654673 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.3643546464 |
|
|
Sep 11 07:53:30 PM UTC 24 |
Sep 11 07:54:36 PM UTC 24 |
1111065856 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.662900544 |
|
|
Sep 11 07:54:20 PM UTC 24 |
Sep 11 07:54:44 PM UTC 24 |
295661395 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.397792308 |
|
|
Sep 11 07:50:37 PM UTC 24 |
Sep 11 07:54:45 PM UTC 24 |
21967724079 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.29729536 |
|
|
Sep 11 07:52:57 PM UTC 24 |
Sep 11 07:54:50 PM UTC 24 |
1325664646 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.3589631911 |
|
|
Sep 11 07:49:59 PM UTC 24 |
Sep 11 07:55:01 PM UTC 24 |
3894941904 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.508662662 |
|
|
Sep 11 07:54:19 PM UTC 24 |
Sep 11 07:55:07 PM UTC 24 |
1290121555 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.2232867637 |
|
|
Sep 11 07:55:09 PM UTC 24 |
Sep 11 07:55:37 PM UTC 24 |
199610394 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.2221019418 |
|
|
Sep 11 07:54:53 PM UTC 24 |
Sep 11 07:55:41 PM UTC 24 |
1872869385 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.1263797753 |
|
|
Sep 11 07:55:02 PM UTC 24 |
Sep 11 07:55:42 PM UTC 24 |
350939203 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.1694029210 |
|
|
Sep 11 07:46:47 PM UTC 24 |
Sep 11 07:55:45 PM UTC 24 |
36268919966 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.688229691 |
|
|
Sep 11 07:54:15 PM UTC 24 |
Sep 11 07:56:03 PM UTC 24 |
6469716150 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.1030504448 |
|
|
Sep 11 07:53:50 PM UTC 24 |
Sep 11 07:56:03 PM UTC 24 |
1851350279 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.3059270500 |
|
|
Sep 11 07:55:10 PM UTC 24 |
Sep 11 07:56:05 PM UTC 24 |
1420270077 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.1759618932 |
|
|
Sep 11 07:51:36 PM UTC 24 |
Sep 11 07:56:09 PM UTC 24 |
6268016472 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.2563823900 |
|
|
Sep 11 07:54:18 PM UTC 24 |
Sep 11 07:56:10 PM UTC 24 |
5153703490 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.3501211951 |
|
|
Sep 11 07:56:06 PM UTC 24 |
Sep 11 07:56:16 PM UTC 24 |
41553152 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.1066057485 |
|
|
Sep 11 07:54:46 PM UTC 24 |
Sep 11 07:56:17 PM UTC 24 |
859728537 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.1534910784 |
|
|
Sep 11 07:56:07 PM UTC 24 |
Sep 11 07:56:18 PM UTC 24 |
49274677 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.680139011 |
|
|
Sep 11 07:49:33 PM UTC 24 |
Sep 11 07:56:31 PM UTC 24 |
5877342568 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.825173560 |
|
|
Sep 11 07:46:01 PM UTC 24 |
Sep 11 07:56:33 PM UTC 24 |
11603637277 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.3280983696 |
|
|
Sep 11 07:53:57 PM UTC 24 |
Sep 11 07:56:39 PM UTC 24 |
3604326381 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.2746524025 |
|
|
Sep 11 07:56:34 PM UTC 24 |
Sep 11 07:56:43 PM UTC 24 |
43493184 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.3065190022 |
|
|
Sep 11 07:55:24 PM UTC 24 |
Sep 11 07:56:48 PM UTC 24 |
185907061 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.3621617845 |
|
|
Sep 11 06:55:43 PM UTC 24 |
Sep 11 07:56:54 PM UTC 24 |
27905094891 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.1070853571 |
|
|
Sep 11 07:56:30 PM UTC 24 |
Sep 11 07:56:55 PM UTC 24 |
230370423 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.3090453553 |
|
|
Sep 11 07:56:58 PM UTC 24 |
Sep 11 07:57:10 PM UTC 24 |
133678655 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.3880184880 |
|
|
Sep 11 07:40:42 PM UTC 24 |
Sep 11 07:57:12 PM UTC 24 |
58688500797 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.3347976231 |
|
|
Sep 11 07:54:35 PM UTC 24 |
Sep 11 07:57:16 PM UTC 24 |
12033112284 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.3356476764 |
|
|
Sep 11 07:56:57 PM UTC 24 |
Sep 11 07:57:23 PM UTC 24 |
224846583 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.1736114394 |
|
|
Sep 11 07:56:24 PM UTC 24 |
Sep 11 07:57:30 PM UTC 24 |
6608027112 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.609791 |
|
|
Sep 11 07:57:08 PM UTC 24 |
Sep 11 07:57:33 PM UTC 24 |
148808195 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.1460339161 |
|
|
Sep 11 07:57:12 PM UTC 24 |
Sep 11 07:57:42 PM UTC 24 |
732100972 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.1793580553 |
|
|
Sep 11 07:57:04 PM UTC 24 |
Sep 11 07:57:47 PM UTC 24 |
790679904 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.1658472269 |
|
|
Sep 11 07:57:41 PM UTC 24 |
Sep 11 07:57:51 PM UTC 24 |
51298432 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.2164861213 |
|
|
Sep 11 07:57:47 PM UTC 24 |
Sep 11 07:57:57 PM UTC 24 |
38401670 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.3466607632 |
|
|
Sep 11 07:56:42 PM UTC 24 |
Sep 11 07:58:04 PM UTC 24 |
2255031270 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.1078253733 |
|
|
Sep 11 07:55:15 PM UTC 24 |
Sep 11 07:58:11 PM UTC 24 |
4573551757 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.2183644932 |
|
|
Sep 11 07:46:29 PM UTC 24 |
Sep 11 07:58:14 PM UTC 24 |
68048914937 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.517794456 |
|
|
Sep 11 07:56:25 PM UTC 24 |
Sep 11 07:58:16 PM UTC 24 |
5389095949 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.3442067361 |
|
|
Sep 11 07:49:27 PM UTC 24 |
Sep 11 07:58:18 PM UTC 24 |
13815521898 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.671013251 |
|
|
Sep 11 07:45:05 PM UTC 24 |
Sep 11 07:58:34 PM UTC 24 |
73109454000 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.1672371871 |
|
|
Sep 11 07:55:31 PM UTC 24 |
Sep 11 07:58:34 PM UTC 24 |
2142799256 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.329767033 |
|
|
Sep 11 07:51:41 PM UTC 24 |
Sep 11 07:58:44 PM UTC 24 |
3093306486 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.3239687638 |
|
|
Sep 11 07:58:12 PM UTC 24 |
Sep 11 07:58:52 PM UTC 24 |
416440819 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1050503855 |
|
|
Sep 11 07:24:12 PM UTC 24 |
Sep 11 07:58:55 PM UTC 24 |
148539197177 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.4140981124 |
|
|
Sep 11 07:58:25 PM UTC 24 |
Sep 11 07:59:04 PM UTC 24 |
278852941 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.3341010205 |
|
|
Sep 11 07:58:59 PM UTC 24 |
Sep 11 07:59:10 PM UTC 24 |
45285522 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.671484771 |
|
|
Sep 11 07:58:39 PM UTC 24 |
Sep 11 07:59:17 PM UTC 24 |
877251977 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.1610725832 |
|
|
Sep 11 07:58:07 PM UTC 24 |
Sep 11 07:59:18 PM UTC 24 |
584995260 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.1568704982 |
|
|
Sep 11 07:56:41 PM UTC 24 |
Sep 11 07:59:23 PM UTC 24 |
8297316155 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.3777627258 |
|
|
Sep 11 07:57:58 PM UTC 24 |
Sep 11 07:59:29 PM UTC 24 |
5733816014 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.3588144669 |
|
|
Sep 11 07:57:19 PM UTC 24 |
Sep 11 07:59:31 PM UTC 24 |
4700427229 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.1594037508 |
|
|
Sep 11 07:58:40 PM UTC 24 |
Sep 11 07:59:43 PM UTC 24 |
1393861469 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.2879441693 |
|
|
Sep 11 07:59:33 PM UTC 24 |
Sep 11 07:59:48 PM UTC 24 |
236409970 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.1532687227 |
|
|
Sep 11 07:57:55 PM UTC 24 |
Sep 11 07:59:50 PM UTC 24 |
8900368621 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.4058105574 |
|
|
Sep 11 07:58:43 PM UTC 24 |
Sep 11 07:59:50 PM UTC 24 |
1458338032 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.791933085 |
|
|
Sep 11 07:59:42 PM UTC 24 |
Sep 11 07:59:52 PM UTC 24 |
45097476 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.2565785525 |
|
|
Sep 11 07:02:08 PM UTC 24 |
Sep 11 07:59:54 PM UTC 24 |
31190223269 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.288063434 |
|
|
Sep 11 07:56:07 PM UTC 24 |
Sep 11 08:00:07 PM UTC 24 |
3852042205 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.4272835279 |
|
|
Sep 11 07:58:17 PM UTC 24 |
Sep 11 08:00:08 PM UTC 24 |
11723379035 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.1531125764 |
|
|
Sep 11 07:42:57 PM UTC 24 |
Sep 11 08:00:17 PM UTC 24 |
106532002205 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.166892635 |
|
|
Sep 11 07:59:52 PM UTC 24 |
Sep 11 08:00:20 PM UTC 24 |
297512375 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.1632727928 |
|
|
Sep 11 06:54:45 PM UTC 24 |
Sep 11 08:00:23 PM UTC 24 |
30800167303 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.4130073442 |
|
|
Sep 11 07:59:19 PM UTC 24 |
Sep 11 08:00:26 PM UTC 24 |
277669128 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.1079788462 |
|
|
Sep 11 07:48:30 PM UTC 24 |
Sep 11 08:00:27 PM UTC 24 |
47916478196 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.1936225088 |
|
|
Sep 11 07:59:54 PM UTC 24 |
Sep 11 08:00:33 PM UTC 24 |
315049723 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.4074856512 |
|
|
Sep 11 07:49:59 PM UTC 24 |
Sep 11 08:00:34 PM UTC 24 |
13628301230 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.1339639686 |
|
|
Sep 11 08:00:20 PM UTC 24 |
Sep 11 08:00:35 PM UTC 24 |
233011739 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.3390782394 |
|
|
Sep 11 07:57:35 PM UTC 24 |
Sep 11 08:00:45 PM UTC 24 |
2194636614 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.3670580030 |
|
|
Sep 11 08:00:29 PM UTC 24 |
Sep 11 08:00:46 PM UTC 24 |
258396051 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.2186274754 |
|
|
Sep 11 08:00:33 PM UTC 24 |
Sep 11 08:00:54 PM UTC 24 |
104267163 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.3097425577 |
|
|
Sep 11 08:00:51 PM UTC 24 |
Sep 11 08:01:02 PM UTC 24 |
46861443 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2061107048 |
|
|
Sep 11 08:00:54 PM UTC 24 |
Sep 11 08:01:02 PM UTC 24 |
38337078 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.1898112547 |
|
|
Sep 11 08:00:17 PM UTC 24 |
Sep 11 08:01:05 PM UTC 24 |
1171868010 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.1286616350 |
|
|
Sep 11 07:59:42 PM UTC 24 |
Sep 11 08:01:06 PM UTC 24 |
8122701189 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.3157546325 |
|
|
Sep 11 07:59:00 PM UTC 24 |
Sep 11 08:01:08 PM UTC 24 |
1273893423 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.3809065740 |
|
|
Sep 11 07:57:37 PM UTC 24 |
Sep 11 08:01:09 PM UTC 24 |
3428943484 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.1648459230 |
|
|
Sep 11 08:00:15 PM UTC 24 |
Sep 11 08:01:21 PM UTC 24 |
910604672 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.2686546602 |
|
|
Sep 11 08:01:11 PM UTC 24 |
Sep 11 08:01:36 PM UTC 24 |
267079913 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.1788385224 |
|
|
Sep 11 07:59:48 PM UTC 24 |
Sep 11 08:01:50 PM UTC 24 |
6495598186 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.762738345 |
|
|
Sep 11 08:01:32 PM UTC 24 |
Sep 11 08:01:51 PM UTC 24 |
340076622 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.324043084 |
|
|
Sep 11 07:59:08 PM UTC 24 |
Sep 11 08:01:52 PM UTC 24 |
464701647 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.495328450 |
|
|
Sep 11 08:00:56 PM UTC 24 |
Sep 11 08:02:06 PM UTC 24 |
4562460180 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.2877156621 |
|
|
Sep 11 06:54:42 PM UTC 24 |
Sep 11 08:02:10 PM UTC 24 |
41783077648 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.497487223 |
|
|
Sep 11 08:01:47 PM UTC 24 |
Sep 11 08:02:22 PM UTC 24 |
967510322 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.2795791856 |
|
|
Sep 11 08:00:47 PM UTC 24 |
Sep 11 08:02:22 PM UTC 24 |
2900866953 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.1093501555 |
|
|
Sep 11 08:01:35 PM UTC 24 |
Sep 11 08:02:23 PM UTC 24 |
1050264444 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.2197538310 |
|
|
Sep 11 08:01:33 PM UTC 24 |
Sep 11 08:02:36 PM UTC 24 |
651237310 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.1414316610 |
|
|
Sep 11 08:00:57 PM UTC 24 |
Sep 11 08:02:37 PM UTC 24 |
8994428731 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.1605302936 |
|
|
Sep 11 08:02:31 PM UTC 24 |
Sep 11 08:02:38 PM UTC 24 |
45290965 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.3332378864 |
|
|
Sep 11 08:02:35 PM UTC 24 |
Sep 11 08:02:46 PM UTC 24 |
48854379 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.684277138 |
|
|
Sep 11 07:59:17 PM UTC 24 |
Sep 11 08:02:49 PM UTC 24 |
5489328587 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.92868450 |
|
|
Sep 11 06:54:11 PM UTC 24 |
Sep 11 08:02:51 PM UTC 24 |
28473697924 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.4083088560 |
|
|
Sep 11 08:01:07 PM UTC 24 |
Sep 11 08:03:02 PM UTC 24 |
2402658085 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.3610172345 |
|
|
Sep 11 07:56:34 PM UTC 24 |
Sep 11 08:03:15 PM UTC 24 |
44172972195 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.746167125 |
|
|
Sep 11 08:03:00 PM UTC 24 |
Sep 11 08:03:24 PM UTC 24 |
235125813 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.1949627262 |
|
|
Sep 11 08:02:18 PM UTC 24 |
Sep 11 08:03:25 PM UTC 24 |
1047021600 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.103647780 |
|
|
Sep 11 08:01:27 PM UTC 24 |
Sep 11 08:03:35 PM UTC 24 |
3030741345 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.1236624523 |
|
|
Sep 11 07:58:34 PM UTC 24 |
Sep 11 08:03:48 PM UTC 24 |
15053217201 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.798479593 |
|
|
Sep 11 08:00:08 PM UTC 24 |
Sep 11 08:03:51 PM UTC 24 |
22444413936 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.1358056077 |
|
|
Sep 11 08:03:12 PM UTC 24 |
Sep 11 08:03:51 PM UTC 24 |
880639836 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.3587662879 |
|
|
Sep 11 08:03:07 PM UTC 24 |
Sep 11 08:03:57 PM UTC 24 |
1210434374 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.495397282 |
|
|
Sep 11 08:02:47 PM UTC 24 |
Sep 11 08:04:00 PM UTC 24 |
7149034740 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.3543466162 |
|
|
Sep 11 08:02:49 PM UTC 24 |
Sep 11 08:04:04 PM UTC 24 |
1685028146 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.390576722 |
|
|
Sep 11 08:03:48 PM UTC 24 |
Sep 11 08:04:08 PM UTC 24 |
451991838 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.1451695808 |
|
|
Sep 11 08:02:17 PM UTC 24 |
Sep 11 08:04:10 PM UTC 24 |
418152812 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.2808023001 |
|
|
Sep 11 08:02:47 PM UTC 24 |
Sep 11 08:04:22 PM UTC 24 |
6601349514 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.1238795103 |
|
|
Sep 11 08:03:27 PM UTC 24 |
Sep 11 08:04:25 PM UTC 24 |
1488568416 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.2641963698 |
|
|
Sep 11 08:04:16 PM UTC 24 |
Sep 11 08:04:28 PM UTC 24 |
208015947 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.4044148889 |
|
|
Sep 11 07:53:58 PM UTC 24 |
Sep 11 08:04:29 PM UTC 24 |
5754261916 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.1664381731 |
|
|
Sep 11 08:04:20 PM UTC 24 |
Sep 11 08:04:30 PM UTC 24 |
50912415 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.778833649 |
|
|
Sep 11 08:03:41 PM UTC 24 |
Sep 11 08:04:33 PM UTC 24 |
917284571 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.741671745 |
|
|
Sep 11 07:53:36 PM UTC 24 |
Sep 11 08:04:37 PM UTC 24 |
17511548515 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.415321307 |
|
|
Sep 11 07:50:50 PM UTC 24 |
Sep 11 08:04:43 PM UTC 24 |
45247928962 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.2420652382 |
|
|
Sep 11 08:04:34 PM UTC 24 |
Sep 11 08:04:44 PM UTC 24 |
38808907 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.3038889153 |
|
|
Sep 11 07:52:48 PM UTC 24 |
Sep 11 08:04:49 PM UTC 24 |
43798315043 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.2704330980 |
|
|
Sep 11 07:54:22 PM UTC 24 |
Sep 11 08:05:00 PM UTC 24 |
61207302543 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.1742288643 |
|
|
Sep 11 08:04:31 PM UTC 24 |
Sep 11 08:05:02 PM UTC 24 |
825429587 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.4223791572 |
|
|
Sep 11 07:07:50 PM UTC 24 |
Sep 11 08:05:37 PM UTC 24 |
33337521910 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.2023994611 |
|
|
Sep 11 07:59:29 PM UTC 24 |
Sep 11 08:05:46 PM UTC 24 |
4443679640 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.2988590129 |
|
|
Sep 11 08:05:00 PM UTC 24 |
Sep 11 08:05:48 PM UTC 24 |
796494586 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.1526327485 |
|
|
Sep 11 08:04:56 PM UTC 24 |
Sep 11 08:05:49 PM UTC 24 |
507166304 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.3134416963 |
|
|
Sep 11 08:05:07 PM UTC 24 |
Sep 11 08:05:50 PM UTC 24 |
944692752 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.4198711268 |
|
|
Sep 11 08:04:49 PM UTC 24 |
Sep 11 08:05:57 PM UTC 24 |
1837307849 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.2458697303 |
|
|
Sep 11 08:04:52 PM UTC 24 |
Sep 11 08:06:00 PM UTC 24 |
776005819 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.3895262343 |
|
|
Sep 11 08:04:14 PM UTC 24 |
Sep 11 08:06:02 PM UTC 24 |
485043177 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.3474582833 |
|
|
Sep 11 08:04:22 PM UTC 24 |
Sep 11 08:06:04 PM UTC 24 |
9897662222 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.186875450 |
|
|
Sep 11 08:06:03 PM UTC 24 |
Sep 11 08:06:16 PM UTC 24 |
198178739 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.295204236 |
|
|
Sep 11 08:06:10 PM UTC 24 |
Sep 11 08:06:20 PM UTC 24 |
50092397 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.2932573269 |
|
|
Sep 11 07:09:37 PM UTC 24 |
Sep 11 08:06:33 PM UTC 24 |
31556881472 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.3197980779 |
|
|
Sep 11 08:04:29 PM UTC 24 |
Sep 11 08:06:45 PM UTC 24 |
5497118221 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.1176413551 |
|
|
Sep 11 07:52:56 PM UTC 24 |
Sep 11 08:06:46 PM UTC 24 |
51460120688 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.46530313 |
|
|
Sep 11 08:06:16 PM UTC 24 |
Sep 11 08:06:48 PM UTC 24 |
401776596 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.4249544489 |
|
|
Sep 11 07:57:17 PM UTC 24 |
Sep 11 08:07:09 PM UTC 24 |
10068580175 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.232376121 |
|
|
Sep 11 08:06:29 PM UTC 24 |
Sep 11 08:07:18 PM UTC 24 |
1196947115 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.1040955741 |
|
|
Sep 11 08:06:22 PM UTC 24 |
Sep 11 08:07:28 PM UTC 24 |
617883725 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.2990130387 |
|
|
Sep 11 08:02:02 PM UTC 24 |
Sep 11 08:07:29 PM UTC 24 |
2756833037 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.2136382009 |
|
|
Sep 11 07:04:09 PM UTC 24 |
Sep 11 08:07:30 PM UTC 24 |
29754881812 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.2362569090 |
|
|
Sep 11 08:00:38 PM UTC 24 |
Sep 11 08:07:30 PM UTC 24 |
4368067523 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.1635286450 |
|
|
Sep 11 08:06:12 PM UTC 24 |
Sep 11 08:07:33 PM UTC 24 |
4415075649 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.779675472 |
|
|
Sep 11 08:07:11 PM UTC 24 |
Sep 11 08:07:38 PM UTC 24 |
147504913 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.2257044071 |
|
|
Sep 11 08:06:58 PM UTC 24 |
Sep 11 08:07:38 PM UTC 24 |
587685140 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.2856115490 |
|
|
Sep 11 07:39:10 PM UTC 24 |
Sep 11 08:07:38 PM UTC 24 |
15138062192 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.4121382342 |
|
|
Sep 11 06:58:12 PM UTC 24 |
Sep 11 08:07:39 PM UTC 24 |
30834520985 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.3372876319 |
|
|
Sep 11 08:06:43 PM UTC 24 |
Sep 11 08:07:39 PM UTC 24 |
528114493 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.1852525379 |
|
|
Sep 11 07:33:35 PM UTC 24 |
Sep 11 08:07:40 PM UTC 24 |
15188526220 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.3205638866 |
|
|
Sep 11 07:51:52 PM UTC 24 |
Sep 11 08:07:40 PM UTC 24 |
15167363894 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.3241757635 |
|
|
Sep 11 07:28:36 PM UTC 24 |
Sep 11 08:07:52 PM UTC 24 |
15575770813 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.1461923300 |
|
|
Sep 11 08:07:11 PM UTC 24 |
Sep 11 08:07:52 PM UTC 24 |
299724517 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3485777477 |
|
|
Sep 11 07:56:02 PM UTC 24 |
Sep 11 08:07:55 PM UTC 24 |
7610802185 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.2981253558 |
|
|
Sep 11 08:07:51 PM UTC 24 |
Sep 11 08:08:00 PM UTC 24 |
203393800 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.1589577687 |
|
|
Sep 11 08:05:26 PM UTC 24 |
Sep 11 08:08:04 PM UTC 24 |
541975632 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.1449816435 |
|
|
Sep 11 08:07:54 PM UTC 24 |
Sep 11 08:08:04 PM UTC 24 |
54685880 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.4046644657 |
|
|
Sep 11 08:07:43 PM UTC 24 |
Sep 11 08:08:09 PM UTC 24 |
168804883 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.258678522 |
|
|
Sep 11 08:05:26 PM UTC 24 |
Sep 11 08:08:09 PM UTC 24 |
4580000879 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.3958088273 |
|
|
Sep 11 08:06:14 PM UTC 24 |
Sep 11 08:08:10 PM UTC 24 |
9859237969 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.543764072 |
|
|
Sep 11 08:05:08 PM UTC 24 |
Sep 11 08:08:15 PM UTC 24 |
1892987544 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.3192666277 |
|
|
Sep 11 08:08:04 PM UTC 24 |
Sep 11 08:08:25 PM UTC 24 |
154898483 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.203421769 |
|
|
Sep 11 07:48:39 PM UTC 24 |
Sep 11 08:08:30 PM UTC 24 |
88059141944 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.3851255620 |
|
|
Sep 11 08:08:19 PM UTC 24 |
Sep 11 08:08:37 PM UTC 24 |
94827055 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.3030833294 |
|
|
Sep 11 08:08:06 PM UTC 24 |
Sep 11 08:08:39 PM UTC 24 |
781998109 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.116803402 |
|
|
Sep 11 08:08:34 PM UTC 24 |
Sep 11 08:08:41 PM UTC 24 |
38109353 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.3719627716 |
|
|
Sep 11 08:08:34 PM UTC 24 |
Sep 11 08:08:43 PM UTC 24 |
53622270 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.276252418 |
|
|
Sep 11 08:08:03 PM UTC 24 |
Sep 11 08:08:54 PM UTC 24 |
555675888 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.3242614399 |
|
|
Sep 11 08:03:03 PM UTC 24 |
Sep 11 08:08:56 PM UTC 24 |
20941364049 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.2720041527 |
|
|
Sep 11 08:08:18 PM UTC 24 |
Sep 11 08:08:57 PM UTC 24 |
317377932 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.1671815522 |
|
|
Sep 11 06:59:59 PM UTC 24 |
Sep 11 08:09:09 PM UTC 24 |
29781975215 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.236721807 |
|
|
Sep 11 08:08:03 PM UTC 24 |
Sep 11 08:09:19 PM UTC 24 |
756752903 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.1800358891 |
|
|
Sep 11 08:09:02 PM UTC 24 |
Sep 11 08:09:19 PM UTC 24 |
145185450 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.3120621479 |
|
|
Sep 11 06:54:08 PM UTC 24 |
Sep 11 08:09:24 PM UTC 24 |
36916163080 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.567108506 |
|
|
Sep 11 08:07:58 PM UTC 24 |
Sep 11 08:09:35 PM UTC 24 |
5312663175 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.2089248248 |
|
|
Sep 11 07:58:20 PM UTC 24 |
Sep 11 08:09:36 PM UTC 24 |
42662001853 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.720403833 |
|
|
Sep 11 08:04:47 PM UTC 24 |
Sep 11 08:09:38 PM UTC 24 |
29643592783 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.508629329 |
|
|
Sep 11 08:08:17 PM UTC 24 |
Sep 11 08:09:38 PM UTC 24 |
2113180208 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.3574615509 |
|
|
Sep 11 08:08:47 PM UTC 24 |
Sep 11 08:09:39 PM UTC 24 |
3431278767 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.2516048855 |
|
|
Sep 11 08:08:54 PM UTC 24 |
Sep 11 08:09:41 PM UTC 24 |
932297007 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.717451201 |
|
|
Sep 11 08:07:34 PM UTC 24 |
Sep 11 08:09:43 PM UTC 24 |
273810232 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.3446300399 |
|
|
Sep 11 08:09:08 PM UTC 24 |
Sep 11 08:09:55 PM UTC 24 |
502292737 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.95447661 |
|
|
Sep 11 08:08:40 PM UTC 24 |
Sep 11 08:09:58 PM UTC 24 |
5664353136 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.3570820119 |
|
|
Sep 11 08:09:24 PM UTC 24 |
Sep 11 08:09:59 PM UTC 24 |
914614569 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.2587744149 |
|
|
Sep 11 08:09:35 PM UTC 24 |
Sep 11 08:09:59 PM UTC 24 |
451774839 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.3035965101 |
|
|
Sep 11 08:09:45 PM UTC 24 |
Sep 11 08:10:09 PM UTC 24 |
555118412 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.1032173227 |
|
|
Sep 11 08:03:51 PM UTC 24 |
Sep 11 08:10:10 PM UTC 24 |
11469768580 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.3721140824 |
|
|
Sep 11 08:10:01 PM UTC 24 |
Sep 11 08:10:11 PM UTC 24 |
45922505 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.232856349 |
|
|
Sep 11 08:10:02 PM UTC 24 |
Sep 11 08:10:13 PM UTC 24 |
166591095 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.3492569894 |
|
|
Sep 11 08:07:53 PM UTC 24 |
Sep 11 08:10:14 PM UTC 24 |
8921415259 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.1756737492 |
|
|
Sep 11 08:04:12 PM UTC 24 |
Sep 11 08:10:26 PM UTC 24 |
10316278285 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.4193842956 |
|
|
Sep 11 08:09:23 PM UTC 24 |
Sep 11 08:10:34 PM UTC 24 |
2477828868 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.1339212770 |
|
|
Sep 11 08:05:13 PM UTC 24 |
Sep 11 08:10:35 PM UTC 24 |
2391458318 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.2914402611 |
|
|
Sep 11 08:10:05 PM UTC 24 |
Sep 11 08:10:57 PM UTC 24 |
3693954699 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.3341280826 |
|
|
Sep 11 08:10:39 PM UTC 24 |
Sep 11 08:11:01 PM UTC 24 |
106116964 ps |
| T1763 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.2511374544 |
|
|
Sep 11 08:10:16 PM UTC 24 |
Sep 11 08:11:10 PM UTC 24 |
464035301 ps |
| T1764 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.2189479672 |
|
|
Sep 11 08:10:36 PM UTC 24 |
Sep 11 08:11:12 PM UTC 24 |
1314210513 ps |
| T1765 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.3921794428 |
|
|
Sep 11 08:10:25 PM UTC 24 |
Sep 11 08:11:21 PM UTC 24 |
698817472 ps |
| T1766 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.1184270624 |
|
|
Sep 11 08:10:41 PM UTC 24 |
Sep 11 08:11:23 PM UTC 24 |
749847445 ps |
| T1767 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.3902721448 |
|
|
Sep 11 08:10:07 PM UTC 24 |
Sep 11 08:11:25 PM UTC 24 |
2181061333 ps |
| T1768 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.4048169638 |
|
|
Sep 11 08:10:05 PM UTC 24 |
Sep 11 08:11:29 PM UTC 24 |
7518750434 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2493175160 |
|
|
Sep 11 08:08:34 PM UTC 24 |
Sep 11 08:11:31 PM UTC 24 |
1501627699 ps |
| T1769 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.2674747328 |
|
|
Sep 11 08:11:27 PM UTC 24 |
Sep 11 08:11:37 PM UTC 24 |
34798290 ps |
| T1770 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.576128174 |
|
|
Sep 11 08:07:51 PM UTC 24 |
Sep 11 08:11:37 PM UTC 24 |
3255231168 ps |
| T1771 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.2667284951 |
|
|
Sep 11 08:11:36 PM UTC 24 |
Sep 11 08:11:46 PM UTC 24 |
46450205 ps |
| T1772 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.2585599531 |
|
|
Sep 11 08:10:58 PM UTC 24 |
Sep 11 08:12:00 PM UTC 24 |
51222479 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.2561375197 |
|
|
Sep 11 08:08:28 PM UTC 24 |
Sep 11 08:12:01 PM UTC 24 |
712964431 ps |
| T1773 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.4075969293 |
|
|
Sep 11 08:10:36 PM UTC 24 |
Sep 11 08:12:08 PM UTC 24 |
2522119237 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.3642609096 |
|
|
Sep 11 08:08:25 PM UTC 24 |
Sep 11 08:12:14 PM UTC 24 |
2489322571 ps |
| T1774 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.420797960 |
|
|
Sep 11 07:56:39 PM UTC 24 |
Sep 11 08:12:24 PM UTC 24 |
60662299792 ps |
| T1775 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.201686024 |
|
|
Sep 11 08:10:01 PM UTC 24 |
Sep 11 08:12:25 PM UTC 24 |
374387722 ps |
| T1776 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.117327122 |
|
|
Sep 11 08:11:46 PM UTC 24 |
Sep 11 08:12:32 PM UTC 24 |
377513014 ps |
| T1777 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.2429919210 |
|
|
Sep 11 07:52:46 PM UTC 24 |
Sep 11 08:12:40 PM UTC 24 |
110215564062 ps |
| T1778 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.1381137775 |
|
|
Sep 11 08:12:24 PM UTC 24 |
Sep 11 08:12:42 PM UTC 24 |
116396935 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.1496970217 |
|
|
Sep 11 08:00:43 PM UTC 24 |
Sep 11 08:12:46 PM UTC 24 |
7000443227 ps |
| T1779 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.384409259 |
|
|
Sep 11 08:11:50 PM UTC 24 |
Sep 11 08:12:47 PM UTC 24 |
486852647 ps |
| T1780 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.1584112050 |
|
|
Sep 11 08:10:01 PM UTC 24 |
Sep 11 08:12:55 PM UTC 24 |
2160747015 ps |
| T1781 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.136192325 |
|
|
Sep 11 08:12:23 PM UTC 24 |
Sep 11 08:13:02 PM UTC 24 |
302830461 ps |
| T1782 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.3479094768 |
|
|
Sep 11 08:09:45 PM UTC 24 |
Sep 11 08:13:03 PM UTC 24 |
2167774028 ps |
| T1783 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.3650930808 |
|
|
Sep 11 08:04:01 PM UTC 24 |
Sep 11 08:13:05 PM UTC 24 |
6260069438 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.259415936 |
|
|
Sep 11 08:00:49 PM UTC 24 |
Sep 11 08:13:07 PM UTC 24 |
17327168061 ps |
| T1784 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.1186727851 |
|
|
Sep 11 08:11:37 PM UTC 24 |
Sep 11 08:13:12 PM UTC 24 |
10570699775 ps |
| T1785 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.2373441053 |
|
|
Sep 11 08:09:04 PM UTC 24 |
Sep 11 08:13:14 PM UTC 24 |
17152637503 ps |
| T1786 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.1545630424 |
|
|
Sep 11 08:13:04 PM UTC 24 |
Sep 11 08:13:15 PM UTC 24 |
51908509 ps |
| T1787 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.1349162113 |
|
|
Sep 11 08:13:05 PM UTC 24 |
Sep 11 08:13:16 PM UTC 24 |
50176031 ps |
| T1788 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.825589936 |
|
|
Sep 11 08:12:03 PM UTC 24 |
Sep 11 08:13:16 PM UTC 24 |
3194421577 ps |
| T1789 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.6931227 |
|
|
Sep 11 08:12:56 PM UTC 24 |
Sep 11 08:13:19 PM UTC 24 |
69716092 ps |