| T1790 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.1348509849 |
|
|
Sep 11 08:12:02 PM UTC 24 |
Sep 11 08:13:23 PM UTC 24 |
1571417938 ps |
| T1791 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.480587405 |
|
|
Sep 11 08:12:32 PM UTC 24 |
Sep 11 08:13:23 PM UTC 24 |
917061072 ps |
| T1792 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.3904812619 |
|
|
Sep 11 08:12:12 PM UTC 24 |
Sep 11 08:13:23 PM UTC 24 |
1707699580 ps |
| T1793 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.32326988 |
|
|
Sep 11 08:11:48 PM UTC 24 |
Sep 11 08:13:31 PM UTC 24 |
5758363249 ps |
| T1794 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.3365446919 |
|
|
Sep 11 08:13:27 PM UTC 24 |
Sep 11 08:13:40 PM UTC 24 |
115651508 ps |
| T1795 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.1322202215 |
|
|
Sep 11 08:13:37 PM UTC 24 |
Sep 11 08:13:51 PM UTC 24 |
89918442 ps |
| T1796 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.2440392997 |
|
|
Sep 11 08:01:28 PM UTC 24 |
Sep 11 08:13:59 PM UTC 24 |
44012270460 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.1717944308 |
|
|
Sep 11 08:13:20 PM UTC 24 |
Sep 11 08:14:02 PM UTC 24 |
1284912510 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.955689773 |
|
|
Sep 11 08:02:16 PM UTC 24 |
Sep 11 08:14:05 PM UTC 24 |
12767332638 ps |
| T1797 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.1412364378 |
|
|
Sep 11 08:13:55 PM UTC 24 |
Sep 11 08:14:09 PM UTC 24 |
210628070 ps |
| T1798 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.4198284370 |
|
|
Sep 11 08:14:03 PM UTC 24 |
Sep 11 08:14:10 PM UTC 24 |
41582375 ps |
| T1799 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.1777112010 |
|
|
Sep 11 08:13:37 PM UTC 24 |
Sep 11 08:14:12 PM UTC 24 |
379775891 ps |
| T1800 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.2898183465 |
|
|
Sep 11 08:13:09 PM UTC 24 |
Sep 11 08:14:14 PM UTC 24 |
7094071673 ps |
| T1801 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.3556543798 |
|
|
Sep 11 08:13:40 PM UTC 24 |
Sep 11 08:14:20 PM UTC 24 |
977438569 ps |
| T1802 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.3556111652 |
|
|
Sep 11 08:13:41 PM UTC 24 |
Sep 11 08:14:30 PM UTC 24 |
928476079 ps |
| T1803 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.1481119727 |
|
|
Sep 11 08:13:49 PM UTC 24 |
Sep 11 08:14:37 PM UTC 24 |
453589226 ps |
| T1804 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.590997885 |
|
|
Sep 11 08:13:11 PM UTC 24 |
Sep 11 08:14:38 PM UTC 24 |
5677176515 ps |
| T1805 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.1675445677 |
|
|
Sep 11 08:14:27 PM UTC 24 |
Sep 11 08:14:43 PM UTC 24 |
100849613 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1856563102 |
|
|
Sep 11 07:51:02 PM UTC 24 |
Sep 11 08:14:43 PM UTC 24 |
94105247401 ps |
| T1806 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.3515067695 |
|
|
Sep 11 08:10:58 PM UTC 24 |
Sep 11 08:14:45 PM UTC 24 |
7344191814 ps |
| T1807 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.4086070724 |
|
|
Sep 11 08:12:48 PM UTC 24 |
Sep 11 08:14:49 PM UTC 24 |
3476055669 ps |
| T1808 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.166445712 |
|
|
Sep 11 08:14:36 PM UTC 24 |
Sep 11 08:14:49 PM UTC 24 |
110966297 ps |
| T1809 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.2424813874 |
|
|
Sep 11 08:14:24 PM UTC 24 |
Sep 11 08:14:50 PM UTC 24 |
253292312 ps |
| T1810 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.3228696747 |
|
|
Sep 11 08:13:32 PM UTC 24 |
Sep 11 08:14:50 PM UTC 24 |
1268442783 ps |
| T1811 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.2657829528 |
|
|
Sep 11 08:03:03 PM UTC 24 |
Sep 11 08:15:04 PM UTC 24 |
79411211997 ps |
| T1812 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.152779247 |
|
|
Sep 11 08:14:58 PM UTC 24 |
Sep 11 08:15:05 PM UTC 24 |
20296489 ps |
| T1813 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.1689368035 |
|
|
Sep 11 06:54:09 PM UTC 24 |
Sep 11 08:15:08 PM UTC 24 |
29324756120 ps |
| T1814 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.3766733918 |
|
|
Sep 11 08:14:31 PM UTC 24 |
Sep 11 08:15:10 PM UTC 24 |
2794349192 ps |
| T1815 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.3419682973 |
|
|
Sep 11 08:14:51 PM UTC 24 |
Sep 11 08:15:15 PM UTC 24 |
239500706 ps |
| T1816 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.1639270309 |
|
|
Sep 11 08:07:13 PM UTC 24 |
Sep 11 08:15:17 PM UTC 24 |
12068070120 ps |
| T1817 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.2235313848 |
|
|
Sep 11 08:13:43 PM UTC 24 |
Sep 11 08:15:18 PM UTC 24 |
1382449750 ps |
| T1818 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.3549617104 |
|
|
Sep 11 08:15:15 PM UTC 24 |
Sep 11 08:15:24 PM UTC 24 |
55526067 ps |
| T1819 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.3077048995 |
|
|
Sep 11 08:14:45 PM UTC 24 |
Sep 11 08:15:24 PM UTC 24 |
411618517 ps |
| T1820 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.2011187286 |
|
|
Sep 11 08:15:15 PM UTC 24 |
Sep 11 08:15:29 PM UTC 24 |
193398733 ps |
| T1821 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.1788126617 |
|
|
Sep 11 08:14:13 PM UTC 24 |
Sep 11 08:15:30 PM UTC 24 |
6882421302 ps |
| T1822 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.686547776 |
|
|
Sep 11 08:15:01 PM UTC 24 |
Sep 11 08:15:35 PM UTC 24 |
255901726 ps |
| T1823 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.3909938367 |
|
|
Sep 11 06:59:33 PM UTC 24 |
Sep 11 08:15:46 PM UTC 24 |
43830829016 ps |
| T1824 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.1894385504 |
|
|
Sep 11 08:14:25 PM UTC 24 |
Sep 11 08:15:58 PM UTC 24 |
5241540488 ps |
| T1825 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.685100633 |
|
|
Sep 11 08:15:27 PM UTC 24 |
Sep 11 08:16:04 PM UTC 24 |
332782960 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.1538961567 |
|
|
Sep 11 08:15:42 PM UTC 24 |
Sep 11 08:16:05 PM UTC 24 |
357014733 ps |
| T1826 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.1010186854 |
|
|
Sep 11 08:15:31 PM UTC 24 |
Sep 11 08:16:07 PM UTC 24 |
279206207 ps |
| T1827 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1810822427 |
|
|
Sep 11 08:09:50 PM UTC 24 |
Sep 11 08:16:15 PM UTC 24 |
5455568696 ps |
| T1828 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1293770902 |
|
|
Sep 11 08:11:19 PM UTC 24 |
Sep 11 08:16:32 PM UTC 24 |
718272754 ps |
| T1829 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.4022080762 |
|
|
Sep 11 08:15:56 PM UTC 24 |
Sep 11 08:16:34 PM UTC 24 |
680813280 ps |
| T1830 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.1181108311 |
|
|
Sep 11 08:15:16 PM UTC 24 |
Sep 11 08:16:36 PM UTC 24 |
8706613159 ps |
| T1831 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.2187787914 |
|
|
Sep 11 08:15:03 PM UTC 24 |
Sep 11 08:16:37 PM UTC 24 |
1368398880 ps |
| T1832 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.2130585310 |
|
|
Sep 11 08:16:32 PM UTC 24 |
Sep 11 08:16:41 PM UTC 24 |
54022614 ps |
| T1833 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.215072550 |
|
|
Sep 11 08:16:32 PM UTC 24 |
Sep 11 08:16:46 PM UTC 24 |
213254178 ps |
| T1834 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.2144725133 |
|
|
Sep 11 08:06:26 PM UTC 24 |
Sep 11 08:16:49 PM UTC 24 |
37801329165 ps |
| T1835 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.2761295178 |
|
|
Sep 11 08:00:11 PM UTC 24 |
Sep 11 08:16:52 PM UTC 24 |
66515129502 ps |
| T1836 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.1276353009 |
|
|
Sep 11 08:08:27 PM UTC 24 |
Sep 11 08:16:54 PM UTC 24 |
14785042952 ps |
| T1837 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.1777682329 |
|
|
Sep 11 08:15:28 PM UTC 24 |
Sep 11 08:17:05 PM UTC 24 |
4729850251 ps |
| T1838 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.3741692332 |
|
|
Sep 11 08:13:48 PM UTC 24 |
Sep 11 08:17:13 PM UTC 24 |
864279519 ps |
| T1839 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.2645294195 |
|
|
Sep 11 08:15:54 PM UTC 24 |
Sep 11 08:17:13 PM UTC 24 |
1420629636 ps |
| T1840 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.2666297460 |
|
|
Sep 11 08:15:49 PM UTC 24 |
Sep 11 08:17:15 PM UTC 24 |
2577004816 ps |
| T1841 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.1810436094 |
|
|
Sep 11 08:16:24 PM UTC 24 |
Sep 11 08:17:18 PM UTC 24 |
1414882232 ps |
| T1842 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.4130156633 |
|
|
Sep 11 08:15:09 PM UTC 24 |
Sep 11 08:17:23 PM UTC 24 |
1958566665 ps |
| T1843 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.472726883 |
|
|
Sep 11 08:15:50 PM UTC 24 |
Sep 11 08:17:25 PM UTC 24 |
2433993225 ps |
| T1844 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.615824484 |
|
|
Sep 11 08:08:03 PM UTC 24 |
Sep 11 08:17:44 PM UTC 24 |
35999400749 ps |
| T1845 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.3508084961 |
|
|
Sep 11 08:09:07 PM UTC 24 |
Sep 11 08:17:54 PM UTC 24 |
34391249668 ps |
| T1846 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.449561250 |
|
|
Sep 11 08:15:40 PM UTC 24 |
Sep 11 08:17:57 PM UTC 24 |
9113472888 ps |
| T1847 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.1027606952 |
|
|
Sep 11 08:14:31 PM UTC 24 |
Sep 11 08:17:59 PM UTC 24 |
16049420203 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3752683047 |
|
|
Sep 11 07:37:14 PM UTC 24 |
Sep 11 08:17:59 PM UTC 24 |
134497075034 ps |
| T1848 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.1220005244 |
|
|
Sep 11 08:17:51 PM UTC 24 |
Sep 11 08:18:00 PM UTC 24 |
192821355 ps |
| T1849 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.1180686800 |
|
|
Sep 11 08:01:19 PM UTC 24 |
Sep 11 08:18:02 PM UTC 24 |
90214152571 ps |
| T1850 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.401786613 |
|
|
Sep 11 08:17:02 PM UTC 24 |
Sep 11 08:18:06 PM UTC 24 |
565552420 ps |
| T1851 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.1498428739 |
|
|
Sep 11 08:17:39 PM UTC 24 |
Sep 11 08:18:09 PM UTC 24 |
557142656 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.888632657 |
|
|
Sep 11 07:45:21 PM UTC 24 |
Sep 11 08:18:10 PM UTC 24 |
136859705421 ps |
| T1852 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.3634558981 |
|
|
Sep 11 08:17:44 PM UTC 24 |
Sep 11 08:18:13 PM UTC 24 |
677208199 ps |
| T1853 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.2198681932 |
|
|
Sep 11 08:18:10 PM UTC 24 |
Sep 11 08:18:20 PM UTC 24 |
44522784 ps |
| T1854 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.157206488 |
|
|
Sep 11 08:13:31 PM UTC 24 |
Sep 11 08:18:23 PM UTC 24 |
21009431520 ps |
| T1855 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.3201788122 |
|
|
Sep 11 08:17:29 PM UTC 24 |
Sep 11 08:18:23 PM UTC 24 |
991598864 ps |
| T1856 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.3496795472 |
|
|
Sep 11 08:17:17 PM UTC 24 |
Sep 11 08:18:25 PM UTC 24 |
2193731125 ps |
| T1857 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.3650609989 |
|
|
Sep 11 08:04:47 PM UTC 24 |
Sep 11 08:18:25 PM UTC 24 |
57070973988 ps |
| T1858 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.3645666327 |
|
|
Sep 11 08:15:11 PM UTC 24 |
Sep 11 08:18:32 PM UTC 24 |
2270734234 ps |
| T1859 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.3576848863 |
|
|
Sep 11 08:17:19 PM UTC 24 |
Sep 11 08:18:35 PM UTC 24 |
1906954784 ps |
| T1860 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.3841381747 |
|
|
Sep 11 08:16:57 PM UTC 24 |
Sep 11 08:18:37 PM UTC 24 |
2430838932 ps |
| T1861 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.2044227402 |
|
|
Sep 11 08:16:58 PM UTC 24 |
Sep 11 08:18:37 PM UTC 24 |
5757234823 ps |
| T1862 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.2241816115 |
|
|
Sep 11 08:17:47 PM UTC 24 |
Sep 11 08:18:46 PM UTC 24 |
98944030 ps |
| T1863 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.1413401082 |
|
|
Sep 11 08:16:41 PM UTC 24 |
Sep 11 08:18:50 PM UTC 24 |
9309419485 ps |
| T1864 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.3848618141 |
|
|
Sep 11 08:10:22 PM UTC 24 |
Sep 11 08:18:56 PM UTC 24 |
45739116139 ps |
| T1865 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.2406267083 |
|
|
Sep 11 08:18:26 PM UTC 24 |
Sep 11 08:18:58 PM UTC 24 |
388579850 ps |
| T1866 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.521027945 |
|
|
Sep 11 08:17:10 PM UTC 24 |
Sep 11 08:19:02 PM UTC 24 |
3072697325 ps |
| T1867 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.3375291738 |
|
|
Sep 11 08:18:34 PM UTC 24 |
Sep 11 08:19:04 PM UTC 24 |
270837409 ps |
| T1868 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.1962796851 |
|
|
Sep 11 08:19:02 PM UTC 24 |
Sep 11 08:19:10 PM UTC 24 |
52713443 ps |
| T1869 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.35036600 |
|
|
Sep 11 08:18:58 PM UTC 24 |
Sep 11 08:19:11 PM UTC 24 |
180610226 ps |
| T1870 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.2525117285 |
|
|
Sep 11 08:18:47 PM UTC 24 |
Sep 11 08:19:15 PM UTC 24 |
513045546 ps |
| T1871 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3557231237 |
|
|
Sep 11 08:16:31 PM UTC 24 |
Sep 11 08:19:18 PM UTC 24 |
324032542 ps |
| T1872 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.1527693811 |
|
|
Sep 11 08:17:01 PM UTC 24 |
Sep 11 08:19:22 PM UTC 24 |
14747118191 ps |
| T1873 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.4205740365 |
|
|
Sep 11 08:18:38 PM UTC 24 |
Sep 11 08:19:23 PM UTC 24 |
465215054 ps |
| T1874 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.3447129430 |
|
|
Sep 11 07:43:40 PM UTC 24 |
Sep 11 08:19:27 PM UTC 24 |
150889893496 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.2864565181 |
|
|
Sep 11 08:18:45 PM UTC 24 |
Sep 11 08:19:27 PM UTC 24 |
1019568862 ps |
| T1875 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_aliasing.2930676266 |
|
|
Sep 11 06:59:43 PM UTC 24 |
Sep 11 08:19:30 PM UTC 24 |
28992466173 ps |
| T1876 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.2544533725 |
|
|
Sep 11 08:18:26 PM UTC 24 |
Sep 11 08:19:34 PM UTC 24 |
1913658057 ps |
| T1877 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.724815980 |
|
|
Sep 11 08:18:31 PM UTC 24 |
Sep 11 08:19:38 PM UTC 24 |
676725930 ps |
| T1878 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.988537058 |
|
|
Sep 11 08:15:06 PM UTC 24 |
Sep 11 08:19:38 PM UTC 24 |
2149558520 ps |
| T1879 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.162265740 |
|
|
Sep 11 08:19:16 PM UTC 24 |
Sep 11 08:19:42 PM UTC 24 |
575731427 ps |
| T1880 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.218528095 |
|
|
Sep 11 08:18:22 PM UTC 24 |
Sep 11 08:19:44 PM UTC 24 |
4966467554 ps |
| T1881 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.125002112 |
|
|
Sep 11 08:18:20 PM UTC 24 |
Sep 11 08:19:53 PM UTC 24 |
9265254366 ps |
| T1882 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.1526800451 |
|
|
Sep 11 08:19:40 PM UTC 24 |
Sep 11 08:19:57 PM UTC 24 |
201098853 ps |
| T1883 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.47261861 |
|
|
Sep 11 08:19:39 PM UTC 24 |
Sep 11 08:19:57 PM UTC 24 |
363038563 ps |
| T1884 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.928461045 |
|
|
Sep 11 08:19:15 PM UTC 24 |
Sep 11 08:20:01 PM UTC 24 |
524904136 ps |
| T1885 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.2105522396 |
|
|
Sep 11 08:19:56 PM UTC 24 |
Sep 11 08:20:07 PM UTC 24 |
53658508 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.103635351 |
|
|
Sep 11 08:12:47 PM UTC 24 |
Sep 11 08:20:08 PM UTC 24 |
2145460757 ps |
| T1886 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.1975952204 |
|
|
Sep 11 08:19:59 PM UTC 24 |
Sep 11 08:20:09 PM UTC 24 |
39611546 ps |
| T1887 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.1201450587 |
|
|
Sep 11 08:18:55 PM UTC 24 |
Sep 11 08:20:13 PM UTC 24 |
165998134 ps |
| T1888 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.92388146 |
|
|
Sep 11 08:19:43 PM UTC 24 |
Sep 11 08:20:20 PM UTC 24 |
924750649 ps |
| T1889 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.1238239159 |
|
|
Sep 11 08:10:52 PM UTC 24 |
Sep 11 08:20:20 PM UTC 24 |
15843680580 ps |
| T1890 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.3296086363 |
|
|
Sep 11 08:19:03 PM UTC 24 |
Sep 11 08:20:23 PM UTC 24 |
7216911681 ps |
| T1891 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.3049743951 |
|
|
Sep 11 08:13:34 PM UTC 24 |
Sep 11 08:20:26 PM UTC 24 |
23794595011 ps |
| T1892 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.2612377167 |
|
|
Sep 11 08:16:12 PM UTC 24 |
Sep 11 08:20:30 PM UTC 24 |
1442856782 ps |
| T1893 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.3079885853 |
|
|
Sep 11 08:19:29 PM UTC 24 |
Sep 11 08:20:31 PM UTC 24 |
813379324 ps |
| T1894 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.958104968 |
|
|
Sep 11 08:19:36 PM UTC 24 |
Sep 11 08:20:38 PM UTC 24 |
1653906087 ps |
| T1895 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.4205123913 |
|
|
Sep 11 08:12:40 PM UTC 24 |
Sep 11 08:20:39 PM UTC 24 |
12577864458 ps |
| T1896 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.3231360221 |
|
|
Sep 11 08:18:26 PM UTC 24 |
Sep 11 08:20:44 PM UTC 24 |
10378518607 ps |
| T1897 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.2753388190 |
|
|
Sep 11 08:13:50 PM UTC 24 |
Sep 11 08:20:48 PM UTC 24 |
12306940966 ps |
| T1898 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.3738111428 |
|
|
Sep 11 08:20:41 PM UTC 24 |
Sep 11 08:20:50 PM UTC 24 |
32737610 ps |
| T1899 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.1297722423 |
|
|
Sep 11 08:19:12 PM UTC 24 |
Sep 11 08:20:52 PM UTC 24 |
4956013620 ps |
| T1900 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.1346346278 |
|
|
Sep 11 08:20:37 PM UTC 24 |
Sep 11 08:20:58 PM UTC 24 |
134973453 ps |
| T1901 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.3249565195 |
|
|
Sep 11 08:20:17 PM UTC 24 |
Sep 11 08:21:02 PM UTC 24 |
500714842 ps |
| T1902 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.785169372 |
|
|
Sep 11 08:20:07 PM UTC 24 |
Sep 11 08:21:04 PM UTC 24 |
1906963685 ps |
| T1903 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.989375559 |
|
|
Sep 11 08:20:34 PM UTC 24 |
Sep 11 08:21:05 PM UTC 24 |
366414080 ps |
| T1904 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.4102453518 |
|
|
Sep 11 08:20:51 PM UTC 24 |
Sep 11 08:21:05 PM UTC 24 |
220990340 ps |
| T1905 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.3916951394 |
|
|
Sep 11 08:20:27 PM UTC 24 |
Sep 11 08:21:11 PM UTC 24 |
708640366 ps |
| T1906 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.424272570 |
|
|
Sep 11 08:21:05 PM UTC 24 |
Sep 11 08:21:13 PM UTC 24 |
50298698 ps |
| T1907 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.2838436073 |
|
|
Sep 11 08:19:59 PM UTC 24 |
Sep 11 08:21:34 PM UTC 24 |
7022322335 ps |
| T1908 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.331108741 |
|
|
Sep 11 08:20:32 PM UTC 24 |
Sep 11 08:21:36 PM UTC 24 |
1875440905 ps |
| T1909 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.3284619670 |
|
|
Sep 11 08:20:01 PM UTC 24 |
Sep 11 08:21:36 PM UTC 24 |
4524689409 ps |
| T1910 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.4093115876 |
|
|
Sep 11 08:19:52 PM UTC 24 |
Sep 11 08:21:37 PM UTC 24 |
1291754754 ps |
| T1911 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.156571190 |
|
|
Sep 11 08:18:49 PM UTC 24 |
Sep 11 08:21:40 PM UTC 24 |
2219162490 ps |
| T1912 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.1204655995 |
|
|
Sep 11 08:21:14 PM UTC 24 |
Sep 11 08:21:41 PM UTC 24 |
221216913 ps |
| T1913 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.2946354171 |
|
|
Sep 11 08:21:29 PM UTC 24 |
Sep 11 08:21:50 PM UTC 24 |
262138473 ps |
| T1914 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.3240065784 |
|
|
Sep 11 08:09:20 PM UTC 24 |
Sep 11 08:22:03 PM UTC 24 |
46808673936 ps |
| T1915 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.1369661209 |
|
|
Sep 11 08:21:30 PM UTC 24 |
Sep 11 08:22:11 PM UTC 24 |
522068524 ps |
| T1916 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.2522438207 |
|
|
Sep 11 08:22:05 PM UTC 24 |
Sep 11 08:22:16 PM UTC 24 |
42804411 ps |
| T1917 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.3977495015 |
|
|
Sep 11 08:22:05 PM UTC 24 |
Sep 11 08:22:17 PM UTC 24 |
145736270 ps |
| T1918 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.1390396567 |
|
|
Sep 11 08:11:55 PM UTC 24 |
Sep 11 08:22:17 PM UTC 24 |
59216606666 ps |
| T1919 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.2597682209 |
|
|
Sep 11 08:21:38 PM UTC 24 |
Sep 11 08:22:18 PM UTC 24 |
739467210 ps |
| T1920 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.2236638004 |
|
|
Sep 11 08:21:14 PM UTC 24 |
Sep 11 08:22:22 PM UTC 24 |
599883129 ps |
| T1921 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.3088266186 |
|
|
Sep 11 08:16:01 PM UTC 24 |
Sep 11 08:22:23 PM UTC 24 |
10604206188 ps |
| T1922 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.389638791 |
|
|
Sep 11 08:21:36 PM UTC 24 |
Sep 11 08:22:26 PM UTC 24 |
939376971 ps |
| T1923 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.2062610681 |
|
|
Sep 11 06:54:48 PM UTC 24 |
Sep 11 08:22:27 PM UTC 24 |
30506890092 ps |
| T1924 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.1066842008 |
|
|
Sep 11 08:21:04 PM UTC 24 |
Sep 11 08:22:45 PM UTC 24 |
8202189939 ps |
| T1925 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.2215962202 |
|
|
Sep 11 08:21:08 PM UTC 24 |
Sep 11 08:22:46 PM UTC 24 |
5892427930 ps |
| T1926 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.12239597 |
|
|
Sep 11 08:21:27 PM UTC 24 |
Sep 11 08:22:58 PM UTC 24 |
1302718084 ps |
| T1927 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.2094650957 |
|
|
Sep 11 08:22:42 PM UTC 24 |
Sep 11 08:23:05 PM UTC 24 |
269046195 ps |
| T1928 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.2968390263 |
|
|
Sep 11 08:19:27 PM UTC 24 |
Sep 11 08:23:14 PM UTC 24 |
15237259844 ps |
| T1929 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.102077702 |
|
|
Sep 11 08:22:52 PM UTC 24 |
Sep 11 08:23:18 PM UTC 24 |
271223948 ps |
| T1930 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.4058399516 |
|
|
Sep 11 08:21:22 PM UTC 24 |
Sep 11 08:23:24 PM UTC 24 |
8228577450 ps |
| T1931 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.1014269363 |
|
|
Sep 11 08:23:10 PM UTC 24 |
Sep 11 08:23:25 PM UTC 24 |
113399980 ps |
| T1932 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.2036665750 |
|
|
Sep 11 08:22:54 PM UTC 24 |
Sep 11 08:23:30 PM UTC 24 |
207950235 ps |
| T1933 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.3775163886 |
|
|
Sep 11 08:22:49 PM UTC 24 |
Sep 11 08:23:37 PM UTC 24 |
1641451119 ps |
| T1934 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.1898764352 |
|
|
Sep 11 08:22:29 PM UTC 24 |
Sep 11 08:23:39 PM UTC 24 |
4535662346 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.4011272164 |
|
|
Sep 11 08:22:41 PM UTC 24 |
Sep 11 08:23:42 PM UTC 24 |
885822692 ps |
| T1935 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.2604307397 |
|
|
Sep 11 07:25:26 PM UTC 24 |
Sep 11 08:23:44 PM UTC 24 |
29336140994 ps |
| T1936 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.670752552 |
|
|
Sep 11 08:22:42 PM UTC 24 |
Sep 11 08:23:47 PM UTC 24 |
6078526835 ps |
| T1937 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.3128791508 |
|
|
Sep 11 08:22:16 PM UTC 24 |
Sep 11 08:23:47 PM UTC 24 |
8415346099 ps |
| T1938 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.3622535265 |
|
|
Sep 11 08:22:37 PM UTC 24 |
Sep 11 08:23:48 PM UTC 24 |
619988518 ps |
| T1939 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.3374974533 |
|
|
Sep 11 08:23:43 PM UTC 24 |
Sep 11 08:23:58 PM UTC 24 |
234992694 ps |
| T1940 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.2168357974 |
|
|
Sep 11 08:23:50 PM UTC 24 |
Sep 11 08:24:00 PM UTC 24 |
51518939 ps |
| T1941 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.1867689881 |
|
|
Sep 11 08:20:51 PM UTC 24 |
Sep 11 08:24:07 PM UTC 24 |
4540945408 ps |
| T1942 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.1763905701 |
|
|
Sep 11 08:17:39 PM UTC 24 |
Sep 11 08:24:14 PM UTC 24 |
10509220951 ps |
| T1943 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.1361492606 |
|
|
Sep 11 08:22:01 PM UTC 24 |
Sep 11 08:24:17 PM UTC 24 |
2451142436 ps |
| T1944 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.1939527121 |
|
|
Sep 11 08:20:49 PM UTC 24 |
Sep 11 08:24:23 PM UTC 24 |
5466829675 ps |
| T1945 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.1591032065 |
|
|
Sep 11 08:24:12 PM UTC 24 |
Sep 11 08:24:25 PM UTC 24 |
101819382 ps |
| T1946 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.2176112307 |
|
|
Sep 11 08:06:22 PM UTC 24 |
Sep 11 08:24:28 PM UTC 24 |
109212163495 ps |
| T1947 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.2440041727 |
|
|
Sep 11 08:19:51 PM UTC 24 |
Sep 11 08:24:29 PM UTC 24 |
8840453165 ps |
| T1948 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.4208805446 |
|
|
Sep 11 08:24:03 PM UTC 24 |
Sep 11 08:24:37 PM UTC 24 |
635253767 ps |
| T1949 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.3554520940 |
|
|
Sep 11 08:24:25 PM UTC 24 |
Sep 11 08:24:44 PM UTC 24 |
164475547 ps |
| T1950 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.1443251080 |
|
|
Sep 11 08:24:26 PM UTC 24 |
Sep 11 08:24:48 PM UTC 24 |
480392023 ps |
| T1951 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.2322604770 |
|
|
Sep 11 08:24:13 PM UTC 24 |
Sep 11 08:24:48 PM UTC 24 |
368889640 ps |
| T1952 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.1799719227 |
|
|
Sep 11 08:24:04 PM UTC 24 |
Sep 11 08:24:50 PM UTC 24 |
547989206 ps |
| T1953 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.4216059744 |
|
|
Sep 11 08:23:49 PM UTC 24 |
Sep 11 08:24:58 PM UTC 24 |
7425697916 ps |
| T1954 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.2393431890 |
|
|
Sep 11 08:24:52 PM UTC 24 |
Sep 11 08:25:01 PM UTC 24 |
49180502 ps |
| T1955 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.2488593987 |
|
|
Sep 11 08:23:10 PM UTC 24 |
Sep 11 08:25:03 PM UTC 24 |
1455581456 ps |
| T1956 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.4160224939 |
|
|
Sep 11 08:24:52 PM UTC 24 |
Sep 11 08:25:04 PM UTC 24 |
248601567 ps |
| T1957 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.143314238 |
|
|
Sep 11 08:24:32 PM UTC 24 |
Sep 11 08:25:20 PM UTC 24 |
1287918380 ps |
| T1958 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.2334363274 |
|
|
Sep 11 08:24:48 PM UTC 24 |
Sep 11 08:25:33 PM UTC 24 |
116067885 ps |
| T1959 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.2934966467 |
|
|
Sep 11 08:23:53 PM UTC 24 |
Sep 11 08:25:41 PM UTC 24 |
5949892168 ps |
| T1960 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.1893367176 |
|
|
Sep 11 08:19:49 PM UTC 24 |
Sep 11 08:25:53 PM UTC 24 |
2020848739 ps |
| T1961 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.4225080876 |
|
|
Sep 11 08:20:56 PM UTC 24 |
Sep 11 08:25:54 PM UTC 24 |
1674488264 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.1972940251 |
|
|
Sep 11 08:21:16 PM UTC 24 |
Sep 11 08:25:59 PM UTC 24 |
21767955567 ps |
| T1962 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.856429611 |
|
|
Sep 11 07:54:48 PM UTC 24 |
Sep 11 08:25:59 PM UTC 24 |
137021751640 ps |
| T1963 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.2613629317 |
|
|
Sep 11 08:08:04 PM UTC 24 |
Sep 11 08:26:00 PM UTC 24 |
108454135097 ps |
| T1964 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.3206635838 |
|
|
Sep 11 08:25:23 PM UTC 24 |
Sep 11 08:26:06 PM UTC 24 |
476312760 ps |
| T1965 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.4072903205 |
|
|
Sep 11 08:25:14 PM UTC 24 |
Sep 11 08:26:09 PM UTC 24 |
539936580 ps |
| T1966 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.3738961645 |
|
|
Sep 11 08:25:30 PM UTC 24 |
Sep 11 08:26:09 PM UTC 24 |
1179685640 ps |
| T1967 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.3743327155 |
|
|
Sep 11 08:25:59 PM UTC 24 |
Sep 11 08:26:09 PM UTC 24 |
66578865 ps |
| T1968 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.662895209 |
|
|
Sep 11 08:22:02 PM UTC 24 |
Sep 11 08:26:20 PM UTC 24 |
7725780266 ps |
| T1969 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.784382247 |
|
|
Sep 11 08:26:03 PM UTC 24 |
Sep 11 08:26:30 PM UTC 24 |
174086432 ps |
| T1970 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.2326195549 |
|
|
Sep 11 08:26:25 PM UTC 24 |
Sep 11 08:26:35 PM UTC 24 |
46055365 ps |
| T1971 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.2263373466 |
|
|
Sep 11 08:25:45 PM UTC 24 |
Sep 11 08:26:37 PM UTC 24 |
602451040 ps |
| T1972 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3322526698 |
|
|
Sep 11 08:26:29 PM UTC 24 |
Sep 11 08:26:37 PM UTC 24 |
45177567 ps |
| T1973 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.742736372 |
|
|
Sep 11 08:25:00 PM UTC 24 |
Sep 11 08:26:37 PM UTC 24 |
8450472466 ps |
| T1974 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.1364181151 |
|
|
Sep 11 08:04:53 PM UTC 24 |
Sep 11 08:26:37 PM UTC 24 |
83515803666 ps |
| T1975 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.3850960635 |
|
|
Sep 11 08:10:24 PM UTC 24 |
Sep 11 08:26:53 PM UTC 24 |
62250778030 ps |
| T1976 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.1016643522 |
|
|
Sep 11 08:26:41 PM UTC 24 |
Sep 11 08:27:02 PM UTC 24 |
145285258 ps |
| T1977 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.736931971 |
|
|
Sep 11 08:26:59 PM UTC 24 |
Sep 11 08:27:07 PM UTC 24 |
68263589 ps |
| T1978 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.1097751576 |
|
|
Sep 11 08:25:13 PM UTC 24 |
Sep 11 08:27:13 PM UTC 24 |
2684471320 ps |
| T1979 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.4073820577 |
|
|
Sep 11 08:18:48 PM UTC 24 |
Sep 11 08:27:21 PM UTC 24 |
14128464575 ps |
| T1980 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.2625465480 |
|
|
Sep 11 08:25:10 PM UTC 24 |
Sep 11 08:27:24 PM UTC 24 |
5949567410 ps |
| T1981 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.802791684 |
|
|
Sep 11 08:26:31 PM UTC 24 |
Sep 11 08:27:31 PM UTC 24 |
609579293 ps |
| T1982 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.1726490051 |
|
|
Sep 11 08:22:00 PM UTC 24 |
Sep 11 08:27:35 PM UTC 24 |
10220958063 ps |
| T1983 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.535379125 |
|
|
Sep 11 07:19:17 PM UTC 24 |
Sep 11 08:27:35 PM UTC 24 |
31430631573 ps |
| T1984 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.2427635691 |
|
|
Sep 11 08:17:07 PM UTC 24 |
Sep 11 08:27:38 PM UTC 24 |
34197318721 ps |
| T1985 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.2774686335 |
|
|
Sep 11 08:27:04 PM UTC 24 |
Sep 11 08:27:41 PM UTC 24 |
521701657 ps |
| T1986 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.15359785 |
|
|
Sep 11 08:24:40 PM UTC 24 |
Sep 11 08:27:43 PM UTC 24 |
2259314356 ps |
| T1987 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.3821239110 |
|
|
Sep 11 08:26:34 PM UTC 24 |
Sep 11 08:27:43 PM UTC 24 |
3640393862 ps |
| T1988 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.3315282727 |
|
|
Sep 11 08:27:22 PM UTC 24 |
Sep 11 08:27:50 PM UTC 24 |
491244570 ps |
| T1989 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.2345309802 |
|
|
Sep 11 08:01:28 PM UTC 24 |
Sep 11 08:27:53 PM UTC 24 |
115213724196 ps |
| T1990 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.2336868416 |
|
|
Sep 11 08:20:45 PM UTC 24 |
Sep 11 08:27:53 PM UTC 24 |
4974869782 ps |
| T1991 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.4096882219 |
|
|
Sep 11 08:27:01 PM UTC 24 |
Sep 11 08:28:00 PM UTC 24 |
751012055 ps |
| T1992 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.2907067993 |
|
|
Sep 11 08:10:35 PM UTC 24 |
Sep 11 08:28:02 PM UTC 24 |
65029627430 ps |
| T1993 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.2606536942 |
|
|
Sep 11 08:27:54 PM UTC 24 |
Sep 11 08:28:02 PM UTC 24 |
47903213 ps |
| T1994 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.1833590427 |
|
|
Sep 11 08:28:00 PM UTC 24 |
Sep 11 08:28:11 PM UTC 24 |
52432933 ps |
| T1995 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.4060680470 |
|
|
Sep 11 08:28:09 PM UTC 24 |
Sep 11 08:28:20 PM UTC 24 |
69660694 ps |
| T1996 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.996634087 |
|
|
Sep 11 08:19:43 PM UTC 24 |
Sep 11 08:28:22 PM UTC 24 |
13694693635 ps |
| T1997 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.3435843072 |
|
|
Sep 11 08:17:41 PM UTC 24 |
Sep 11 08:28:22 PM UTC 24 |
10588179586 ps |
| T1998 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.2689039629 |
|
|
Sep 11 08:11:56 PM UTC 24 |
Sep 11 08:28:24 PM UTC 24 |
62079184961 ps |
| T1999 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.2235947007 |
|
|
Sep 11 08:27:18 PM UTC 24 |
Sep 11 08:28:24 PM UTC 24 |
1410279635 ps |
| T2000 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.551845323 |
|
|
Sep 11 08:26:33 PM UTC 24 |
Sep 11 08:28:27 PM UTC 24 |
7481468718 ps |
| T2001 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.3058121665 |
|
|
Sep 11 08:20:21 PM UTC 24 |
Sep 11 08:28:48 PM UTC 24 |
34529589345 ps |
| T2002 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.2646029262 |
|
|
Sep 11 08:24:42 PM UTC 24 |
Sep 11 08:28:48 PM UTC 24 |
797719419 ps |
| T2003 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.765803544 |
|
|
Sep 11 08:18:28 PM UTC 24 |
Sep 11 08:28:55 PM UTC 24 |
40581387804 ps |
| T2004 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.1370087028 |
|
|
Sep 11 08:28:26 PM UTC 24 |
Sep 11 08:28:55 PM UTC 24 |
1003853630 ps |
| T2005 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.1700710124 |
|
|
Sep 11 08:28:50 PM UTC 24 |
Sep 11 08:29:00 PM UTC 24 |
47918408 ps |
| T2006 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.3999426710 |
|
|
Sep 11 08:28:05 PM UTC 24 |
Sep 11 08:29:00 PM UTC 24 |
1353782278 ps |
| T2007 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.223252692 |
|
|
Sep 11 08:28:51 PM UTC 24 |
Sep 11 08:29:04 PM UTC 24 |
172808858 ps |
| T2008 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.879232803 |
|
|
Sep 11 08:00:15 PM UTC 24 |
Sep 11 08:29:10 PM UTC 24 |
123604038595 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.265979894 |
|
|
Sep 11 08:22:01 PM UTC 24 |
Sep 11 08:29:10 PM UTC 24 |
1799508099 ps |
| T2009 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.259634309 |
|
|
Sep 11 08:27:45 PM UTC 24 |
Sep 11 08:29:11 PM UTC 24 |
1304067538 ps |
| T2010 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.3073261835 |
|
|
Sep 11 08:24:46 PM UTC 24 |
Sep 11 08:29:18 PM UTC 24 |
7315639240 ps |
| T2011 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.1952116549 |
|
|
Sep 11 08:28:28 PM UTC 24 |
Sep 11 08:29:20 PM UTC 24 |
1248747550 ps |
| T2012 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.3329826225 |
|
|
Sep 11 08:27:57 PM UTC 24 |
Sep 11 08:29:22 PM UTC 24 |
8040084259 ps |
| T2013 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.3934357620 |
|
|
Sep 11 08:28:19 PM UTC 24 |
Sep 11 08:29:26 PM UTC 24 |
1191797370 ps |
| T2014 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.721349737 |
|
|
Sep 11 08:28:35 PM UTC 24 |
Sep 11 08:29:26 PM UTC 24 |
1458590671 ps |
| T2015 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.108637698 |
|
|
Sep 11 08:27:59 PM UTC 24 |
Sep 11 08:29:29 PM UTC 24 |
5812277398 ps |
| T2016 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.2364050407 |
|
|
Sep 11 08:26:19 PM UTC 24 |
Sep 11 08:29:34 PM UTC 24 |
2413729419 ps |
| T2017 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.2180988274 |
|
|
Sep 11 08:29:34 PM UTC 24 |
Sep 11 08:29:51 PM UTC 24 |
287582907 ps |
| T2018 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.3499407808 |
|
|
Sep 11 08:29:28 PM UTC 24 |
Sep 11 08:29:55 PM UTC 24 |
674133084 ps |
| T2019 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.3242821901 |
|
|
Sep 11 08:29:22 PM UTC 24 |
Sep 11 08:29:58 PM UTC 24 |
410944563 ps |
| T2020 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.1234113192 |
|
|
Sep 11 08:29:42 PM UTC 24 |
Sep 11 08:29:58 PM UTC 24 |
197185250 ps |
| T2021 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.322974875 |
|
|
Sep 11 08:29:19 PM UTC 24 |
Sep 11 08:30:00 PM UTC 24 |
1033711996 ps |
| T2022 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.2210265992 |
|
|
Sep 11 08:28:28 PM UTC 24 |
Sep 11 08:30:00 PM UTC 24 |
2232833647 ps |
| T2023 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.1533505974 |
|
|
Sep 11 08:18:46 PM UTC 24 |
Sep 11 08:30:00 PM UTC 24 |
11813780536 ps |
| T2024 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.1003531703 |
|
|
Sep 11 08:27:37 PM UTC 24 |
Sep 11 08:30:01 PM UTC 24 |
274441292 ps |
| T2025 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.231403603 |
|
|
Sep 11 08:28:45 PM UTC 24 |
Sep 11 08:30:02 PM UTC 24 |
2073727498 ps |
| T2026 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.3487396445 |
|
|
Sep 11 08:14:36 PM UTC 24 |
Sep 11 08:30:07 PM UTC 24 |
59927322510 ps |
| T2027 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.1063952541 |
|
|
Sep 11 08:27:00 PM UTC 24 |
Sep 11 08:30:08 PM UTC 24 |
11377454821 ps |
| T2028 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.2207188536 |
|
|
Sep 11 08:29:59 PM UTC 24 |
Sep 11 08:30:11 PM UTC 24 |
172018702 ps |