| T2268 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.233201486 |
|
|
Sep 11 08:46:30 PM UTC 24 |
Sep 11 08:47:01 PM UTC 24 |
380729884 ps |
| T2269 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.1232414991 |
|
|
Sep 11 08:44:32 PM UTC 24 |
Sep 11 08:47:03 PM UTC 24 |
1483632561 ps |
| T2270 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.2757977542 |
|
|
Sep 11 08:46:52 PM UTC 24 |
Sep 11 08:47:03 PM UTC 24 |
178170413 ps |
| T2271 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.1268505106 |
|
|
Sep 11 08:46:24 PM UTC 24 |
Sep 11 08:47:09 PM UTC 24 |
538865656 ps |
| T2272 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.91213317 |
|
|
Sep 11 08:47:01 PM UTC 24 |
Sep 11 08:47:10 PM UTC 24 |
42473778 ps |
| T2273 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.1850145585 |
|
|
Sep 11 08:46:42 PM UTC 24 |
Sep 11 08:47:13 PM UTC 24 |
255461604 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.2445516166 |
|
|
Sep 11 08:38:08 PM UTC 24 |
Sep 11 08:47:18 PM UTC 24 |
9660559540 ps |
| T2274 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.639168683 |
|
|
Sep 11 08:46:31 PM UTC 24 |
Sep 11 08:47:22 PM UTC 24 |
1356590299 ps |
| T2275 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.2061977367 |
|
|
Sep 11 08:41:30 PM UTC 24 |
Sep 11 08:47:24 PM UTC 24 |
20539420908 ps |
| T2276 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.42495064 |
|
|
Sep 11 08:46:44 PM UTC 24 |
Sep 11 08:47:27 PM UTC 24 |
127780079 ps |
| T2277 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.3613004228 |
|
|
Sep 11 08:33:35 PM UTC 24 |
Sep 11 08:47:30 PM UTC 24 |
61158775241 ps |
| T2278 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.2656654449 |
|
|
Sep 11 08:39:10 PM UTC 24 |
Sep 11 08:47:34 PM UTC 24 |
13011296984 ps |
| T2279 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.3913460496 |
|
|
Sep 11 08:33:36 PM UTC 24 |
Sep 11 08:47:35 PM UTC 24 |
71780522790 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.1673896548 |
|
|
Sep 11 08:35:20 PM UTC 24 |
Sep 11 08:47:39 PM UTC 24 |
15010082588 ps |
| T2280 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.3484972171 |
|
|
Sep 11 08:46:12 PM UTC 24 |
Sep 11 08:47:42 PM UTC 24 |
7614513741 ps |
| T2281 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.1824925653 |
|
|
Sep 11 08:43:56 PM UTC 24 |
Sep 11 08:47:47 PM UTC 24 |
15312980393 ps |
| T2282 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.1708665501 |
|
|
Sep 11 08:47:32 PM UTC 24 |
Sep 11 08:47:47 PM UTC 24 |
243801354 ps |
| T2283 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.2522209209 |
|
|
Sep 11 08:45:44 PM UTC 24 |
Sep 11 08:47:51 PM UTC 24 |
3807694251 ps |
| T2284 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.2031887695 |
|
|
Sep 11 08:47:24 PM UTC 24 |
Sep 11 08:47:54 PM UTC 24 |
672625186 ps |
| T2285 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.2893925062 |
|
|
Sep 11 08:47:09 PM UTC 24 |
Sep 11 08:47:57 PM UTC 24 |
479051842 ps |
| T2286 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.2740560564 |
|
|
Sep 11 08:47:52 PM UTC 24 |
Sep 11 08:47:59 PM UTC 24 |
38498613 ps |
| T2287 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.2266874928 |
|
|
Sep 11 08:47:10 PM UTC 24 |
Sep 11 08:47:59 PM UTC 24 |
572737449 ps |
| T2288 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.1131804709 |
|
|
Sep 11 08:47:48 PM UTC 24 |
Sep 11 08:48:00 PM UTC 24 |
205778330 ps |
| T2289 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.774305532 |
|
|
Sep 11 08:47:33 PM UTC 24 |
Sep 11 08:48:08 PM UTC 24 |
305832498 ps |
| T2290 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.3331573368 |
|
|
Sep 11 08:47:23 PM UTC 24 |
Sep 11 08:48:11 PM UTC 24 |
1489791419 ps |
| T2291 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.1881883196 |
|
|
Sep 11 08:37:46 PM UTC 24 |
Sep 11 08:48:12 PM UTC 24 |
41539067091 ps |
| T2292 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.2988551657 |
|
|
Sep 11 08:47:06 PM UTC 24 |
Sep 11 08:48:14 PM UTC 24 |
4990611771 ps |
| T2293 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.1105783532 |
|
|
Sep 11 08:41:57 PM UTC 24 |
Sep 11 08:48:15 PM UTC 24 |
10945911734 ps |
| T2294 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.2519272044 |
|
|
Sep 11 08:46:21 PM UTC 24 |
Sep 11 08:48:19 PM UTC 24 |
6480595952 ps |
| T2295 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.2212055974 |
|
|
Sep 11 08:47:25 PM UTC 24 |
Sep 11 08:48:23 PM UTC 24 |
1676624903 ps |
| T2296 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.154388905 |
|
|
Sep 11 08:48:09 PM UTC 24 |
Sep 11 08:48:25 PM UTC 24 |
91017906 ps |
| T2297 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.119023774 |
|
|
Sep 11 08:47:28 PM UTC 24 |
Sep 11 08:48:25 PM UTC 24 |
1315926366 ps |
| T2298 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.790734070 |
|
|
Sep 11 08:40:39 PM UTC 24 |
Sep 11 08:48:31 PM UTC 24 |
15119366744 ps |
| T2299 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.119716495 |
|
|
Sep 11 08:48:20 PM UTC 24 |
Sep 11 08:48:33 PM UTC 24 |
56315992 ps |
| T2300 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.562782722 |
|
|
Sep 11 08:48:01 PM UTC 24 |
Sep 11 08:48:39 PM UTC 24 |
1192029335 ps |
| T2301 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.2558578100 |
|
|
Sep 11 08:47:02 PM UTC 24 |
Sep 11 08:48:40 PM UTC 24 |
9693781449 ps |
| T2302 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.234727038 |
|
|
Sep 11 08:48:19 PM UTC 24 |
Sep 11 08:48:41 PM UTC 24 |
306477246 ps |
| T2303 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.1591543023 |
|
|
Sep 11 08:48:03 PM UTC 24 |
Sep 11 08:48:42 PM UTC 24 |
418442107 ps |
| T2304 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.2540838074 |
|
|
Sep 11 08:48:15 PM UTC 24 |
Sep 11 08:48:46 PM UTC 24 |
295323067 ps |
| T2305 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.3391255376 |
|
|
Sep 11 08:48:36 PM UTC 24 |
Sep 11 08:48:49 PM UTC 24 |
228336240 ps |
| T2306 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.1317783754 |
|
|
Sep 11 08:48:41 PM UTC 24 |
Sep 11 08:48:51 PM UTC 24 |
46375034 ps |
| T2307 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.1615097993 |
|
|
Sep 11 08:48:23 PM UTC 24 |
Sep 11 08:49:00 PM UTC 24 |
306121478 ps |
| T2308 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.1755456186 |
|
|
Sep 11 08:43:06 PM UTC 24 |
Sep 11 08:49:05 PM UTC 24 |
10274835389 ps |
| T2309 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.2635848571 |
|
|
Sep 11 08:47:55 PM UTC 24 |
Sep 11 08:49:10 PM UTC 24 |
7442903862 ps |
| T2310 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.2253439050 |
|
|
Sep 11 08:49:08 PM UTC 24 |
Sep 11 08:49:19 PM UTC 24 |
83862527 ps |
| T2311 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.2618742357 |
|
|
Sep 11 08:48:17 PM UTC 24 |
Sep 11 08:49:19 PM UTC 24 |
2428729112 ps |
| T2312 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.302943826 |
|
|
Sep 11 08:49:06 PM UTC 24 |
Sep 11 08:49:23 PM UTC 24 |
148236972 ps |
| T2313 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.3219694299 |
|
|
Sep 11 08:41:53 PM UTC 24 |
Sep 11 08:49:24 PM UTC 24 |
1793592603 ps |
| T2314 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.3878327217 |
|
|
Sep 11 08:48:49 PM UTC 24 |
Sep 11 08:49:30 PM UTC 24 |
343962034 ps |
| T2315 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.1653159457 |
|
|
Sep 11 08:48:45 PM UTC 24 |
Sep 11 08:49:30 PM UTC 24 |
3302961671 ps |
| T2316 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.3916436532 |
|
|
Sep 11 08:48:21 PM UTC 24 |
Sep 11 08:49:32 PM UTC 24 |
933276738 ps |
| T2317 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.2704632441 |
|
|
Sep 11 08:49:10 PM UTC 24 |
Sep 11 08:49:35 PM UTC 24 |
392939706 ps |
| T2318 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.3480335564 |
|
|
Sep 11 08:46:46 PM UTC 24 |
Sep 11 08:49:41 PM UTC 24 |
573256147 ps |
| T2319 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.2372941299 |
|
|
Sep 11 08:48:35 PM UTC 24 |
Sep 11 08:49:42 PM UTC 24 |
158528345 ps |
| T2320 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.1199794795 |
|
|
Sep 11 08:48:45 PM UTC 24 |
Sep 11 08:49:46 PM UTC 24 |
556373767 ps |
| T2321 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.1467588060 |
|
|
Sep 11 08:49:33 PM UTC 24 |
Sep 11 08:49:47 PM UTC 24 |
212591891 ps |
| T2322 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.2727265437 |
|
|
Sep 11 08:19:35 PM UTC 24 |
Sep 11 08:49:47 PM UTC 24 |
107710373825 ps |
| T2323 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.582324002 |
|
|
Sep 11 08:47:49 PM UTC 24 |
Sep 11 08:49:50 PM UTC 24 |
531887096 ps |
| T2324 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.974954474 |
|
|
Sep 11 08:49:42 PM UTC 24 |
Sep 11 08:49:52 PM UTC 24 |
53507133 ps |
| T2325 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.3550736808 |
|
|
Sep 11 08:48:41 PM UTC 24 |
Sep 11 08:49:52 PM UTC 24 |
6944521032 ps |
| T2326 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.4177295316 |
|
|
Sep 11 08:21:26 PM UTC 24 |
Sep 11 08:49:55 PM UTC 24 |
118351277434 ps |
| T2327 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.3481248310 |
|
|
Sep 11 08:47:58 PM UTC 24 |
Sep 11 08:49:59 PM UTC 24 |
6611500179 ps |
| T2328 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.1574393148 |
|
|
Sep 11 08:49:59 PM UTC 24 |
Sep 11 08:50:13 PM UTC 24 |
282638191 ps |
| T2329 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.2634638719 |
|
|
Sep 11 08:49:07 PM UTC 24 |
Sep 11 08:50:14 PM UTC 24 |
2092079516 ps |
| T2330 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.2389585706 |
|
|
Sep 11 08:49:53 PM UTC 24 |
Sep 11 08:50:14 PM UTC 24 |
197742206 ps |
| T2331 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.4080090305 |
|
|
Sep 11 08:48:58 PM UTC 24 |
Sep 11 08:50:21 PM UTC 24 |
2470045190 ps |
| T2332 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.3936618994 |
|
|
Sep 11 08:49:50 PM UTC 24 |
Sep 11 08:50:22 PM UTC 24 |
333735583 ps |
| T2333 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.3425724384 |
|
|
Sep 11 08:49:56 PM UTC 24 |
Sep 11 08:50:24 PM UTC 24 |
2021720400 ps |
| T2334 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.3478105704 |
|
|
Sep 11 08:48:11 PM UTC 24 |
Sep 11 08:50:29 PM UTC 24 |
8191780143 ps |
| T2335 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.3049796317 |
|
|
Sep 11 08:50:24 PM UTC 24 |
Sep 11 08:50:36 PM UTC 24 |
248077442 ps |
| T2336 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.1719802074 |
|
|
Sep 11 08:50:11 PM UTC 24 |
Sep 11 08:50:37 PM UTC 24 |
717344331 ps |
| T2337 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.3530192193 |
|
|
Sep 11 08:22:49 PM UTC 24 |
Sep 11 08:50:41 PM UTC 24 |
102678380179 ps |
| T2338 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.1965909314 |
|
|
Sep 11 08:50:07 PM UTC 24 |
Sep 11 08:50:46 PM UTC 24 |
1241802449 ps |
| T2339 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.762372565 |
|
|
Sep 11 08:48:29 PM UTC 24 |
Sep 11 08:50:46 PM UTC 24 |
1775510923 ps |
| T2340 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.2675754904 |
|
|
Sep 11 08:50:36 PM UTC 24 |
Sep 11 08:50:46 PM UTC 24 |
58120441 ps |
| T2341 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.2113790557 |
|
|
Sep 11 08:44:34 PM UTC 24 |
Sep 11 08:50:46 PM UTC 24 |
11210026730 ps |
| T2342 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.521132707 |
|
|
Sep 11 08:50:09 PM UTC 24 |
Sep 11 08:50:49 PM UTC 24 |
435483909 ps |
| T2343 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.1672834889 |
|
|
Sep 11 08:45:25 PM UTC 24 |
Sep 11 08:50:53 PM UTC 24 |
31369104814 ps |
| T2344 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.4018371716 |
|
|
Sep 11 08:51:22 PM UTC 24 |
Sep 11 08:51:32 PM UTC 24 |
49431647 ps |
| T2345 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.3100281305 |
|
|
Sep 11 08:46:45 PM UTC 24 |
Sep 11 08:50:55 PM UTC 24 |
3590651020 ps |
| T2346 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.900473342 |
|
|
Sep 11 08:50:08 PM UTC 24 |
Sep 11 08:50:55 PM UTC 24 |
908145400 ps |
| T2347 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.549404977 |
|
|
Sep 11 08:45:24 PM UTC 24 |
Sep 11 08:50:59 PM UTC 24 |
20291171799 ps |
| T2348 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.2635081585 |
|
|
Sep 11 08:50:47 PM UTC 24 |
Sep 11 08:51:01 PM UTC 24 |
127166491 ps |
| T2349 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.1744880354 |
|
|
Sep 11 08:46:42 PM UTC 24 |
Sep 11 08:51:02 PM UTC 24 |
3280543246 ps |
| T2350 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.2257076941 |
|
|
Sep 11 08:51:06 PM UTC 24 |
Sep 11 08:51:12 PM UTC 24 |
24780841 ps |
| T2351 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.877611543 |
|
|
Sep 11 08:50:39 PM UTC 24 |
Sep 11 08:51:21 PM UTC 24 |
1065252468 ps |
| T2352 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.1115265159 |
|
|
Sep 11 08:49:46 PM UTC 24 |
Sep 11 08:51:27 PM UTC 24 |
6124048601 ps |
| T2353 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.3540203297 |
|
|
Sep 11 08:50:18 PM UTC 24 |
Sep 11 08:51:27 PM UTC 24 |
1094569116 ps |
| T2354 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.3455065413 |
|
|
Sep 11 08:50:56 PM UTC 24 |
Sep 11 08:51:29 PM UTC 24 |
221058228 ps |
| T2355 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.1716923948 |
|
|
Sep 11 08:49:31 PM UTC 24 |
Sep 11 08:51:29 PM UTC 24 |
551027021 ps |
| T2356 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.3179554907 |
|
|
Sep 11 08:51:18 PM UTC 24 |
Sep 11 08:51:30 PM UTC 24 |
142002991 ps |
| T2357 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.759118687 |
|
|
Sep 11 08:49:47 PM UTC 24 |
Sep 11 08:51:38 PM UTC 24 |
5367228331 ps |
| T2358 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.2522522314 |
|
|
Sep 11 08:51:08 PM UTC 24 |
Sep 11 08:51:51 PM UTC 24 |
1273175045 ps |
| T2359 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.2778962075 |
|
|
Sep 11 08:51:03 PM UTC 24 |
Sep 11 08:51:55 PM UTC 24 |
2151085743 ps |
| T2360 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.3784430767 |
|
|
Sep 11 08:50:36 PM UTC 24 |
Sep 11 08:52:07 PM UTC 24 |
8863429761 ps |
| T2361 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.2950483092 |
|
|
Sep 11 08:50:38 PM UTC 24 |
Sep 11 08:52:13 PM UTC 24 |
6801245205 ps |
| T2362 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.1884252164 |
|
|
Sep 11 08:51:08 PM UTC 24 |
Sep 11 08:52:15 PM UTC 24 |
2097298904 ps |
| T2363 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.3854227828 |
|
|
Sep 11 08:50:17 PM UTC 24 |
Sep 11 08:52:24 PM UTC 24 |
300175449 ps |
| T2364 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.918695158 |
|
|
Sep 11 08:51:44 PM UTC 24 |
Sep 11 08:52:29 PM UTC 24 |
369591161 ps |
| T2365 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.675013379 |
|
|
Sep 11 08:51:56 PM UTC 24 |
Sep 11 08:52:34 PM UTC 24 |
818865203 ps |
| T2366 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.1000366931 |
|
|
Sep 11 08:51:54 PM UTC 24 |
Sep 11 08:52:42 PM UTC 24 |
1535976912 ps |
| T2367 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.2440772888 |
|
|
Sep 11 08:51:59 PM UTC 24 |
Sep 11 08:52:44 PM UTC 24 |
278224547 ps |
| T2368 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.845705271 |
|
|
Sep 11 08:48:58 PM UTC 24 |
Sep 11 08:52:47 PM UTC 24 |
11518647671 ps |
| T2369 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.1106714131 |
|
|
Sep 11 08:51:38 PM UTC 24 |
Sep 11 08:52:52 PM UTC 24 |
1935451198 ps |
| T2370 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.3547590147 |
|
|
Sep 11 08:51:23 PM UTC 24 |
Sep 11 08:52:52 PM UTC 24 |
8652731333 ps |
| T2371 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.898837558 |
|
|
Sep 11 08:51:55 PM UTC 24 |
Sep 11 08:53:00 PM UTC 24 |
1367384764 ps |
| T2372 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.3871984735 |
|
|
Sep 11 08:52:49 PM UTC 24 |
Sep 11 08:53:04 PM UTC 24 |
230193958 ps |
| T2373 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.4189764956 |
|
|
Sep 11 08:52:56 PM UTC 24 |
Sep 11 08:53:06 PM UTC 24 |
49755521 ps |
| T2374 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.977817996 |
|
|
Sep 11 08:52:17 PM UTC 24 |
Sep 11 08:53:11 PM UTC 24 |
1219270566 ps |
| T2375 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.2013055291 |
|
|
Sep 11 08:51:26 PM UTC 24 |
Sep 11 08:53:15 PM UTC 24 |
5557705526 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.528042208 |
|
|
Sep 11 08:45:47 PM UTC 24 |
Sep 11 08:53:16 PM UTC 24 |
7328551538 ps |
| T2376 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.1441720849 |
|
|
Sep 11 08:47:37 PM UTC 24 |
Sep 11 08:53:34 PM UTC 24 |
2228091320 ps |
| T2377 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.2221207109 |
|
|
Sep 11 08:43:06 PM UTC 24 |
Sep 11 08:53:35 PM UTC 24 |
9986847736 ps |
| T2378 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.2624134100 |
|
|
Sep 11 08:50:50 PM UTC 24 |
Sep 11 08:53:42 PM UTC 24 |
13031214124 ps |
| T2379 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.2171406464 |
|
|
Sep 11 08:53:12 PM UTC 24 |
Sep 11 08:53:53 PM UTC 24 |
356411730 ps |
| T2380 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.4012591784 |
|
|
Sep 11 08:53:32 PM UTC 24 |
Sep 11 08:53:55 PM UTC 24 |
166021001 ps |
| T2381 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.938953654 |
|
|
Sep 11 08:53:41 PM UTC 24 |
Sep 11 08:53:56 PM UTC 24 |
328322662 ps |
| T2382 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.264039716 |
|
|
Sep 11 08:51:13 PM UTC 24 |
Sep 11 08:53:58 PM UTC 24 |
393057461 ps |
| T2383 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.1068741497 |
|
|
Sep 11 08:52:58 PM UTC 24 |
Sep 11 08:54:03 PM UTC 24 |
7285794707 ps |
| T2384 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.3753697210 |
|
|
Sep 11 08:46:02 PM UTC 24 |
Sep 11 08:54:08 PM UTC 24 |
15050795046 ps |
| T2385 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.4053779218 |
|
|
Sep 11 08:53:37 PM UTC 24 |
Sep 11 08:54:16 PM UTC 24 |
779839182 ps |
| T2386 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.3755541845 |
|
|
Sep 11 08:52:38 PM UTC 24 |
Sep 11 08:54:16 PM UTC 24 |
1344461555 ps |
| T2387 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.2357428678 |
|
|
Sep 11 08:53:43 PM UTC 24 |
Sep 11 08:54:19 PM UTC 24 |
693988455 ps |
| T2388 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.3591424526 |
|
|
Sep 11 08:53:27 PM UTC 24 |
Sep 11 08:54:21 PM UTC 24 |
2596789247 ps |
| T2389 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.1358079903 |
|
|
Sep 11 08:53:09 PM UTC 24 |
Sep 11 08:54:26 PM UTC 24 |
1888329870 ps |
| T2390 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.1557131279 |
|
|
Sep 11 08:47:44 PM UTC 24 |
Sep 11 08:54:26 PM UTC 24 |
12153689968 ps |
| T2391 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.390559585 |
|
|
Sep 11 08:54:23 PM UTC 24 |
Sep 11 08:54:30 PM UTC 24 |
39938030 ps |
| T2392 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.1333552528 |
|
|
Sep 11 08:54:20 PM UTC 24 |
Sep 11 08:54:32 PM UTC 24 |
231653482 ps |
| T2393 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.1713171178 |
|
|
Sep 11 08:50:15 PM UTC 24 |
Sep 11 08:54:32 PM UTC 24 |
3757590698 ps |
| T2394 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.3099785142 |
|
|
Sep 11 08:53:05 PM UTC 24 |
Sep 11 08:54:40 PM UTC 24 |
4532133710 ps |
| T2395 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.4115854730 |
|
|
Sep 11 08:49:15 PM UTC 24 |
Sep 11 08:54:46 PM UTC 24 |
3498454914 ps |
| T2396 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.1603480576 |
|
|
Sep 11 08:53:26 PM UTC 24 |
Sep 11 08:54:46 PM UTC 24 |
1693355228 ps |
| T2397 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.2670140691 |
|
|
Sep 11 08:51:17 PM UTC 24 |
Sep 11 08:54:54 PM UTC 24 |
2500096543 ps |
| T2398 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.208188577 |
|
|
Sep 11 08:54:58 PM UTC 24 |
Sep 11 08:55:09 PM UTC 24 |
81773032 ps |
| T2399 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.2575269637 |
|
|
Sep 11 08:40:17 PM UTC 24 |
Sep 11 08:55:17 PM UTC 24 |
50323429684 ps |
| T2400 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.1643117001 |
|
|
Sep 11 08:54:01 PM UTC 24 |
Sep 11 08:55:20 PM UTC 24 |
2462102678 ps |
| T2401 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.2172637461 |
|
|
Sep 11 08:54:25 PM UTC 24 |
Sep 11 08:55:23 PM UTC 24 |
5449060138 ps |
| T2402 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.2417499375 |
|
|
Sep 11 08:54:40 PM UTC 24 |
Sep 11 08:55:23 PM UTC 24 |
442589838 ps |
| T2403 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.902827163 |
|
|
Sep 11 08:50:21 PM UTC 24 |
Sep 11 08:55:37 PM UTC 24 |
5551078404 ps |
| T2404 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.2684144487 |
|
|
Sep 11 08:54:50 PM UTC 24 |
Sep 11 08:55:38 PM UTC 24 |
1510097394 ps |
| T2405 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.2172195300 |
|
|
Sep 11 08:54:56 PM UTC 24 |
Sep 11 08:55:38 PM UTC 24 |
494212408 ps |
| T2406 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.1123869921 |
|
|
Sep 11 08:54:58 PM UTC 24 |
Sep 11 08:55:46 PM UTC 24 |
812553860 ps |
| T2407 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.784828628 |
|
|
Sep 11 08:55:35 PM UTC 24 |
Sep 11 08:55:46 PM UTC 24 |
55819268 ps |
| T2408 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.54884847 |
|
|
Sep 11 08:51:12 PM UTC 24 |
Sep 11 08:55:46 PM UTC 24 |
2953894097 ps |
| T2409 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.179943745 |
|
|
Sep 11 08:48:04 PM UTC 24 |
Sep 11 08:55:49 PM UTC 24 |
28991095464 ps |
| T2410 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.1469854227 |
|
|
Sep 11 08:55:43 PM UTC 24 |
Sep 11 08:55:51 PM UTC 24 |
41507474 ps |
| T2411 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.3117526968 |
|
|
Sep 11 08:54:46 PM UTC 24 |
Sep 11 08:55:59 PM UTC 24 |
1884958469 ps |
| T2412 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.229307633 |
|
|
Sep 11 08:54:29 PM UTC 24 |
Sep 11 08:56:03 PM UTC 24 |
5418374645 ps |
| T2413 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.3723651439 |
|
|
Sep 11 08:55:49 PM UTC 24 |
Sep 11 08:56:07 PM UTC 24 |
390758049 ps |
| T2414 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.2093493076 |
|
|
Sep 11 08:54:35 PM UTC 24 |
Sep 11 08:56:20 PM UTC 24 |
2561503189 ps |
| T2415 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.2440793803 |
|
|
Sep 11 08:56:07 PM UTC 24 |
Sep 11 08:56:21 PM UTC 24 |
74586174 ps |
| T2416 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.1968039925 |
|
|
Sep 11 08:56:11 PM UTC 24 |
Sep 11 08:56:22 PM UTC 24 |
38012244 ps |
| T2417 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.1267929161 |
|
|
Sep 11 08:56:15 PM UTC 24 |
Sep 11 08:56:26 PM UTC 24 |
61255711 ps |
| T2418 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.3274120821 |
|
|
Sep 11 08:52:42 PM UTC 24 |
Sep 11 08:56:31 PM UTC 24 |
975468957 ps |
| T2419 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.3762359654 |
|
|
Sep 11 08:55:59 PM UTC 24 |
Sep 11 08:56:46 PM UTC 24 |
539041368 ps |
| T2420 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.3579583563 |
|
|
Sep 11 08:56:32 PM UTC 24 |
Sep 11 08:56:47 PM UTC 24 |
19232310 ps |
| T2421 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.47520147 |
|
|
Sep 11 08:56:24 PM UTC 24 |
Sep 11 08:56:49 PM UTC 24 |
197238669 ps |
| T2422 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.2641728426 |
|
|
Sep 11 08:54:08 PM UTC 24 |
Sep 11 08:56:52 PM UTC 24 |
2767524211 ps |
| T2423 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.299505347 |
|
|
Sep 11 08:56:14 PM UTC 24 |
Sep 11 08:56:56 PM UTC 24 |
832854576 ps |
| T2424 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.1495732526 |
|
|
Sep 11 08:56:48 PM UTC 24 |
Sep 11 08:56:57 PM UTC 24 |
50332635 ps |
| T2425 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.4197724322 |
|
|
Sep 11 08:56:48 PM UTC 24 |
Sep 11 08:56:58 PM UTC 24 |
37632372 ps |
| T2426 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.3954049896 |
|
|
Sep 11 08:46:28 PM UTC 24 |
Sep 11 08:57:01 PM UTC 24 |
48410278594 ps |
| T2427 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.446474857 |
|
|
Sep 11 08:36:15 PM UTC 24 |
Sep 11 08:57:04 PM UTC 24 |
98722129923 ps |
| T2428 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.4013057391 |
|
|
Sep 11 08:52:21 PM UTC 24 |
Sep 11 08:57:18 PM UTC 24 |
4304579028 ps |
| T2429 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.414710341 |
|
|
Sep 11 08:37:45 PM UTC 24 |
Sep 11 08:57:21 PM UTC 24 |
109764868493 ps |
| T2430 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.1025666167 |
|
|
Sep 11 08:55:49 PM UTC 24 |
Sep 11 08:57:24 PM UTC 24 |
4320449293 ps |
| T2431 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.1797435088 |
|
|
Sep 11 08:51:15 PM UTC 24 |
Sep 11 08:57:25 PM UTC 24 |
11210515531 ps |
| T2432 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.777992661 |
|
|
Sep 11 08:42:49 PM UTC 24 |
Sep 11 08:57:39 PM UTC 24 |
47829309776 ps |
| T2433 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.1022449011 |
|
|
Sep 11 08:55:03 PM UTC 24 |
Sep 11 08:57:47 PM UTC 24 |
1944052925 ps |
| T2434 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.3409902708 |
|
|
Sep 11 08:56:04 PM UTC 24 |
Sep 11 08:57:49 PM UTC 24 |
8233681355 ps |
| T2435 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.2521247823 |
|
|
Sep 11 08:55:46 PM UTC 24 |
Sep 11 08:57:56 PM UTC 24 |
8464217767 ps |
| T2436 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.592751238 |
|
|
Sep 11 08:57:13 PM UTC 24 |
Sep 11 08:57:59 PM UTC 24 |
588852858 ps |
| T2437 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.3334506464 |
|
|
Sep 11 08:57:19 PM UTC 24 |
Sep 11 08:58:00 PM UTC 24 |
700438547 ps |
| T2438 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.4148482987 |
|
|
Sep 11 08:46:25 PM UTC 24 |
Sep 11 08:58:01 PM UTC 24 |
69316417408 ps |
| T2439 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.3097560066 |
|
|
Sep 11 08:57:27 PM UTC 24 |
Sep 11 08:58:05 PM UTC 24 |
851923683 ps |
| T2440 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.2931921518 |
|
|
Sep 11 08:57:30 PM UTC 24 |
Sep 11 08:58:06 PM UTC 24 |
397712907 ps |
| T2441 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.2915367828 |
|
|
Sep 11 08:40:04 PM UTC 24 |
Sep 11 08:58:06 PM UTC 24 |
107213198080 ps |
| T2442 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.3086208624 |
|
|
Sep 11 08:57:44 PM UTC 24 |
Sep 11 08:58:10 PM UTC 24 |
142246449 ps |
| T2443 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.1410374395 |
|
|
Sep 11 08:57:08 PM UTC 24 |
Sep 11 08:58:12 PM UTC 24 |
4044583251 ps |
| T2444 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.289829232 |
|
|
Sep 11 08:28:14 PM UTC 24 |
Sep 11 08:58:15 PM UTC 24 |
128851819829 ps |
| T2445 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.3385767544 |
|
|
Sep 11 08:57:12 PM UTC 24 |
Sep 11 08:58:18 PM UTC 24 |
2189862440 ps |
| T2446 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.3221095790 |
|
|
Sep 11 08:57:44 PM UTC 24 |
Sep 11 08:58:20 PM UTC 24 |
718021679 ps |
| T2447 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.3837147760 |
|
|
Sep 11 08:43:52 PM UTC 24 |
Sep 11 08:58:21 PM UTC 24 |
80784923479 ps |
| T2448 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.1117942790 |
|
|
Sep 11 08:56:57 PM UTC 24 |
Sep 11 08:58:22 PM UTC 24 |
7689792008 ps |
| T2449 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.3485889220 |
|
|
Sep 11 08:58:14 PM UTC 24 |
Sep 11 08:58:23 PM UTC 24 |
50318961 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.1795014023 |
|
|
Sep 11 08:49:26 PM UTC 24 |
Sep 11 08:58:29 PM UTC 24 |
15357819699 ps |
| T2450 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.2162776700 |
|
|
Sep 11 08:58:20 PM UTC 24 |
Sep 11 08:58:29 PM UTC 24 |
40475450 ps |
| T2451 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.1489274908 |
|
|
Sep 11 08:54:00 PM UTC 24 |
Sep 11 08:58:30 PM UTC 24 |
7578304630 ps |
| T2452 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.2618614455 |
|
|
Sep 11 08:47:24 PM UTC 24 |
Sep 11 08:58:38 PM UTC 24 |
47681575004 ps |
| T2453 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.2611298428 |
|
|
Sep 11 08:47:21 PM UTC 24 |
Sep 11 08:58:44 PM UTC 24 |
46393641733 ps |
| T2454 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.2825095302 |
|
|
Sep 11 08:48:06 PM UTC 24 |
Sep 11 08:58:51 PM UTC 24 |
52895181682 ps |
| T2455 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.3286654170 |
|
|
Sep 11 08:58:38 PM UTC 24 |
Sep 11 08:58:52 PM UTC 24 |
112377312 ps |
| T2456 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.3251845466 |
|
|
Sep 11 08:57:24 PM UTC 24 |
Sep 11 08:58:52 PM UTC 24 |
5365989279 ps |
| T2457 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.3980142539 |
|
|
Sep 11 08:54:52 PM UTC 24 |
Sep 11 08:58:53 PM UTC 24 |
16024362226 ps |
| T2458 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.1014020128 |
|
|
Sep 11 08:48:51 PM UTC 24 |
Sep 11 08:58:57 PM UTC 24 |
56984300529 ps |
| T2459 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.1844881567 |
|
|
Sep 11 08:58:40 PM UTC 24 |
Sep 11 08:58:57 PM UTC 24 |
439841628 ps |
| T2460 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.4214743040 |
|
|
Sep 11 08:57:21 PM UTC 24 |
Sep 11 08:59:04 PM UTC 24 |
5754654883 ps |
| T2461 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.2751930185 |
|
|
Sep 11 08:58:56 PM UTC 24 |
Sep 11 08:59:04 PM UTC 24 |
44548460 ps |
| T2462 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.2940614267 |
|
|
Sep 11 08:50:07 PM UTC 24 |
Sep 11 08:59:04 PM UTC 24 |
30902608121 ps |
| T2463 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.2624422321 |
|
|
Sep 11 08:54:20 PM UTC 24 |
Sep 11 08:59:05 PM UTC 24 |
5049489926 ps |
| T2464 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.3352385465 |
|
|
Sep 11 08:58:29 PM UTC 24 |
Sep 11 08:59:06 PM UTC 24 |
424768204 ps |
| T2465 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.2782011462 |
|
|
Sep 11 08:59:02 PM UTC 24 |
Sep 11 08:59:13 PM UTC 24 |
55677654 ps |
| T2466 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.699222261 |
|
|
Sep 11 09:06:23 PM UTC 24 |
Sep 11 09:06:33 PM UTC 24 |
43649301 ps |
| T2467 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.1527317747 |
|
|
Sep 11 08:58:42 PM UTC 24 |
Sep 11 08:59:14 PM UTC 24 |
240520480 ps |
| T2468 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.213081339 |
|
|
Sep 11 08:49:11 PM UTC 24 |
Sep 11 08:59:22 PM UTC 24 |
17704063450 ps |
| T2469 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.1577265189 |
|
|
Sep 11 08:58:42 PM UTC 24 |
Sep 11 08:59:29 PM UTC 24 |
1274565216 ps |
| T2470 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.2069854311 |
|
|
Sep 11 08:59:16 PM UTC 24 |
Sep 11 08:59:29 PM UTC 24 |
110185380 ps |
| T2471 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.2087160423 |
|
|
Sep 11 08:56:41 PM UTC 24 |
Sep 11 08:59:33 PM UTC 24 |
372360866 ps |
| T2472 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.1877661800 |
|
|
Sep 11 08:58:24 PM UTC 24 |
Sep 11 08:59:33 PM UTC 24 |
1389457636 ps |
| T2473 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.1578704502 |
|
|
Sep 11 08:58:21 PM UTC 24 |
Sep 11 08:59:43 PM UTC 24 |
7479590455 ps |
| T2474 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.4266572246 |
|
|
Sep 11 08:59:17 PM UTC 24 |
Sep 11 08:59:44 PM UTC 24 |
203552041 ps |
| T2475 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.3547797934 |
|
|
Sep 11 08:37:49 PM UTC 24 |
Sep 11 08:59:45 PM UTC 24 |
94273769646 ps |
| T2476 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.3778710046 |
|
|
Sep 11 08:55:16 PM UTC 24 |
Sep 11 08:59:51 PM UTC 24 |
988331500 ps |
| T2477 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.618461330 |
|
|
Sep 11 08:51:52 PM UTC 24 |
Sep 11 08:59:52 PM UTC 24 |
33460574950 ps |
| T2478 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.1135440894 |
|
|
Sep 11 08:59:24 PM UTC 24 |
Sep 11 08:59:54 PM UTC 24 |
220377692 ps |
| T2479 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.3599281295 |
|
|
Sep 11 08:58:34 PM UTC 24 |
Sep 11 08:59:57 PM UTC 24 |
2094616032 ps |
| T2480 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.181413580 |
|
|
Sep 11 08:59:27 PM UTC 24 |
Sep 11 09:00:02 PM UTC 24 |
1056545716 ps |
| T2481 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.2298087372 |
|
|
Sep 11 08:59:52 PM UTC 24 |
Sep 11 09:00:02 PM UTC 24 |
45696904 ps |
| T2482 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.260962712 |
|
|
Sep 11 08:58:26 PM UTC 24 |
Sep 11 09:00:02 PM UTC 24 |
4811913620 ps |
| T2483 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.3106146019 |
|
|
Sep 11 08:59:24 PM UTC 24 |
Sep 11 09:00:06 PM UTC 24 |
1572185348 ps |
| T2484 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.3546196977 |
|
|
Sep 11 08:59:58 PM UTC 24 |
Sep 11 09:00:08 PM UTC 24 |
55646341 ps |
| T2485 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.3834473306 |
|
|
Sep 11 08:49:55 PM UTC 24 |
Sep 11 09:00:08 PM UTC 24 |
39441938834 ps |
| T2486 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.1709542269 |
|
|
Sep 11 08:58:47 PM UTC 24 |
Sep 11 09:00:13 PM UTC 24 |
325232102 ps |
| T2487 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.489647419 |
|
|
Sep 11 08:59:09 PM UTC 24 |
Sep 11 09:00:16 PM UTC 24 |
7082641289 ps |
| T2488 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.2067084202 |
|
|
Sep 11 08:59:21 PM UTC 24 |
Sep 11 09:00:26 PM UTC 24 |
878733619 ps |
| T2489 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.882014331 |
|
|
Sep 11 09:00:04 PM UTC 24 |
Sep 11 09:00:30 PM UTC 24 |
268534828 ps |
| T2490 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.1854285051 |
|
|
Sep 11 08:58:04 PM UTC 24 |
Sep 11 09:00:35 PM UTC 24 |
2362467776 ps |
| T2491 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.1489418733 |
|
|
Sep 11 08:59:29 PM UTC 24 |
Sep 11 09:00:35 PM UTC 24 |
2027685528 ps |
| T2492 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.1356843798 |
|
|
Sep 11 08:58:13 PM UTC 24 |
Sep 11 09:00:37 PM UTC 24 |
209561777 ps |
| T2493 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.394481351 |
|
|
Sep 11 09:00:31 PM UTC 24 |
Sep 11 09:00:47 PM UTC 24 |
377461359 ps |
| T2494 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.1551013659 |
|
|
Sep 11 08:25:28 PM UTC 24 |
Sep 11 09:00:52 PM UTC 24 |
125943150334 ps |
| T2495 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.701805685 |
|
|
Sep 11 09:00:09 PM UTC 24 |
Sep 11 09:00:56 PM UTC 24 |
510629895 ps |
| T2496 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.311352473 |
|
|
Sep 11 08:47:17 PM UTC 24 |
Sep 11 09:00:58 PM UTC 24 |
75961371445 ps |
| T2497 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.1157300971 |
|
|
Sep 11 09:00:29 PM UTC 24 |
Sep 11 09:01:02 PM UTC 24 |
297731514 ps |
| T2498 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.1363820604 |
|
|
Sep 11 09:00:52 PM UTC 24 |
Sep 11 09:01:02 PM UTC 24 |
178358355 ps |
| T2499 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.1768276627 |
|
|
Sep 11 09:00:54 PM UTC 24 |
Sep 11 09:01:04 PM UTC 24 |
46660929 ps |
| T2500 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.1484049710 |
|
|
Sep 11 08:59:56 PM UTC 24 |
Sep 11 09:01:05 PM UTC 24 |
7357809636 ps |
| T2501 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.2288050422 |
|
|
Sep 11 09:00:30 PM UTC 24 |
Sep 11 09:01:12 PM UTC 24 |
1400064996 ps |
| T2502 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.3511179786 |
|
|
Sep 11 08:57:51 PM UTC 24 |
Sep 11 09:01:13 PM UTC 24 |
2416837368 ps |
| T2503 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.3010254046 |
|
|
Sep 11 08:59:36 PM UTC 24 |
Sep 11 09:01:14 PM UTC 24 |
223563941 ps |
| T2504 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.3585414252 |
|
|
Sep 11 09:00:25 PM UTC 24 |
Sep 11 09:01:16 PM UTC 24 |
1470400645 ps |
| T2505 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.800245619 |
|
|
Sep 11 09:00:06 PM UTC 24 |
Sep 11 09:01:16 PM UTC 24 |
4734807893 ps |
| T2506 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.3842049413 |
|
|
Sep 11 08:55:12 PM UTC 24 |
Sep 11 09:01:23 PM UTC 24 |
5093507044 ps |
| T2507 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.3006541294 |
|
|
Sep 11 08:50:50 PM UTC 24 |
Sep 11 09:01:29 PM UTC 24 |
65324444891 ps |
| T2508 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.3277669562 |
|
|
Sep 11 08:59:13 PM UTC 24 |
Sep 11 09:01:32 PM UTC 24 |
6088792958 ps |
| T2509 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.759578503 |
|
|
Sep 11 09:00:39 PM UTC 24 |
Sep 11 09:01:33 PM UTC 24 |
191221423 ps |
| T2510 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.1320232633 |
|
|
Sep 11 09:01:26 PM UTC 24 |
Sep 11 09:01:36 PM UTC 24 |
157404688 ps |
| T2511 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.1023720649 |
|
|
Sep 11 09:01:12 PM UTC 24 |
Sep 11 09:01:41 PM UTC 24 |
248329988 ps |
| T2512 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.3558139397 |
|
|
Sep 11 08:59:32 PM UTC 24 |
Sep 11 09:01:43 PM UTC 24 |
3853201157 ps |
| T2513 |
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.3740339891 |
|
|
Sep 11 09:01:38 PM UTC 24 |
Sep 11 09:01:47 PM UTC 24 |
22034952 ps |