| T943 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_smoketest.1510065035 |
|
|
Sep 19 02:00:37 AM UTC 24 |
Sep 19 02:05:59 AM UTC 24 |
3362073430 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.891955992 |
|
|
Sep 19 12:59:54 AM UTC 24 |
Sep 19 02:06:10 AM UTC 24 |
15346541880 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_manufacturer.11321250 |
|
|
Sep 19 02:01:29 AM UTC 24 |
Sep 19 02:06:24 AM UTC 24 |
2482027380 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_smoketest.351475295 |
|
|
Sep 19 01:56:45 AM UTC 24 |
Sep 19 02:06:25 AM UTC 24 |
6727376328 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3939414278 |
|
|
Sep 19 01:02:04 AM UTC 24 |
Sep 19 02:07:12 AM UTC 24 |
14612134729 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2207621954 |
|
|
Sep 19 01:01:07 AM UTC 24 |
Sep 19 02:07:34 AM UTC 24 |
15505975995 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1675996345 |
|
|
Sep 19 01:02:03 AM UTC 24 |
Sep 19 02:08:08 AM UTC 24 |
15022778640 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.519324466 |
|
|
Sep 19 12:58:11 AM UTC 24 |
Sep 19 02:08:42 AM UTC 24 |
15280666338 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sival_flash_info_access.1028779921 |
|
|
Sep 19 02:03:26 AM UTC 24 |
Sep 19 02:08:43 AM UTC 24 |
3109202540 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2929314515 |
|
|
Sep 19 12:55:33 AM UTC 24 |
Sep 19 02:09:26 AM UTC 24 |
14486965700 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.1374665371 |
|
|
Sep 19 12:09:07 AM UTC 24 |
Sep 19 02:09:31 AM UTC 24 |
51130922500 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2604626729 |
|
|
Sep 19 12:58:47 AM UTC 24 |
Sep 19 02:09:35 AM UTC 24 |
15693759814 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pattgen_ios.3790163109 |
|
|
Sep 19 02:05:14 AM UTC 24 |
Sep 19 02:09:55 AM UTC 24 |
2763337100 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3396428930 |
|
|
Sep 19 12:57:27 AM UTC 24 |
Sep 19 02:10:07 AM UTC 24 |
15208675810 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.1381474505 |
|
|
Sep 19 02:06:17 AM UTC 24 |
Sep 19 02:10:28 AM UTC 24 |
3866033720 ps |
| T25 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.3743527849 |
|
|
Sep 19 02:06:01 AM UTC 24 |
Sep 19 02:10:57 AM UTC 24 |
2975682822 ps |
| T39 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1043174068 |
|
|
Sep 19 02:05:54 AM UTC 24 |
Sep 19 02:11:19 AM UTC 24 |
2899075428 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1502896436 |
|
|
Sep 19 12:57:42 AM UTC 24 |
Sep 19 02:11:23 AM UTC 24 |
15606200320 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_tpm.1629810286 |
|
|
Sep 19 02:08:54 AM UTC 24 |
Sep 19 02:13:39 AM UTC 24 |
2908160743 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.3836512662 |
|
|
Sep 19 02:09:39 AM UTC 24 |
Sep 19 02:14:09 AM UTC 24 |
3429476699 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1838299675 |
|
|
Sep 19 12:58:08 AM UTC 24 |
Sep 19 02:14:10 AM UTC 24 |
15395304568 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx.599207013 |
|
|
Sep 19 02:05:58 AM UTC 24 |
Sep 19 02:14:35 AM UTC 24 |
4143361996 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx2.3125037135 |
|
|
Sep 19 02:05:58 AM UTC 24 |
Sep 19 02:15:42 AM UTC 24 |
4157433220 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1980033817 |
|
|
Sep 19 02:03:53 AM UTC 24 |
Sep 19 02:15:53 AM UTC 24 |
6406438172 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.4041235263 |
|
|
Sep 19 02:09:38 AM UTC 24 |
Sep 19 02:16:14 AM UTC 24 |
3022157090 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.1069522260 |
|
|
Sep 19 02:03:39 AM UTC 24 |
Sep 19 02:16:23 AM UTC 24 |
5763595960 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3124125386 |
|
|
Sep 19 02:07:21 AM UTC 24 |
Sep 19 02:16:47 AM UTC 24 |
4629829307 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx3.1276280095 |
|
|
Sep 19 02:06:02 AM UTC 24 |
Sep 19 02:16:59 AM UTC 24 |
4618981888 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pincfg.1079472944 |
|
|
Sep 18 11:57:14 PM UTC 24 |
Sep 19 02:17:29 AM UTC 24 |
31519433460 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1909661448 |
|
|
Sep 19 02:11:14 AM UTC 24 |
Sep 19 02:18:03 AM UTC 24 |
4442826101 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3332314655 |
|
|
Sep 19 12:59:02 AM UTC 24 |
Sep 19 02:18:09 AM UTC 24 |
15602645240 ps |
| T42 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.596552210 |
|
|
Sep 19 02:11:09 AM UTC 24 |
Sep 19 02:18:18 AM UTC 24 |
4136775920 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.1769351081 |
|
|
Sep 19 02:04:38 AM UTC 24 |
Sep 19 02:18:26 AM UTC 24 |
7073582120 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx1.978687072 |
|
|
Sep 19 02:06:28 AM UTC 24 |
Sep 19 02:18:34 AM UTC 24 |
4085170496 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.126777089 |
|
|
Sep 19 02:12:13 AM UTC 24 |
Sep 19 02:19:26 AM UTC 24 |
3895900638 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.4240672684 |
|
|
Sep 19 02:15:04 AM UTC 24 |
Sep 19 02:20:09 AM UTC 24 |
3164245400 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.3021669450 |
|
|
Sep 19 02:08:16 AM UTC 24 |
Sep 19 02:20:17 AM UTC 24 |
3919658370 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2416904734 |
|
|
Sep 19 02:15:20 AM UTC 24 |
Sep 19 02:20:20 AM UTC 24 |
3027783760 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through_collision.3130905371 |
|
|
Sep 19 02:10:51 AM UTC 24 |
Sep 19 02:20:26 AM UTC 24 |
4682646475 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_dev.1975142118 |
|
|
Sep 19 01:18:32 AM UTC 24 |
Sep 19 02:20:32 AM UTC 24 |
41024361746 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod_end.2016085287 |
|
|
Sep 19 01:07:31 AM UTC 24 |
Sep 19 02:20:40 AM UTC 24 |
15721942660 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.4108928302 |
|
|
Sep 19 02:17:28 AM UTC 24 |
Sep 19 02:21:14 AM UTC 24 |
2874160837 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1365206948 |
|
|
Sep 19 02:07:52 AM UTC 24 |
Sep 19 02:21:15 AM UTC 24 |
4883516652 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod.586570180 |
|
|
Sep 19 01:05:37 AM UTC 24 |
Sep 19 02:21:21 AM UTC 24 |
15788784210 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.187552087 |
|
|
Sep 19 02:19:36 AM UTC 24 |
Sep 19 02:21:37 AM UTC 24 |
2921230056 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.4137058323 |
|
|
Sep 19 01:16:51 AM UTC 24 |
Sep 19 02:21:40 AM UTC 24 |
41011549763 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3551981101 |
|
|
Sep 19 02:11:00 AM UTC 24 |
Sep 19 02:21:48 AM UTC 24 |
4528372700 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.2967542322 |
|
|
Sep 19 02:11:00 AM UTC 24 |
Sep 19 02:21:50 AM UTC 24 |
4353981144 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3898862131 |
|
|
Sep 19 02:07:56 AM UTC 24 |
Sep 19 02:21:50 AM UTC 24 |
5530564466 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.537238327 |
|
|
Sep 19 02:07:24 AM UTC 24 |
Sep 19 02:22:01 AM UTC 24 |
5306771580 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.661209896 |
|
|
Sep 19 02:20:07 AM UTC 24 |
Sep 19 02:22:13 AM UTC 24 |
3067419807 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.315581572 |
|
|
Sep 19 02:19:30 AM UTC 24 |
Sep 19 02:22:34 AM UTC 24 |
3119098941 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2320663970 |
|
|
Sep 19 02:17:41 AM UTC 24 |
Sep 19 02:22:38 AM UTC 24 |
2491934056 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.1671229791 |
|
|
Sep 19 02:10:58 AM UTC 24 |
Sep 19 02:23:31 AM UTC 24 |
6315198399 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_rma.605858323 |
|
|
Sep 19 01:09:47 AM UTC 24 |
Sep 19 02:25:25 AM UTC 24 |
15011851485 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.916261915 |
|
|
Sep 19 02:07:40 AM UTC 24 |
Sep 19 02:26:00 AM UTC 24 |
8851259586 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3472709323 |
|
|
Sep 19 12:59:08 AM UTC 24 |
Sep 19 02:26:15 AM UTC 24 |
17380965660 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.2787344045 |
|
|
Sep 19 02:22:14 AM UTC 24 |
Sep 19 02:26:38 AM UTC 24 |
3269094552 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1435211115 |
|
|
Sep 19 02:16:40 AM UTC 24 |
Sep 19 02:27:40 AM UTC 24 |
4069255212 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.222719544 |
|
|
Sep 19 02:24:17 AM UTC 24 |
Sep 19 02:28:15 AM UTC 24 |
2769095802 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1104046881 |
|
|
Sep 19 02:12:11 AM UTC 24 |
Sep 19 02:28:33 AM UTC 24 |
6138492662 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_dev.268063812 |
|
|
Sep 19 01:05:05 AM UTC 24 |
Sep 19 02:28:38 AM UTC 24 |
15491167520 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.1688995546 |
|
|
Sep 19 02:07:14 AM UTC 24 |
Sep 19 02:28:51 AM UTC 24 |
9096936114 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.3034564346 |
|
|
Sep 19 02:12:09 AM UTC 24 |
Sep 19 02:29:42 AM UTC 24 |
6295296264 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.970069345 |
|
|
Sep 19 02:24:11 AM UTC 24 |
Sep 19 02:30:45 AM UTC 24 |
5188492744 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2733943226 |
|
|
Sep 19 02:23:48 AM UTC 24 |
Sep 19 02:30:56 AM UTC 24 |
3977817076 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.656195404 |
|
|
Sep 19 01:23:53 AM UTC 24 |
Sep 19 02:31:05 AM UTC 24 |
15000699650 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.2088943170 |
|
|
Sep 19 02:23:31 AM UTC 24 |
Sep 19 02:31:13 AM UTC 24 |
4021824038 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3764690012 |
|
|
Sep 19 02:24:02 AM UTC 24 |
Sep 19 02:31:46 AM UTC 24 |
6785050324 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.3874476000 |
|
|
Sep 19 02:26:44 AM UTC 24 |
Sep 19 02:31:47 AM UTC 24 |
3249427480 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.364572133 |
|
|
Sep 19 02:15:04 AM UTC 24 |
Sep 19 02:33:10 AM UTC 24 |
5824884477 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3001023946 |
|
|
Sep 19 02:27:23 AM UTC 24 |
Sep 19 02:33:10 AM UTC 24 |
3061315198 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_smoketest.1147915672 |
|
|
Sep 19 01:56:44 AM UTC 24 |
Sep 19 02:33:41 AM UTC 24 |
10025632628 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.3299211934 |
|
|
Sep 19 02:24:13 AM UTC 24 |
Sep 19 02:33:45 AM UTC 24 |
6458996620 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3189843036 |
|
|
Sep 19 02:23:52 AM UTC 24 |
Sep 19 02:33:47 AM UTC 24 |
6803886460 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_rma.167333381 |
|
|
Sep 19 01:19:41 AM UTC 24 |
Sep 19 02:33:50 AM UTC 24 |
31024919732 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2634712684 |
|
|
Sep 19 01:27:58 AM UTC 24 |
Sep 19 02:34:06 AM UTC 24 |
14945028418 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.1457880581 |
|
|
Sep 19 02:18:09 AM UTC 24 |
Sep 19 02:34:25 AM UTC 24 |
9616333441 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3314850581 |
|
|
Sep 19 02:26:09 AM UTC 24 |
Sep 19 02:34:43 AM UTC 24 |
4916313864 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.265223524 |
|
|
Sep 19 02:19:26 AM UTC 24 |
Sep 19 02:34:58 AM UTC 24 |
11422758150 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3860161536 |
|
|
Sep 19 02:29:39 AM UTC 24 |
Sep 19 02:36:29 AM UTC 24 |
4143805838 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.4137949663 |
|
|
Sep 19 02:29:43 AM UTC 24 |
Sep 19 02:36:44 AM UTC 24 |
3719575816 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3046666162 |
|
|
Sep 19 02:23:58 AM UTC 24 |
Sep 19 02:36:45 AM UTC 24 |
8536462088 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3887026505 |
|
|
Sep 19 02:16:40 AM UTC 24 |
Sep 19 02:37:02 AM UTC 24 |
8409222872 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2631794115 |
|
|
Sep 19 02:23:52 AM UTC 24 |
Sep 19 02:37:16 AM UTC 24 |
8695411420 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.4104300150 |
|
|
Sep 19 02:17:11 AM UTC 24 |
Sep 19 02:37:36 AM UTC 24 |
9589504080 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3865198510 |
|
|
Sep 19 02:17:12 AM UTC 24 |
Sep 19 02:37:39 AM UTC 24 |
7835663082 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.922732507 |
|
|
Sep 19 02:28:32 AM UTC 24 |
Sep 19 02:38:04 AM UTC 24 |
6637401720 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3104847605 |
|
|
Sep 19 12:57:39 AM UTC 24 |
Sep 19 02:38:12 AM UTC 24 |
18658703036 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1067843173 |
|
|
Sep 19 02:30:27 AM UTC 24 |
Sep 19 02:38:23 AM UTC 24 |
8148598482 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.1897563591 |
|
|
Sep 19 02:35:44 AM UTC 24 |
Sep 19 02:39:20 AM UTC 24 |
3434296920 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2443452149 |
|
|
Sep 19 02:28:31 AM UTC 24 |
Sep 19 02:39:37 AM UTC 24 |
5127913001 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.2260768315 |
|
|
Sep 19 12:25:15 AM UTC 24 |
Sep 19 02:40:21 AM UTC 24 |
26770575336 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.4163333313 |
|
|
Sep 19 02:35:58 AM UTC 24 |
Sep 19 02:40:40 AM UTC 24 |
2980898533 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.3899885096 |
|
|
Sep 19 02:31:59 AM UTC 24 |
Sep 19 02:41:31 AM UTC 24 |
4552859300 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.3948540504 |
|
|
Sep 19 02:38:30 AM UTC 24 |
Sep 19 02:42:04 AM UTC 24 |
3060291685 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2810569343 |
|
|
Sep 19 02:32:05 AM UTC 24 |
Sep 19 02:42:05 AM UTC 24 |
19304351956 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.3078417231 |
|
|
Sep 19 02:35:56 AM UTC 24 |
Sep 19 02:42:07 AM UTC 24 |
3380948902 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.3387362217 |
|
|
Sep 19 02:12:04 AM UTC 24 |
Sep 19 02:42:10 AM UTC 24 |
20025357155 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.1536687970 |
|
|
Sep 19 02:35:57 AM UTC 24 |
Sep 19 02:42:23 AM UTC 24 |
3439565600 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.1502847605 |
|
|
Sep 19 02:39:09 AM UTC 24 |
Sep 19 02:42:25 AM UTC 24 |
3119608760 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.3034504338 |
|
|
Sep 19 02:35:51 AM UTC 24 |
Sep 19 02:42:58 AM UTC 24 |
3059311766 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.124997160 |
|
|
Sep 19 02:32:05 AM UTC 24 |
Sep 19 02:43:11 AM UTC 24 |
5853603030 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.1658920335 |
|
|
Sep 19 02:36:00 AM UTC 24 |
Sep 19 02:43:20 AM UTC 24 |
4573044490 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2048307856 |
|
|
Sep 19 02:24:16 AM UTC 24 |
Sep 19 02:43:33 AM UTC 24 |
12645331748 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3936764334 |
|
|
Sep 19 01:31:28 AM UTC 24 |
Sep 19 02:43:50 AM UTC 24 |
14699274052 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.1411409010 |
|
|
Sep 19 02:39:09 AM UTC 24 |
Sep 19 02:43:51 AM UTC 24 |
2669112024 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3225763433 |
|
|
Sep 19 02:31:59 AM UTC 24 |
Sep 19 02:44:34 AM UTC 24 |
10282766306 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_mem_scramble.3765780647 |
|
|
Sep 19 02:34:03 AM UTC 24 |
Sep 19 02:44:41 AM UTC 24 |
3294071168 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3563236947 |
|
|
Sep 19 02:38:00 AM UTC 24 |
Sep 19 02:45:03 AM UTC 24 |
3617983772 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_timeout.812653926 |
|
|
Sep 19 02:35:58 AM UTC 24 |
Sep 19 02:45:35 AM UTC 24 |
5304699800 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.155509544 |
|
|
Sep 19 01:21:58 AM UTC 24 |
Sep 19 02:47:02 AM UTC 24 |
17008957632 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_randomness.3965829456 |
|
|
Sep 19 02:32:42 AM UTC 24 |
Sep 19 02:47:03 AM UTC 24 |
6041499486 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3522321219 |
|
|
Sep 19 02:35:51 AM UTC 24 |
Sep 19 02:47:30 AM UTC 24 |
4502556128 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.2589735873 |
|
|
Sep 19 02:40:05 AM UTC 24 |
Sep 19 02:47:35 AM UTC 24 |
2488443808 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1293533956 |
|
|
Sep 19 02:44:41 AM UTC 24 |
Sep 19 02:47:44 AM UTC 24 |
2456522740 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en.999978230 |
|
|
Sep 19 02:44:41 AM UTC 24 |
Sep 19 02:48:06 AM UTC 24 |
2491960049 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_kat_test.3597159247 |
|
|
Sep 19 02:44:51 AM UTC 24 |
Sep 19 02:48:34 AM UTC 24 |
3126493220 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.3966578709 |
|
|
Sep 19 02:44:58 AM UTC 24 |
Sep 19 02:49:28 AM UTC 24 |
2890419512 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.3483564325 |
|
|
Sep 19 02:40:20 AM UTC 24 |
Sep 19 02:49:55 AM UTC 24 |
3048165240 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.963276374 |
|
|
Sep 19 02:44:56 AM UTC 24 |
Sep 19 02:49:59 AM UTC 24 |
3015630814 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.61152408 |
|
|
Sep 19 02:44:51 AM UTC 24 |
Sep 19 02:50:05 AM UTC 24 |
2800159056 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.2829902331 |
|
|
Sep 19 02:23:49 AM UTC 24 |
Sep 19 02:51:47 AM UTC 24 |
10710302600 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.323102424 |
|
|
Sep 19 02:07:39 AM UTC 24 |
Sep 19 02:51:54 AM UTC 24 |
13162795852 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3221181386 |
|
|
Sep 19 12:58:14 AM UTC 24 |
Sep 19 02:51:58 AM UTC 24 |
23491241500 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.29456626 |
|
|
Sep 19 02:47:59 AM UTC 24 |
Sep 19 02:52:26 AM UTC 24 |
3477466680 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_app_rom.3575424529 |
|
|
Sep 19 02:48:48 AM UTC 24 |
Sep 19 02:52:35 AM UTC 24 |
2347375452 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.1282718106 |
|
|
Sep 19 02:36:00 AM UTC 24 |
Sep 19 02:52:42 AM UTC 24 |
5934976200 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1549138394 |
|
|
Sep 19 02:23:53 AM UTC 24 |
Sep 19 02:52:48 AM UTC 24 |
16172705314 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1684277017 |
|
|
Sep 19 02:48:34 AM UTC 24 |
Sep 19 02:53:07 AM UTC 24 |
3286771497 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.2292938507 |
|
|
Sep 19 02:48:51 AM UTC 24 |
Sep 19 02:53:18 AM UTC 24 |
3552859396 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.769261748 |
|
|
Sep 19 02:45:00 AM UTC 24 |
Sep 19 02:54:18 AM UTC 24 |
3781001640 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.455607651 |
|
|
Sep 19 02:22:34 AM UTC 24 |
Sep 19 02:54:19 AM UTC 24 |
24028686688 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.2437619124 |
|
|
Sep 19 02:39:12 AM UTC 24 |
Sep 19 02:54:36 AM UTC 24 |
4054121200 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3987734485 |
|
|
Sep 19 02:41:21 AM UTC 24 |
Sep 19 02:54:51 AM UTC 24 |
8216532872 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.1142509910 |
|
|
Sep 19 02:23:50 AM UTC 24 |
Sep 19 02:54:53 AM UTC 24 |
14752404308 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.311218617 |
|
|
Sep 19 02:48:35 AM UTC 24 |
Sep 19 02:55:09 AM UTC 24 |
3315519770 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3310428184 |
|
|
Sep 19 02:38:01 AM UTC 24 |
Sep 19 02:55:43 AM UTC 24 |
9722222670 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.8464030 |
|
|
Sep 19 01:01:33 AM UTC 24 |
Sep 19 02:56:38 AM UTC 24 |
22917312328 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.3508041819 |
|
|
Sep 19 02:52:55 AM UTC 24 |
Sep 19 02:56:50 AM UTC 24 |
2258981615 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3587835013 |
|
|
Sep 19 12:59:15 AM UTC 24 |
Sep 19 02:56:56 AM UTC 24 |
23682003357 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.3974973042 |
|
|
Sep 19 02:37:12 AM UTC 24 |
Sep 19 02:58:10 AM UTC 24 |
7642419112 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.245650357 |
|
|
Sep 19 01:01:34 AM UTC 24 |
Sep 19 02:58:14 AM UTC 24 |
22659730827 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.928373661 |
|
|
Sep 19 01:00:05 AM UTC 24 |
Sep 19 02:58:28 AM UTC 24 |
23241290160 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.3673200027 |
|
|
Sep 19 02:54:14 AM UTC 24 |
Sep 19 02:59:18 AM UTC 24 |
3254582104 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1859897442 |
|
|
Sep 19 02:49:15 AM UTC 24 |
Sep 19 02:59:57 AM UTC 24 |
8152647483 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.645454156 |
|
|
Sep 19 02:53:54 AM UTC 24 |
Sep 19 03:00:31 AM UTC 24 |
4485964792 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3127146354 |
|
|
Sep 19 12:58:00 AM UTC 24 |
Sep 19 03:01:05 AM UTC 24 |
24138137034 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2546405553 |
|
|
Sep 19 02:55:40 AM UTC 24 |
Sep 19 03:01:20 AM UTC 24 |
3297507566 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3041311429 |
|
|
Sep 19 02:51:03 AM UTC 24 |
Sep 19 03:01:41 AM UTC 24 |
8387397644 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2380812993 |
|
|
Sep 19 02:51:02 AM UTC 24 |
Sep 19 03:01:55 AM UTC 24 |
5583546319 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3850512381 |
|
|
Sep 19 12:59:06 AM UTC 24 |
Sep 19 03:02:17 AM UTC 24 |
24569640504 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3325570244 |
|
|
Sep 19 02:55:55 AM UTC 24 |
Sep 19 03:02:29 AM UTC 24 |
3902238680 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.3185832537 |
|
|
Sep 19 02:28:58 AM UTC 24 |
Sep 19 03:02:30 AM UTC 24 |
24097893280 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3313823412 |
|
|
Sep 19 02:44:52 AM UTC 24 |
Sep 19 03:02:42 AM UTC 24 |
7371341368 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.1577426506 |
|
|
Sep 19 02:54:13 AM UTC 24 |
Sep 19 03:03:03 AM UTC 24 |
4023120030 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1114649601 |
|
|
Sep 19 02:55:56 AM UTC 24 |
Sep 19 03:03:09 AM UTC 24 |
4098659184 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2967817121 |
|
|
Sep 19 02:23:31 AM UTC 24 |
Sep 19 03:03:21 AM UTC 24 |
28422762415 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs.1771707163 |
|
|
Sep 19 02:44:52 AM UTC 24 |
Sep 19 03:03:35 AM UTC 24 |
5912720956 ps |
| T1037 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.4284121716 |
|
|
Sep 19 02:38:04 AM UTC 24 |
Sep 19 03:03:43 AM UTC 24 |
8069444100 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.980022311 |
|
|
Sep 19 02:50:12 AM UTC 24 |
Sep 19 03:03:48 AM UTC 24 |
5835298566 ps |
| T1038 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.3530825287 |
|
|
Sep 19 03:00:40 AM UTC 24 |
Sep 19 03:03:52 AM UTC 24 |
2367445780 ps |
| T1039 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.3769838675 |
|
|
Sep 19 02:45:49 AM UTC 24 |
Sep 19 03:04:20 AM UTC 24 |
7335756868 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.2804190482 |
|
|
Sep 19 02:51:04 AM UTC 24 |
Sep 19 03:04:24 AM UTC 24 |
6782025892 ps |
| T1040 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2919643017 |
|
|
Sep 19 02:56:01 AM UTC 24 |
Sep 19 03:05:10 AM UTC 24 |
4978885852 ps |
| T1041 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2566144957 |
|
|
Sep 19 03:00:03 AM UTC 24 |
Sep 19 03:05:17 AM UTC 24 |
3621680760 ps |
| T1042 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3218706522 |
|
|
Sep 19 02:52:55 AM UTC 24 |
Sep 19 03:05:37 AM UTC 24 |
7089846400 ps |
| T1043 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_reset_frequency.3444606200 |
|
|
Sep 19 02:59:20 AM UTC 24 |
Sep 19 03:06:29 AM UTC 24 |
3255058748 ps |
| T1044 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.130188806 |
|
|
Sep 19 02:56:01 AM UTC 24 |
Sep 19 03:06:37 AM UTC 24 |
7104332553 ps |
| T1045 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1026621513 |
|
|
Sep 19 02:57:44 AM UTC 24 |
Sep 19 03:06:52 AM UTC 24 |
3411194940 ps |
| T1046 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.929115841 |
|
|
Sep 19 02:45:02 AM UTC 24 |
Sep 19 03:07:02 AM UTC 24 |
6304037800 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_aes.1965567750 |
|
|
Sep 19 02:46:20 AM UTC 24 |
Sep 19 03:07:12 AM UTC 24 |
7990436380 ps |
| T1047 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.855709151 |
|
|
Sep 19 02:56:26 AM UTC 24 |
Sep 19 03:07:30 AM UTC 24 |
4643357896 ps |
| T1048 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2793003747 |
|
|
Sep 19 01:00:02 AM UTC 24 |
Sep 19 03:07:35 AM UTC 24 |
24717951242 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.2582616661 |
|
|
Sep 19 02:52:56 AM UTC 24 |
Sep 19 03:07:39 AM UTC 24 |
6084908000 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.821078507 |
|
|
Sep 19 02:54:12 AM UTC 24 |
Sep 19 03:07:40 AM UTC 24 |
5322635440 ps |
| T1049 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.2040733053 |
|
|
Sep 19 03:04:49 AM UTC 24 |
Sep 19 03:07:50 AM UTC 24 |
2386731829 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.161020939 |
|
|
Sep 19 03:05:03 AM UTC 24 |
Sep 19 03:08:00 AM UTC 24 |
2590479881 ps |
| T1050 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2952611750 |
|
|
Sep 19 02:57:19 AM UTC 24 |
Sep 19 03:08:10 AM UTC 24 |
4852276246 ps |
| T1051 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4052956600 |
|
|
Sep 19 02:57:44 AM UTC 24 |
Sep 19 03:08:20 AM UTC 24 |
5629858914 ps |
| T1052 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.2657029506 |
|
|
Sep 19 03:05:59 AM UTC 24 |
Sep 19 03:08:28 AM UTC 24 |
2153411188 ps |
| T1053 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2564402343 |
|
|
Sep 19 02:59:19 AM UTC 24 |
Sep 19 03:08:39 AM UTC 24 |
4795193444 ps |
| T1054 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2671479396 |
|
|
Sep 19 02:59:15 AM UTC 24 |
Sep 19 03:08:42 AM UTC 24 |
3990544720 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_program_error.872605786 |
|
|
Sep 19 03:02:38 AM UTC 24 |
Sep 19 03:09:25 AM UTC 24 |
4811225010 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1189213671 |
|
|
Sep 19 03:03:42 AM UTC 24 |
Sep 19 03:10:01 AM UTC 24 |
7642675556 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.175791315 |
|
|
Sep 19 03:01:34 AM UTC 24 |
Sep 19 03:10:10 AM UTC 24 |
6126037340 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1795567595 |
|
|
Sep 19 03:06:02 AM UTC 24 |
Sep 19 03:10:12 AM UTC 24 |
2229542824 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2581900735 |
|
|
Sep 19 03:07:24 AM UTC 24 |
Sep 19 03:10:21 AM UTC 24 |
2784365006 ps |
| T1055 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation.1872958525 |
|
|
Sep 19 02:45:02 AM UTC 24 |
Sep 19 03:10:55 AM UTC 24 |
8754031600 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.4216986184 |
|
|
Sep 19 02:44:31 AM UTC 24 |
Sep 19 03:10:58 AM UTC 24 |
7953572232 ps |
| T1056 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3160460558 |
|
|
Sep 19 03:04:50 AM UTC 24 |
Sep 19 03:11:19 AM UTC 24 |
5746922660 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.3158490796 |
|
|
Sep 19 03:05:02 AM UTC 24 |
Sep 19 03:11:41 AM UTC 24 |
5850307412 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1347771059 |
|
|
Sep 19 03:04:49 AM UTC 24 |
Sep 19 03:11:44 AM UTC 24 |
4564825925 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3214379817 |
|
|
Sep 19 03:04:43 AM UTC 24 |
Sep 19 03:11:46 AM UTC 24 |
4142443848 ps |
| T1057 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3670582951 |
|
|
Sep 19 03:04:42 AM UTC 24 |
Sep 19 03:12:03 AM UTC 24 |
5584245388 ps |
| T1058 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2070963705 |
|
|
Sep 19 02:38:29 AM UTC 24 |
Sep 19 03:12:03 AM UTC 24 |
9461255560 ps |
| T1059 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3355548764 |
|
|
Sep 19 03:01:16 AM UTC 24 |
Sep 19 03:12:24 AM UTC 24 |
5120779864 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.3986022575 |
|
|
Sep 19 02:53:55 AM UTC 24 |
Sep 19 03:12:29 AM UTC 24 |
6101763744 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.475054759 |
|
|
Sep 19 03:04:50 AM UTC 24 |
Sep 19 03:12:50 AM UTC 24 |
4700474432 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1418726939 |
|
|
Sep 19 03:04:44 AM UTC 24 |
Sep 19 03:12:57 AM UTC 24 |
6227262696 ps |
| T1060 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.1197758591 |
|
|
Sep 19 03:09:53 AM UTC 24 |
Sep 19 03:13:22 AM UTC 24 |
2589777109 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.523499056 |
|
|
Sep 19 03:05:04 AM UTC 24 |
Sep 19 03:13:31 AM UTC 24 |
4122367500 ps |
| T1061 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1003851735 |
|
|
Sep 19 03:10:08 AM UTC 24 |
Sep 19 03:13:34 AM UTC 24 |
3228303364 ps |
| T1062 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.1085467903 |
|
|
Sep 19 03:10:06 AM UTC 24 |
Sep 19 03:13:55 AM UTC 24 |
3178063228 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2684103754 |
|
|
Sep 19 03:09:51 AM UTC 24 |
Sep 19 03:14:19 AM UTC 24 |
3511700975 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2420239743 |
|
|
Sep 19 03:10:15 AM UTC 24 |
Sep 19 03:14:33 AM UTC 24 |
3284391440 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.1192482812 |
|
|
Sep 19 02:41:06 AM UTC 24 |
Sep 19 03:15:51 AM UTC 24 |
10447385682 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_prod.4061262752 |
|
|
Sep 19 02:45:28 AM UTC 24 |
Sep 19 03:15:52 AM UTC 24 |
10544368130 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.1728426102 |
|
|
Sep 19 03:07:25 AM UTC 24 |
Sep 19 03:16:12 AM UTC 24 |
5562404150 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.928252553 |
|
|
Sep 19 03:02:24 AM UTC 24 |
Sep 19 03:16:31 AM UTC 24 |
7186680620 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_volatile_raw_unlock.3259710996 |
|
|
Sep 19 03:16:10 AM UTC 24 |
Sep 19 03:17:53 AM UTC 24 |
3027643153 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.318454786 |
|
|
Sep 19 03:10:18 AM UTC 24 |
Sep 19 03:18:03 AM UTC 24 |
4319797414 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.1453610449 |
|
|
Sep 19 03:10:20 AM UTC 24 |
Sep 19 03:18:14 AM UTC 24 |
9619451368 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.3391309895 |
|
|
Sep 19 03:15:24 AM UTC 24 |
Sep 19 03:18:21 AM UTC 24 |
3167141672 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.2743716950 |
|
|
Sep 19 03:16:16 AM UTC 24 |
Sep 19 03:18:58 AM UTC 24 |
2407023472 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.3742327922 |
|
|
Sep 19 03:14:37 AM UTC 24 |
Sep 19 03:19:02 AM UTC 24 |
3316877114 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_raw_unlock.3490569354 |
|
|
Sep 19 03:15:01 AM UTC 24 |
Sep 19 03:19:36 AM UTC 24 |
6444883024 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1321274515 |
|
|
Sep 19 03:09:46 AM UTC 24 |
Sep 19 03:19:52 AM UTC 24 |
4672217383 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.282203251 |
|
|
Sep 19 03:16:04 AM UTC 24 |
Sep 19 03:20:52 AM UTC 24 |
3306020760 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.438176747 |
|
|
Sep 19 02:55:21 AM UTC 24 |
Sep 19 03:21:04 AM UTC 24 |
10327429370 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.159318050 |
|
|
Sep 19 03:10:13 AM UTC 24 |
Sep 19 03:21:05 AM UTC 24 |
4846619508 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.1416498654 |
|
|
Sep 19 03:15:23 AM UTC 24 |
Sep 19 03:21:31 AM UTC 24 |
2867360380 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3304729856 |
|
|
Sep 19 03:03:43 AM UTC 24 |
Sep 19 03:21:59 AM UTC 24 |
23882356526 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.3910657838 |
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|
Sep 19 03:16:42 AM UTC 24 |
Sep 19 03:22:01 AM UTC 24 |
3343374315 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.1797795207 |
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|
Sep 19 03:17:12 AM UTC 24 |
Sep 19 03:22:44 AM UTC 24 |
3712391400 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.4072067510 |
|
|
Sep 19 03:16:56 AM UTC 24 |
Sep 19 03:22:46 AM UTC 24 |
2677069258 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.871401472 |
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|
Sep 19 03:01:49 AM UTC 24 |
Sep 19 03:23:05 AM UTC 24 |
13791427192 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.374107724 |
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|
Sep 19 02:45:28 AM UTC 24 |
Sep 19 03:23:16 AM UTC 24 |
11864555939 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_plic_smoketest.165220733 |
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|
Sep 19 03:19:49 AM UTC 24 |
Sep 19 03:23:46 AM UTC 24 |
2549545068 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.3680268651 |
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|
Sep 19 03:19:07 AM UTC 24 |
Sep 19 03:23:50 AM UTC 24 |
3488315376 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.2481007288 |
|
|
Sep 19 03:21:52 AM UTC 24 |
Sep 19 03:23:53 AM UTC 24 |
2042145080 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.4200609529 |
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|
Sep 19 03:20:35 AM UTC 24 |
Sep 19 03:23:51 AM UTC 24 |
2038311360 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.1941062026 |
|
|
Sep 19 03:19:50 AM UTC 24 |
Sep 19 03:24:10 AM UTC 24 |
3283999800 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency.3479339469 |
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|
Sep 19 02:42:17 AM UTC 24 |
Sep 19 03:24:30 AM UTC 24 |
10306488256 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3456010505 |
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|
Sep 19 02:29:39 AM UTC 24 |
Sep 19 03:24:55 AM UTC 24 |
20475609646 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_smoketest.1125516700 |
|
|
Sep 19 03:16:41 AM UTC 24 |
Sep 19 03:24:57 AM UTC 24 |
3720006568 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.1233067696 |
|
|
Sep 19 03:19:12 AM UTC 24 |
Sep 19 03:24:58 AM UTC 24 |
4628747400 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.3983738576 |
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|
Sep 19 03:20:20 AM UTC 24 |
Sep 19 03:24:59 AM UTC 24 |
2490238234 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.1435766485 |
|
|
Sep 19 03:22:11 AM UTC 24 |
Sep 19 03:25:31 AM UTC 24 |
1894940824 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.3598030402 |
|
|
Sep 19 03:16:13 AM UTC 24 |
Sep 19 03:25:36 AM UTC 24 |
4692967162 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.4061170488 |
|
|
Sep 19 03:21:53 AM UTC 24 |
Sep 19 03:25:49 AM UTC 24 |
2489170430 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.3887112002 |
|
|
Sep 19 03:22:55 AM UTC 24 |
Sep 19 03:26:00 AM UTC 24 |
3046709080 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_smoketest.1377127160 |
|
|
Sep 19 03:21:49 AM UTC 24 |
Sep 19 03:27:16 AM UTC 24 |
3234828436 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1477311938 |
|
|
Sep 19 03:10:19 AM UTC 24 |
Sep 19 03:27:31 AM UTC 24 |
6740128545 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.1663132034 |
|
|
Sep 19 03:22:56 AM UTC 24 |
Sep 19 03:28:03 AM UTC 24 |
3694679300 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.312297583 |
|
|
Sep 19 03:19:13 AM UTC 24 |
Sep 19 03:28:11 AM UTC 24 |
6007119210 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.2799820342 |
|
|
Sep 19 03:26:08 AM UTC 24 |
Sep 19 03:30:09 AM UTC 24 |
2221967320 ps |
| T26 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.3386673507 |
|
|
Sep 19 03:26:07 AM UTC 24 |
Sep 19 03:31:05 AM UTC 24 |
3984909900 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.2839218965 |
|
|
Sep 19 03:26:09 AM UTC 24 |
Sep 19 03:31:06 AM UTC 24 |
2808003320 ps |
| T20 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3156953921 |
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|
Sep 19 03:24:05 AM UTC 24 |
Sep 19 03:31:18 AM UTC 24 |
3480830105 ps |