| T1335 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.4071532857 |
|
|
Sep 19 05:22:43 AM UTC 24 |
Sep 19 06:43:19 AM UTC 24 |
21059730592 ps |
| T1336 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.2763823892 |
|
|
Sep 19 05:10:15 AM UTC 24 |
Sep 19 06:44:49 AM UTC 24 |
22285339766 ps |
| T1337 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.1281413191 |
|
|
Sep 19 04:50:04 AM UTC 24 |
Sep 19 06:47:28 AM UTC 24 |
26482357400 ps |
| T1338 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3931210670 |
|
|
Sep 19 03:27:05 AM UTC 24 |
Sep 19 07:03:06 AM UTC 24 |
61422131333 ps |
| T1339 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2559509 |
|
|
Sep 19 02:06:16 AM UTC 24 |
Sep 19 07:08:18 AM UTC 24 |
81461594088 ps |
| T1340 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.3772304908 |
|
|
Sep 19 05:24:52 AM UTC 24 |
Sep 19 07:13:27 AM UTC 24 |
30185554980 ps |
| T1341 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.4289361305 |
|
|
Sep 19 03:26:54 AM UTC 24 |
Sep 19 07:16:34 AM UTC 24 |
66364899626 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2839322524 |
|
|
Sep 19 12:52:56 AM UTC 24 |
Sep 19 07:23:58 AM UTC 24 |
129927016059 ps |
| T1342 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1041242120 |
|
|
Sep 19 03:26:24 AM UTC 24 |
Sep 19 07:46:37 AM UTC 24 |
82440966213 ps |
| T1343 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3312909890 |
|
|
Sep 19 04:08:05 AM UTC 24 |
Sep 19 07:57:22 AM UTC 24 |
255902214524 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3207591269 |
|
|
Sep 19 03:09:50 AM UTC 24 |
Sep 19 08:57:21 AM UTC 24 |
143566199696 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.166412602 |
|
|
Sep 18 09:27:57 PM UTC 24 |
Sep 18 09:28:04 PM UTC 24 |
48502281 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1387464026 |
|
|
Sep 18 09:27:59 PM UTC 24 |
Sep 18 09:28:07 PM UTC 24 |
44225758 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.2452591743 |
|
|
Sep 18 09:36:32 PM UTC 24 |
Sep 18 09:37:17 PM UTC 24 |
494869521 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1907673175 |
|
|
Sep 18 09:28:01 PM UTC 24 |
Sep 18 09:28:08 PM UTC 24 |
7396476 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.3988118552 |
|
|
Sep 18 09:28:02 PM UTC 24 |
Sep 18 09:28:12 PM UTC 24 |
64331171 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.2657313555 |
|
|
Sep 18 09:28:08 PM UTC 24 |
Sep 18 09:28:15 PM UTC 24 |
37689089 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3640935772 |
|
|
Sep 18 09:28:08 PM UTC 24 |
Sep 18 09:28:16 PM UTC 24 |
40144300 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.2403216786 |
|
|
Sep 18 09:27:57 PM UTC 24 |
Sep 18 09:28:17 PM UTC 24 |
281400083 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2526226992 |
|
|
Sep 18 09:27:59 PM UTC 24 |
Sep 18 09:28:22 PM UTC 24 |
171539453 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.2302465079 |
|
|
Sep 18 09:27:59 PM UTC 24 |
Sep 18 09:28:27 PM UTC 24 |
275762818 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.3515439928 |
|
|
Sep 18 09:28:01 PM UTC 24 |
Sep 18 09:28:34 PM UTC 24 |
499261995 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.2883889557 |
|
|
Sep 18 09:28:02 PM UTC 24 |
Sep 18 09:28:35 PM UTC 24 |
827492048 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.2667472691 |
|
|
Sep 18 09:28:00 PM UTC 24 |
Sep 18 09:28:38 PM UTC 24 |
445026422 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.2332665604 |
|
|
Sep 18 09:28:02 PM UTC 24 |
Sep 18 09:28:38 PM UTC 24 |
1248892506 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2164720546 |
|
|
Sep 18 09:28:37 PM UTC 24 |
Sep 18 09:28:55 PM UTC 24 |
95911850 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.1976700062 |
|
|
Sep 18 09:28:36 PM UTC 24 |
Sep 18 09:28:55 PM UTC 24 |
292168344 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.2148134732 |
|
|
Sep 18 09:28:16 PM UTC 24 |
Sep 18 09:28:58 PM UTC 24 |
548700806 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.4155889984 |
|
|
Sep 18 09:28:45 PM UTC 24 |
Sep 18 09:28:58 PM UTC 24 |
13854023 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.1819001895 |
|
|
Sep 18 09:28:16 PM UTC 24 |
Sep 18 09:29:02 PM UTC 24 |
541263946 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.4091164458 |
|
|
Sep 18 09:28:00 PM UTC 24 |
Sep 18 09:29:13 PM UTC 24 |
7804827951 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.1222272265 |
|
|
Sep 18 09:28:28 PM UTC 24 |
Sep 18 09:29:14 PM UTC 24 |
508867961 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.974797400 |
|
|
Sep 18 09:28:33 PM UTC 24 |
Sep 18 09:29:15 PM UTC 24 |
1170959052 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.2997942070 |
|
|
Sep 18 09:29:11 PM UTC 24 |
Sep 18 09:29:20 PM UTC 24 |
159684001 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.2219698727 |
|
|
Sep 18 09:29:15 PM UTC 24 |
Sep 18 09:29:22 PM UTC 24 |
50008581 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2236271718 |
|
|
Sep 18 09:27:58 PM UTC 24 |
Sep 18 09:29:27 PM UTC 24 |
6697344867 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.4204427462 |
|
|
Sep 18 09:28:06 PM UTC 24 |
Sep 18 09:29:27 PM UTC 24 |
7660603392 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.887811093 |
|
|
Sep 18 09:28:35 PM UTC 24 |
Sep 18 09:29:32 PM UTC 24 |
2123177637 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.3185577348 |
|
|
Sep 18 09:29:34 PM UTC 24 |
Sep 18 09:29:44 PM UTC 24 |
75477548 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.996558631 |
|
|
Sep 18 09:29:33 PM UTC 24 |
Sep 18 09:29:52 PM UTC 24 |
314169977 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.3744693643 |
|
|
Sep 18 09:29:38 PM UTC 24 |
Sep 18 09:29:55 PM UTC 24 |
477583215 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.450933029 |
|
|
Sep 18 09:29:24 PM UTC 24 |
Sep 18 09:29:56 PM UTC 24 |
215942533 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.123543976 |
|
|
Sep 18 09:29:25 PM UTC 24 |
Sep 18 09:29:57 PM UTC 24 |
376470823 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.2031623762 |
|
|
Sep 18 09:29:22 PM UTC 24 |
Sep 18 09:30:03 PM UTC 24 |
2463642864 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.2306453688 |
|
|
Sep 18 09:28:04 PM UTC 24 |
Sep 18 09:30:12 PM UTC 24 |
3541296230 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.88989000 |
|
|
Sep 18 09:28:08 PM UTC 24 |
Sep 18 09:30:20 PM UTC 24 |
6417423377 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.2526580283 |
|
|
Sep 18 09:29:48 PM UTC 24 |
Sep 18 09:30:21 PM UTC 24 |
203324456 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.4055649644 |
|
|
Sep 18 09:29:43 PM UTC 24 |
Sep 18 09:30:28 PM UTC 24 |
956660648 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.1414947846 |
|
|
Sep 18 09:30:39 PM UTC 24 |
Sep 18 09:30:49 PM UTC 24 |
35510391 ps |
| T1344 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.1860709205 |
|
|
Sep 18 09:30:44 PM UTC 24 |
Sep 18 09:30:51 PM UTC 24 |
35730095 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1090642167 |
|
|
Sep 18 09:28:39 PM UTC 24 |
Sep 18 09:31:02 PM UTC 24 |
305067513 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.759407771 |
|
|
Sep 18 09:29:57 PM UTC 24 |
Sep 18 09:31:07 PM UTC 24 |
908175073 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.3358980648 |
|
|
Sep 18 09:30:59 PM UTC 24 |
Sep 18 09:31:11 PM UTC 24 |
96749461 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.964156401 |
|
|
Sep 18 09:27:59 PM UTC 24 |
Sep 18 09:31:12 PM UTC 24 |
5268568692 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3851216549 |
|
|
Sep 18 09:28:01 PM UTC 24 |
Sep 18 09:31:13 PM UTC 24 |
3415886739 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.3106051267 |
|
|
Sep 18 09:29:19 PM UTC 24 |
Sep 18 09:31:30 PM UTC 24 |
8852334590 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.3105728658 |
|
|
Sep 18 09:30:49 PM UTC 24 |
Sep 18 09:31:38 PM UTC 24 |
1382268553 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.2293549491 |
|
|
Sep 18 09:27:55 PM UTC 24 |
Sep 18 09:31:45 PM UTC 24 |
7271472152 ps |
| T1345 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.623457559 |
|
|
Sep 18 09:31:28 PM UTC 24 |
Sep 18 09:31:49 PM UTC 24 |
350377872 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.209261297 |
|
|
Sep 18 09:31:20 PM UTC 24 |
Sep 18 09:31:49 PM UTC 24 |
468218677 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.1037098101 |
|
|
Sep 18 09:31:37 PM UTC 24 |
Sep 18 09:31:57 PM UTC 24 |
132017870 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.113698629 |
|
|
Sep 18 09:28:04 PM UTC 24 |
Sep 18 09:32:04 PM UTC 24 |
5082559160 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.4142587622 |
|
|
Sep 18 09:29:26 PM UTC 24 |
Sep 18 09:32:04 PM UTC 24 |
16225948020 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.3642688699 |
|
|
Sep 18 09:29:48 PM UTC 24 |
Sep 18 09:32:04 PM UTC 24 |
1956234642 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.2563863138 |
|
|
Sep 18 09:30:51 PM UTC 24 |
Sep 18 09:32:04 PM UTC 24 |
4743117687 ps |
| T1346 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.3447246911 |
|
|
Sep 18 09:31:44 PM UTC 24 |
Sep 18 09:32:12 PM UTC 24 |
258253295 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.4196158391 |
|
|
Sep 18 09:28:47 PM UTC 24 |
Sep 18 09:32:24 PM UTC 24 |
4627321560 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.3338627460 |
|
|
Sep 18 09:31:35 PM UTC 24 |
Sep 18 09:32:38 PM UTC 24 |
1927535810 ps |
| T1347 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.505461488 |
|
|
Sep 18 09:32:34 PM UTC 24 |
Sep 18 09:32:43 PM UTC 24 |
47890677 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.1177222104 |
|
|
Sep 18 09:32:34 PM UTC 24 |
Sep 18 09:32:48 PM UTC 24 |
222701576 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.251769801 |
|
|
Sep 18 09:29:02 PM UTC 24 |
Sep 18 09:32:51 PM UTC 24 |
3532091296 ps |
| T1348 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.3068419923 |
|
|
Sep 18 09:30:49 PM UTC 24 |
Sep 18 09:32:54 PM UTC 24 |
10546391629 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.3801139284 |
|
|
Sep 18 09:28:01 PM UTC 24 |
Sep 18 09:33:04 PM UTC 24 |
4223349290 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.1345121350 |
|
|
Sep 18 09:28:03 PM UTC 24 |
Sep 18 09:33:10 PM UTC 24 |
9312953181 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.3846087227 |
|
|
Sep 18 09:28:43 PM UTC 24 |
Sep 18 09:33:35 PM UTC 24 |
3315427254 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.1715914362 |
|
|
Sep 18 09:33:41 PM UTC 24 |
Sep 18 09:33:51 PM UTC 24 |
42117728 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.1665936273 |
|
|
Sep 18 09:33:14 PM UTC 24 |
Sep 18 09:33:56 PM UTC 24 |
324697276 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.4260614386 |
|
|
Sep 18 09:33:26 PM UTC 24 |
Sep 18 09:34:00 PM UTC 24 |
206389522 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.3411613998 |
|
|
Sep 18 09:32:44 PM UTC 24 |
Sep 18 09:34:08 PM UTC 24 |
8478126009 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.2860257888 |
|
|
Sep 18 09:33:09 PM UTC 24 |
Sep 18 09:34:09 PM UTC 24 |
1469123221 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.2459548123 |
|
|
Sep 18 09:27:59 PM UTC 24 |
Sep 18 09:34:11 PM UTC 24 |
4555707962 ps |
| T1349 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.460008216 |
|
|
Sep 18 09:34:05 PM UTC 24 |
Sep 18 09:34:22 PM UTC 24 |
125897971 ps |
| T1350 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.1256734431 |
|
|
Sep 18 09:32:56 PM UTC 24 |
Sep 18 09:34:34 PM UTC 24 |
4453118521 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.608108190 |
|
|
Sep 18 09:33:34 PM UTC 24 |
Sep 18 09:34:44 PM UTC 24 |
2896296870 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.3354519762 |
|
|
Sep 18 09:34:21 PM UTC 24 |
Sep 18 09:34:58 PM UTC 24 |
738596347 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.601711953 |
|
|
Sep 18 09:34:24 PM UTC 24 |
Sep 18 09:35:11 PM UTC 24 |
1253145977 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.4137139372 |
|
|
Sep 18 09:31:42 PM UTC 24 |
Sep 18 09:35:38 PM UTC 24 |
2650104787 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.690015084 |
|
|
Sep 18 09:35:42 PM UTC 24 |
Sep 18 09:35:57 PM UTC 24 |
217157158 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.2462596342 |
|
|
Sep 18 09:28:50 PM UTC 24 |
Sep 18 09:36:00 PM UTC 24 |
4142756750 ps |
| T1351 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.36693175 |
|
|
Sep 18 09:27:59 PM UTC 24 |
Sep 18 09:36:00 PM UTC 24 |
12212040547 ps |
| T1352 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.4026936280 |
|
|
Sep 18 09:36:04 PM UTC 24 |
Sep 18 09:36:14 PM UTC 24 |
50491879 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.1199841103 |
|
|
Sep 18 09:27:57 PM UTC 24 |
Sep 18 09:36:21 PM UTC 24 |
33528717840 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.3226960545 |
|
|
Sep 18 09:32:27 PM UTC 24 |
Sep 18 09:36:56 PM UTC 24 |
3691954960 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.1267885668 |
|
|
Sep 18 09:32:10 PM UTC 24 |
Sep 18 09:37:05 PM UTC 24 |
4520023472 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.287016053 |
|
|
Sep 18 09:36:31 PM UTC 24 |
Sep 18 09:37:16 PM UTC 24 |
360667604 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.4206748872 |
|
|
Sep 18 09:34:39 PM UTC 24 |
Sep 18 09:37:22 PM UTC 24 |
406413445 ps |
| T1353 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.2071272596 |
|
|
Sep 18 09:29:08 PM UTC 24 |
Sep 18 09:37:23 PM UTC 24 |
13000731248 ps |
| T1354 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.3748109223 |
|
|
Sep 18 09:36:18 PM UTC 24 |
Sep 18 09:37:24 PM UTC 24 |
5707277124 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.1582871506 |
|
|
Sep 18 09:31:50 PM UTC 24 |
Sep 18 09:37:30 PM UTC 24 |
10234815217 ps |
| T1355 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.1457776289 |
|
|
Sep 18 09:36:27 PM UTC 24 |
Sep 18 09:37:39 PM UTC 24 |
4811224824 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.379378088 |
|
|
Sep 18 09:30:13 PM UTC 24 |
Sep 18 09:37:47 PM UTC 24 |
7835606878 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.472410092 |
|
|
Sep 18 09:28:32 PM UTC 24 |
Sep 18 09:37:51 PM UTC 24 |
30205292430 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.1204015755 |
|
|
Sep 18 09:34:37 PM UTC 24 |
Sep 18 09:37:53 PM UTC 24 |
5960054195 ps |
| T1356 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.1785352016 |
|
|
Sep 18 09:37:36 PM UTC 24 |
Sep 18 09:37:57 PM UTC 24 |
346678700 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.3012032233 |
|
|
Sep 18 09:37:22 PM UTC 24 |
Sep 18 09:38:06 PM UTC 24 |
892158370 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.748298454 |
|
|
Sep 18 09:29:55 PM UTC 24 |
Sep 18 09:38:15 PM UTC 24 |
5752122502 ps |
| T1357 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.1259488711 |
|
|
Sep 18 09:37:46 PM UTC 24 |
Sep 18 09:38:18 PM UTC 24 |
614870816 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.3087653719 |
|
|
Sep 18 09:30:31 PM UTC 24 |
Sep 18 09:38:19 PM UTC 24 |
4875817644 ps |
| T1358 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.1238028044 |
|
|
Sep 18 09:38:00 PM UTC 24 |
Sep 18 09:38:20 PM UTC 24 |
336759987 ps |
| T1359 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.114483823 |
|
|
Sep 18 09:37:43 PM UTC 24 |
Sep 18 09:38:25 PM UTC 24 |
249845910 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.1954167912 |
|
|
Sep 18 09:31:20 PM UTC 24 |
Sep 18 09:38:40 PM UTC 24 |
23841764434 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.4213670191 |
|
|
Sep 18 09:34:35 PM UTC 24 |
Sep 18 09:38:42 PM UTC 24 |
812552666 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.2735201245 |
|
|
Sep 18 09:34:40 PM UTC 24 |
Sep 18 09:38:47 PM UTC 24 |
4577431460 ps |
| T1360 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.1528196911 |
|
|
Sep 18 09:38:37 PM UTC 24 |
Sep 18 09:38:50 PM UTC 24 |
161899129 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.1928136020 |
|
|
Sep 18 09:28:44 PM UTC 24 |
Sep 18 09:38:51 PM UTC 24 |
18665308419 ps |
| T1361 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.2224678841 |
|
|
Sep 18 09:37:46 PM UTC 24 |
Sep 18 09:38:53 PM UTC 24 |
1253689094 ps |
| T1362 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.329661676 |
|
|
Sep 18 09:38:46 PM UTC 24 |
Sep 18 09:38:56 PM UTC 24 |
42180148 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.1957160234 |
|
|
Sep 18 09:31:43 PM UTC 24 |
Sep 18 09:38:56 PM UTC 24 |
10894359843 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.302333736 |
|
|
Sep 18 09:27:59 PM UTC 24 |
Sep 18 09:39:04 PM UTC 24 |
73908700532 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1753199764 |
|
|
Sep 18 09:28:03 PM UTC 24 |
Sep 18 09:39:08 PM UTC 24 |
10478809980 ps |
| T1363 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2460728535 |
|
|
Sep 18 09:28:04 PM UTC 24 |
Sep 18 09:39:11 PM UTC 24 |
13675675363 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.1343064218 |
|
|
Sep 18 09:32:01 PM UTC 24 |
Sep 18 09:39:17 PM UTC 24 |
7113391005 ps |
| T1364 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.4175021277 |
|
|
Sep 18 09:39:17 PM UTC 24 |
Sep 18 09:39:35 PM UTC 24 |
355371459 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.1533616012 |
|
|
Sep 18 09:37:51 PM UTC 24 |
Sep 18 09:39:41 PM UTC 24 |
255174720 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.4196195806 |
|
|
Sep 18 09:38:55 PM UTC 24 |
Sep 18 09:39:42 PM UTC 24 |
352925114 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.950634907 |
|
|
Sep 18 09:34:31 PM UTC 24 |
Sep 18 09:39:42 PM UTC 24 |
7651379586 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.2971091352 |
|
|
Sep 18 09:38:49 PM UTC 24 |
Sep 18 09:39:51 PM UTC 24 |
1874790377 ps |
| T1365 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.3628362627 |
|
|
Sep 18 09:38:46 PM UTC 24 |
Sep 18 09:40:04 PM UTC 24 |
8485974993 ps |
| T1366 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.3397420449 |
|
|
Sep 18 09:38:50 PM UTC 24 |
Sep 18 09:40:10 PM UTC 24 |
3627405153 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.2597312596 |
|
|
Sep 18 09:39:26 PM UTC 24 |
Sep 18 09:40:13 PM UTC 24 |
290418284 ps |
| T1367 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.502186299 |
|
|
Sep 18 09:39:23 PM UTC 24 |
Sep 18 09:40:15 PM UTC 24 |
1385927163 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.1754800944 |
|
|
Sep 18 09:40:16 PM UTC 24 |
Sep 18 09:40:28 PM UTC 24 |
260065796 ps |
| T1368 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.3516970245 |
|
|
Sep 18 09:39:23 PM UTC 24 |
Sep 18 09:40:30 PM UTC 24 |
1416634318 ps |
| T1369 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.120510133 |
|
|
Sep 18 09:39:39 PM UTC 24 |
Sep 18 09:40:34 PM UTC 24 |
9013345 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.1432698559 |
|
|
Sep 18 09:30:12 PM UTC 24 |
Sep 18 09:40:39 PM UTC 24 |
6833094523 ps |
| T1370 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.217722305 |
|
|
Sep 18 09:40:34 PM UTC 24 |
Sep 18 09:40:44 PM UTC 24 |
55317825 ps |
| T1371 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.399122216 |
|
|
Sep 18 09:39:39 PM UTC 24 |
Sep 18 09:40:49 PM UTC 24 |
1908095454 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.4235695793 |
|
|
Sep 18 09:39:17 PM UTC 24 |
Sep 18 09:40:55 PM UTC 24 |
2551061935 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.217993820 |
|
|
Sep 18 09:33:22 PM UTC 24 |
Sep 18 09:40:59 PM UTC 24 |
29083969919 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.2885262985 |
|
|
Sep 18 09:38:25 PM UTC 24 |
Sep 18 09:41:05 PM UTC 24 |
3165077183 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.906886476 |
|
|
Sep 18 09:32:20 PM UTC 24 |
Sep 18 09:41:07 PM UTC 24 |
7897422470 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3557985103 |
|
|
Sep 18 09:31:25 PM UTC 24 |
Sep 18 09:41:13 PM UTC 24 |
37994424985 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.107726232 |
|
|
Sep 18 09:28:21 PM UTC 24 |
Sep 18 09:41:13 PM UTC 24 |
48907708468 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.1224629351 |
|
|
Sep 18 09:40:41 PM UTC 24 |
Sep 18 09:41:26 PM UTC 24 |
1122602638 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.4067527950 |
|
|
Sep 18 09:35:29 PM UTC 24 |
Sep 18 09:41:35 PM UTC 24 |
3335640006 ps |
| T1372 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.1781813974 |
|
|
Sep 18 09:41:20 PM UTC 24 |
Sep 18 09:41:41 PM UTC 24 |
209587330 ps |
| T1373 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.4204199431 |
|
|
Sep 18 09:40:44 PM UTC 24 |
Sep 18 09:41:48 PM UTC 24 |
3900979890 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.3830444674 |
|
|
Sep 18 09:40:38 PM UTC 24 |
Sep 18 09:41:51 PM UTC 24 |
7261638885 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.28956084 |
|
|
Sep 18 09:39:18 PM UTC 24 |
Sep 18 09:41:52 PM UTC 24 |
10742963959 ps |
| T1374 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.2342516786 |
|
|
Sep 18 09:40:57 PM UTC 24 |
Sep 18 09:41:54 PM UTC 24 |
546234981 ps |
| T1375 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.2584999997 |
|
|
Sep 18 09:41:29 PM UTC 24 |
Sep 18 09:41:55 PM UTC 24 |
552823147 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.4082055451 |
|
|
Sep 18 09:41:04 PM UTC 24 |
Sep 18 09:41:58 PM UTC 24 |
1212551888 ps |
| T1376 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.1266372109 |
|
|
Sep 18 09:41:26 PM UTC 24 |
Sep 18 09:41:59 PM UTC 24 |
200897385 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.4072360205 |
|
|
Sep 18 09:29:26 PM UTC 24 |
Sep 18 09:42:03 PM UTC 24 |
44493796059 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.491808424 |
|
|
Sep 18 09:32:16 PM UTC 24 |
Sep 18 09:42:14 PM UTC 24 |
6110758488 ps |
| T1377 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.175264258 |
|
|
Sep 18 09:29:09 PM UTC 24 |
Sep 18 09:42:23 PM UTC 24 |
19265411423 ps |
| T1378 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.1309907883 |
|
|
Sep 18 09:42:16 PM UTC 24 |
Sep 18 09:42:26 PM UTC 24 |
46847225 ps |
| T1379 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.903702913 |
|
|
Sep 18 09:42:18 PM UTC 24 |
Sep 18 09:42:28 PM UTC 24 |
37413833 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.1783620840 |
|
|
Sep 18 09:30:23 PM UTC 24 |
Sep 18 09:42:28 PM UTC 24 |
5173085543 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1243290814 |
|
|
Sep 18 09:38:05 PM UTC 24 |
Sep 18 09:42:34 PM UTC 24 |
4038643255 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.2474395791 |
|
|
Sep 18 09:41:33 PM UTC 24 |
Sep 18 09:42:36 PM UTC 24 |
682156201 ps |
| T1380 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.2790664182 |
|
|
Sep 18 09:42:30 PM UTC 24 |
Sep 18 09:42:40 PM UTC 24 |
39746533 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.2624482277 |
|
|
Sep 18 09:37:48 PM UTC 24 |
Sep 18 09:42:45 PM UTC 24 |
3359716197 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.94035141 |
|
|
Sep 18 09:40:12 PM UTC 24 |
Sep 18 09:42:51 PM UTC 24 |
3180916400 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.4210817111 |
|
|
Sep 18 09:41:15 PM UTC 24 |
Sep 18 09:42:52 PM UTC 24 |
2120210270 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.2871409247 |
|
|
Sep 18 09:41:42 PM UTC 24 |
Sep 18 09:43:03 PM UTC 24 |
289874412 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.2820613757 |
|
|
Sep 18 09:31:04 PM UTC 24 |
Sep 18 09:43:03 PM UTC 24 |
66136099439 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.3385505343 |
|
|
Sep 18 09:28:23 PM UTC 24 |
Sep 18 09:43:06 PM UTC 24 |
97388986714 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.2466153074 |
|
|
Sep 18 09:42:53 PM UTC 24 |
Sep 18 09:43:06 PM UTC 24 |
102109615 ps |
| T1381 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.792237887 |
|
|
Sep 18 09:42:58 PM UTC 24 |
Sep 18 09:43:14 PM UTC 24 |
105056904 ps |
| T1382 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.3893746177 |
|
|
Sep 18 09:42:27 PM UTC 24 |
Sep 18 09:43:17 PM UTC 24 |
444625752 ps |
| T1383 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.189755995 |
|
|
Sep 18 09:43:04 PM UTC 24 |
Sep 18 09:43:31 PM UTC 24 |
148673286 ps |
| T1384 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.1258984886 |
|
|
Sep 18 09:42:24 PM UTC 24 |
Sep 18 09:43:43 PM UTC 24 |
7825953950 ps |
| T1385 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.4150033525 |
|
|
Sep 18 09:42:23 PM UTC 24 |
Sep 18 09:43:43 PM UTC 24 |
5017296323 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.3656047215 |
|
|
Sep 18 09:42:58 PM UTC 24 |
Sep 18 09:43:46 PM UTC 24 |
421930145 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.1249608365 |
|
|
Sep 18 09:29:36 PM UTC 24 |
Sep 18 09:43:53 PM UTC 24 |
59795330869 ps |
| T1386 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.1864209515 |
|
|
Sep 18 09:43:41 PM UTC 24 |
Sep 18 09:43:56 PM UTC 24 |
239013675 ps |
| T1387 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.1256060815 |
|
|
Sep 18 09:43:47 PM UTC 24 |
Sep 18 09:43:58 PM UTC 24 |
45819934 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.1974811388 |
|
|
Sep 18 09:30:20 PM UTC 24 |
Sep 18 09:43:58 PM UTC 24 |
9177649340 ps |
| T1388 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.1921466226 |
|
|
Sep 18 09:43:05 PM UTC 24 |
Sep 18 09:44:07 PM UTC 24 |
1130516205 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1566024714 |
|
|
Sep 18 09:43:15 PM UTC 24 |
Sep 18 09:44:12 PM UTC 24 |
194359944 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3107137442 |
|
|
Sep 18 09:28:52 PM UTC 24 |
Sep 18 09:44:43 PM UTC 24 |
11270514936 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.1518106017 |
|
|
Sep 18 09:33:19 PM UTC 24 |
Sep 18 09:44:52 PM UTC 24 |
60864032990 ps |
| T1389 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.1262404618 |
|
|
Sep 18 09:43:22 PM UTC 24 |
Sep 18 09:44:53 PM UTC 24 |
790330014 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.2265368882 |
|
|
Sep 18 09:44:11 PM UTC 24 |
Sep 18 09:44:54 PM UTC 24 |
533503721 ps |
| T1390 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.3881251633 |
|
|
Sep 18 09:44:41 PM UTC 24 |
Sep 18 09:45:11 PM UTC 24 |
497474434 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.3525762414 |
|
|
Sep 18 09:44:10 PM UTC 24 |
Sep 18 09:45:15 PM UTC 24 |
555840637 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1765070673 |
|
|
Sep 18 09:39:47 PM UTC 24 |
Sep 18 09:45:16 PM UTC 24 |
4393094364 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.4217778295 |
|
|
Sep 18 09:34:53 PM UTC 24 |
Sep 18 09:45:23 PM UTC 24 |
5490758148 ps |
| T1391 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.3787590892 |
|
|
Sep 18 09:44:00 PM UTC 24 |
Sep 18 09:45:34 PM UTC 24 |
7336542816 ps |
| T1392 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.2906670450 |
|
|
Sep 18 09:45:22 PM UTC 24 |
Sep 18 09:45:40 PM UTC 24 |
404331103 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.3438117007 |
|
|
Sep 18 09:44:25 PM UTC 24 |
Sep 18 09:45:44 PM UTC 24 |
730775127 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.1242623672 |
|
|
Sep 18 09:42:17 PM UTC 24 |
Sep 18 09:45:46 PM UTC 24 |
3162111076 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.1596835710 |
|
|
Sep 18 09:45:14 PM UTC 24 |
Sep 18 09:45:47 PM UTC 24 |
285744443 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.1240092949 |
|
|
Sep 18 09:44:11 PM UTC 24 |
Sep 18 09:46:01 PM UTC 24 |
6025075052 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.2614548661 |
|
|
Sep 18 09:30:01 PM UTC 24 |
Sep 18 09:46:04 PM UTC 24 |
21852793840 ps |
| T1393 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.1739496143 |
|
|
Sep 18 09:42:33 PM UTC 24 |
Sep 18 09:46:13 PM UTC 24 |
23042688271 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.2075208265 |
|
|
Sep 18 09:44:32 PM UTC 24 |
Sep 18 09:46:15 PM UTC 24 |
2398103706 ps |
| T1394 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.798036381 |
|
|
Sep 18 09:46:10 PM UTC 24 |
Sep 18 09:46:20 PM UTC 24 |
49568659 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.336729242 |
|
|
Sep 18 09:46:15 PM UTC 24 |
Sep 18 09:46:30 PM UTC 24 |
229506372 ps |
| T1395 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.2355294117 |
|
|
Sep 18 09:38:19 PM UTC 24 |
Sep 18 09:46:48 PM UTC 24 |
6834368196 ps |
| T1396 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.3781825623 |
|
|
Sep 18 09:44:24 PM UTC 24 |
Sep 18 09:46:55 PM UTC 24 |
11145376710 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.1941060286 |
|
|
Sep 18 09:43:12 PM UTC 24 |
Sep 18 09:47:07 PM UTC 24 |
6505405523 ps |
| T1397 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.61035834 |
|
|
Sep 18 09:46:35 PM UTC 24 |
Sep 18 09:47:13 PM UTC 24 |
399632440 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.4001840271 |
|
|
Sep 18 09:42:06 PM UTC 24 |
Sep 18 09:47:37 PM UTC 24 |
6768667050 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.262406218 |
|
|
Sep 18 09:46:41 PM UTC 24 |
Sep 18 09:47:38 PM UTC 24 |
474561016 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.1808769080 |
|
|
Sep 18 09:38:15 PM UTC 24 |
Sep 18 09:47:46 PM UTC 24 |
5601499697 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.3175666938 |
|
|
Sep 18 09:45:21 PM UTC 24 |
Sep 18 09:47:53 PM UTC 24 |
3112018413 ps |
| T1398 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.2600790989 |
|
|
Sep 18 09:47:43 PM UTC 24 |
Sep 18 09:47:57 PM UTC 24 |
155726997 ps |
| T1399 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.3026677079 |
|
|
Sep 18 09:47:26 PM UTC 24 |
Sep 18 09:48:00 PM UTC 24 |
736436364 ps |
| T1400 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.1687149148 |
|
|
Sep 18 09:47:37 PM UTC 24 |
Sep 18 09:48:03 PM UTC 24 |
199712340 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.1223055884 |
|
|
Sep 18 09:45:21 PM UTC 24 |
Sep 18 09:48:05 PM UTC 24 |
382699373 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.1600742324 |
|
|
Sep 18 09:39:34 PM UTC 24 |
Sep 18 09:48:07 PM UTC 24 |
13284447883 ps |
| T1401 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.229809923 |
|
|
Sep 18 09:27:55 PM UTC 24 |
Sep 18 09:48:18 PM UTC 24 |
10329360644 ps |
| T1402 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.4004501254 |
|
|
Sep 18 09:46:15 PM UTC 24 |
Sep 18 09:48:19 PM UTC 24 |
7733398639 ps |
| T1403 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.601966302 |
|
|
Sep 18 09:46:25 PM UTC 24 |
Sep 18 09:48:20 PM UTC 24 |
4889360181 ps |
| T1404 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3218392653 |
|
|
Sep 18 09:48:08 PM UTC 24 |
Sep 18 09:48:23 PM UTC 24 |
281677874 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.3925611326 |
|
|
Sep 18 09:43:36 PM UTC 24 |
Sep 18 09:48:31 PM UTC 24 |
4419319204 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.43306931 |
|
|
Sep 18 09:28:01 PM UTC 24 |
Sep 18 09:48:33 PM UTC 24 |
89939379624 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.988265380 |
|
|
Sep 18 09:45:36 PM UTC 24 |
Sep 18 09:48:34 PM UTC 24 |
1939768239 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.145622235 |
|
|
Sep 18 09:44:28 PM UTC 24 |
Sep 18 09:48:38 PM UTC 24 |
13032104477 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.1233483003 |
|
|
Sep 18 09:46:56 PM UTC 24 |
Sep 18 09:48:42 PM UTC 24 |
1120454599 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.2487857338 |
|
|
Sep 18 09:45:44 PM UTC 24 |
Sep 18 09:48:48 PM UTC 24 |
643625115 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.1503992032 |
|
|
Sep 18 09:39:11 PM UTC 24 |
Sep 18 09:48:55 PM UTC 24 |
35628573490 ps |
| T1405 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3298926155 |
|
|
Sep 18 09:48:46 PM UTC 24 |
Sep 18 09:48:56 PM UTC 24 |
51765693 ps |
| T1406 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.3667678867 |
|
|
Sep 18 09:48:47 PM UTC 24 |
Sep 18 09:48:58 PM UTC 24 |
54926893 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.1366655726 |
|
|
Sep 18 09:41:36 PM UTC 24 |
Sep 18 09:49:06 PM UTC 24 |
5938987135 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.3268396016 |
|
|
Sep 18 09:46:10 PM UTC 24 |
Sep 18 09:49:11 PM UTC 24 |
2835298888 ps |
| T1407 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.1886721368 |
|
|
Sep 18 09:49:03 PM UTC 24 |
Sep 18 09:49:13 PM UTC 24 |
36147040 ps |
| T1408 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2358489906 |
|
|
Sep 18 09:48:49 PM UTC 24 |
Sep 18 09:49:33 PM UTC 24 |
3216495761 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.229818930 |
|
|
Sep 18 09:41:43 PM UTC 24 |
Sep 18 09:49:37 PM UTC 24 |
13812034862 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.3360266234 |
|
|
Sep 18 09:49:01 PM UTC 24 |
Sep 18 09:49:44 PM UTC 24 |
1137269481 ps |
| T1409 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.3710324597 |
|
|
Sep 18 09:49:28 PM UTC 24 |
Sep 18 09:49:48 PM UTC 24 |
257456207 ps |
| T1410 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.4290388987 |
|
|
Sep 18 09:49:37 PM UTC 24 |
Sep 18 09:49:56 PM UTC 24 |
234605645 ps |
| T1411 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.1701314498 |
|
|
Sep 18 09:36:52 PM UTC 24 |
Sep 18 09:50:21 PM UTC 24 |
54195984234 ps |
| T1412 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.3476637548 |
|
|
Sep 18 09:48:51 PM UTC 24 |
Sep 18 09:50:31 PM UTC 24 |
9339802282 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.334677819 |
|
|
Sep 18 09:43:20 PM UTC 24 |
Sep 18 09:50:32 PM UTC 24 |
2927283190 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.3409575790 |
|
|
Sep 18 09:49:25 PM UTC 24 |
Sep 18 09:50:40 PM UTC 24 |
2368916605 ps |
| T1413 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.3127123594 |
|
|
Sep 18 09:49:27 PM UTC 24 |
Sep 18 09:50:44 PM UTC 24 |
1630369763 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.723510779 |
|
|
Sep 18 09:40:02 PM UTC 24 |
Sep 18 09:50:49 PM UTC 24 |
6081629084 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.2912462043 |
|
|
Sep 18 09:45:47 PM UTC 24 |
Sep 18 09:50:52 PM UTC 24 |
4483074396 ps |
| T1414 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.3880369645 |
|
|
Sep 18 09:35:05 PM UTC 24 |
Sep 18 09:50:54 PM UTC 24 |
7958331021 ps |
| T1415 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1084953150 |
|
|
Sep 18 09:51:00 PM UTC 24 |
Sep 18 09:51:11 PM UTC 24 |
53429784 ps |
| T1416 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.567479783 |
|
|
Sep 18 09:51:01 PM UTC 24 |
Sep 18 09:51:15 PM UTC 24 |
189045491 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.2713982755 |
|
|
Sep 18 09:49:42 PM UTC 24 |
Sep 18 09:51:20 PM UTC 24 |
884770635 ps |
| T1417 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.2194472164 |
|
|
Sep 18 09:46:43 PM UTC 24 |
Sep 18 09:51:24 PM UTC 24 |
27128270901 ps |
| T1418 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.2187410184 |
|
|
Sep 18 09:39:10 PM UTC 24 |
Sep 18 09:51:25 PM UTC 24 |
58839274300 ps |
| T1419 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.3125149737 |
|
|
Sep 18 09:43:34 PM UTC 24 |
Sep 18 09:51:29 PM UTC 24 |
5680239569 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2635197076 |
|
|
Sep 18 09:48:17 PM UTC 24 |
Sep 18 09:51:56 PM UTC 24 |
661963012 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.1691151541 |
|
|
Sep 18 09:41:51 PM UTC 24 |
Sep 18 09:52:04 PM UTC 24 |
5712957146 ps |