Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.18 95.53 94.11 95.38 94.93 97.57 99.59


Total test records in report: 2931
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html | tests61.html | tests62.html
T1263 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx1.3527011872 Sep 19 05:06:54 AM UTC 24 Sep 19 05:17:04 AM UTC 24 4034919340 ps
T1264 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx2.174895780 Sep 19 05:07:20 AM UTC 24 Sep 19 05:17:16 AM UTC 24 4237039532 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.4218094924 Sep 19 05:09:58 AM UTC 24 Sep 19 05:17:17 AM UTC 24 3960783752 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.1577402102 Sep 19 05:04:30 AM UTC 24 Sep 19 05:17:24 AM UTC 24 6538514714 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2435449240 Sep 19 05:09:58 AM UTC 24 Sep 19 05:17:40 AM UTC 24 7473735224 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx.288149199 Sep 19 05:06:37 AM UTC 24 Sep 19 05:18:02 AM UTC 24 4453563906 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx3.4127324946 Sep 19 05:09:29 AM UTC 24 Sep 19 05:18:39 AM UTC 24 4016999920 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_rma.1498859589 Sep 19 05:12:21 AM UTC 24 Sep 19 05:19:50 AM UTC 24 5631437721 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.60494234 Sep 19 05:02:42 AM UTC 24 Sep 19 05:20:03 AM UTC 24 7213463728 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1502515201 Sep 19 05:09:28 AM UTC 24 Sep 19 05:20:18 AM UTC 24 3843651481 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.3412515506 Sep 19 05:10:37 AM UTC 24 Sep 19 05:21:22 AM UTC 24 7309916916 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.2312158067 Sep 19 05:09:30 AM UTC 24 Sep 19 05:21:30 AM UTC 24 5017628096 ps
T1265 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3908162881 Sep 19 04:01:36 AM UTC 24 Sep 19 05:21:57 AM UTC 24 18829098585 ps
T721 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.583685728 Sep 19 05:14:05 AM UTC 24 Sep 19 05:22:14 AM UTC 24 5799974666 ps
T1266 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.1509792150 Sep 19 05:14:07 AM UTC 24 Sep 19 05:22:52 AM UTC 24 4234028808 ps
T710 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.712751045 Sep 19 05:16:36 AM UTC 24 Sep 19 05:23:02 AM UTC 24 4053816216 ps
T1267 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.3827928359 Sep 19 05:13:04 AM UTC 24 Sep 19 05:23:03 AM UTC 24 5636215683 ps
T1268 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_lc_ctrl_transition.2488617387 Sep 19 05:16:07 AM UTC 24 Sep 19 05:23:55 AM UTC 24 4678782628 ps
T1269 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.1587784089 Sep 19 05:14:08 AM UTC 24 Sep 19 05:24:00 AM UTC 24 4904929300 ps
T1270 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_testunlock0.409403659 Sep 19 05:11:24 AM UTC 24 Sep 19 05:24:43 AM UTC 24 8073439758 ps
T1271 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.1331495575 Sep 19 05:09:23 AM UTC 24 Sep 19 05:25:47 AM UTC 24 10461540374 ps
T1272 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency.546026021 Sep 19 04:13:46 AM UTC 24 Sep 19 05:26:45 AM UTC 24 15142165540 ps
T736 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1565345053 Sep 19 05:19:01 AM UTC 24 Sep 19 05:27:17 AM UTC 24 4566383520 ps
T711 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.4228613557 Sep 19 05:19:23 AM UTC 24 Sep 19 05:27:29 AM UTC 24 4208813858 ps
T782 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.2802209316 Sep 19 05:18:29 AM UTC 24 Sep 19 05:27:40 AM UTC 24 6061276330 ps
T1273 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.979683883 Sep 19 05:00:15 AM UTC 24 Sep 19 05:28:04 AM UTC 24 8680056000 ps
T1274 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1262655776 Sep 19 05:09:19 AM UTC 24 Sep 19 05:28:06 AM UTC 24 9481622693 ps
T713 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2928539703 Sep 19 05:22:20 AM UTC 24 Sep 19 05:28:08 AM UTC 24 3841900648 ps
T1275 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.3997921869 Sep 19 05:19:07 AM UTC 24 Sep 19 05:28:14 AM UTC 24 6244466146 ps
T1276 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.1192320488 Sep 19 05:19:01 AM UTC 24 Sep 19 05:29:39 AM UTC 24 4571135834 ps
T1277 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_self_hash.1516457625 Sep 19 03:15:26 AM UTC 24 Sep 19 05:30:00 AM UTC 24 26995177268 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.3144471236 Sep 19 05:18:57 AM UTC 24 Sep 19 05:30:08 AM UTC 24 6179556776 ps
T796 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1717638362 Sep 19 05:24:04 AM UTC 24 Sep 19 05:30:24 AM UTC 24 3557144432 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.1463179725 Sep 19 03:42:48 AM UTC 24 Sep 19 05:30:55 AM UTC 24 49533308946 ps
T1278 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_lc_ctrl_transition.4021882683 Sep 19 05:24:03 AM UTC 24 Sep 19 05:31:19 AM UTC 24 4968252811 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.878776228 Sep 19 04:21:27 AM UTC 24 Sep 19 05:32:13 AM UTC 24 14945939540 ps
T777 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.1364346948 Sep 19 05:21:04 AM UTC 24 Sep 19 05:32:24 AM UTC 24 5758282970 ps
T1279 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.1681121711 Sep 19 05:24:03 AM UTC 24 Sep 19 05:32:47 AM UTC 24 4339823822 ps
T645 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.39545832 Sep 19 05:11:01 AM UTC 24 Sep 19 05:34:16 AM UTC 24 12589641451 ps
T1280 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_smoketest.1833104020 Sep 19 04:53:50 AM UTC 24 Sep 19 05:34:20 AM UTC 24 11260872960 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.312457801 Sep 19 05:27:31 AM UTC 24 Sep 19 05:34:34 AM UTC 24 3763047040 ps
T693 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2267474019 Sep 19 05:29:20 AM UTC 24 Sep 19 05:35:05 AM UTC 24 4104231620 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.3391362748 Sep 19 05:24:53 AM UTC 24 Sep 19 05:35:16 AM UTC 24 4902185640 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.2273993464 Sep 19 05:26:32 AM UTC 24 Sep 19 05:35:17 AM UTC 24 5905023026 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.2700077366 Sep 19 05:22:59 AM UTC 24 Sep 19 05:35:18 AM UTC 24 5843152192 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_lc_ctrl_transition.3618979722 Sep 19 05:28:27 AM UTC 24 Sep 19 05:36:41 AM UTC 24 6447504577 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.2668477142 Sep 19 05:28:21 AM UTC 24 Sep 19 05:37:35 AM UTC 24 5313431764 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.53628107 Sep 19 05:29:25 AM UTC 24 Sep 19 05:38:42 AM UTC 24 5443084480 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.87167766 Sep 19 05:30:25 AM UTC 24 Sep 19 05:38:54 AM UTC 24 4462737128 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.108103114 Sep 19 05:29:22 AM UTC 24 Sep 19 05:39:15 AM UTC 24 6068637010 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.376676808 Sep 19 05:31:11 AM UTC 24 Sep 19 05:39:31 AM UTC 24 6383995439 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2168175080 Sep 19 05:31:41 AM UTC 24 Sep 19 05:40:08 AM UTC 24 3863084122 ps
T1281 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_lc_ctrl_transition.985256054 Sep 19 05:19:19 AM UTC 24 Sep 19 05:40:29 AM UTC 24 9737690341 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.4126956428 Sep 19 05:32:11 AM UTC 24 Sep 19 05:40:34 AM UTC 24 4365264032 ps
T748 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2701325545 Sep 19 05:33:10 AM UTC 24 Sep 19 05:40:45 AM UTC 24 3736588472 ps
T1282 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.1787643932 Sep 19 03:42:47 AM UTC 24 Sep 19 05:40:50 AM UTC 24 48953283198 ps
T1283 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.3208056333 Sep 19 05:32:11 AM UTC 24 Sep 19 05:41:01 AM UTC 24 3545659244 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_rst_inputs.4155272193 Sep 19 04:44:24 AM UTC 24 Sep 19 05:41:08 AM UTC 24 20703719792 ps
T787 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1255488406 Sep 19 05:35:29 AM UTC 24 Sep 19 05:41:46 AM UTC 24 4019637138 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3637720438 Sep 19 05:36:28 AM UTC 24 Sep 19 05:41:59 AM UTC 24 3154083824 ps
T730 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.1680898781 Sep 19 05:31:07 AM UTC 24 Sep 19 05:42:23 AM UTC 24 5813630358 ps
T1284 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.2615891989 Sep 19 05:22:19 AM UTC 24 Sep 19 05:42:27 AM UTC 24 11600934584 ps
T1285 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_test_unlocked0.4201410251 Sep 19 04:47:30 AM UTC 24 Sep 19 05:42:30 AM UTC 24 11634744928 ps
T1286 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.2333697058 Sep 19 05:32:55 AM UTC 24 Sep 19 05:42:57 AM UTC 24 5884404837 ps
T1287 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.372462183 Sep 19 05:35:27 AM UTC 24 Sep 19 05:42:57 AM UTC 24 3276793000 ps
T708 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.1936779564 Sep 19 05:33:29 AM UTC 24 Sep 19 05:43:24 AM UTC 24 4639504692 ps
T1288 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.3239476557 Sep 19 05:21:05 AM UTC 24 Sep 19 05:44:15 AM UTC 24 7838458100 ps
T804 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.940051016 Sep 19 05:37:28 AM UTC 24 Sep 19 05:45:33 AM UTC 24 3602529880 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.1193696538 Sep 19 05:35:30 AM UTC 24 Sep 19 05:46:24 AM UTC 24 6005878216 ps
T681 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.2284797426 Sep 19 05:36:22 AM UTC 24 Sep 19 05:46:35 AM UTC 24 4973679480 ps
T778 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2440807847 Sep 19 05:40:55 AM UTC 24 Sep 19 05:46:50 AM UTC 24 3229147658 ps
T783 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2839796303 Sep 19 05:39:42 AM UTC 24 Sep 19 05:46:56 AM UTC 24 3604336176 ps
T1289 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.127641614 Sep 19 05:19:07 AM UTC 24 Sep 19 05:47:36 AM UTC 24 8509613720 ps
T1290 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.3764187018 Sep 19 05:00:11 AM UTC 24 Sep 19 05:47:44 AM UTC 24 13257815920 ps
T756 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2214800280 Sep 19 05:43:15 AM UTC 24 Sep 19 05:48:47 AM UTC 24 2965232844 ps
T743 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.775763953 Sep 19 05:42:44 AM UTC 24 Sep 19 05:49:51 AM UTC 24 4220073392 ps
T745 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.2352862593 Sep 19 05:55:02 AM UTC 24 Sep 19 06:05:32 AM UTC 24 5417836800 ps
T725 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.106950570 Sep 19 05:44:15 AM UTC 24 Sep 19 05:50:37 AM UTC 24 3825093100 ps
T752 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.244940659 Sep 19 05:43:55 AM UTC 24 Sep 19 05:50:37 AM UTC 24 3374591792 ps
T802 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.4175569228 Sep 19 05:38:22 AM UTC 24 Sep 19 05:50:42 AM UTC 24 5921123180 ps
T1291 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.686805201 Sep 19 04:45:41 AM UTC 24 Sep 19 05:50:50 AM UTC 24 14083649399 ps
T712 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.3257050000 Sep 19 05:42:29 AM UTC 24 Sep 19 05:50:53 AM UTC 24 5171416116 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2297862808 Sep 19 05:42:51 AM UTC 24 Sep 19 05:50:55 AM UTC 24 4446808400 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.3964774291 Sep 19 05:42:51 AM UTC 24 Sep 19 05:51:45 AM UTC 24 5640254408 ps
T770 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.364970207 Sep 19 05:44:15 AM UTC 24 Sep 19 05:51:53 AM UTC 24 3431748860 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.978306652 Sep 19 05:42:15 AM UTC 24 Sep 19 05:51:59 AM UTC 24 6042232396 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.805207975 Sep 19 05:40:13 AM UTC 24 Sep 19 05:51:59 AM UTC 24 4604251380 ps
T733 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2298149240 Sep 19 05:43:15 AM UTC 24 Sep 19 05:52:27 AM UTC 24 4162521032 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2927415254 Sep 19 05:46:32 AM UTC 24 Sep 19 05:52:53 AM UTC 24 4213209476 ps
T684 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.3294359630 Sep 19 05:42:47 AM UTC 24 Sep 19 05:52:56 AM UTC 24 5496373104 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.2977316124 Sep 19 05:44:09 AM UTC 24 Sep 19 05:53:19 AM UTC 24 4121691848 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2920137995 Sep 19 05:47:18 AM UTC 24 Sep 19 05:53:45 AM UTC 24 4008390520 ps
T678 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.3804466194 Sep 19 05:44:10 AM UTC 24 Sep 19 05:53:58 AM UTC 24 5235807256 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.1639518415 Sep 19 05:43:56 AM UTC 24 Sep 19 05:54:02 AM UTC 24 5599984520 ps
T726 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1207497 Sep 19 05:47:48 AM UTC 24 Sep 19 05:54:47 AM UTC 24 3890842264 ps
T1292 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.1494084355 Sep 19 04:45:31 AM UTC 24 Sep 19 05:54:48 AM UTC 24 14995515096 ps
T1293 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2743411516 Sep 19 04:48:59 AM UTC 24 Sep 19 05:54:55 AM UTC 24 14314831948 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1947405317 Sep 19 05:49:34 AM UTC 24 Sep 19 05:55:00 AM UTC 24 3544073396 ps
T1294 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod_end.1179892264 Sep 19 04:47:55 AM UTC 24 Sep 19 05:55:55 AM UTC 24 14736255358 ps
T679 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1238098854 Sep 19 05:48:36 AM UTC 24 Sep 19 05:56:01 AM UTC 24 4108191856 ps
T1295 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.2438077939 Sep 19 05:28:26 AM UTC 24 Sep 19 05:56:08 AM UTC 24 8949994936 ps
T1296 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.1328468148 Sep 19 04:46:23 AM UTC 24 Sep 19 05:56:45 AM UTC 24 27227153886 ps
T1297 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod.257544679 Sep 19 04:47:42 AM UTC 24 Sep 19 05:56:46 AM UTC 24 15209607759 ps
T1298 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.3069655984 Sep 19 05:46:32 AM UTC 24 Sep 19 05:56:49 AM UTC 24 4720535000 ps
T1299 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_rma.1588460241 Sep 19 04:47:43 AM UTC 24 Sep 19 05:56:52 AM UTC 24 15053792369 ps
T767 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.2437464224 Sep 19 05:47:47 AM UTC 24 Sep 19 05:57:30 AM UTC 24 4020409990 ps
T1300 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.4218201995 Sep 19 04:44:03 AM UTC 24 Sep 19 05:57:53 AM UTC 24 21917228619 ps
T1301 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2926842525 Sep 19 04:48:53 AM UTC 24 Sep 19 05:58:09 AM UTC 24 14937492560 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.3580902224 Sep 19 05:47:41 AM UTC 24 Sep 19 05:58:11 AM UTC 24 5910918602 ps
T760 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.2817797029 Sep 19 05:45:01 AM UTC 24 Sep 19 05:58:47 AM UTC 24 5471246636 ps
T680 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.2422341113 Sep 19 05:48:36 AM UTC 24 Sep 19 05:58:54 AM UTC 24 5118200880 ps
T803 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2970721743 Sep 19 05:53:14 AM UTC 24 Sep 19 05:59:14 AM UTC 24 3809021248 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3657669776 Sep 19 05:52:57 AM UTC 24 Sep 19 05:59:24 AM UTC 24 4060111116 ps
T1302 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_dev.3823411684 Sep 19 04:47:02 AM UTC 24 Sep 19 05:59:45 AM UTC 24 14998721264 ps
T792 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.661125244 Sep 19 05:52:58 AM UTC 24 Sep 19 05:59:49 AM UTC 24 3363568600 ps
T759 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3880355995 Sep 19 05:53:24 AM UTC 24 Sep 19 06:00:20 AM UTC 24 4577216862 ps
T700 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3805055309 Sep 19 05:54:30 AM UTC 24 Sep 19 06:00:29 AM UTC 24 3254930440 ps
T1303 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.3634202140 Sep 19 05:36:28 AM UTC 24 Sep 19 06:00:31 AM UTC 24 8493478448 ps
T749 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1314881066 Sep 19 05:54:15 AM UTC 24 Sep 19 06:00:55 AM UTC 24 3452358750 ps
T685 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.4179775364 Sep 19 05:50:38 AM UTC 24 Sep 19 06:00:58 AM UTC 24 4618922584 ps
T724 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.752239680 Sep 19 05:52:15 AM UTC 24 Sep 19 06:01:11 AM UTC 24 4694597712 ps
T1304 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1945727997 Sep 19 04:42:31 AM UTC 24 Sep 19 06:01:22 AM UTC 24 24677416888 ps
T716 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.970048237 Sep 19 05:52:30 AM UTC 24 Sep 19 06:01:36 AM UTC 24 4878553320 ps
T1305 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.4086247665 Sep 19 04:48:29 AM UTC 24 Sep 19 06:01:42 AM UTC 24 15186108238 ps
T769 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1855456471 Sep 19 05:56:02 AM UTC 24 Sep 19 06:01:50 AM UTC 24 3883618660 ps
T1306 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.3757947011 Sep 19 05:53:28 AM UTC 24 Sep 19 06:02:19 AM UTC 24 4874723852 ps
T702 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.283562546 Sep 19 05:55:05 AM UTC 24 Sep 19 06:02:20 AM UTC 24 3464031844 ps
T784 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2683136978 Sep 19 05:55:09 AM UTC 24 Sep 19 06:02:38 AM UTC 24 3489707232 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2897090261 Sep 19 05:56:04 AM UTC 24 Sep 19 06:02:50 AM UTC 24 3794083428 ps
T1307 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.3269253364 Sep 19 05:36:28 AM UTC 24 Sep 19 06:02:52 AM UTC 24 8159990612 ps
T728 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.485111146 Sep 19 05:55:05 AM UTC 24 Sep 19 06:03:00 AM UTC 24 4777132120 ps
T789 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.3036734989 Sep 19 05:53:27 AM UTC 24 Sep 19 06:03:29 AM UTC 24 5772910836 ps
T722 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.2656013131 Sep 19 05:53:11 AM UTC 24 Sep 19 06:03:48 AM UTC 24 6028651640 ps
T717 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1418508739 Sep 19 05:57:03 AM UTC 24 Sep 19 06:04:07 AM UTC 24 3735398188 ps
T705 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2864719854 Sep 19 05:57:04 AM UTC 24 Sep 19 06:04:15 AM UTC 24 3708729666 ps
T1308 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.3105285273 Sep 19 05:40:14 AM UTC 24 Sep 19 06:04:19 AM UTC 24 7925368680 ps
T706 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3132124292 Sep 19 05:58:36 AM UTC 24 Sep 19 06:04:27 AM UTC 24 3767652872 ps
T1309 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1565944274 Sep 19 05:59:07 AM UTC 24 Sep 19 06:04:56 AM UTC 24 3840171440 ps
T709 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.49500761 Sep 19 05:58:20 AM UTC 24 Sep 19 06:05:27 AM UTC 24 4292295560 ps
T696 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2456891282 Sep 19 05:58:31 AM UTC 24 Sep 19 06:05:31 AM UTC 24 4139668290 ps
T718 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.1299787404 Sep 19 05:55:00 AM UTC 24 Sep 19 06:05:36 AM UTC 24 6302854224 ps
T1310 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.1474773973 Sep 19 04:48:55 AM UTC 24 Sep 19 06:05:49 AM UTC 24 16944991218 ps
T703 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.1615249695 Sep 19 05:55:08 AM UTC 24 Sep 19 06:06:00 AM UTC 24 6197940780 ps
T691 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.2432875640 Sep 19 05:56:08 AM UTC 24 Sep 19 06:06:13 AM UTC 24 4918745480 ps
T682 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.3422198869 Sep 19 05:58:17 AM UTC 24 Sep 19 06:06:41 AM UTC 24 4726097224 ps
T788 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.352982783 Sep 19 06:00:08 AM UTC 24 Sep 19 06:06:44 AM UTC 24 3367417544 ps
T771 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1154252548 Sep 19 06:00:41 AM UTC 24 Sep 19 06:06:53 AM UTC 24 4332416450 ps
T692 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.74202332 Sep 19 05:59:45 AM UTC 24 Sep 19 06:07:05 AM UTC 24 4045745044 ps
T729 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.2062100144 Sep 19 05:55:03 AM UTC 24 Sep 19 06:07:17 AM UTC 24 6544909886 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.3829342131 Sep 19 05:58:33 AM UTC 24 Sep 19 06:07:33 AM UTC 24 5225146796 ps
T753 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.3193435001 Sep 19 05:56:06 AM UTC 24 Sep 19 06:07:35 AM UTC 24 5832957164 ps
T765 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2075424339 Sep 19 06:02:21 AM UTC 24 Sep 19 06:07:39 AM UTC 24 3939958240 ps
T766 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.1645015932 Sep 19 05:58:17 AM UTC 24 Sep 19 06:09:38 AM UTC 24 4849814770 ps
T738 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.2570509368 Sep 19 05:57:05 AM UTC 24 Sep 19 06:09:41 AM UTC 24 5135975504 ps
T1311 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.824976231 Sep 19 06:03:31 AM UTC 24 Sep 19 06:09:56 AM UTC 24 3265160088 ps
T780 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1126736355 Sep 19 06:03:08 AM UTC 24 Sep 19 06:10:03 AM UTC 24 3903546542 ps
T714 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2783926290 Sep 19 06:05:14 AM UTC 24 Sep 19 06:10:03 AM UTC 24 3241918360 ps
T737 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1947959894 Sep 19 06:03:46 AM UTC 24 Sep 19 06:10:06 AM UTC 24 3707284638 ps
T1312 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_all_escalation_resets.2361618783 Sep 19 06:00:08 AM UTC 24 Sep 19 06:10:10 AM UTC 24 4860786608 ps
T797 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1771000372 Sep 19 06:05:15 AM UTC 24 Sep 19 06:10:13 AM UTC 24 3255810214 ps
T740 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_all_escalation_resets.3922860304 Sep 19 06:03:19 AM UTC 24 Sep 19 06:10:18 AM UTC 24 4882005512 ps
T739 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.2132845066 Sep 19 05:59:44 AM UTC 24 Sep 19 06:10:26 AM UTC 24 6113564358 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.3228953648 Sep 19 06:03:10 AM UTC 24 Sep 19 06:11:01 AM UTC 24 5141256220 ps
T1313 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.1243475770 Sep 19 05:01:56 AM UTC 24 Sep 19 06:11:03 AM UTC 24 15658673606 ps
T757 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3711447078 Sep 19 06:04:46 AM UTC 24 Sep 19 06:11:10 AM UTC 24 3407467560 ps
T798 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.1681541080 Sep 19 06:01:25 AM UTC 24 Sep 19 06:11:15 AM UTC 24 5243626330 ps
T1314 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.1937376950 Sep 19 05:29:26 AM UTC 24 Sep 19 06:11:17 AM UTC 24 12359064514 ps
T683 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.875145629 Sep 19 06:00:40 AM UTC 24 Sep 19 06:11:18 AM UTC 24 5489043864 ps
T779 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3541153039 Sep 19 06:04:48 AM UTC 24 Sep 19 06:11:18 AM UTC 24 3885601770 ps
T758 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.1824323978 Sep 19 06:01:49 AM UTC 24 Sep 19 06:11:34 AM UTC 24 4866880532 ps
T1315 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.2939444156 Sep 19 05:59:07 AM UTC 24 Sep 19 06:11:38 AM UTC 24 5807175784 ps
T773 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3024466394 Sep 19 06:05:16 AM UTC 24 Sep 19 06:11:41 AM UTC 24 4730730264 ps
T1316 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.573787952 Sep 19 05:25:27 AM UTC 24 Sep 19 06:11:45 AM UTC 24 13536304704 ps
T774 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3828468511 Sep 19 06:05:46 AM UTC 24 Sep 19 06:12:06 AM UTC 24 3955240632 ps
T727 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_all_escalation_resets.753677363 Sep 19 06:03:13 AM UTC 24 Sep 19 06:12:18 AM UTC 24 4413941044 ps
T1317 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3275624678 Sep 19 06:05:33 AM UTC 24 Sep 19 06:12:35 AM UTC 24 4211224746 ps
T1318 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.815968015 Sep 19 05:31:10 AM UTC 24 Sep 19 06:12:54 AM UTC 24 13763601592 ps
T694 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.2140102479 Sep 19 06:04:08 AM UTC 24 Sep 19 06:13:17 AM UTC 24 4525731016 ps
T701 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2643620825 Sep 19 06:08:33 AM UTC 24 Sep 19 06:13:45 AM UTC 24 3596795100 ps
T776 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1536649156 Sep 19 06:07:58 AM UTC 24 Sep 19 06:13:46 AM UTC 24 4130358160 ps
T1319 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.71158463 Sep 19 06:09:11 AM UTC 24 Sep 19 06:13:56 AM UTC 24 3250564976 ps
T755 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.1472702801 Sep 19 06:05:16 AM UTC 24 Sep 19 06:13:59 AM UTC 24 5435058568 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.2289439143 Sep 19 06:05:32 AM UTC 24 Sep 19 06:14:00 AM UTC 24 5969219668 ps
T1320 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_all_escalation_resets.2355945157 Sep 19 06:05:51 AM UTC 24 Sep 19 06:14:19 AM UTC 24 5423045260 ps
T793 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.3729246424 Sep 19 06:05:00 AM UTC 24 Sep 19 06:14:55 AM UTC 24 6320984824 ps
T686 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3675097095 Sep 19 06:09:03 AM UTC 24 Sep 19 06:14:57 AM UTC 24 3570717208 ps
T1321 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.631800486 Sep 19 06:09:09 AM UTC 24 Sep 19 06:15:18 AM UTC 24 3477385208 ps
T734 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3446859000 Sep 19 06:09:00 AM UTC 24 Sep 19 06:15:19 AM UTC 24 3634429840 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_all_escalation_resets.2686371501 Sep 19 06:05:52 AM UTC 24 Sep 19 06:15:31 AM UTC 24 5864654320 ps
T800 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1881319629 Sep 19 06:09:13 AM UTC 24 Sep 19 06:15:42 AM UTC 24 3790443528 ps
T781 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.534460279 Sep 19 06:09:06 AM UTC 24 Sep 19 06:15:46 AM UTC 24 4217461608 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.2959205105 Sep 19 06:09:04 AM UTC 24 Sep 19 06:16:08 AM UTC 24 3963680670 ps
T744 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.689360115 Sep 19 06:08:00 AM UTC 24 Sep 19 06:16:33 AM UTC 24 5416418928 ps
T697 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.2281944081 Sep 19 06:08:38 AM UTC 24 Sep 19 06:17:03 AM UTC 24 5615255000 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.2341242484 Sep 19 06:09:02 AM UTC 24 Sep 19 06:17:29 AM UTC 24 5472364680 ps
T735 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.1273165693 Sep 19 06:09:08 AM UTC 24 Sep 19 06:18:35 AM UTC 24 5479660728 ps
T754 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1822537583 Sep 19 06:13:33 AM UTC 24 Sep 19 06:18:59 AM UTC 24 3992847568 ps
T790 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.4163282361 Sep 19 06:13:32 AM UTC 24 Sep 19 06:19:10 AM UTC 24 3507111130 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.231691949 Sep 19 06:08:55 AM UTC 24 Sep 19 06:19:22 AM UTC 24 5440318430 ps
T785 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3752619172 Sep 19 06:14:22 AM UTC 24 Sep 19 06:19:27 AM UTC 24 4146558340 ps
T795 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.357281026 Sep 19 06:13:47 AM UTC 24 Sep 19 06:19:29 AM UTC 24 3435274236 ps
T762 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1145923825 Sep 19 06:13:53 AM UTC 24 Sep 19 06:19:31 AM UTC 24 3450923640 ps
T707 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.334553316 Sep 19 06:12:33 AM UTC 24 Sep 19 06:19:45 AM UTC 24 4500803720 ps
T731 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.2289114275 Sep 19 06:09:12 AM UTC 24 Sep 19 06:20:10 AM UTC 24 6295567170 ps
T1322 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2965956586 Sep 19 06:15:06 AM UTC 24 Sep 19 06:20:41 AM UTC 24 3617970510 ps
T1323 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.4253544175 Sep 19 05:39:38 AM UTC 24 Sep 19 06:20:43 AM UTC 24 13441334152 ps
T746 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.544399432 Sep 19 06:12:00 AM UTC 24 Sep 19 06:20:45 AM UTC 24 5522654824 ps
T786 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3317277952 Sep 19 06:14:23 AM UTC 24 Sep 19 06:20:45 AM UTC 24 4102246592 ps
T763 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.4222590066 Sep 19 06:15:31 AM UTC 24 Sep 19 06:21:29 AM UTC 24 3638442016 ps
T768 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.4151352270 Sep 19 06:16:50 AM UTC 24 Sep 19 06:21:59 AM UTC 24 3696145866 ps
T732 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_all_escalation_resets.714228372 Sep 19 06:13:45 AM UTC 24 Sep 19 06:22:19 AM UTC 24 4725106800 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.231092132 Sep 19 06:14:43 AM UTC 24 Sep 19 06:22:43 AM UTC 24 4193848066 ps
T775 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.3126454392 Sep 19 06:13:37 AM UTC 24 Sep 19 06:22:45 AM UTC 24 5068264380 ps
T704 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.725870630 Sep 19 06:17:14 AM UTC 24 Sep 19 06:23:00 AM UTC 24 3351014770 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2114367488 Sep 19 06:16:40 AM UTC 24 Sep 19 06:23:10 AM UTC 24 3999537204 ps
T751 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1890181703 Sep 19 06:16:35 AM UTC 24 Sep 19 06:23:15 AM UTC 24 3585345178 ps
T698 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.3680568967 Sep 19 06:14:09 AM UTC 24 Sep 19 06:23:22 AM UTC 24 4772323062 ps
T741 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3459979919 Sep 19 06:16:44 AM UTC 24 Sep 19 06:23:27 AM UTC 24 4113239500 ps
T799 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.3385721181 Sep 19 06:13:27 AM UTC 24 Sep 19 06:23:44 AM UTC 24 4742330504 ps
T1324 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.399431574 Sep 19 06:17:17 AM UTC 24 Sep 19 06:23:48 AM UTC 24 4303862890 ps
T699 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.2710388722 Sep 19 06:13:56 AM UTC 24 Sep 19 06:23:52 AM UTC 24 6231751436 ps
T1325 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2076855710 Sep 19 06:16:37 AM UTC 24 Sep 19 06:24:01 AM UTC 24 4002956104 ps
T750 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3894620212 Sep 19 06:17:18 AM UTC 24 Sep 19 06:24:07 AM UTC 24 4037394880 ps
T1326 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.1415354860 Sep 19 06:17:17 AM UTC 24 Sep 19 06:24:20 AM UTC 24 4779093254 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.1717876943 Sep 19 06:17:20 AM UTC 24 Sep 19 06:24:34 AM UTC 24 5264465056 ps
T794 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3605588372 Sep 19 06:17:22 AM UTC 24 Sep 19 06:24:36 AM UTC 24 4183841758 ps
T1327 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.2376531763 Sep 19 05:20:58 AM UTC 24 Sep 19 06:24:37 AM UTC 24 15120004392 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.2538461963 Sep 19 06:14:32 AM UTC 24 Sep 19 06:24:48 AM UTC 24 4707757376 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/91.chip_sw_all_escalation_resets.792935000 Sep 19 06:17:24 AM UTC 24 Sep 19 06:25:02 AM UTC 24 6164275000 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.2188809548 Sep 19 06:13:47 AM UTC 24 Sep 19 06:25:07 AM UTC 24 6167786700 ps
T1328 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.1047832966 Sep 19 05:18:42 AM UTC 24 Sep 19 06:25:17 AM UTC 24 14978869840 ps
T791 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.3292520217 Sep 19 06:14:25 AM UTC 24 Sep 19 06:25:25 AM UTC 24 5527455884 ps
T1329 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.1287090874 Sep 19 06:17:27 AM UTC 24 Sep 19 06:25:39 AM UTC 24 4846663468 ps
T1330 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.3401247141 Sep 19 06:17:24 AM UTC 24 Sep 19 06:26:02 AM UTC 24 4556380210 ps
T1331 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.459556050 Sep 19 06:16:06 AM UTC 24 Sep 19 06:26:09 AM UTC 24 4677392936 ps
T1332 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.2195387828 Sep 19 06:16:37 AM UTC 24 Sep 19 06:26:18 AM UTC 24 6001143344 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_all_escalation_resets.3025472060 Sep 19 06:16:38 AM UTC 24 Sep 19 06:26:23 AM UTC 24 4995643920 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.3492195384 Sep 19 06:17:43 AM UTC 24 Sep 19 06:26:24 AM UTC 24 4928876820 ps
T761 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.3914808812 Sep 19 06:17:03 AM UTC 24 Sep 19 06:26:53 AM UTC 24 5680337620 ps
T723 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.1794447481 Sep 19 06:16:11 AM UTC 24 Sep 19 06:27:03 AM UTC 24 4659866692 ps
T720 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.2843200100 Sep 19 06:17:24 AM UTC 24 Sep 19 06:27:09 AM UTC 24 4924510768 ps
T747 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.2214467506 Sep 19 06:16:43 AM UTC 24 Sep 19 06:27:12 AM UTC 24 5211783320 ps
T695 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.420116733 Sep 19 06:16:53 AM UTC 24 Sep 19 06:27:16 AM UTC 24 5020299208 ps
T801 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.1432673167 Sep 19 06:19:56 AM UTC 24 Sep 19 06:28:06 AM UTC 24 5156071572 ps
T715 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.2324120723 Sep 19 06:18:16 AM UTC 24 Sep 19 06:28:35 AM UTC 24 5522323016 ps
T1333 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.1930336824 Sep 19 06:19:59 AM UTC 24 Sep 19 06:28:59 AM UTC 24 4975892928 ps
T742 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.2623625201 Sep 19 06:19:56 AM UTC 24 Sep 19 06:29:06 AM UTC 24 6131714248 ps
T772 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.2077789689 Sep 19 06:20:00 AM UTC 24 Sep 19 06:30:00 AM UTC 24 5396535596 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_inject_scramble_seed.982786055 Sep 19 02:07:40 AM UTC 24 Sep 19 06:33:23 AM UTC 24 69240850136 ps
T1334 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.4171840187 Sep 19 05:17:16 AM UTC 24 Sep 19 06:41:27 AM UTC 24 20729556686 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%