| T2514 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.2666717097 |
|
|
Sep 18 11:22:32 PM UTC 24 |
Sep 18 11:28:46 PM UTC 24 |
38278135880 ps |
| T2515 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.3821154687 |
|
|
Sep 18 11:28:42 PM UTC 24 |
Sep 18 11:28:54 PM UTC 24 |
36136407 ps |
| T2516 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.2695168993 |
|
|
Sep 18 11:28:34 PM UTC 24 |
Sep 18 11:28:58 PM UTC 24 |
315081646 ps |
| T2517 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.1628939171 |
|
|
Sep 18 11:26:47 PM UTC 24 |
Sep 18 11:29:00 PM UTC 24 |
429657786 ps |
| T2518 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.2363891901 |
|
|
Sep 18 11:28:42 PM UTC 24 |
Sep 18 11:29:05 PM UTC 24 |
173833606 ps |
| T2519 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.1894146145 |
|
|
Sep 18 11:26:38 PM UTC 24 |
Sep 18 11:29:07 PM UTC 24 |
4990277024 ps |
| T2520 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.2221345781 |
|
|
Sep 18 11:24:14 PM UTC 24 |
Sep 18 11:29:11 PM UTC 24 |
9395042123 ps |
| T2521 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.665455218 |
|
|
Sep 18 11:20:27 PM UTC 24 |
Sep 18 11:29:15 PM UTC 24 |
12785879198 ps |
| T2522 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.3757626783 |
|
|
Sep 18 11:29:08 PM UTC 24 |
Sep 18 11:29:16 PM UTC 24 |
52196937 ps |
| T2523 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.2149716022 |
|
|
Sep 18 11:28:39 PM UTC 24 |
Sep 18 11:29:16 PM UTC 24 |
985941184 ps |
| T2524 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.4045727485 |
|
|
Sep 18 11:29:08 PM UTC 24 |
Sep 18 11:29:17 PM UTC 24 |
48048561 ps |
| T2525 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.3221428216 |
|
|
Sep 18 11:13:39 PM UTC 24 |
Sep 18 11:29:18 PM UTC 24 |
60570926322 ps |
| T2526 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.2977064779 |
|
|
Sep 18 11:28:43 PM UTC 24 |
Sep 18 11:29:25 PM UTC 24 |
931382769 ps |
| T2527 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.2644158700 |
|
|
Sep 18 11:28:00 PM UTC 24 |
Sep 18 11:29:26 PM UTC 24 |
8664402282 ps |
| T2528 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.4280484540 |
|
|
Sep 18 11:27:59 PM UTC 24 |
Sep 18 11:29:33 PM UTC 24 |
5296228348 ps |
| T2529 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.3111206710 |
|
|
Sep 18 11:24:33 PM UTC 24 |
Sep 18 11:29:37 PM UTC 24 |
5859400877 ps |
| T2530 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.3483920449 |
|
|
Sep 18 11:23:48 PM UTC 24 |
Sep 18 11:29:41 PM UTC 24 |
36054815319 ps |
| T2531 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.2814444734 |
|
|
Sep 18 11:27:45 PM UTC 24 |
Sep 18 11:29:50 PM UTC 24 |
4393005639 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.666429028 |
|
|
Sep 18 11:19:12 PM UTC 24 |
Sep 18 11:29:51 PM UTC 24 |
19477083602 ps |
| T2532 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.2441979559 |
|
|
Sep 18 11:29:27 PM UTC 24 |
Sep 18 11:29:59 PM UTC 24 |
263701369 ps |
| T2533 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.2094514442 |
|
|
Sep 18 11:28:35 PM UTC 24 |
Sep 18 11:30:00 PM UTC 24 |
2113989147 ps |
| T2534 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.4072536719 |
|
|
Sep 18 11:29:44 PM UTC 24 |
Sep 18 11:30:01 PM UTC 24 |
99058306 ps |
| T2535 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.1534324272 |
|
|
Sep 18 11:28:12 PM UTC 24 |
Sep 18 11:30:12 PM UTC 24 |
2785806799 ps |
| T2536 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.265182104 |
|
|
Sep 18 11:30:10 PM UTC 24 |
Sep 18 11:30:21 PM UTC 24 |
50024202 ps |
| T2537 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.486396485 |
|
|
Sep 18 11:29:43 PM UTC 24 |
Sep 18 11:30:23 PM UTC 24 |
668640900 ps |
| T2538 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.2989734707 |
|
|
Sep 18 11:30:16 PM UTC 24 |
Sep 18 11:30:25 PM UTC 24 |
44347806 ps |
| T2539 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.2421740140 |
|
|
Sep 18 11:13:56 PM UTC 24 |
Sep 18 11:30:30 PM UTC 24 |
65359210627 ps |
| T2540 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.3436888486 |
|
|
Sep 18 11:29:40 PM UTC 24 |
Sep 18 11:30:31 PM UTC 24 |
1560815386 ps |
| T2541 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.3011772385 |
|
|
Sep 18 11:29:45 PM UTC 24 |
Sep 18 11:30:34 PM UTC 24 |
542736622 ps |
| T2542 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.33999033 |
|
|
Sep 18 11:30:33 PM UTC 24 |
Sep 18 11:30:46 PM UTC 24 |
63465265 ps |
| T2543 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.2653133700 |
|
|
Sep 18 11:29:22 PM UTC 24 |
Sep 18 11:30:52 PM UTC 24 |
5230495168 ps |
| T2544 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.2992246821 |
|
|
Sep 18 11:30:27 PM UTC 24 |
Sep 18 11:30:53 PM UTC 24 |
604417062 ps |
| T2545 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.4227574505 |
|
|
Sep 18 11:29:22 PM UTC 24 |
Sep 18 11:30:53 PM UTC 24 |
2441087657 ps |
| T2546 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.660145575 |
|
|
Sep 18 11:24:28 PM UTC 24 |
Sep 18 11:30:56 PM UTC 24 |
5041668537 ps |
| T2547 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.1534612037 |
|
|
Sep 18 11:29:59 PM UTC 24 |
Sep 18 11:30:59 PM UTC 24 |
733179956 ps |
| T2548 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.1161204236 |
|
|
Sep 18 11:26:33 PM UTC 24 |
Sep 18 11:31:06 PM UTC 24 |
4575806592 ps |
| T2549 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.3302240343 |
|
|
Sep 18 11:29:15 PM UTC 24 |
Sep 18 11:31:08 PM UTC 24 |
7613392490 ps |
| T2550 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.2922389049 |
|
|
Sep 18 11:29:41 PM UTC 24 |
Sep 18 11:31:09 PM UTC 24 |
2039688020 ps |
| T2551 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.4150090187 |
|
|
Sep 18 11:27:53 PM UTC 24 |
Sep 18 11:31:12 PM UTC 24 |
1510136856 ps |
| T2552 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.705363053 |
|
|
Sep 18 11:31:02 PM UTC 24 |
Sep 18 11:31:29 PM UTC 24 |
265450444 ps |
| T2553 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.3158579341 |
|
|
Sep 18 11:30:27 PM UTC 24 |
Sep 18 11:31:34 PM UTC 24 |
4773623264 ps |
| T2554 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.3300217319 |
|
|
Sep 18 11:21:28 PM UTC 24 |
Sep 18 11:31:35 PM UTC 24 |
8461892170 ps |
| T2555 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.3781705111 |
|
|
Sep 18 11:31:28 PM UTC 24 |
Sep 18 11:31:41 PM UTC 24 |
212324127 ps |
| T2556 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.4121116956 |
|
|
Sep 18 11:25:30 PM UTC 24 |
Sep 18 11:31:41 PM UTC 24 |
11880328893 ps |
| T2557 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.527264755 |
|
|
Sep 18 11:31:04 PM UTC 24 |
Sep 18 11:31:43 PM UTC 24 |
657642599 ps |
| T2558 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.3481120778 |
|
|
Sep 18 11:31:36 PM UTC 24 |
Sep 18 11:31:44 PM UTC 24 |
51800629 ps |
| T2559 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.653161892 |
|
|
Sep 18 11:30:23 PM UTC 24 |
Sep 18 11:31:47 PM UTC 24 |
8172403121 ps |
| T2560 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.3913706176 |
|
|
Sep 18 11:31:17 PM UTC 24 |
Sep 18 11:31:50 PM UTC 24 |
533040291 ps |
| T2561 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.2804498669 |
|
|
Sep 18 11:31:24 PM UTC 24 |
Sep 18 11:31:55 PM UTC 24 |
295947132 ps |
| T2562 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.1837420818 |
|
|
Sep 18 11:29:50 PM UTC 24 |
Sep 18 11:31:59 PM UTC 24 |
1750539418 ps |
| T2563 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.1481371827 |
|
|
Sep 18 11:31:01 PM UTC 24 |
Sep 18 11:32:01 PM UTC 24 |
1854852225 ps |
| T2564 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.2640254702 |
|
|
Sep 18 11:16:38 PM UTC 24 |
Sep 18 11:32:10 PM UTC 24 |
9730072126 ps |
| T2565 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.259995847 |
|
|
Sep 18 11:31:55 PM UTC 24 |
Sep 18 11:32:11 PM UTC 24 |
106491229 ps |
| T2566 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.4242783877 |
|
|
Sep 18 11:31:21 PM UTC 24 |
Sep 18 11:32:13 PM UTC 24 |
111302671 ps |
| T2567 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.1870688631 |
|
|
Sep 18 11:31:42 PM UTC 24 |
Sep 18 11:32:14 PM UTC 24 |
659631111 ps |
| T2568 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_large_delays.1630484615 |
|
|
Sep 18 11:27:08 PM UTC 24 |
Sep 18 11:32:19 PM UTC 24 |
26502856109 ps |
| T2569 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.2057113335 |
|
|
Sep 18 11:25:28 PM UTC 24 |
Sep 18 11:32:22 PM UTC 24 |
3162324120 ps |
| T2570 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.2042190997 |
|
|
Sep 18 11:25:31 PM UTC 24 |
Sep 18 11:32:32 PM UTC 24 |
13410073722 ps |
| T2571 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.2886225136 |
|
|
Sep 18 11:32:14 PM UTC 24 |
Sep 18 11:32:32 PM UTC 24 |
174011992 ps |
| T2572 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.4264435472 |
|
|
Sep 18 11:32:15 PM UTC 24 |
Sep 18 11:32:33 PM UTC 24 |
99830415 ps |
| T2573 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.1304553416 |
|
|
Sep 18 11:29:39 PM UTC 24 |
Sep 18 11:32:35 PM UTC 24 |
11437386088 ps |
| T2574 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.3075694449 |
|
|
Sep 18 11:32:11 PM UTC 24 |
Sep 18 11:32:36 PM UTC 24 |
296691664 ps |
| T2575 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.1364961847 |
|
|
Sep 18 11:30:54 PM UTC 24 |
Sep 18 11:32:40 PM UTC 24 |
1231480971 ps |
| T2576 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.1199133224 |
|
|
Sep 18 11:28:55 PM UTC 24 |
Sep 18 11:32:41 PM UTC 24 |
6717958145 ps |
| T2577 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.996593564 |
|
|
Sep 18 11:32:21 PM UTC 24 |
Sep 18 11:32:50 PM UTC 24 |
236233032 ps |
| T2578 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.3965538261 |
|
|
Sep 18 11:32:40 PM UTC 24 |
Sep 18 11:32:52 PM UTC 24 |
162499544 ps |
| T2579 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.425786492 |
|
|
Sep 18 11:32:42 PM UTC 24 |
Sep 18 11:32:53 PM UTC 24 |
48811521 ps |
| T2580 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.136240902 |
|
|
Sep 18 11:32:17 PM UTC 24 |
Sep 18 11:32:57 PM UTC 24 |
323125352 ps |
| T2581 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.2236360941 |
|
|
Sep 18 11:24:55 PM UTC 24 |
Sep 18 11:32:59 PM UTC 24 |
43540228171 ps |
| T2582 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.893669897 |
|
|
Sep 18 11:25:28 PM UTC 24 |
Sep 18 11:32:59 PM UTC 24 |
9834668005 ps |
| T2583 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.2857663421 |
|
|
Sep 18 11:05:15 PM UTC 24 |
Sep 18 11:33:02 PM UTC 24 |
98742364341 ps |
| T2584 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.640963042 |
|
|
Sep 18 11:31:36 PM UTC 24 |
Sep 18 11:33:09 PM UTC 24 |
8417196517 ps |
| T2585 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.2269599142 |
|
|
Sep 18 11:31:41 PM UTC 24 |
Sep 18 11:33:15 PM UTC 24 |
5713007990 ps |
| T2586 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.2775202412 |
|
|
Sep 18 11:32:11 PM UTC 24 |
Sep 18 11:33:22 PM UTC 24 |
2191687852 ps |
| T2587 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.3532073839 |
|
|
Sep 18 11:33:19 PM UTC 24 |
Sep 18 11:33:25 PM UTC 24 |
6706425 ps |
| T2588 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.4158541334 |
|
|
Sep 18 11:33:07 PM UTC 24 |
Sep 18 11:33:25 PM UTC 24 |
276576198 ps |
| T2589 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.10258230 |
|
|
Sep 18 11:33:02 PM UTC 24 |
Sep 18 11:33:25 PM UTC 24 |
195059719 ps |
| T2590 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.466643636 |
|
|
Sep 18 10:58:52 PM UTC 24 |
Sep 18 11:33:31 PM UTC 24 |
124499174132 ps |
| T2591 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.4174217817 |
|
|
Sep 18 11:33:03 PM UTC 24 |
Sep 18 11:33:38 PM UTC 24 |
565901694 ps |
| T2592 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.3042521217 |
|
|
Sep 18 11:24:04 PM UTC 24 |
Sep 18 11:33:39 PM UTC 24 |
41614415704 ps |
| T2593 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.2771278067 |
|
|
Sep 18 11:33:20 PM UTC 24 |
Sep 18 11:33:41 PM UTC 24 |
428268833 ps |
| T2594 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.368384727 |
|
|
Sep 18 11:33:32 PM UTC 24 |
Sep 18 11:33:42 PM UTC 24 |
183992382 ps |
| T2595 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.1307462992 |
|
|
Sep 18 11:33:34 PM UTC 24 |
Sep 18 11:33:44 PM UTC 24 |
49131496 ps |
| T2596 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.3917193246 |
|
|
Sep 18 11:32:48 PM UTC 24 |
Sep 18 11:33:45 PM UTC 24 |
1559610904 ps |
| T2597 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.395802198 |
|
|
Sep 18 11:19:58 PM UTC 24 |
Sep 18 11:33:45 PM UTC 24 |
53287869484 ps |
| T2598 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.1618147178 |
|
|
Sep 18 11:33:01 PM UTC 24 |
Sep 18 11:34:04 PM UTC 24 |
2225174854 ps |
| T2599 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.138217925 |
|
|
Sep 18 11:26:30 PM UTC 24 |
Sep 18 11:34:06 PM UTC 24 |
11463383504 ps |
| T2600 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_large_delays.429812958 |
|
|
Sep 18 11:28:21 PM UTC 24 |
Sep 18 11:34:08 PM UTC 24 |
33876739592 ps |
| T2601 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.3198132771 |
|
|
Sep 18 11:33:50 PM UTC 24 |
Sep 18 11:34:17 PM UTC 24 |
232166369 ps |
| T2602 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.723543641 |
|
|
Sep 18 11:18:43 PM UTC 24 |
Sep 18 11:34:17 PM UTC 24 |
52352417277 ps |
| T2603 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.2673645473 |
|
|
Sep 18 11:32:42 PM UTC 24 |
Sep 18 11:34:17 PM UTC 24 |
8192732927 ps |
| T2604 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.3176792052 |
|
|
Sep 18 11:33:19 PM UTC 24 |
Sep 18 11:34:21 PM UTC 24 |
1464578642 ps |
| T2605 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.1258498423 |
|
|
Sep 18 11:34:13 PM UTC 24 |
Sep 18 11:34:22 PM UTC 24 |
39648134 ps |
| T2606 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.109656487 |
|
|
Sep 18 11:34:13 PM UTC 24 |
Sep 18 11:34:23 PM UTC 24 |
33525942 ps |
| T2607 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.1428568388 |
|
|
Sep 18 11:32:46 PM UTC 24 |
Sep 18 11:34:27 PM UTC 24 |
5944484554 ps |
| T2608 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.140335521 |
|
|
Sep 18 11:33:54 PM UTC 24 |
Sep 18 11:34:43 PM UTC 24 |
419849626 ps |
| T2609 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.47733176 |
|
|
Sep 18 11:34:10 PM UTC 24 |
Sep 18 11:34:47 PM UTC 24 |
585449749 ps |
| T2610 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.802202579 |
|
|
Sep 18 11:13:46 PM UTC 24 |
Sep 18 11:34:49 PM UTC 24 |
100933467779 ps |
| T2611 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.735150162 |
|
|
Sep 18 11:33:37 PM UTC 24 |
Sep 18 11:34:51 PM UTC 24 |
7794459171 ps |
| T2612 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.2916798226 |
|
|
Sep 18 11:34:47 PM UTC 24 |
Sep 18 11:34:57 PM UTC 24 |
43274703 ps |
| T2613 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.4140977537 |
|
|
Sep 18 11:34:47 PM UTC 24 |
Sep 18 11:34:58 PM UTC 24 |
54554347 ps |
| T2614 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.3999774561 |
|
|
Sep 18 11:28:41 PM UTC 24 |
Sep 18 11:35:00 PM UTC 24 |
2576571354 ps |
| T2615 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.4227539140 |
|
|
Sep 18 11:34:54 PM UTC 24 |
Sep 18 11:35:04 PM UTC 24 |
34450645 ps |
| T2616 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.125244194 |
|
|
Sep 18 11:32:25 PM UTC 24 |
Sep 18 11:35:06 PM UTC 24 |
526551221 ps |
| T2617 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.111763571 |
|
|
Sep 18 11:26:14 PM UTC 24 |
Sep 18 11:35:14 PM UTC 24 |
38821073406 ps |
| T2618 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.3458341093 |
|
|
Sep 18 11:34:10 PM UTC 24 |
Sep 18 11:35:14 PM UTC 24 |
2284293882 ps |
| T2619 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.3032750026 |
|
|
Sep 18 11:33:47 PM UTC 24 |
Sep 18 11:35:21 PM UTC 24 |
3955169349 ps |
| T2620 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.3815038165 |
|
|
Sep 18 11:33:27 PM UTC 24 |
Sep 18 11:35:22 PM UTC 24 |
1843136181 ps |
| T2621 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.3128401578 |
|
|
Sep 18 11:34:50 PM UTC 24 |
Sep 18 11:35:25 PM UTC 24 |
680317119 ps |
| T2622 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.1616826308 |
|
|
Sep 18 11:31:20 PM UTC 24 |
Sep 18 11:35:34 PM UTC 24 |
7432635377 ps |
| T2623 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.1070350121 |
|
|
Sep 18 11:34:46 PM UTC 24 |
Sep 18 11:35:34 PM UTC 24 |
3449938244 ps |
| T2624 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.1999204781 |
|
|
Sep 18 11:34:08 PM UTC 24 |
Sep 18 11:35:41 PM UTC 24 |
1086850116 ps |
| T2625 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.3064208805 |
|
|
Sep 18 11:27:10 PM UTC 24 |
Sep 18 11:35:43 PM UTC 24 |
28537468773 ps |
| T2626 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.1897420862 |
|
|
Sep 18 11:35:30 PM UTC 24 |
Sep 18 11:35:43 PM UTC 24 |
77688933 ps |
| T2627 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.3270770535 |
|
|
Sep 18 11:34:07 PM UTC 24 |
Sep 18 11:35:56 PM UTC 24 |
2580416978 ps |
| T2628 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.1037232399 |
|
|
Sep 18 11:34:49 PM UTC 24 |
Sep 18 11:35:56 PM UTC 24 |
6473496436 ps |
| T2629 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.3998433289 |
|
|
Sep 18 11:35:48 PM UTC 24 |
Sep 18 11:35:58 PM UTC 24 |
48395795 ps |
| T2630 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.2140273908 |
|
|
Sep 18 11:35:50 PM UTC 24 |
Sep 18 11:35:59 PM UTC 24 |
47279612 ps |
| T2631 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.2779550729 |
|
|
Sep 18 11:35:27 PM UTC 24 |
Sep 18 11:36:09 PM UTC 24 |
571181140 ps |
| T2632 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.2956191761 |
|
|
Sep 18 11:08:24 PM UTC 24 |
Sep 18 11:36:13 PM UTC 24 |
128754912090 ps |
| T2633 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.1538290913 |
|
|
Sep 18 11:36:03 PM UTC 24 |
Sep 18 11:36:15 PM UTC 24 |
69039802 ps |
| T2634 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.3656355626 |
|
|
Sep 18 11:35:14 PM UTC 24 |
Sep 18 11:36:22 PM UTC 24 |
1658101375 ps |
| T2635 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.2536992174 |
|
|
Sep 18 11:35:22 PM UTC 24 |
Sep 18 11:36:24 PM UTC 24 |
2076703094 ps |
| T2636 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.3626870227 |
|
|
Sep 18 11:36:07 PM UTC 24 |
Sep 18 11:36:32 PM UTC 24 |
232321451 ps |
| T2637 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.3058468568 |
|
|
Sep 18 11:36:22 PM UTC 24 |
Sep 18 11:36:37 PM UTC 24 |
227999203 ps |
| T2638 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.1367186031 |
|
|
Sep 18 11:15:01 PM UTC 24 |
Sep 18 11:36:38 PM UTC 24 |
86154681361 ps |
| T2639 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.3092453468 |
|
|
Sep 18 11:35:29 PM UTC 24 |
Sep 18 11:36:38 PM UTC 24 |
1348117067 ps |
| T2640 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.3427793488 |
|
|
Sep 18 11:36:39 PM UTC 24 |
Sep 18 11:36:54 PM UTC 24 |
59461414 ps |
| T2641 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.2285292659 |
|
|
Sep 18 11:36:01 PM UTC 24 |
Sep 18 11:37:03 PM UTC 24 |
4197674774 ps |
| T2642 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.646745146 |
|
|
Sep 18 11:36:27 PM UTC 24 |
Sep 18 11:37:04 PM UTC 24 |
1318133370 ps |
| T2643 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.1100919622 |
|
|
Sep 18 11:30:06 PM UTC 24 |
Sep 18 11:37:07 PM UTC 24 |
6909696475 ps |
| T2644 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.2798814347 |
|
|
Sep 18 11:36:46 PM UTC 24 |
Sep 18 11:37:10 PM UTC 24 |
212923535 ps |
| T2645 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.3447769391 |
|
|
Sep 18 11:32:29 PM UTC 24 |
Sep 18 11:37:16 PM UTC 24 |
3594791848 ps |
| T2646 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.3323625640 |
|
|
Sep 18 11:37:08 PM UTC 24 |
Sep 18 11:37:17 PM UTC 24 |
44426469 ps |
| T2647 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.3644787823 |
|
|
Sep 18 11:35:54 PM UTC 24 |
Sep 18 11:37:19 PM UTC 24 |
9370942897 ps |
| T2648 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.550357676 |
|
|
Sep 18 11:37:10 PM UTC 24 |
Sep 18 11:37:21 PM UTC 24 |
55061643 ps |
| T2649 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.1892210199 |
|
|
Sep 18 11:36:25 PM UTC 24 |
Sep 18 11:37:31 PM UTC 24 |
2697783513 ps |
| T2650 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.3337863913 |
|
|
Sep 18 11:36:42 PM UTC 24 |
Sep 18 11:37:32 PM UTC 24 |
1302862450 ps |
| T2651 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.2350149405 |
|
|
Sep 18 11:07:16 PM UTC 24 |
Sep 18 11:37:37 PM UTC 24 |
130533204440 ps |
| T2652 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.2281688457 |
|
|
Sep 18 11:33:23 PM UTC 24 |
Sep 18 11:37:42 PM UTC 24 |
592971507 ps |
| T2653 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.3357468641 |
|
|
Sep 18 11:27:11 PM UTC 24 |
Sep 18 11:37:46 PM UTC 24 |
45934377672 ps |
| T2654 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.3492351884 |
|
|
Sep 18 11:34:35 PM UTC 24 |
Sep 18 11:37:49 PM UTC 24 |
5950740624 ps |
| T2655 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.47451257 |
|
|
Sep 18 11:16:04 PM UTC 24 |
Sep 18 11:37:50 PM UTC 24 |
89731793744 ps |
| T2656 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.2888736309 |
|
|
Sep 18 11:36:27 PM UTC 24 |
Sep 18 11:37:55 PM UTC 24 |
2336939451 ps |
| T2657 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.642514699 |
|
|
Sep 18 11:37:50 PM UTC 24 |
Sep 18 11:38:01 PM UTC 24 |
59298312 ps |
| T2658 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.2842163231 |
|
|
Sep 18 11:37:36 PM UTC 24 |
Sep 18 11:38:05 PM UTC 24 |
372220799 ps |
| T2659 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.2738288915 |
|
|
Sep 18 11:37:35 PM UTC 24 |
Sep 18 11:38:08 PM UTC 24 |
984534751 ps |
| T2660 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.611090514 |
|
|
Sep 18 11:32:37 PM UTC 24 |
Sep 18 11:38:11 PM UTC 24 |
1260624142 ps |
| T2661 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.71261324 |
|
|
Sep 18 11:37:50 PM UTC 24 |
Sep 18 11:38:12 PM UTC 24 |
211404202 ps |
| T2662 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.1036490254 |
|
|
Sep 18 11:38:01 PM UTC 24 |
Sep 18 11:38:13 PM UTC 24 |
87001146 ps |
| T2663 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all.4287383404 |
|
|
Sep 18 11:35:30 PM UTC 24 |
Sep 18 11:38:17 PM UTC 24 |
1861647986 ps |
| T2664 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.1111511233 |
|
|
Sep 18 11:31:25 PM UTC 24 |
Sep 18 11:38:23 PM UTC 24 |
1606922762 ps |
| T2665 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.2577534215 |
|
|
Sep 18 11:38:16 PM UTC 24 |
Sep 18 11:38:28 PM UTC 24 |
55711787 ps |
| T2666 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.2697327506 |
|
|
Sep 18 11:38:03 PM UTC 24 |
Sep 18 11:38:28 PM UTC 24 |
574324936 ps |
| T2667 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.102203041 |
|
|
Sep 18 11:38:22 PM UTC 24 |
Sep 18 11:38:32 PM UTC 24 |
49743834 ps |
| T2668 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.3611163276 |
|
|
Sep 18 11:38:26 PM UTC 24 |
Sep 18 11:38:33 PM UTC 24 |
47154277 ps |
| T2669 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_slow_rsp.1706199485 |
|
|
Sep 18 11:32:06 PM UTC 24 |
Sep 18 11:38:36 PM UTC 24 |
25788573371 ps |
| T2670 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.4251334815 |
|
|
Sep 18 11:37:09 PM UTC 24 |
Sep 18 11:38:39 PM UTC 24 |
7345033552 ps |
| T2671 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.3239526191 |
|
|
Sep 18 11:37:25 PM UTC 24 |
Sep 18 11:38:42 PM UTC 24 |
4625613519 ps |
| T2672 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_error.2463205313 |
|
|
Sep 18 11:35:43 PM UTC 24 |
Sep 18 11:38:48 PM UTC 24 |
2757840657 ps |
| T2673 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.1991179253 |
|
|
Sep 18 11:37:45 PM UTC 24 |
Sep 18 11:38:55 PM UTC 24 |
1502901526 ps |
| T2674 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.909940419 |
|
|
Sep 18 11:38:57 PM UTC 24 |
Sep 18 11:39:13 PM UTC 24 |
154160740 ps |
| T2675 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.2692493373 |
|
|
Sep 18 11:38:39 PM UTC 24 |
Sep 18 11:39:21 PM UTC 24 |
432659658 ps |
| T2676 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.3916254826 |
|
|
Sep 18 11:38:43 PM UTC 24 |
Sep 18 11:39:22 PM UTC 24 |
458433524 ps |
| T2677 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.3189315749 |
|
|
Sep 18 11:29:52 PM UTC 24 |
Sep 18 11:39:32 PM UTC 24 |
4350278262 ps |
| T2678 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.4229928762 |
|
|
Sep 18 11:37:04 PM UTC 24 |
Sep 18 11:39:35 PM UTC 24 |
540616041 ps |
| T2679 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.794942542 |
|
|
Sep 18 11:39:23 PM UTC 24 |
Sep 18 11:39:37 PM UTC 24 |
173015589 ps |
| T2680 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_large_delays.77672055 |
|
|
Sep 18 11:29:29 PM UTC 24 |
Sep 18 11:39:39 PM UTC 24 |
56144460703 ps |
| T2681 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.2481920504 |
|
|
Sep 18 11:38:33 PM UTC 24 |
Sep 18 11:39:46 PM UTC 24 |
2048475043 ps |
| T2682 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.646227166 |
|
|
Sep 18 11:39:01 PM UTC 24 |
Sep 18 11:39:52 PM UTC 24 |
983101402 ps |
| T2683 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.232253524 |
|
|
Sep 18 11:38:35 PM UTC 24 |
Sep 18 11:39:54 PM UTC 24 |
3492372477 ps |
| T2684 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.3111240519 |
|
|
Sep 18 11:39:45 PM UTC 24 |
Sep 18 11:39:54 PM UTC 24 |
40167200 ps |
| T2685 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.2663008036 |
|
|
Sep 18 11:38:56 PM UTC 24 |
Sep 18 11:39:58 PM UTC 24 |
1725905094 ps |
| T2686 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.1176657758 |
|
|
Sep 18 11:39:02 PM UTC 24 |
Sep 18 11:40:00 PM UTC 24 |
1151011181 ps |
| T2687 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all.2739573627 |
|
|
Sep 18 11:39:07 PM UTC 24 |
Sep 18 11:40:05 PM UTC 24 |
1411848178 ps |
| T2688 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.4183763446 |
|
|
Sep 18 11:38:31 PM UTC 24 |
Sep 18 11:40:15 PM UTC 24 |
8048943573 ps |
| T2689 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_error.2791934851 |
|
|
Sep 18 11:36:53 PM UTC 24 |
Sep 18 11:40:24 PM UTC 24 |
6417518154 ps |
| T2690 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.321818530 |
|
|
Sep 18 11:40:04 PM UTC 24 |
Sep 18 11:40:24 PM UTC 24 |
134880439 ps |
| T2691 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.368537925 |
|
|
Sep 18 11:40:19 PM UTC 24 |
Sep 18 11:40:42 PM UTC 24 |
329004886 ps |
| T2692 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.2767054286 |
|
|
Sep 18 11:40:24 PM UTC 24 |
Sep 18 11:40:47 PM UTC 24 |
181479792 ps |
| T2693 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.1099338696 |
|
|
Sep 18 11:40:14 PM UTC 24 |
Sep 18 11:40:48 PM UTC 24 |
410050487 ps |
| T2694 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.2841925436 |
|
|
Sep 18 11:40:27 PM UTC 24 |
Sep 18 11:40:56 PM UTC 24 |
503689367 ps |
| T2695 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.2288202780 |
|
|
Sep 18 11:40:04 PM UTC 24 |
Sep 18 11:40:59 PM UTC 24 |
544602556 ps |
| T2696 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_slow_rsp.802913793 |
|
|
Sep 18 11:36:12 PM UTC 24 |
Sep 18 11:41:01 PM UTC 24 |
20329181525 ps |
| T2697 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.1507527265 |
|
|
Sep 18 11:38:13 PM UTC 24 |
Sep 18 11:41:06 PM UTC 24 |
1283630704 ps |
| T2698 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.1986716650 |
|
|
Sep 18 11:40:56 PM UTC 24 |
Sep 18 11:41:08 PM UTC 24 |
7070801 ps |
| T2699 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.4262637139 |
|
|
Sep 18 11:40:25 PM UTC 24 |
Sep 18 11:41:18 PM UTC 24 |
1379433230 ps |
| T2700 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.962853656 |
|
|
Sep 18 11:39:50 PM UTC 24 |
Sep 18 11:41:21 PM UTC 24 |
7940654316 ps |
| T2701 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.1053033542 |
|
|
Sep 18 11:41:14 PM UTC 24 |
Sep 18 11:41:22 PM UTC 24 |
50409692 ps |
| T2702 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.2989977139 |
|
|
Sep 18 11:41:18 PM UTC 24 |
Sep 18 11:41:26 PM UTC 24 |
48569183 ps |
| T2703 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_slow_rsp.448833357 |
|
|
Sep 18 11:37:38 PM UTC 24 |
Sep 18 11:41:31 PM UTC 24 |
15369200825 ps |
| T2704 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.1148314951 |
|
|
Sep 18 11:39:51 PM UTC 24 |
Sep 18 11:41:41 PM UTC 24 |
4874962302 ps |
| T2705 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all.1845710965 |
|
|
Sep 18 11:38:09 PM UTC 24 |
Sep 18 11:41:44 PM UTC 24 |
5058941972 ps |
| T2706 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.2284945560 |
|
|
Sep 18 11:39:10 PM UTC 24 |
Sep 18 11:41:54 PM UTC 24 |
501949201 ps |
| T2707 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_large_delays.1628392553 |
|
|
Sep 18 11:33:51 PM UTC 24 |
Sep 18 11:42:00 PM UTC 24 |
43748213635 ps |
| T2708 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.3257350139 |
|
|
Sep 18 11:41:31 PM UTC 24 |
Sep 18 11:42:09 PM UTC 24 |
427062673 ps |
| T2709 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.3637425862 |
|
|
Sep 18 11:28:59 PM UTC 24 |
Sep 18 11:42:11 PM UTC 24 |
17981897016 ps |
| T2710 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.805572259 |
|
|
Sep 18 11:41:46 PM UTC 24 |
Sep 18 11:42:15 PM UTC 24 |
326777264 ps |
| T2711 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_large_delays.3402473940 |
|
|
Sep 18 11:32:58 PM UTC 24 |
Sep 18 11:42:16 PM UTC 24 |
56998364893 ps |
| T2712 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.1534410112 |
|
|
Sep 18 11:41:30 PM UTC 24 |
Sep 18 11:42:16 PM UTC 24 |
1132906675 ps |
| T2713 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.775682124 |
|
|
Sep 18 11:42:01 PM UTC 24 |
Sep 18 11:42:18 PM UTC 24 |
72880501 ps |
| T2714 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.791442253 |
|
|
Sep 18 11:41:16 PM UTC 24 |
Sep 18 11:42:28 PM UTC 24 |
7645799449 ps |
| T2715 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.376044968 |
|
|
Sep 18 11:33:25 PM UTC 24 |
Sep 18 11:42:37 PM UTC 24 |
5547142719 ps |
| T2716 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_slow_rsp.1998151337 |
|
|
Sep 18 11:38:42 PM UTC 24 |
Sep 18 11:42:39 PM UTC 24 |
14581906281 ps |
| T2717 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.3992546892 |
|
|
Sep 18 11:41:55 PM UTC 24 |
Sep 18 11:42:40 PM UTC 24 |
551930408 ps |
| T2718 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.172626498 |
|
|
Sep 18 11:42:14 PM UTC 24 |
Sep 18 11:42:41 PM UTC 24 |
275568987 ps |
| T2719 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_slow_rsp.1581895818 |
|
|
Sep 18 11:33:02 PM UTC 24 |
Sep 18 11:42:43 PM UTC 24 |
44051764123 ps |
| T2720 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.2449616757 |
|
|
Sep 18 11:42:46 PM UTC 24 |
Sep 18 11:42:54 PM UTC 24 |
43338169 ps |
| T2721 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.1028042798 |
|
|
Sep 18 11:42:42 PM UTC 24 |
Sep 18 11:42:57 PM UTC 24 |
242300921 ps |
| T2722 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.1975801095 |
|
|
Sep 18 11:41:52 PM UTC 24 |
Sep 18 11:42:59 PM UTC 24 |
2089955635 ps |
| T2723 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.3303866627 |
|
|
Sep 18 11:39:16 PM UTC 24 |
Sep 18 11:43:04 PM UTC 24 |
3300499071 ps |
| T2724 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.2221873323 |
|
|
Sep 18 11:11:56 PM UTC 24 |
Sep 18 11:43:10 PM UTC 24 |
123241815737 ps |
| T2725 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.1709026631 |
|
|
Sep 18 11:42:48 PM UTC 24 |
Sep 18 11:43:14 PM UTC 24 |
209719634 ps |
| T2726 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all.3586818735 |
|
|
Sep 18 11:40:34 PM UTC 24 |
Sep 18 11:43:17 PM UTC 24 |
2508596878 ps |
| T2727 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.4239833201 |
|
|
Sep 18 11:41:26 PM UTC 24 |
Sep 18 11:43:21 PM UTC 24 |
4953382930 ps |
| T2728 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.3656992844 |
|
|
Sep 18 11:43:11 PM UTC 24 |
Sep 18 11:43:29 PM UTC 24 |
235369628 ps |
| T2729 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.2607457628 |
|
|
Sep 18 11:43:21 PM UTC 24 |
Sep 18 11:43:34 PM UTC 24 |
266159046 ps |
| T2730 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.1243462772 |
|
|
Sep 18 11:42:58 PM UTC 24 |
Sep 18 11:43:36 PM UTC 24 |
303041498 ps |
| T2731 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.2094482424 |
|
|
Sep 18 11:43:29 PM UTC 24 |
Sep 18 11:43:40 PM UTC 24 |
236664308 ps |
| T2732 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_error.4153158688 |
|
|
Sep 18 11:40:55 PM UTC 24 |
Sep 18 11:43:45 PM UTC 24 |
2453569772 ps |
| T2733 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.3746426389 |
|
|
Sep 18 11:42:45 PM UTC 24 |
Sep 18 11:43:48 PM UTC 24 |
6501799067 ps |
| T2734 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_large_delays.4001523015 |
|
|
Sep 18 11:30:43 PM UTC 24 |
Sep 18 11:43:50 PM UTC 24 |
84002232659 ps |
| T2735 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.902627953 |
|
|
Sep 18 11:10:39 PM UTC 24 |
Sep 18 11:43:52 PM UTC 24 |
102079687622 ps |
| T2736 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.2950975964 |
|
|
Sep 18 11:21:10 PM UTC 24 |
Sep 18 11:43:55 PM UTC 24 |
87619270164 ps |
| T2737 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.3528823882 |
|
|
Sep 18 11:13:06 PM UTC 24 |
Sep 18 11:43:58 PM UTC 24 |
120763828315 ps |
| T2738 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.3258717320 |
|
|
Sep 18 11:43:52 PM UTC 24 |
Sep 18 11:44:01 PM UTC 24 |
215077607 ps |
| T2739 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.2070558176 |
|
|
Sep 18 11:43:06 PM UTC 24 |
Sep 18 11:44:08 PM UTC 24 |
764687137 ps |
| T2740 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.4275626073 |
|
|
Sep 18 11:43:58 PM UTC 24 |
Sep 18 11:44:09 PM UTC 24 |
47923899 ps |
| T2741 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_error.3212238209 |
|
|
Sep 18 11:42:31 PM UTC 24 |
Sep 18 11:44:15 PM UTC 24 |
2546186311 ps |
| T2742 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.1248246863 |
|
|
Sep 18 11:42:46 PM UTC 24 |
Sep 18 11:44:23 PM UTC 24 |
6549790906 ps |
| T2743 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_slow_rsp.687509847 |
|
|
Sep 18 11:30:51 PM UTC 24 |
Sep 18 11:44:26 PM UTC 24 |
55527481102 ps |
| T2744 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.3868132313 |
|
|
Sep 18 11:43:20 PM UTC 24 |
Sep 18 11:44:37 PM UTC 24 |
1915330592 ps |
| T2745 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_error.3586387664 |
|
|
Sep 18 11:38:18 PM UTC 24 |
Sep 18 11:44:40 PM UTC 24 |
10692075238 ps |
| T2746 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device.2986058852 |
|
|
Sep 18 11:44:21 PM UTC 24 |
Sep 18 11:44:41 PM UTC 24 |
102660612 ps |
| T2747 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_same_source.404265588 |
|
|
Sep 18 11:44:29 PM UTC 24 |
Sep 18 11:44:41 PM UTC 24 |
58122044 ps |
| T2748 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.1592245172 |
|
|
Sep 18 11:34:37 PM UTC 24 |
Sep 18 11:44:52 PM UTC 24 |
5939089233 ps |
| T2749 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_slow_rsp.3493796774 |
|
|
Sep 18 11:29:36 PM UTC 24 |
Sep 18 11:44:53 PM UTC 24 |
58542282516 ps |
| T2750 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_zero_delays.232822583 |
|
|
Sep 18 11:44:17 PM UTC 24 |
Sep 18 11:44:54 PM UTC 24 |
354139453 ps |
| T2751 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.2391701167 |
|
|
Sep 18 11:30:56 PM UTC 24 |
Sep 18 11:44:56 PM UTC 24 |
58250671796 ps |
| T2752 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_slow_rsp.540737813 |
|
|
Sep 18 11:28:31 PM UTC 24 |
Sep 18 11:45:00 PM UTC 24 |
67269091073 ps |
| T2753 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.350839635 |
|
|
Sep 18 11:35:42 PM UTC 24 |
Sep 18 11:45:00 PM UTC 24 |
6642907524 ps |
| T2754 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.3106770307 |
|
|
Sep 18 11:44:07 PM UTC 24 |
Sep 18 11:45:07 PM UTC 24 |
2949234230 ps |
| T2755 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.1827199115 |
|
|
Sep 18 11:36:53 PM UTC 24 |
Sep 18 11:45:16 PM UTC 24 |
3063252653 ps |
| T2756 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.1085858206 |
|
|
Sep 18 11:44:41 PM UTC 24 |
Sep 18 11:45:17 PM UTC 24 |
300605631 ps |
| T2757 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_unmapped_addr.1379711972 |
|
|
Sep 18 11:44:40 PM UTC 24 |
Sep 18 11:45:20 PM UTC 24 |
926229877 ps |
| T2758 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.4294473013 |
|
|
Sep 18 11:44:32 PM UTC 24 |
Sep 18 11:45:21 PM UTC 24 |
1247160005 ps |
| T2759 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_zero_delays.2125132925 |
|
|
Sep 18 11:45:12 PM UTC 24 |
Sep 18 11:45:21 PM UTC 24 |
51997852 ps |
| T2760 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.1747008835 |
|
|
Sep 18 11:45:10 PM UTC 24 |
Sep 18 11:45:23 PM UTC 24 |
209041378 ps |
| T2761 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.3658791673 |
|
|
Sep 18 11:38:50 PM UTC 24 |
Sep 18 11:45:30 PM UTC 24 |
18572918400 ps |
| T2762 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random.1939430769 |
|
|
Sep 18 11:44:09 PM UTC 24 |
Sep 18 11:45:35 PM UTC 24 |
1954523640 ps |