| T2024 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.225588811 |
|
|
Sep 18 10:48:48 PM UTC 24 |
Sep 18 10:56:06 PM UTC 24 |
1114408277 ps |
| T2025 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.1056899848 |
|
|
Sep 18 10:55:51 PM UTC 24 |
Sep 18 10:56:08 PM UTC 24 |
250227288 ps |
| T2026 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.4292976821 |
|
|
Sep 18 10:54:29 PM UTC 24 |
Sep 18 10:56:12 PM UTC 24 |
6011352927 ps |
| T2027 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.1067038039 |
|
|
Sep 18 10:55:10 PM UTC 24 |
Sep 18 10:56:12 PM UTC 24 |
143737959 ps |
| T2028 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.3922514440 |
|
|
Sep 18 10:54:13 PM UTC 24 |
Sep 18 10:56:13 PM UTC 24 |
341035835 ps |
| T2029 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.1869428089 |
|
|
Sep 18 10:55:51 PM UTC 24 |
Sep 18 10:56:14 PM UTC 24 |
215062442 ps |
| T2030 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.3457699188 |
|
|
Sep 18 10:55:37 PM UTC 24 |
Sep 18 10:56:18 PM UTC 24 |
406740498 ps |
| T2031 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.729993237 |
|
|
Sep 18 10:54:24 PM UTC 24 |
Sep 18 10:56:19 PM UTC 24 |
5699636964 ps |
| T2032 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.4009464085 |
|
|
Sep 18 10:52:52 PM UTC 24 |
Sep 18 10:56:25 PM UTC 24 |
4434617144 ps |
| T2033 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.3891954063 |
|
|
Sep 18 10:56:01 PM UTC 24 |
Sep 18 10:56:27 PM UTC 24 |
104537847 ps |
| T2034 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.2210386859 |
|
|
Sep 18 10:56:25 PM UTC 24 |
Sep 18 10:56:33 PM UTC 24 |
51866715 ps |
| T2035 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.3797737673 |
|
|
Sep 18 10:56:24 PM UTC 24 |
Sep 18 10:56:39 PM UTC 24 |
239545050 ps |
| T2036 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.2957068559 |
|
|
Sep 18 10:55:23 PM UTC 24 |
Sep 18 10:56:44 PM UTC 24 |
6466892224 ps |
| T2037 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.1822442453 |
|
|
Sep 18 10:55:36 PM UTC 24 |
Sep 18 10:56:50 PM UTC 24 |
6878763403 ps |
| T2038 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.1143134481 |
|
|
Sep 18 10:55:26 PM UTC 24 |
Sep 18 10:56:51 PM UTC 24 |
5636287869 ps |
| T2039 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.2551509426 |
|
|
Sep 18 10:56:38 PM UTC 24 |
Sep 18 10:56:55 PM UTC 24 |
190146522 ps |
| T2040 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.4205458767 |
|
|
Sep 18 10:56:40 PM UTC 24 |
Sep 18 10:56:58 PM UTC 24 |
551268609 ps |
| T2041 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.2903482188 |
|
|
Sep 18 10:55:57 PM UTC 24 |
Sep 18 10:56:59 PM UTC 24 |
1455311209 ps |
| T2042 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.2499798653 |
|
|
Sep 18 10:56:33 PM UTC 24 |
Sep 18 10:57:09 PM UTC 24 |
458325641 ps |
| T2043 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.229470102 |
|
|
Sep 18 10:55:41 PM UTC 24 |
Sep 18 10:57:10 PM UTC 24 |
2364175842 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.2333953548 |
|
|
Sep 18 10:50:51 PM UTC 24 |
Sep 18 10:57:13 PM UTC 24 |
7592841628 ps |
| T2044 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.1260013885 |
|
|
Sep 18 10:56:35 PM UTC 24 |
Sep 18 10:57:17 PM UTC 24 |
329711840 ps |
| T2045 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.1746025414 |
|
|
Sep 18 10:56:39 PM UTC 24 |
Sep 18 10:57:24 PM UTC 24 |
1601063954 ps |
| T2046 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.76292306 |
|
|
Sep 18 10:57:14 PM UTC 24 |
Sep 18 10:57:25 PM UTC 24 |
60586501 ps |
| T2047 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.435223950 |
|
|
Sep 18 10:46:59 PM UTC 24 |
Sep 18 10:57:25 PM UTC 24 |
65451083266 ps |
| T2048 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.1203055469 |
|
|
Sep 18 10:57:18 PM UTC 24 |
Sep 18 10:57:29 PM UTC 24 |
47002883 ps |
| T2049 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.2717341980 |
|
|
Sep 18 10:56:50 PM UTC 24 |
Sep 18 10:57:32 PM UTC 24 |
476378073 ps |
| T2050 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.1475546424 |
|
|
Sep 18 10:56:44 PM UTC 24 |
Sep 18 10:57:34 PM UTC 24 |
283926906 ps |
| T2051 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.977231364 |
|
|
Sep 18 10:56:48 PM UTC 24 |
Sep 18 10:57:35 PM UTC 24 |
1128097468 ps |
| T2052 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.937513197 |
|
|
Sep 18 10:55:14 PM UTC 24 |
Sep 18 10:57:51 PM UTC 24 |
2041482609 ps |
| T2053 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.1800867106 |
|
|
Sep 18 10:45:20 PM UTC 24 |
Sep 18 10:57:56 PM UTC 24 |
68171947238 ps |
| T2054 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.928719522 |
|
|
Sep 18 10:56:59 PM UTC 24 |
Sep 18 10:58:02 PM UTC 24 |
228449856 ps |
| T2055 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.3463129014 |
|
|
Sep 18 10:57:54 PM UTC 24 |
Sep 18 10:58:05 PM UTC 24 |
169694436 ps |
| T2056 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.3365760805 |
|
|
Sep 18 10:57:29 PM UTC 24 |
Sep 18 10:58:05 PM UTC 24 |
433651389 ps |
| T2057 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.1419264417 |
|
|
Sep 18 10:57:17 PM UTC 24 |
Sep 18 10:58:06 PM UTC 24 |
4785843018 ps |
| T2058 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.1596910354 |
|
|
Sep 18 10:56:33 PM UTC 24 |
Sep 18 10:58:15 PM UTC 24 |
8601365763 ps |
| T2059 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.2384160620 |
|
|
Sep 18 10:57:55 PM UTC 24 |
Sep 18 10:58:16 PM UTC 24 |
530943301 ps |
| T2060 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.3178466411 |
|
|
Sep 18 10:56:31 PM UTC 24 |
Sep 18 10:58:22 PM UTC 24 |
5806992291 ps |
| T2061 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.1964564727 |
|
|
Sep 18 10:53:56 PM UTC 24 |
Sep 18 10:58:23 PM UTC 24 |
2830702545 ps |
| T2062 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.2464773824 |
|
|
Sep 18 10:51:56 PM UTC 24 |
Sep 18 10:58:25 PM UTC 24 |
11653267084 ps |
| T2063 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.3271082119 |
|
|
Sep 18 10:58:22 PM UTC 24 |
Sep 18 10:58:33 PM UTC 24 |
190920186 ps |
| T2064 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.850802282 |
|
|
Sep 18 10:57:50 PM UTC 24 |
Sep 18 10:58:34 PM UTC 24 |
1047952970 ps |
| T2065 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.1665837137 |
|
|
Sep 18 10:56:06 PM UTC 24 |
Sep 18 10:58:34 PM UTC 24 |
4331823688 ps |
| T2066 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.534259107 |
|
|
Sep 18 10:58:32 PM UTC 24 |
Sep 18 10:58:42 PM UTC 24 |
46320456 ps |
| T2067 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.131256580 |
|
|
Sep 18 10:57:23 PM UTC 24 |
Sep 18 10:58:43 PM UTC 24 |
2259993776 ps |
| T2068 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.2369360927 |
|
|
Sep 18 10:57:49 PM UTC 24 |
Sep 18 10:58:44 PM UTC 24 |
577161921 ps |
| T2069 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.646124320 |
|
|
Sep 18 10:55:06 PM UTC 24 |
Sep 18 10:58:48 PM UTC 24 |
262872569 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.2487382563 |
|
|
Sep 18 10:54:06 PM UTC 24 |
Sep 18 10:58:52 PM UTC 24 |
1444655898 ps |
| T2070 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.2504266649 |
|
|
Sep 18 10:58:43 PM UTC 24 |
Sep 18 10:58:53 PM UTC 24 |
49849778 ps |
| T2071 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1807924227 |
|
|
Sep 18 10:57:23 PM UTC 24 |
Sep 18 10:58:53 PM UTC 24 |
4269301604 ps |
| T2072 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.2862601641 |
|
|
Sep 18 10:42:31 PM UTC 24 |
Sep 18 10:58:55 PM UTC 24 |
94226499503 ps |
| T2073 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.341303684 |
|
|
Sep 18 10:03:19 PM UTC 24 |
Sep 18 10:58:59 PM UTC 24 |
26057550994 ps |
| T2074 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.4194385733 |
|
|
Sep 18 10:58:34 PM UTC 24 |
Sep 18 10:59:09 PM UTC 24 |
934365354 ps |
| T2075 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.4040629561 |
|
|
Sep 18 10:59:01 PM UTC 24 |
Sep 18 10:59:10 PM UTC 24 |
131832373 ps |
| T2076 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.4253853422 |
|
|
Sep 18 10:58:49 PM UTC 24 |
Sep 18 10:59:16 PM UTC 24 |
213567595 ps |
| T2077 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.2688172384 |
|
|
Sep 18 10:59:02 PM UTC 24 |
Sep 18 10:59:22 PM UTC 24 |
115271794 ps |
| T2078 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.1168298003 |
|
|
Sep 18 10:50:14 PM UTC 24 |
Sep 18 10:59:23 PM UTC 24 |
52668870087 ps |
| T2079 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.385751581 |
|
|
Sep 18 10:59:17 PM UTC 24 |
Sep 18 10:59:27 PM UTC 24 |
44397962 ps |
| T2080 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.4210163593 |
|
|
Sep 18 10:59:22 PM UTC 24 |
Sep 18 10:59:29 PM UTC 24 |
47857277 ps |
| T2081 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.542444424 |
|
|
Sep 18 10:47:39 PM UTC 24 |
Sep 18 10:59:34 PM UTC 24 |
12501306722 ps |
| T2082 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.3906986060 |
|
|
Sep 18 10:59:19 PM UTC 24 |
Sep 18 10:59:39 PM UTC 24 |
34792768 ps |
| T2083 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.2627385640 |
|
|
Sep 18 10:59:10 PM UTC 24 |
Sep 18 10:59:40 PM UTC 24 |
280979004 ps |
| T2084 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.1944994864 |
|
|
Sep 18 10:57:05 PM UTC 24 |
Sep 18 10:59:40 PM UTC 24 |
5041390230 ps |
| T2085 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.1759644654 |
|
|
Sep 18 10:57:11 PM UTC 24 |
Sep 18 10:59:41 PM UTC 24 |
1596220363 ps |
| T2086 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.2910785437 |
|
|
Sep 18 10:58:33 PM UTC 24 |
Sep 18 10:59:46 PM UTC 24 |
6985507316 ps |
| T2087 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.2640293425 |
|
|
Sep 18 09:59:41 PM UTC 24 |
Sep 18 10:59:52 PM UTC 24 |
27062645487 ps |
| T2088 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.3671231567 |
|
|
Sep 18 10:59:38 PM UTC 24 |
Sep 18 10:59:56 PM UTC 24 |
309389825 ps |
| T2089 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.2871857210 |
|
|
Sep 18 10:58:02 PM UTC 24 |
Sep 18 11:00:01 PM UTC 24 |
3782234832 ps |
| T2090 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.1683365431 |
|
|
Sep 18 10:58:49 PM UTC 24 |
Sep 18 11:00:03 PM UTC 24 |
3276758776 ps |
| T2091 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.3651471032 |
|
|
Sep 18 10:57:38 PM UTC 24 |
Sep 18 11:00:17 PM UTC 24 |
2825584235 ps |
| T2092 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.2040756954 |
|
|
Sep 18 11:00:08 PM UTC 24 |
Sep 18 11:00:18 PM UTC 24 |
88431054 ps |
| T2093 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.3833685121 |
|
|
Sep 18 10:59:26 PM UTC 24 |
Sep 18 11:00:20 PM UTC 24 |
3880972540 ps |
| T2094 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.650369033 |
|
|
Sep 18 10:59:38 PM UTC 24 |
Sep 18 11:00:25 PM UTC 24 |
583687296 ps |
| T2095 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.3660355956 |
|
|
Sep 18 10:58:36 PM UTC 24 |
Sep 18 11:00:32 PM UTC 24 |
6155639920 ps |
| T2096 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.2734511555 |
|
|
Sep 18 11:00:26 PM UTC 24 |
Sep 18 11:00:35 PM UTC 24 |
43611263 ps |
| T2097 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.3902164503 |
|
|
Sep 18 10:35:20 PM UTC 24 |
Sep 18 11:00:36 PM UTC 24 |
112352941833 ps |
| T2098 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.3915486157 |
|
|
Sep 18 11:00:31 PM UTC 24 |
Sep 18 11:00:40 PM UTC 24 |
46784191 ps |
| T2099 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.1043639050 |
|
|
Sep 18 10:59:59 PM UTC 24 |
Sep 18 11:00:45 PM UTC 24 |
1543142440 ps |
| T2100 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.4227631629 |
|
|
Sep 18 10:59:00 PM UTC 24 |
Sep 18 11:00:46 PM UTC 24 |
2760486827 ps |
| T2101 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.1721225636 |
|
|
Sep 18 10:59:23 PM UTC 24 |
Sep 18 11:01:08 PM UTC 24 |
9429091368 ps |
| T2102 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.1995969928 |
|
|
Sep 18 11:00:02 PM UTC 24 |
Sep 18 11:01:11 PM UTC 24 |
1349165462 ps |
| T2103 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.3562511999 |
|
|
Sep 18 11:00:50 PM UTC 24 |
Sep 18 11:01:30 PM UTC 24 |
300054620 ps |
| T2104 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.792073106 |
|
|
Sep 18 11:00:46 PM UTC 24 |
Sep 18 11:01:31 PM UTC 24 |
1005449190 ps |
| T2105 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.654004663 |
|
|
Sep 18 10:56:22 PM UTC 24 |
Sep 18 11:01:34 PM UTC 24 |
5655368628 ps |
| T2106 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.1877807657 |
|
|
Sep 18 10:47:17 PM UTC 24 |
Sep 18 11:01:34 PM UTC 24 |
57667998759 ps |
| T2107 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.30936348 |
|
|
Sep 18 11:00:03 PM UTC 24 |
Sep 18 11:01:41 PM UTC 24 |
2307328479 ps |
| T2108 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.3232882326 |
|
|
Sep 18 11:01:15 PM UTC 24 |
Sep 18 11:01:44 PM UTC 24 |
257299959 ps |
| T2109 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.3086245013 |
|
|
Sep 18 10:51:22 PM UTC 24 |
Sep 18 11:01:47 PM UTC 24 |
39528638566 ps |
| T2110 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.1813534660 |
|
|
Sep 18 11:01:15 PM UTC 24 |
Sep 18 11:01:52 PM UTC 24 |
573695583 ps |
| T2111 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.279791772 |
|
|
Sep 18 11:01:11 PM UTC 24 |
Sep 18 11:01:53 PM UTC 24 |
462149971 ps |
| T2112 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.4047138964 |
|
|
Sep 18 11:00:48 PM UTC 24 |
Sep 18 11:02:02 PM UTC 24 |
4818139582 ps |
| T2113 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_aliasing.3181196716 |
|
|
Sep 18 09:32:27 PM UTC 24 |
Sep 18 11:02:05 PM UTC 24 |
36380662846 ps |
| T2114 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.473907357 |
|
|
Sep 18 11:01:38 PM UTC 24 |
Sep 18 11:02:08 PM UTC 24 |
608788356 ps |
| T2115 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.1738972187 |
|
|
Sep 18 11:02:02 PM UTC 24 |
Sep 18 11:02:14 PM UTC 24 |
187273429 ps |
| T2116 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.1895590152 |
|
|
Sep 18 11:02:08 PM UTC 24 |
Sep 18 11:02:17 PM UTC 24 |
47431644 ps |
| T2117 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.1334547403 |
|
|
Sep 18 10:59:12 PM UTC 24 |
Sep 18 11:02:18 PM UTC 24 |
570249965 ps |
| T2118 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.411528952 |
|
|
Sep 18 10:59:51 PM UTC 24 |
Sep 18 11:02:20 PM UTC 24 |
3692877257 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.1741056437 |
|
|
Sep 18 10:53:03 PM UTC 24 |
Sep 18 11:02:21 PM UTC 24 |
8192665974 ps |
| T2119 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.2934782296 |
|
|
Sep 18 10:59:07 PM UTC 24 |
Sep 18 11:02:26 PM UTC 24 |
2260471916 ps |
| T2120 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.399363825 |
|
|
Sep 18 10:57:57 PM UTC 24 |
Sep 18 11:02:29 PM UTC 24 |
9522415770 ps |
| T2121 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.1649219470 |
|
|
Sep 18 11:02:22 PM UTC 24 |
Sep 18 11:02:39 PM UTC 24 |
201669846 ps |
| T2122 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.3021417838 |
|
|
Sep 18 11:02:21 PM UTC 24 |
Sep 18 11:02:44 PM UTC 24 |
219113793 ps |
| T2123 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.772175350 |
|
|
Sep 18 11:00:38 PM UTC 24 |
Sep 18 11:02:54 PM UTC 24 |
8646532749 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.404330248 |
|
|
Sep 18 10:58:00 PM UTC 24 |
Sep 18 11:02:55 PM UTC 24 |
808680648 ps |
| T2124 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.732032776 |
|
|
Sep 18 11:00:53 PM UTC 24 |
Sep 18 11:03:05 PM UTC 24 |
10236745827 ps |
| T2125 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.239137677 |
|
|
Sep 18 11:02:15 PM UTC 24 |
Sep 18 11:03:17 PM UTC 24 |
4587356406 ps |
| T2126 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.2834725960 |
|
|
Sep 18 11:02:39 PM UTC 24 |
Sep 18 11:03:24 PM UTC 24 |
1043701591 ps |
| T2127 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.1851873007 |
|
|
Sep 18 11:02:50 PM UTC 24 |
Sep 18 11:03:27 PM UTC 24 |
609779254 ps |
| T2128 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.2831075592 |
|
|
Sep 18 11:01:05 PM UTC 24 |
Sep 18 11:03:28 PM UTC 24 |
3619214393 ps |
| T2129 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.1588605963 |
|
|
Sep 18 11:02:45 PM UTC 24 |
Sep 18 11:03:32 PM UTC 24 |
1240756557 ps |
| T2130 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.141594465 |
|
|
Sep 18 11:03:25 PM UTC 24 |
Sep 18 11:03:32 PM UTC 24 |
56535454 ps |
| T2131 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.1532483658 |
|
|
Sep 18 10:58:45 PM UTC 24 |
Sep 18 11:03:35 PM UTC 24 |
23559970131 ps |
| T2132 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.64959225 |
|
|
Sep 18 11:03:26 PM UTC 24 |
Sep 18 11:03:35 PM UTC 24 |
160314792 ps |
| T2133 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.903083011 |
|
|
Sep 18 11:02:47 PM UTC 24 |
Sep 18 11:03:37 PM UTC 24 |
1328037588 ps |
| T2134 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.2267514345 |
|
|
Sep 18 10:57:35 PM UTC 24 |
Sep 18 11:03:38 PM UTC 24 |
37768614411 ps |
| T2135 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.3684267507 |
|
|
Sep 18 10:59:53 PM UTC 24 |
Sep 18 11:03:43 PM UTC 24 |
14177189365 ps |
| T2136 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.3445954917 |
|
|
Sep 18 10:52:23 PM UTC 24 |
Sep 18 11:03:44 PM UTC 24 |
67043899385 ps |
| T2137 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.788855059 |
|
|
Sep 18 10:44:09 PM UTC 24 |
Sep 18 11:03:47 PM UTC 24 |
95339838642 ps |
| T2138 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.2478498699 |
|
|
Sep 18 10:54:14 PM UTC 24 |
Sep 18 11:03:55 PM UTC 24 |
15313406341 ps |
| T2139 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.1538432661 |
|
|
Sep 18 11:00:10 PM UTC 24 |
Sep 18 11:04:00 PM UTC 24 |
2957558597 ps |
| T2140 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.1124439458 |
|
|
Sep 18 11:00:22 PM UTC 24 |
Sep 18 11:04:02 PM UTC 24 |
4492907871 ps |
| T2141 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.844428259 |
|
|
Sep 18 11:02:14 PM UTC 24 |
Sep 18 11:04:04 PM UTC 24 |
8980470026 ps |
| T2142 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.239628654 |
|
|
Sep 18 11:04:04 PM UTC 24 |
Sep 18 11:04:25 PM UTC 24 |
554001757 ps |
| T2143 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.675634050 |
|
|
Sep 18 11:01:41 PM UTC 24 |
Sep 18 11:04:32 PM UTC 24 |
4367398211 ps |
| T2144 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.1007070477 |
|
|
Sep 18 11:03:53 PM UTC 24 |
Sep 18 11:04:33 PM UTC 24 |
490740495 ps |
| T2145 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.744026275 |
|
|
Sep 18 11:04:06 PM UTC 24 |
Sep 18 11:04:35 PM UTC 24 |
684911283 ps |
| T2146 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.2621134496 |
|
|
Sep 18 10:52:20 PM UTC 24 |
Sep 18 11:04:41 PM UTC 24 |
52561686578 ps |
| T2147 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.2273945586 |
|
|
Sep 18 11:04:30 PM UTC 24 |
Sep 18 11:04:42 PM UTC 24 |
175502884 ps |
| T2148 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.1454695694 |
|
|
Sep 18 11:04:04 PM UTC 24 |
Sep 18 11:04:43 PM UTC 24 |
616490366 ps |
| T2149 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.3055386052 |
|
|
Sep 18 11:04:36 PM UTC 24 |
Sep 18 11:04:43 PM UTC 24 |
53953698 ps |
| T2150 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.157983946 |
|
|
Sep 18 11:02:38 PM UTC 24 |
Sep 18 11:04:49 PM UTC 24 |
2926626225 ps |
| T2151 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.1009677187 |
|
|
Sep 18 11:04:10 PM UTC 24 |
Sep 18 11:04:50 PM UTC 24 |
682041564 ps |
| T2152 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.2259826214 |
|
|
Sep 18 11:03:37 PM UTC 24 |
Sep 18 11:04:57 PM UTC 24 |
8445954236 ps |
| T2153 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.553122788 |
|
|
Sep 18 10:55:33 PM UTC 24 |
Sep 18 11:05:03 PM UTC 24 |
37825198501 ps |
| T2154 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.2049169519 |
|
|
Sep 18 11:02:33 PM UTC 24 |
Sep 18 11:05:03 PM UTC 24 |
10069568321 ps |
| T2155 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.334005404 |
|
|
Sep 18 11:04:03 PM UTC 24 |
Sep 18 11:05:07 PM UTC 24 |
1347584443 ps |
| T2156 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.3919983825 |
|
|
Sep 18 11:00:14 PM UTC 24 |
Sep 18 11:05:09 PM UTC 24 |
8132200672 ps |
| T2157 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.2671641883 |
|
|
Sep 18 11:05:01 PM UTC 24 |
Sep 18 11:05:15 PM UTC 24 |
133097147 ps |
| T2158 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.2038631496 |
|
|
Sep 18 11:05:04 PM UTC 24 |
Sep 18 11:05:16 PM UTC 24 |
79381782 ps |
| T2159 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.3423538367 |
|
|
Sep 18 11:05:10 PM UTC 24 |
Sep 18 11:05:20 PM UTC 24 |
53047857 ps |
| T2160 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.4131074561 |
|
|
Sep 18 11:03:43 PM UTC 24 |
Sep 18 11:05:28 PM UTC 24 |
5640475069 ps |
| T2161 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.1201980308 |
|
|
Sep 18 11:03:51 PM UTC 24 |
Sep 18 11:05:28 PM UTC 24 |
2554173019 ps |
| T2162 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.2700177417 |
|
|
Sep 18 11:03:12 PM UTC 24 |
Sep 18 11:05:31 PM UTC 24 |
271673297 ps |
| T2163 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.2180318363 |
|
|
Sep 18 11:03:00 PM UTC 24 |
Sep 18 11:05:33 PM UTC 24 |
323856514 ps |
| T2164 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.4017222100 |
|
|
Sep 18 11:05:16 PM UTC 24 |
Sep 18 11:05:38 PM UTC 24 |
253458246 ps |
| T2165 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.1797774101 |
|
|
Sep 18 11:05:22 PM UTC 24 |
Sep 18 11:05:39 PM UTC 24 |
121976149 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.2634599460 |
|
|
Sep 18 11:02:04 PM UTC 24 |
Sep 18 11:05:51 PM UTC 24 |
3609619201 ps |
| T2166 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.2142137525 |
|
|
Sep 18 10:56:34 PM UTC 24 |
Sep 18 11:05:52 PM UTC 24 |
39540623692 ps |
| T2167 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.3387791530 |
|
|
Sep 18 11:05:44 PM UTC 24 |
Sep 18 11:06:00 PM UTC 24 |
236789023 ps |
| T2168 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.218930182 |
|
|
Sep 18 11:05:50 PM UTC 24 |
Sep 18 11:06:00 PM UTC 24 |
39244483 ps |
| T2169 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.361887119 |
|
|
Sep 18 11:05:32 PM UTC 24 |
Sep 18 11:06:01 PM UTC 24 |
200337379 ps |
| T2170 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.1820544099 |
|
|
Sep 18 11:05:38 PM UTC 24 |
Sep 18 11:06:01 PM UTC 24 |
109145121 ps |
| T2171 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.396386704 |
|
|
Sep 18 10:57:40 PM UTC 24 |
Sep 18 11:06:01 PM UTC 24 |
36777039453 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.3142902352 |
|
|
Sep 18 10:58:21 PM UTC 24 |
Sep 18 11:06:06 PM UTC 24 |
1399927387 ps |
| T2172 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.658070137 |
|
|
Sep 18 10:59:14 PM UTC 24 |
Sep 18 11:06:10 PM UTC 24 |
13578928292 ps |
| T2173 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.372342210 |
|
|
Sep 18 10:52:03 PM UTC 24 |
Sep 18 11:06:15 PM UTC 24 |
9158141589 ps |
| T2174 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.660469051 |
|
|
Sep 18 11:05:28 PM UTC 24 |
Sep 18 11:06:18 PM UTC 24 |
1376788084 ps |
| T2175 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.3642659749 |
|
|
Sep 18 11:05:00 PM UTC 24 |
Sep 18 11:06:18 PM UTC 24 |
5618604880 ps |
| T2176 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.3807368624 |
|
|
Sep 18 11:06:02 PM UTC 24 |
Sep 18 11:06:19 PM UTC 24 |
265786292 ps |
| T2177 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.2530039995 |
|
|
Sep 18 10:50:27 PM UTC 24 |
Sep 18 11:06:20 PM UTC 24 |
72028408242 ps |
| T2178 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.3772080219 |
|
|
Sep 18 11:04:13 PM UTC 24 |
Sep 18 11:06:22 PM UTC 24 |
3378189072 ps |
| T2179 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.1152779032 |
|
|
Sep 18 11:02:50 PM UTC 24 |
Sep 18 11:06:24 PM UTC 24 |
5422956479 ps |
| T2180 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.2260197925 |
|
|
Sep 18 11:04:48 PM UTC 24 |
Sep 18 11:06:30 PM UTC 24 |
7103077678 ps |
| T2181 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.4252063245 |
|
|
Sep 18 11:05:59 PM UTC 24 |
Sep 18 11:06:31 PM UTC 24 |
383243344 ps |
| T2182 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.2966072242 |
|
|
Sep 18 11:06:29 PM UTC 24 |
Sep 18 11:06:42 PM UTC 24 |
68981342 ps |
| T2183 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.1397955864 |
|
|
Sep 18 10:51:16 PM UTC 24 |
Sep 18 11:06:48 PM UTC 24 |
44160941986 ps |
| T2184 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.2788235038 |
|
|
Sep 18 10:52:35 PM UTC 24 |
Sep 18 11:06:50 PM UTC 24 |
55827734207 ps |
| T2185 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.2283864481 |
|
|
Sep 18 11:06:43 PM UTC 24 |
Sep 18 11:06:54 PM UTC 24 |
52404749 ps |
| T2186 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.2895062183 |
|
|
Sep 18 11:06:29 PM UTC 24 |
Sep 18 11:06:55 PM UTC 24 |
583965214 ps |
| T2187 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.2146350803 |
|
|
Sep 18 11:06:33 PM UTC 24 |
Sep 18 11:06:58 PM UTC 24 |
650032184 ps |
| T2188 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.1877875240 |
|
|
Sep 18 11:05:32 PM UTC 24 |
Sep 18 11:06:58 PM UTC 24 |
2587505434 ps |
| T2189 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.2746923583 |
|
|
Sep 18 11:06:46 PM UTC 24 |
Sep 18 11:07:00 PM UTC 24 |
206096395 ps |
| T2190 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.725790163 |
|
|
Sep 18 11:06:30 PM UTC 24 |
Sep 18 11:07:04 PM UTC 24 |
845431624 ps |
| T2191 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.2874361489 |
|
|
Sep 18 10:56:42 PM UTC 24 |
Sep 18 11:07:07 PM UTC 24 |
42064202256 ps |
| T2192 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.1538535707 |
|
|
Sep 18 10:39:40 PM UTC 24 |
Sep 18 11:07:13 PM UTC 24 |
103106047907 ps |
| T2193 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.2304513740 |
|
|
Sep 18 11:06:54 PM UTC 24 |
Sep 18 11:07:16 PM UTC 24 |
223047963 ps |
| T2194 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.1034726843 |
|
|
Sep 18 11:05:49 PM UTC 24 |
Sep 18 11:07:17 PM UTC 24 |
8060509076 ps |
| T2195 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.811358531 |
|
|
Sep 18 11:04:24 PM UTC 24 |
Sep 18 11:07:23 PM UTC 24 |
5811702094 ps |
| T2196 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.3936840620 |
|
|
Sep 18 11:05:56 PM UTC 24 |
Sep 18 11:07:32 PM UTC 24 |
5855833407 ps |
| T2197 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.2897145116 |
|
|
Sep 18 10:45:28 PM UTC 24 |
Sep 18 11:07:36 PM UTC 24 |
90215986393 ps |
| T2198 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.2926365679 |
|
|
Sep 18 11:04:15 PM UTC 24 |
Sep 18 11:07:42 PM UTC 24 |
1825564051 ps |
| T2199 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.3058141303 |
|
|
Sep 18 11:06:52 PM UTC 24 |
Sep 18 11:07:45 PM UTC 24 |
616926802 ps |
| T2200 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.1470324956 |
|
|
Sep 18 11:07:02 PM UTC 24 |
Sep 18 11:07:51 PM UTC 24 |
3422836973 ps |
| T2201 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.3190880225 |
|
|
Sep 18 11:06:23 PM UTC 24 |
Sep 18 11:07:55 PM UTC 24 |
2042188936 ps |
| T2202 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.2405130947 |
|
|
Sep 18 11:06:59 PM UTC 24 |
Sep 18 11:07:56 PM UTC 24 |
5026918362 ps |
| T2203 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.3881825729 |
|
|
Sep 18 11:07:43 PM UTC 24 |
Sep 18 11:07:56 PM UTC 24 |
230420169 ps |
| T2204 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.1164051475 |
|
|
Sep 18 11:07:48 PM UTC 24 |
Sep 18 11:07:57 PM UTC 24 |
44347002 ps |
| T2205 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.3059525657 |
|
|
Sep 18 11:07:18 PM UTC 24 |
Sep 18 11:07:57 PM UTC 24 |
547719202 ps |
| T2206 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.4206932343 |
|
|
Sep 18 11:07:24 PM UTC 24 |
Sep 18 11:08:03 PM UTC 24 |
215999547 ps |
| T2207 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.2112712017 |
|
|
Sep 18 11:07:29 PM UTC 24 |
Sep 18 11:08:04 PM UTC 24 |
306513416 ps |
| T2208 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.339245061 |
|
|
Sep 18 11:02:34 PM UTC 24 |
Sep 18 11:08:06 PM UTC 24 |
28872696617 ps |
| T2209 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.1734546307 |
|
|
Sep 18 11:05:34 PM UTC 24 |
Sep 18 11:08:08 PM UTC 24 |
5318391559 ps |
| T2210 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.4087483022 |
|
|
Sep 18 11:08:00 PM UTC 24 |
Sep 18 11:08:14 PM UTC 24 |
116198677 ps |
| T2211 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.214901114 |
|
|
Sep 18 11:07:09 PM UTC 24 |
Sep 18 11:08:15 PM UTC 24 |
1873841967 ps |
| T2212 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.9102106 |
|
|
Sep 18 11:01:07 PM UTC 24 |
Sep 18 11:08:20 PM UTC 24 |
30290939765 ps |
| T2213 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.1264506730 |
|
|
Sep 18 11:06:51 PM UTC 24 |
Sep 18 11:08:28 PM UTC 24 |
5581992652 ps |
| T2214 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.3709891318 |
|
|
Sep 18 11:07:31 PM UTC 24 |
Sep 18 11:08:35 PM UTC 24 |
857751259 ps |
| T2215 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.2537265971 |
|
|
Sep 18 11:07:22 PM UTC 24 |
Sep 18 11:08:36 PM UTC 24 |
1514100529 ps |
| T2216 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.2529495480 |
|
|
Sep 18 11:08:27 PM UTC 24 |
Sep 18 11:08:50 PM UTC 24 |
142261260 ps |
| T2217 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.2668537066 |
|
|
Sep 18 11:07:54 PM UTC 24 |
Sep 18 11:08:51 PM UTC 24 |
4021060799 ps |
| T2218 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.2274957066 |
|
|
Sep 18 11:08:42 PM UTC 24 |
Sep 18 11:08:52 PM UTC 24 |
47205093 ps |
| T2219 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.2110030803 |
|
|
Sep 18 11:06:42 PM UTC 24 |
Sep 18 11:08:53 PM UTC 24 |
325762083 ps |
| T2220 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.3475288194 |
|
|
Sep 18 11:08:07 PM UTC 24 |
Sep 18 11:08:54 PM UTC 24 |
577479901 ps |
| T2221 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.613819564 |
|
|
Sep 18 11:08:43 PM UTC 24 |
Sep 18 11:08:55 PM UTC 24 |
181528777 ps |
| T2222 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.292853473 |
|
|
Sep 18 11:08:27 PM UTC 24 |
Sep 18 11:08:56 PM UTC 24 |
329323428 ps |
| T2223 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.4050736004 |
|
|
Sep 18 11:02:01 PM UTC 24 |
Sep 18 11:09:02 PM UTC 24 |
7896989265 ps |
| T2224 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.2484090328 |
|
|
Sep 18 11:08:23 PM UTC 24 |
Sep 18 11:09:02 PM UTC 24 |
987748466 ps |
| T2225 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.1184351645 |
|
|
Sep 18 11:06:48 PM UTC 24 |
Sep 18 11:09:03 PM UTC 24 |
9996779114 ps |
| T2226 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.2541101028 |
|
|
Sep 18 11:09:02 PM UTC 24 |
Sep 18 11:09:15 PM UTC 24 |
64207703 ps |
| T2227 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.279523387 |
|
|
Sep 18 11:07:49 PM UTC 24 |
Sep 18 11:09:33 PM UTC 24 |
9723469240 ps |
| T2228 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.612107302 |
|
|
Sep 18 11:09:21 PM UTC 24 |
Sep 18 11:09:33 PM UTC 24 |
158183315 ps |
| T2229 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.86036778 |
|
|
Sep 18 10:09:44 PM UTC 24 |
Sep 18 11:09:38 PM UTC 24 |
30786838048 ps |
| T2230 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.2631912873 |
|
|
Sep 18 11:09:27 PM UTC 24 |
Sep 18 11:09:41 PM UTC 24 |
137399302 ps |
| T2231 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.1177758186 |
|
|
Sep 18 10:42:45 PM UTC 24 |
Sep 18 11:09:41 PM UTC 24 |
113871139699 ps |
| T2232 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.2104399167 |
|
|
Sep 18 11:09:02 PM UTC 24 |
Sep 18 11:09:47 PM UTC 24 |
1033798687 ps |
| T2233 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.3792473375 |
|
|
Sep 18 10:53:40 PM UTC 24 |
Sep 18 11:09:47 PM UTC 24 |
90243189380 ps |
| T2234 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.36943226 |
|
|
Sep 18 11:09:30 PM UTC 24 |
Sep 18 11:09:51 PM UTC 24 |
430819275 ps |
| T2235 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.2860638333 |
|
|
Sep 18 11:08:27 PM UTC 24 |
Sep 18 11:09:56 PM UTC 24 |
2069679241 ps |
| T2236 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.3534743513 |
|
|
Sep 18 11:04:04 PM UTC 24 |
Sep 18 11:10:07 PM UTC 24 |
28495658255 ps |
| T2237 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.1479929981 |
|
|
Sep 18 11:08:59 PM UTC 24 |
Sep 18 11:10:09 PM UTC 24 |
4277176327 ps |
| T2238 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.1123756074 |
|
|
Sep 18 10:59:53 PM UTC 24 |
Sep 18 11:10:10 PM UTC 24 |
43442140445 ps |
| T2239 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.541705621 |
|
|
Sep 18 11:00:12 PM UTC 24 |
Sep 18 11:10:11 PM UTC 24 |
4779967343 ps |
| T2240 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.1612048825 |
|
|
Sep 18 11:10:05 PM UTC 24 |
Sep 18 11:10:15 PM UTC 24 |
240941037 ps |
| T2241 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.144845687 |
|
|
Sep 18 11:04:03 PM UTC 24 |
Sep 18 11:10:17 PM UTC 24 |
26287528219 ps |
| T2242 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.1412708160 |
|
|
Sep 18 10:36:24 PM UTC 24 |
Sep 18 11:10:19 PM UTC 24 |
133400630563 ps |
| T2243 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.1930239118 |
|
|
Sep 18 11:10:10 PM UTC 24 |
Sep 18 11:10:21 PM UTC 24 |
54985137 ps |
| T2244 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.246817006 |
|
|
Sep 18 11:08:20 PM UTC 24 |
Sep 18 11:10:23 PM UTC 24 |
3530295410 ps |
| T2245 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.143281666 |
|
|
Sep 18 11:02:03 PM UTC 24 |
Sep 18 11:10:41 PM UTC 24 |
13765013163 ps |
| T2246 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.1888343048 |
|
|
Sep 18 11:10:17 PM UTC 24 |
Sep 18 11:10:44 PM UTC 24 |
181649511 ps |
| T2247 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.2841645620 |
|
|
Sep 18 11:07:29 PM UTC 24 |
Sep 18 11:10:49 PM UTC 24 |
4509025142 ps |
| T2248 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.61462840 |
|
|
Sep 18 11:08:49 PM UTC 24 |
Sep 18 11:11:03 PM UTC 24 |
8495599994 ps |
| T2249 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.3938376392 |
|
|
Sep 18 11:09:23 PM UTC 24 |
Sep 18 11:11:09 PM UTC 24 |
2590708621 ps |
| T2250 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.542398652 |
|
|
Sep 18 11:10:35 PM UTC 24 |
Sep 18 11:11:09 PM UTC 24 |
418443423 ps |
| T2251 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.4278817108 |
|
|
Sep 18 11:10:16 PM UTC 24 |
Sep 18 11:11:12 PM UTC 24 |
1780644456 ps |
| T2252 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.4246778902 |
|
|
Sep 18 11:10:38 PM UTC 24 |
Sep 18 11:11:14 PM UTC 24 |
735019383 ps |
| T2253 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.1454052013 |
|
|
Sep 18 11:10:44 PM UTC 24 |
Sep 18 11:11:18 PM UTC 24 |
948906871 ps |
| T2254 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.227422459 |
|
|
Sep 18 11:10:11 PM UTC 24 |
Sep 18 11:11:20 PM UTC 24 |
7002459641 ps |
| T2255 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.404677412 |
|
|
Sep 18 11:11:15 PM UTC 24 |
Sep 18 11:11:25 PM UTC 24 |
47231629 ps |
| T2256 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.3977665432 |
|
|
Sep 18 11:11:20 PM UTC 24 |
Sep 18 11:11:30 PM UTC 24 |
43589724 ps |
| T2257 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.1743276751 |
|
|
Sep 18 11:10:44 PM UTC 24 |
Sep 18 11:11:30 PM UTC 24 |
830758859 ps |
| T2258 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.190782141 |
|
|
Sep 18 11:09:24 PM UTC 24 |
Sep 18 11:11:35 PM UTC 24 |
2725857042 ps |
| T2259 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.4108209481 |
|
|
Sep 18 11:06:38 PM UTC 24 |
Sep 18 11:11:37 PM UTC 24 |
3252406952 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1427065580 |
|
|
Sep 18 11:05:45 PM UTC 24 |
Sep 18 11:11:50 PM UTC 24 |
9470115393 ps |
| T2260 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.3389015823 |
|
|
Sep 18 11:10:09 PM UTC 24 |
Sep 18 11:11:51 PM UTC 24 |
5637556953 ps |
| T2261 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.2778789588 |
|
|
Sep 18 11:10:51 PM UTC 24 |
Sep 18 11:11:54 PM UTC 24 |
700572669 ps |
| T2262 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.2571372470 |
|
|
Sep 18 11:05:11 PM UTC 24 |
Sep 18 11:11:59 PM UTC 24 |
38906144939 ps |
| T2263 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2009600158 |
|
|
Sep 18 10:55:39 PM UTC 24 |
Sep 18 11:12:02 PM UTC 24 |
65745475478 ps |
| T2264 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.667449732 |
|
|
Sep 18 11:08:06 PM UTC 24 |
Sep 18 11:12:03 PM UTC 24 |
19846170741 ps |
| T2265 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.1940556877 |
|
|
Sep 18 11:11:50 PM UTC 24 |
Sep 18 11:12:06 PM UTC 24 |
136593576 ps |
| T2266 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.3296753217 |
|
|
Sep 18 10:53:49 PM UTC 24 |
Sep 18 11:12:07 PM UTC 24 |
68711771177 ps |