| T1788 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.424034074 |
|
|
Sep 18 10:24:14 PM UTC 24 |
Sep 18 10:39:09 PM UTC 24 |
88058496824 ps |
| T1789 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.218625982 |
|
|
Sep 18 10:38:58 PM UTC 24 |
Sep 18 10:39:10 PM UTC 24 |
207470519 ps |
| T1790 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.3763388919 |
|
|
Sep 18 10:38:36 PM UTC 24 |
Sep 18 10:39:11 PM UTC 24 |
838082652 ps |
| T1791 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.390276624 |
|
|
Sep 18 10:38:04 PM UTC 24 |
Sep 18 10:39:15 PM UTC 24 |
1027104132 ps |
| T1792 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.1370472340 |
|
|
Sep 18 09:28:04 PM UTC 24 |
Sep 18 10:39:18 PM UTC 24 |
40808500744 ps |
| T1793 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.3108602831 |
|
|
Sep 18 10:38:19 PM UTC 24 |
Sep 18 10:39:25 PM UTC 24 |
2371689598 ps |
| T1794 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.405406646 |
|
|
Sep 18 10:35:50 PM UTC 24 |
Sep 18 10:39:36 PM UTC 24 |
1477814766 ps |
| T1795 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.602919979 |
|
|
Sep 18 10:24:17 PM UTC 24 |
Sep 18 10:39:41 PM UTC 24 |
55036293744 ps |
| T1796 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.1460687265 |
|
|
Sep 18 10:39:27 PM UTC 24 |
Sep 18 10:39:54 PM UTC 24 |
262177262 ps |
| T1797 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.600292777 |
|
|
Sep 18 10:35:09 PM UTC 24 |
Sep 18 10:39:59 PM UTC 24 |
19999629988 ps |
| T1798 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.3641878041 |
|
|
Sep 18 10:39:45 PM UTC 24 |
Sep 18 10:40:14 PM UTC 24 |
172325723 ps |
| T1799 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.3871284947 |
|
|
Sep 18 10:39:37 PM UTC 24 |
Sep 18 10:40:14 PM UTC 24 |
334401011 ps |
| T1800 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.2998538324 |
|
|
Sep 18 10:38:48 PM UTC 24 |
Sep 18 10:40:22 PM UTC 24 |
3459846244 ps |
| T1801 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.267117465 |
|
|
Sep 18 10:39:39 PM UTC 24 |
Sep 18 10:40:23 PM UTC 24 |
1097285289 ps |
| T1802 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.3530463239 |
|
|
Sep 18 10:39:46 PM UTC 24 |
Sep 18 10:40:25 PM UTC 24 |
388862210 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.2827687876 |
|
|
Sep 18 10:21:23 PM UTC 24 |
Sep 18 10:40:30 PM UTC 24 |
97768493696 ps |
| T1803 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.2976516083 |
|
|
Sep 18 10:39:23 PM UTC 24 |
Sep 18 10:40:32 PM UTC 24 |
2134624766 ps |
| T1804 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.3426996158 |
|
|
Sep 18 10:36:51 PM UTC 24 |
Sep 18 10:40:32 PM UTC 24 |
2512150790 ps |
| T1805 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.1507516378 |
|
|
Sep 18 10:39:03 PM UTC 24 |
Sep 18 10:40:35 PM UTC 24 |
8892650947 ps |
| T1806 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.1984712200 |
|
|
Sep 18 10:39:53 PM UTC 24 |
Sep 18 10:40:35 PM UTC 24 |
711506072 ps |
| T1807 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.177730077 |
|
|
Sep 18 10:39:21 PM UTC 24 |
Sep 18 10:40:46 PM UTC 24 |
5300675543 ps |
| T1808 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.559977691 |
|
|
Sep 18 10:37:14 PM UTC 24 |
Sep 18 10:40:49 PM UTC 24 |
667224752 ps |
| T1809 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.1594695529 |
|
|
Sep 18 10:40:44 PM UTC 24 |
Sep 18 10:40:51 PM UTC 24 |
39135676 ps |
| T1810 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.931375111 |
|
|
Sep 18 10:40:45 PM UTC 24 |
Sep 18 10:40:54 PM UTC 24 |
38965448 ps |
| T1811 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.1191013890 |
|
|
Sep 18 10:35:34 PM UTC 24 |
Sep 18 10:40:57 PM UTC 24 |
9031962071 ps |
| T1812 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.2354132291 |
|
|
Sep 18 10:30:21 PM UTC 24 |
Sep 18 10:41:00 PM UTC 24 |
63484158353 ps |
| T1813 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.2249571177 |
|
|
Sep 18 10:35:32 PM UTC 24 |
Sep 18 10:41:00 PM UTC 24 |
1593732191 ps |
| T1814 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.3539897760 |
|
|
Sep 18 10:37:53 PM UTC 24 |
Sep 18 10:41:08 PM UTC 24 |
19750845142 ps |
| T1815 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.4018020957 |
|
|
Sep 18 10:40:57 PM UTC 24 |
Sep 18 10:41:10 PM UTC 24 |
167348872 ps |
| T1816 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.3964822976 |
|
|
Sep 18 10:41:04 PM UTC 24 |
Sep 18 10:41:42 PM UTC 24 |
296987619 ps |
| T1817 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.2041790631 |
|
|
Sep 18 10:41:23 PM UTC 24 |
Sep 18 10:41:45 PM UTC 24 |
199604914 ps |
| T1818 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.2212806649 |
|
|
Sep 18 10:40:58 PM UTC 24 |
Sep 18 10:41:49 PM UTC 24 |
407648383 ps |
| T1819 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.3263205948 |
|
|
Sep 18 10:41:41 PM UTC 24 |
Sep 18 10:41:51 PM UTC 24 |
228248707 ps |
| T1820 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.537285118 |
|
|
Sep 18 10:41:17 PM UTC 24 |
Sep 18 10:41:56 PM UTC 24 |
549793820 ps |
| T1821 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.2522653752 |
|
|
Sep 18 10:26:08 PM UTC 24 |
Sep 18 10:41:58 PM UTC 24 |
54479651094 ps |
| T1822 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.1812304660 |
|
|
Sep 18 10:41:20 PM UTC 24 |
Sep 18 10:42:00 PM UTC 24 |
222623359 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.1494885110 |
|
|
Sep 18 10:34:39 PM UTC 24 |
Sep 18 10:42:02 PM UTC 24 |
1589979907 ps |
| T1823 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.700294266 |
|
|
Sep 18 10:27:58 PM UTC 24 |
Sep 18 10:42:14 PM UTC 24 |
53773846097 ps |
| T1824 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.3664685794 |
|
|
Sep 18 10:42:13 PM UTC 24 |
Sep 18 10:42:24 PM UTC 24 |
56547663 ps |
| T1825 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.4044171261 |
|
|
Sep 18 10:42:27 PM UTC 24 |
Sep 18 10:42:37 PM UTC 24 |
26529241 ps |
| T1826 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.2314296405 |
|
|
Sep 18 10:40:51 PM UTC 24 |
Sep 18 10:42:45 PM UTC 24 |
10776000588 ps |
| T1827 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.1779306040 |
|
|
Sep 18 10:40:53 PM UTC 24 |
Sep 18 10:42:46 PM UTC 24 |
5825951086 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.1096261260 |
|
|
Sep 18 10:21:37 PM UTC 24 |
Sep 18 10:42:52 PM UTC 24 |
79571527514 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.2808974448 |
|
|
Sep 18 10:40:06 PM UTC 24 |
Sep 18 10:42:52 PM UTC 24 |
2021102932 ps |
| T1828 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.1782684347 |
|
|
Sep 18 10:41:15 PM UTC 24 |
Sep 18 10:42:57 PM UTC 24 |
2490565223 ps |
| T1829 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.3926045449 |
|
|
Sep 18 10:36:52 PM UTC 24 |
Sep 18 10:42:58 PM UTC 24 |
3476366792 ps |
| T1830 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.2799165133 |
|
|
Sep 18 10:42:22 PM UTC 24 |
Sep 18 10:42:59 PM UTC 24 |
318319893 ps |
| T1831 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.2195158768 |
|
|
Sep 18 10:40:13 PM UTC 24 |
Sep 18 10:43:04 PM UTC 24 |
682852101 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.999773487 |
|
|
Sep 18 10:35:26 PM UTC 24 |
Sep 18 10:43:09 PM UTC 24 |
11259337156 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.2881897782 |
|
|
Sep 18 10:29:11 PM UTC 24 |
Sep 18 10:43:22 PM UTC 24 |
59038693115 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2217579920 |
|
|
Sep 18 10:40:27 PM UTC 24 |
Sep 18 10:43:23 PM UTC 24 |
303497056 ps |
| T1832 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.2890908577 |
|
|
Sep 18 10:42:55 PM UTC 24 |
Sep 18 10:43:36 PM UTC 24 |
1475561308 ps |
| T1833 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.2528045030 |
|
|
Sep 18 10:43:30 PM UTC 24 |
Sep 18 10:43:38 PM UTC 24 |
43750858 ps |
| T1834 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.1461950167 |
|
|
Sep 18 10:43:14 PM UTC 24 |
Sep 18 10:43:40 PM UTC 24 |
577750432 ps |
| T1835 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.26442324 |
|
|
Sep 18 10:43:15 PM UTC 24 |
Sep 18 10:43:41 PM UTC 24 |
396272203 ps |
| T1836 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.3813388668 |
|
|
Sep 18 10:42:35 PM UTC 24 |
Sep 18 10:43:42 PM UTC 24 |
767781080 ps |
| T1837 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.1155940894 |
|
|
Sep 18 10:43:33 PM UTC 24 |
Sep 18 10:43:43 PM UTC 24 |
57033628 ps |
| T1838 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.2415139075 |
|
|
Sep 18 10:42:12 PM UTC 24 |
Sep 18 10:43:47 PM UTC 24 |
8988037415 ps |
| T1839 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.170889801 |
|
|
Sep 18 10:43:09 PM UTC 24 |
Sep 18 10:43:56 PM UTC 24 |
966646073 ps |
| T1840 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.3618602089 |
|
|
Sep 18 10:41:01 PM UTC 24 |
Sep 18 10:44:03 PM UTC 24 |
14800121888 ps |
| T1841 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.1378588351 |
|
|
Sep 18 10:42:19 PM UTC 24 |
Sep 18 10:44:05 PM UTC 24 |
5355735937 ps |
| T1842 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.1030718137 |
|
|
Sep 18 10:41:29 PM UTC 24 |
Sep 18 10:44:07 PM UTC 24 |
259096550 ps |
| T1843 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.1387014911 |
|
|
Sep 18 10:34:23 PM UTC 24 |
Sep 18 10:44:08 PM UTC 24 |
32478099948 ps |
| T1844 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.194822452 |
|
|
Sep 18 10:22:56 PM UTC 24 |
Sep 18 10:44:14 PM UTC 24 |
79549655119 ps |
| T1845 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.959914321 |
|
|
Sep 18 10:38:43 PM UTC 24 |
Sep 18 10:44:17 PM UTC 24 |
4041967483 ps |
| T1846 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.4144478895 |
|
|
Sep 18 10:44:03 PM UTC 24 |
Sep 18 10:44:23 PM UTC 24 |
113970992 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.1643364998 |
|
|
Sep 18 10:38:09 PM UTC 24 |
Sep 18 10:44:31 PM UTC 24 |
23483338514 ps |
| T1847 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.3301968932 |
|
|
Sep 18 10:44:17 PM UTC 24 |
Sep 18 10:44:38 PM UTC 24 |
522406223 ps |
| T1848 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.3253531169 |
|
|
Sep 18 10:43:50 PM UTC 24 |
Sep 18 10:44:48 PM UTC 24 |
1726440834 ps |
| T1849 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.2274164756 |
|
|
Sep 18 10:41:39 PM UTC 24 |
Sep 18 10:44:50 PM UTC 24 |
3696217291 ps |
| T1850 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.3608976 |
|
|
Sep 18 10:44:09 PM UTC 24 |
Sep 18 10:44:53 PM UTC 24 |
416414017 ps |
| T1851 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.398326794 |
|
|
Sep 18 10:44:42 PM UTC 24 |
Sep 18 10:44:54 PM UTC 24 |
154432981 ps |
| T1852 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.2729926681 |
|
|
Sep 18 10:43:39 PM UTC 24 |
Sep 18 10:45:01 PM UTC 24 |
8096470241 ps |
| T1853 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.377083723 |
|
|
Sep 18 10:44:22 PM UTC 24 |
Sep 18 10:45:02 PM UTC 24 |
830625138 ps |
| T1854 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.2648787311 |
|
|
Sep 18 10:44:52 PM UTC 24 |
Sep 18 10:45:02 PM UTC 24 |
43552149 ps |
| T1855 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.2279486902 |
|
|
Sep 18 10:43:50 PM UTC 24 |
Sep 18 10:45:08 PM UTC 24 |
5795430808 ps |
| T1856 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.2130428406 |
|
|
Sep 18 10:34:11 PM UTC 24 |
Sep 18 10:45:11 PM UTC 24 |
71079028431 ps |
| T1857 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.4158306027 |
|
|
Sep 18 10:44:27 PM UTC 24 |
Sep 18 10:45:11 PM UTC 24 |
329377106 ps |
| T1858 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.1949303129 |
|
|
Sep 18 10:44:14 PM UTC 24 |
Sep 18 10:45:21 PM UTC 24 |
1743353090 ps |
| T1859 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.2994692139 |
|
|
Sep 18 10:31:30 PM UTC 24 |
Sep 18 10:45:55 PM UTC 24 |
60739834691 ps |
| T1860 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.3847706388 |
|
|
Sep 18 10:45:37 PM UTC 24 |
Sep 18 10:45:58 PM UTC 24 |
367048656 ps |
| T1861 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.3795067199 |
|
|
Sep 18 10:44:32 PM UTC 24 |
Sep 18 10:46:02 PM UTC 24 |
2310892230 ps |
| T1862 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.38625816 |
|
|
Sep 18 10:35:07 PM UTC 24 |
Sep 18 10:46:04 PM UTC 24 |
70498055761 ps |
| T1863 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.2035229867 |
|
|
Sep 18 10:45:39 PM UTC 24 |
Sep 18 10:46:07 PM UTC 24 |
412955184 ps |
| T1864 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.2149785985 |
|
|
Sep 18 10:41:25 PM UTC 24 |
Sep 18 10:46:10 PM UTC 24 |
8182784402 ps |
| T1865 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.4060056892 |
|
|
Sep 18 10:45:43 PM UTC 24 |
Sep 18 10:46:18 PM UTC 24 |
695330150 ps |
| T1866 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.2888615486 |
|
|
Sep 18 10:44:37 PM UTC 24 |
Sep 18 10:46:20 PM UTC 24 |
2727391416 ps |
| T1867 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.2590124008 |
|
|
Sep 18 10:45:18 PM UTC 24 |
Sep 18 10:46:28 PM UTC 24 |
561408308 ps |
| T1868 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.2550206185 |
|
|
Sep 18 10:45:18 PM UTC 24 |
Sep 18 10:46:31 PM UTC 24 |
2065027472 ps |
| T1869 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.1937322358 |
|
|
Sep 18 10:46:37 PM UTC 24 |
Sep 18 10:46:47 PM UTC 24 |
43902029 ps |
| T1870 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.2454383179 |
|
|
Sep 18 10:45:30 PM UTC 24 |
Sep 18 10:46:48 PM UTC 24 |
1693505877 ps |
| T1871 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.920549554 |
|
|
Sep 18 10:46:36 PM UTC 24 |
Sep 18 10:46:49 PM UTC 24 |
199656730 ps |
| T1872 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.1778031637 |
|
|
Sep 18 09:57:19 PM UTC 24 |
Sep 18 10:46:58 PM UTC 24 |
29578961216 ps |
| T1873 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.1426871481 |
|
|
Sep 18 10:44:58 PM UTC 24 |
Sep 18 10:47:00 PM UTC 24 |
8072368598 ps |
| T1874 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.1212576962 |
|
|
Sep 18 10:32:59 PM UTC 24 |
Sep 18 10:47:00 PM UTC 24 |
90577339740 ps |
| T1875 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.2368843755 |
|
|
Sep 18 10:45:07 PM UTC 24 |
Sep 18 10:47:02 PM UTC 24 |
5031042794 ps |
| T1876 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.3466862790 |
|
|
Sep 18 10:45:28 PM UTC 24 |
Sep 18 10:47:07 PM UTC 24 |
2510293824 ps |
| T1877 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.3284468187 |
|
|
Sep 18 10:44:08 PM UTC 24 |
Sep 18 10:47:07 PM UTC 24 |
8660597877 ps |
| T1878 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.752616512 |
|
|
Sep 18 10:46:56 PM UTC 24 |
Sep 18 10:47:11 PM UTC 24 |
91653106 ps |
| T1879 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.1968951109 |
|
|
Sep 18 10:39:38 PM UTC 24 |
Sep 18 10:47:24 PM UTC 24 |
41435877698 ps |
| T1880 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2526239331 |
|
|
Sep 18 10:44:06 PM UTC 24 |
Sep 18 10:47:36 PM UTC 24 |
15285289510 ps |
| T1881 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.3807784375 |
|
|
Sep 18 10:46:50 PM UTC 24 |
Sep 18 10:47:41 PM UTC 24 |
1226934426 ps |
| T1882 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.2697743089 |
|
|
Sep 18 10:47:32 PM UTC 24 |
Sep 18 10:47:41 PM UTC 24 |
22950941 ps |
| T1883 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.522171422 |
|
|
Sep 18 10:43:24 PM UTC 24 |
Sep 18 10:47:44 PM UTC 24 |
6211603604 ps |
| T1884 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.491234838 |
|
|
Sep 18 10:28:59 PM UTC 24 |
Sep 18 10:47:44 PM UTC 24 |
108066238629 ps |
| T1885 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.3904157019 |
|
|
Sep 18 10:40:16 PM UTC 24 |
Sep 18 10:47:55 PM UTC 24 |
14532790334 ps |
| T1886 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.3443390537 |
|
|
Sep 18 10:47:15 PM UTC 24 |
Sep 18 10:47:55 PM UTC 24 |
824908517 ps |
| T1887 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.2689565793 |
|
|
Sep 18 10:41:01 PM UTC 24 |
Sep 18 10:47:58 PM UTC 24 |
33971964479 ps |
| T1888 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.2774977462 |
|
|
Sep 18 10:32:59 PM UTC 24 |
Sep 18 10:48:01 PM UTC 24 |
69185770370 ps |
| T1889 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.2959437140 |
|
|
Sep 18 10:41:29 PM UTC 24 |
Sep 18 10:48:03 PM UTC 24 |
11149498312 ps |
| T1890 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.3487664354 |
|
|
Sep 18 10:46:48 PM UTC 24 |
Sep 18 10:48:10 PM UTC 24 |
5870494511 ps |
| T1891 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.2632492931 |
|
|
Sep 18 10:47:51 PM UTC 24 |
Sep 18 10:48:13 PM UTC 24 |
75178005 ps |
| T1892 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.2021998110 |
|
|
Sep 18 10:48:04 PM UTC 24 |
Sep 18 10:48:15 PM UTC 24 |
234557127 ps |
| T1893 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.2890387884 |
|
|
Sep 18 10:47:33 PM UTC 24 |
Sep 18 10:48:16 PM UTC 24 |
667329424 ps |
| T1894 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.2734924414 |
|
|
Sep 18 10:48:10 PM UTC 24 |
Sep 18 10:48:21 PM UTC 24 |
50070168 ps |
| T1895 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.433452659 |
|
|
Sep 18 10:46:38 PM UTC 24 |
Sep 18 10:48:21 PM UTC 24 |
7538616835 ps |
| T1896 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.3090471182 |
|
|
Sep 18 10:45:51 PM UTC 24 |
Sep 18 10:48:24 PM UTC 24 |
1961661240 ps |
| T1897 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.2915605713 |
|
|
Sep 18 10:30:23 PM UTC 24 |
Sep 18 10:48:24 PM UTC 24 |
67030197478 ps |
| T1898 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.2485788280 |
|
|
Sep 18 10:47:32 PM UTC 24 |
Sep 18 10:48:31 PM UTC 24 |
1264234102 ps |
| T1899 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.4068228722 |
|
|
Sep 18 10:42:32 PM UTC 24 |
Sep 18 10:48:33 PM UTC 24 |
20484725859 ps |
| T1900 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.2343363985 |
|
|
Sep 18 10:36:20 PM UTC 24 |
Sep 18 10:48:33 PM UTC 24 |
77601692967 ps |
| T1901 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.731654640 |
|
|
Sep 18 10:44:36 PM UTC 24 |
Sep 18 10:48:36 PM UTC 24 |
2082621380 ps |
| T1902 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.2518245178 |
|
|
Sep 18 10:47:39 PM UTC 24 |
Sep 18 10:48:38 PM UTC 24 |
571205212 ps |
| T1903 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.468410994 |
|
|
Sep 18 10:48:28 PM UTC 24 |
Sep 18 10:48:41 PM UTC 24 |
253561014 ps |
| T1904 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.2773643209 |
|
|
Sep 18 10:47:29 PM UTC 24 |
Sep 18 10:48:42 PM UTC 24 |
2269894323 ps |
| T1905 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.1889311160 |
|
|
Sep 18 10:38:41 PM UTC 24 |
Sep 18 10:48:48 PM UTC 24 |
17723463618 ps |
| T1906 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.1896964919 |
|
|
Sep 18 10:48:24 PM UTC 24 |
Sep 18 10:48:56 PM UTC 24 |
406568416 ps |
| T1907 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.2036064474 |
|
|
Sep 18 10:48:57 PM UTC 24 |
Sep 18 10:49:06 PM UTC 24 |
38847741 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.2340823318 |
|
|
Sep 18 10:08:06 PM UTC 24 |
Sep 18 10:49:09 PM UTC 24 |
130959607680 ps |
| T1908 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.1206268474 |
|
|
Sep 18 10:49:00 PM UTC 24 |
Sep 18 10:49:09 PM UTC 24 |
43342606 ps |
| T1909 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.2961541286 |
|
|
Sep 18 10:48:35 PM UTC 24 |
Sep 18 10:49:10 PM UTC 24 |
1242568440 ps |
| T1910 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.163405301 |
|
|
Sep 18 10:44:44 PM UTC 24 |
Sep 18 10:49:11 PM UTC 24 |
4761666993 ps |
| T1911 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.923154785 |
|
|
Sep 18 09:48:33 PM UTC 24 |
Sep 18 10:49:14 PM UTC 24 |
28744219620 ps |
| T1912 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.1017898585 |
|
|
Sep 18 10:48:41 PM UTC 24 |
Sep 18 10:49:16 PM UTC 24 |
803198440 ps |
| T1913 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.2745874209 |
|
|
Sep 18 10:48:47 PM UTC 24 |
Sep 18 10:49:18 PM UTC 24 |
494074748 ps |
| T1914 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.1694198692 |
|
|
Sep 18 10:48:14 PM UTC 24 |
Sep 18 10:49:21 PM UTC 24 |
3206333960 ps |
| T1915 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.947601930 |
|
|
Sep 18 10:49:07 PM UTC 24 |
Sep 18 10:49:24 PM UTC 24 |
181879494 ps |
| T1916 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.3450542000 |
|
|
Sep 18 10:49:04 PM UTC 24 |
Sep 18 10:49:28 PM UTC 24 |
171916048 ps |
| T1917 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.1605525202 |
|
|
Sep 18 10:48:10 PM UTC 24 |
Sep 18 10:49:29 PM UTC 24 |
8396144682 ps |
| T1918 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.2903232365 |
|
|
Sep 18 10:31:24 PM UTC 24 |
Sep 18 10:49:31 PM UTC 24 |
100987684707 ps |
| T1919 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.2670411125 |
|
|
Sep 18 10:48:40 PM UTC 24 |
Sep 18 10:49:33 PM UTC 24 |
604437910 ps |
| T1920 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.2130893991 |
|
|
Sep 18 10:48:41 PM UTC 24 |
Sep 18 10:49:36 PM UTC 24 |
1305695594 ps |
| T1921 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.181805729 |
|
|
Sep 18 10:48:15 PM UTC 24 |
Sep 18 10:49:43 PM UTC 24 |
1940069168 ps |
| T1922 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.2715903615 |
|
|
Sep 18 10:34:19 PM UTC 24 |
Sep 18 10:49:45 PM UTC 24 |
56332748741 ps |
| T1923 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.3006186432 |
|
|
Sep 18 10:48:52 PM UTC 24 |
Sep 18 10:49:53 PM UTC 24 |
898523659 ps |
| T1924 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.3701975891 |
|
|
Sep 18 10:49:41 PM UTC 24 |
Sep 18 10:49:57 PM UTC 24 |
292554401 ps |
| T1925 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.2228896678 |
|
|
Sep 18 10:49:46 PM UTC 24 |
Sep 18 10:49:58 PM UTC 24 |
184146829 ps |
| T1926 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.2025353423 |
|
|
Sep 18 10:49:13 PM UTC 24 |
Sep 18 10:50:02 PM UTC 24 |
2856959830 ps |
| T1927 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.3636674852 |
|
|
Sep 18 10:49:49 PM UTC 24 |
Sep 18 10:50:02 PM UTC 24 |
189667923 ps |
| T1928 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.2131067028 |
|
|
Sep 18 10:46:26 PM UTC 24 |
Sep 18 10:50:04 PM UTC 24 |
3531824578 ps |
| T1929 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3665784705 |
|
|
Sep 18 10:43:30 PM UTC 24 |
Sep 18 10:50:05 PM UTC 24 |
6885521389 ps |
| T1930 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.2666526457 |
|
|
Sep 18 10:49:58 PM UTC 24 |
Sep 18 10:50:07 PM UTC 24 |
50948100 ps |
| T1931 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.2950037441 |
|
|
Sep 18 10:49:37 PM UTC 24 |
Sep 18 10:50:15 PM UTC 24 |
443268199 ps |
| T1932 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.3582340182 |
|
|
Sep 18 10:49:36 PM UTC 24 |
Sep 18 10:50:23 PM UTC 24 |
1158128645 ps |
| T1933 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.3137710453 |
|
|
Sep 18 10:49:34 PM UTC 24 |
Sep 18 10:50:32 PM UTC 24 |
566969486 ps |
| T1934 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.181007647 |
|
|
Sep 18 10:50:04 PM UTC 24 |
Sep 18 10:50:35 PM UTC 24 |
253442979 ps |
| T1935 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.1104734296 |
|
|
Sep 18 10:49:39 PM UTC 24 |
Sep 18 10:50:39 PM UTC 24 |
1147593771 ps |
| T1936 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.2259468331 |
|
|
Sep 18 10:50:03 PM UTC 24 |
Sep 18 10:50:39 PM UTC 24 |
374042084 ps |
| T1937 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.2964038022 |
|
|
Sep 18 10:49:45 PM UTC 24 |
Sep 18 10:50:41 PM UTC 24 |
211712692 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.4114379532 |
|
|
Sep 18 10:38:57 PM UTC 24 |
Sep 18 10:50:44 PM UTC 24 |
16505058097 ps |
| T1938 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.477962896 |
|
|
Sep 18 10:50:36 PM UTC 24 |
Sep 18 10:50:47 PM UTC 24 |
36333223 ps |
| T1939 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.3951763184 |
|
|
Sep 18 10:50:28 PM UTC 24 |
Sep 18 10:50:48 PM UTC 24 |
445623687 ps |
| T1940 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.3652164257 |
|
|
Sep 18 10:49:03 PM UTC 24 |
Sep 18 10:50:51 PM UTC 24 |
9204735408 ps |
| T1941 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.3424752154 |
|
|
Sep 18 09:32:14 PM UTC 24 |
Sep 18 10:50:52 PM UTC 24 |
45015537185 ps |
| T1942 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.3068097194 |
|
|
Sep 18 10:48:26 PM UTC 24 |
Sep 18 10:50:58 PM UTC 24 |
9659192562 ps |
| T1943 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.4271079706 |
|
|
Sep 18 10:50:31 PM UTC 24 |
Sep 18 10:51:00 PM UTC 24 |
336526421 ps |
| T1944 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.375288379 |
|
|
Sep 18 10:50:20 PM UTC 24 |
Sep 18 10:51:10 PM UTC 24 |
735767355 ps |
| T1945 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.1413506517 |
|
|
Sep 18 10:49:03 PM UTC 24 |
Sep 18 10:51:11 PM UTC 24 |
6822885899 ps |
| T1946 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.3879726655 |
|
|
Sep 18 10:51:02 PM UTC 24 |
Sep 18 10:51:12 PM UTC 24 |
50684366 ps |
| T1947 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.1233552394 |
|
|
Sep 18 10:51:01 PM UTC 24 |
Sep 18 10:51:13 PM UTC 24 |
170257867 ps |
| T1948 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.2362200787 |
|
|
Sep 18 10:49:19 PM UTC 24 |
Sep 18 10:51:27 PM UTC 24 |
3822707714 ps |
| T1949 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.3882250882 |
|
|
Sep 18 10:49:58 PM UTC 24 |
Sep 18 10:51:35 PM UTC 24 |
4401000993 ps |
| T1950 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.2382712261 |
|
|
Sep 18 10:50:36 PM UTC 24 |
Sep 18 10:51:36 PM UTC 24 |
159018997 ps |
| T1951 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.397744760 |
|
|
Sep 18 10:50:00 PM UTC 24 |
Sep 18 10:51:38 PM UTC 24 |
8671463098 ps |
| T1952 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.3514031195 |
|
|
Sep 18 10:51:12 PM UTC 24 |
Sep 18 10:51:40 PM UTC 24 |
456769687 ps |
| T1953 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.2740992306 |
|
|
Sep 18 10:50:28 PM UTC 24 |
Sep 18 10:51:47 PM UTC 24 |
2362264486 ps |
| T1954 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.1555806058 |
|
|
Sep 18 10:51:28 PM UTC 24 |
Sep 18 10:51:47 PM UTC 24 |
490659376 ps |
| T1955 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.2606906721 |
|
|
Sep 18 10:51:38 PM UTC 24 |
Sep 18 10:51:54 PM UTC 24 |
260744682 ps |
| T1956 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.106970130 |
|
|
Sep 18 10:51:22 PM UTC 24 |
Sep 18 10:51:54 PM UTC 24 |
596127184 ps |
| T1957 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.1108380623 |
|
|
Sep 18 10:51:40 PM UTC 24 |
Sep 18 10:51:56 PM UTC 24 |
85172923 ps |
| T1958 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.1720126152 |
|
|
Sep 18 10:46:31 PM UTC 24 |
Sep 18 10:52:04 PM UTC 24 |
8396876027 ps |
| T1959 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.2772758667 |
|
|
Sep 18 10:51:16 PM UTC 24 |
Sep 18 10:52:05 PM UTC 24 |
483922374 ps |
| T1960 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.586619990 |
|
|
Sep 18 10:50:11 PM UTC 24 |
Sep 18 10:52:09 PM UTC 24 |
8000698247 ps |
| T1961 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.858373705 |
|
|
Sep 18 10:51:29 PM UTC 24 |
Sep 18 10:52:16 PM UTC 24 |
1317236324 ps |
| T1962 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.70144670 |
|
|
Sep 18 10:52:09 PM UTC 24 |
Sep 18 10:52:18 PM UTC 24 |
38104960 ps |
| T1963 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.309087311 |
|
|
Sep 18 10:52:08 PM UTC 24 |
Sep 18 10:52:19 PM UTC 24 |
238103619 ps |
| T1964 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.1505109145 |
|
|
Sep 18 10:41:03 PM UTC 24 |
Sep 18 10:52:24 PM UTC 24 |
50568150811 ps |
| T1965 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.3743129366 |
|
|
Sep 18 10:39:37 PM UTC 24 |
Sep 18 10:52:25 PM UTC 24 |
42879598535 ps |
| T1966 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.1945858824 |
|
|
Sep 18 10:51:39 PM UTC 24 |
Sep 18 10:52:31 PM UTC 24 |
212805624 ps |
| T1967 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.3850369540 |
|
|
Sep 18 10:51:10 PM UTC 24 |
Sep 18 10:52:34 PM UTC 24 |
5120551046 ps |
| T1968 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.1316996482 |
|
|
Sep 18 10:52:22 PM UTC 24 |
Sep 18 10:52:35 PM UTC 24 |
66277661 ps |
| T1969 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.861186959 |
|
|
Sep 18 10:51:10 PM UTC 24 |
Sep 18 10:52:41 PM UTC 24 |
7213749063 ps |
| T1970 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.2456571917 |
|
|
Sep 18 10:52:45 PM UTC 24 |
Sep 18 10:52:59 PM UTC 24 |
280784420 ps |
| T1971 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.3126149006 |
|
|
Sep 18 10:48:25 PM UTC 24 |
Sep 18 10:53:00 PM UTC 24 |
29926817420 ps |
| T1972 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.2306360925 |
|
|
Sep 18 10:52:56 PM UTC 24 |
Sep 18 10:53:05 PM UTC 24 |
7607031 ps |
| T1973 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.1757556943 |
|
|
Sep 18 10:52:19 PM UTC 24 |
Sep 18 10:53:10 PM UTC 24 |
461502952 ps |
| T1974 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.4048296818 |
|
|
Sep 18 10:47:42 PM UTC 24 |
Sep 18 10:53:13 PM UTC 24 |
8680402910 ps |
| T1975 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.1137796521 |
|
|
Sep 18 10:50:48 PM UTC 24 |
Sep 18 10:53:15 PM UTC 24 |
4582246859 ps |
| T1976 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.894706853 |
|
|
Sep 18 10:52:45 PM UTC 24 |
Sep 18 10:53:18 PM UTC 24 |
230319369 ps |
| T1977 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.411919483 |
|
|
Sep 18 10:52:33 PM UTC 24 |
Sep 18 10:53:20 PM UTC 24 |
1168375870 ps |
| T1978 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.1260588814 |
|
|
Sep 18 10:52:41 PM UTC 24 |
Sep 18 10:53:20 PM UTC 24 |
1198500523 ps |
| T1979 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.3465393612 |
|
|
Sep 18 10:50:33 PM UTC 24 |
Sep 18 10:53:21 PM UTC 24 |
3409428181 ps |
| T1980 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.3655839961 |
|
|
Sep 18 10:53:07 PM UTC 24 |
Sep 18 10:53:21 PM UTC 24 |
219722883 ps |
| T1981 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.2435018006 |
|
|
Sep 18 10:53:12 PM UTC 24 |
Sep 18 10:53:22 PM UTC 24 |
56049787 ps |
| T1982 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.3050731053 |
|
|
Sep 18 10:51:41 PM UTC 24 |
Sep 18 10:53:27 PM UTC 24 |
2708379037 ps |
| T1983 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.647005922 |
|
|
Sep 18 10:53:02 PM UTC 24 |
Sep 18 10:53:37 PM UTC 24 |
265074312 ps |
| T1984 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.1238424114 |
|
|
Sep 18 10:52:16 PM UTC 24 |
Sep 18 10:53:44 PM UTC 24 |
5591133562 ps |
| T1985 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.705159355 |
|
|
Sep 18 10:46:30 PM UTC 24 |
Sep 18 10:53:45 PM UTC 24 |
12523018946 ps |
| T1986 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.336016021 |
|
|
Sep 18 10:33:00 PM UTC 24 |
Sep 18 10:53:49 PM UTC 24 |
84877022159 ps |
| T1987 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.3789747427 |
|
|
Sep 18 10:52:43 PM UTC 24 |
Sep 18 10:53:50 PM UTC 24 |
1444608080 ps |
| T1988 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.496174667 |
|
|
Sep 18 10:52:11 PM UTC 24 |
Sep 18 10:53:51 PM UTC 24 |
8039752278 ps |
| T1989 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.2826545400 |
|
|
Sep 18 09:28:01 PM UTC 24 |
Sep 18 10:53:53 PM UTC 24 |
29400596512 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.4032660354 |
|
|
Sep 18 10:38:04 PM UTC 24 |
Sep 18 10:53:54 PM UTC 24 |
64811716255 ps |
| T1990 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.3417462596 |
|
|
Sep 18 10:53:35 PM UTC 24 |
Sep 18 10:53:58 PM UTC 24 |
152658031 ps |
| T1991 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.3862740152 |
|
|
Sep 18 10:45:22 PM UTC 24 |
Sep 18 10:53:58 PM UTC 24 |
34733051917 ps |
| T1992 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.3685569440 |
|
|
Sep 18 10:53:50 PM UTC 24 |
Sep 18 10:54:01 PM UTC 24 |
209808228 ps |
| T1993 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.3888657949 |
|
|
Sep 18 10:53:32 PM UTC 24 |
Sep 18 10:54:10 PM UTC 24 |
402296506 ps |
| T1994 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.3257939305 |
|
|
Sep 18 10:53:49 PM UTC 24 |
Sep 18 10:54:17 PM UTC 24 |
176848601 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.3950547515 |
|
|
Sep 18 10:43:28 PM UTC 24 |
Sep 18 10:54:19 PM UTC 24 |
14740927982 ps |
| T1995 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.734709429 |
|
|
Sep 18 10:54:12 PM UTC 24 |
Sep 18 10:54:22 PM UTC 24 |
217798806 ps |
| T1996 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.2294945598 |
|
|
Sep 18 10:54:16 PM UTC 24 |
Sep 18 10:54:25 PM UTC 24 |
54834069 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.3388443820 |
|
|
Sep 18 10:53:47 PM UTC 24 |
Sep 18 10:54:29 PM UTC 24 |
542844856 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.1259317750 |
|
|
Sep 18 10:49:47 PM UTC 24 |
Sep 18 10:54:29 PM UTC 24 |
5385729639 ps |
| T1997 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.4021014236 |
|
|
Sep 18 10:53:47 PM UTC 24 |
Sep 18 10:54:38 PM UTC 24 |
1107570993 ps |
| T1998 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.1111413118 |
|
|
Sep 18 10:54:21 PM UTC 24 |
Sep 18 10:54:47 PM UTC 24 |
505852946 ps |
| T1999 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.2228035259 |
|
|
Sep 18 10:53:29 PM UTC 24 |
Sep 18 10:54:48 PM UTC 24 |
7584025001 ps |
| T2000 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.678172105 |
|
|
Sep 18 10:54:38 PM UTC 24 |
Sep 18 10:54:48 PM UTC 24 |
110641432 ps |
| T2001 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.160693671 |
|
|
Sep 18 10:48:32 PM UTC 24 |
Sep 18 10:54:51 PM UTC 24 |
26693692763 ps |
| T2002 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.3422483655 |
|
|
Sep 18 09:27:57 PM UTC 24 |
Sep 18 10:54:55 PM UTC 24 |
38401766787 ps |
| T2003 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.3163043410 |
|
|
Sep 18 10:31:32 PM UTC 24 |
Sep 18 10:54:55 PM UTC 24 |
90839856326 ps |
| T2004 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.177518604 |
|
|
Sep 18 10:54:21 PM UTC 24 |
Sep 18 10:54:57 PM UTC 24 |
292139285 ps |
| T2005 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.475313107 |
|
|
Sep 18 10:53:46 PM UTC 24 |
Sep 18 10:55:07 PM UTC 24 |
5334327499 ps |
| T2006 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.190257231 |
|
|
Sep 18 10:54:28 PM UTC 24 |
Sep 18 10:55:09 PM UTC 24 |
3179102297 ps |
| T2007 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.642402704 |
|
|
Sep 18 10:53:31 PM UTC 24 |
Sep 18 10:55:14 PM UTC 24 |
5109513338 ps |
| T2008 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.588490368 |
|
|
Sep 18 10:54:44 PM UTC 24 |
Sep 18 10:55:15 PM UTC 24 |
1110973445 ps |
| T2009 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.2231157813 |
|
|
Sep 18 10:54:48 PM UTC 24 |
Sep 18 10:55:15 PM UTC 24 |
353828498 ps |
| T2010 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.3374720167 |
|
|
Sep 18 10:54:58 PM UTC 24 |
Sep 18 10:55:19 PM UTC 24 |
125757587 ps |
| T2011 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.3356488002 |
|
|
Sep 18 10:53:47 PM UTC 24 |
Sep 18 10:55:22 PM UTC 24 |
1062547076 ps |
| T2012 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.3651328293 |
|
|
Sep 18 10:55:15 PM UTC 24 |
Sep 18 10:55:23 PM UTC 24 |
44546061 ps |
| T2013 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.998146628 |
|
|
Sep 18 10:54:55 PM UTC 24 |
Sep 18 10:55:27 PM UTC 24 |
321371836 ps |
| T2014 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.2723871290 |
|
|
Sep 18 10:55:18 PM UTC 24 |
Sep 18 10:55:27 PM UTC 24 |
170041551 ps |
| T2015 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.3486797911 |
|
|
Sep 18 10:51:15 PM UTC 24 |
Sep 18 10:55:34 PM UTC 24 |
25328969783 ps |
| T2016 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.3085920850 |
|
|
Sep 18 10:54:50 PM UTC 24 |
Sep 18 10:55:38 PM UTC 24 |
1088937317 ps |
| T2017 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.127001876 |
|
|
Sep 18 10:43:24 PM UTC 24 |
Sep 18 10:55:50 PM UTC 24 |
4553757775 ps |
| T2018 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.1879977750 |
|
|
Sep 18 10:55:48 PM UTC 24 |
Sep 18 10:55:58 PM UTC 24 |
37303325 ps |
| T2019 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.1948730460 |
|
|
Sep 18 10:55:21 PM UTC 24 |
Sep 18 10:55:59 PM UTC 24 |
508161808 ps |
| T2020 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.1586125155 |
|
|
Sep 18 10:54:21 PM UTC 24 |
Sep 18 10:56:02 PM UTC 24 |
9254013691 ps |
| T2021 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.2010029139 |
|
|
Sep 18 10:48:50 PM UTC 24 |
Sep 18 10:56:02 PM UTC 24 |
9435093892 ps |
| T2022 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.1676139620 |
|
|
Sep 18 10:49:07 PM UTC 24 |
Sep 18 10:56:02 PM UTC 24 |
43646170265 ps |
| T2023 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.1752359587 |
|
|
Sep 18 10:55:48 PM UTC 24 |
Sep 18 10:56:05 PM UTC 24 |
192767833 ps |