| T1420 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.2079745068 |
|
|
Sep 18 09:51:17 PM UTC 24 |
Sep 18 09:52:12 PM UTC 24 |
1265916967 ps |
| T1421 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.101978626 |
|
|
Sep 18 09:51:42 PM UTC 24 |
Sep 18 09:52:16 PM UTC 24 |
1029181364 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.588318207 |
|
|
Sep 18 09:51:20 PM UTC 24 |
Sep 18 09:52:22 PM UTC 24 |
574887277 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.2843992436 |
|
|
Sep 18 09:49:11 PM UTC 24 |
Sep 18 09:52:22 PM UTC 24 |
3704347267 ps |
| T1422 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.1412685343 |
|
|
Sep 18 09:51:53 PM UTC 24 |
Sep 18 09:52:32 PM UTC 24 |
404884885 ps |
| T1423 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.1966759494 |
|
|
Sep 18 09:52:00 PM UTC 24 |
Sep 18 09:52:32 PM UTC 24 |
529118827 ps |
| T1424 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2429404969 |
|
|
Sep 18 09:51:14 PM UTC 24 |
Sep 18 09:52:38 PM UTC 24 |
4032475939 ps |
| T1425 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.3024536433 |
|
|
Sep 18 09:51:09 PM UTC 24 |
Sep 18 09:52:46 PM UTC 24 |
7986986474 ps |
| T1426 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.72002778 |
|
|
Sep 18 09:50:02 PM UTC 24 |
Sep 18 09:52:47 PM UTC 24 |
1583026889 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.3896218187 |
|
|
Sep 18 09:45:52 PM UTC 24 |
Sep 18 09:52:48 PM UTC 24 |
5585512168 ps |
| T1427 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1411672913 |
|
|
Sep 18 09:52:24 PM UTC 24 |
Sep 18 09:52:50 PM UTC 24 |
681492589 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.2444284240 |
|
|
Sep 18 09:28:03 PM UTC 24 |
Sep 18 09:53:03 PM UTC 24 |
15825035796 ps |
| T1428 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.2916093529 |
|
|
Sep 18 09:53:07 PM UTC 24 |
Sep 18 09:53:15 PM UTC 24 |
52240861 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.4250979647 |
|
|
Sep 18 09:36:41 PM UTC 24 |
Sep 18 09:53:15 PM UTC 24 |
111091685314 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3589981599 |
|
|
Sep 18 09:53:13 PM UTC 24 |
Sep 18 09:53:20 PM UTC 24 |
52874698 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2334343914 |
|
|
Sep 18 09:49:43 PM UTC 24 |
Sep 18 09:53:29 PM UTC 24 |
490301443 ps |
| T1429 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.3379714252 |
|
|
Sep 18 09:51:56 PM UTC 24 |
Sep 18 09:53:35 PM UTC 24 |
2157684182 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.2638127842 |
|
|
Sep 18 09:48:23 PM UTC 24 |
Sep 18 09:53:38 PM UTC 24 |
7660318819 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.3487232797 |
|
|
Sep 18 09:48:09 PM UTC 24 |
Sep 18 09:53:40 PM UTC 24 |
7893279599 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.1521886027 |
|
|
Sep 18 09:40:11 PM UTC 24 |
Sep 18 09:53:40 PM UTC 24 |
10943638288 ps |
| T1430 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.485014937 |
|
|
Sep 18 09:50:08 PM UTC 24 |
Sep 18 09:53:48 PM UTC 24 |
2108281965 ps |
| T1431 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.3368423603 |
|
|
Sep 18 09:53:31 PM UTC 24 |
Sep 18 09:53:53 PM UTC 24 |
176633194 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1259715177 |
|
|
Sep 18 09:48:27 PM UTC 24 |
Sep 18 09:53:59 PM UTC 24 |
8614537143 ps |
| T1432 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.1786622810 |
|
|
Sep 18 09:53:21 PM UTC 24 |
Sep 18 09:54:02 PM UTC 24 |
325282714 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.3861412633 |
|
|
Sep 18 09:53:47 PM UTC 24 |
Sep 18 09:54:12 PM UTC 24 |
294970603 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.560058383 |
|
|
Sep 18 09:52:32 PM UTC 24 |
Sep 18 09:54:12 PM UTC 24 |
2603722965 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.384196617 |
|
|
Sep 18 09:48:37 PM UTC 24 |
Sep 18 09:54:21 PM UTC 24 |
4431706104 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.3249406847 |
|
|
Sep 18 09:50:52 PM UTC 24 |
Sep 18 09:54:27 PM UTC 24 |
3396379738 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.2357255542 |
|
|
Sep 18 09:54:08 PM UTC 24 |
Sep 18 09:54:34 PM UTC 24 |
157001452 ps |
| T1433 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.4178106197 |
|
|
Sep 18 09:53:16 PM UTC 24 |
Sep 18 09:54:36 PM UTC 24 |
4818454804 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.1600458003 |
|
|
Sep 18 09:54:14 PM UTC 24 |
Sep 18 09:54:58 PM UTC 24 |
1128942312 ps |
| T1434 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3878057062 |
|
|
Sep 18 09:54:11 PM UTC 24 |
Sep 18 09:55:01 PM UTC 24 |
920824147 ps |
| T1435 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.987895920 |
|
|
Sep 18 09:53:13 PM UTC 24 |
Sep 18 09:55:08 PM UTC 24 |
10745539031 ps |
| T1436 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.2329805099 |
|
|
Sep 18 09:55:06 PM UTC 24 |
Sep 18 09:55:16 PM UTC 24 |
53140502 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.3870856313 |
|
|
Sep 18 09:55:04 PM UTC 24 |
Sep 18 09:55:17 PM UTC 24 |
187839723 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.3578943087 |
|
|
Sep 18 09:43:32 PM UTC 24 |
Sep 18 09:55:22 PM UTC 24 |
5614178432 ps |
| T1437 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.2008449076 |
|
|
Sep 18 09:54:04 PM UTC 24 |
Sep 18 09:55:24 PM UTC 24 |
2548853327 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.338011067 |
|
|
Sep 18 09:41:00 PM UTC 24 |
Sep 18 09:55:25 PM UTC 24 |
81937024357 ps |
| T1438 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.1908832603 |
|
|
Sep 18 09:54:09 PM UTC 24 |
Sep 18 09:55:42 PM UTC 24 |
2157613824 ps |
| T1439 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.991323370 |
|
|
Sep 18 09:55:38 PM UTC 24 |
Sep 18 09:55:46 PM UTC 24 |
154154611 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.2713912906 |
|
|
Sep 18 09:49:09 PM UTC 24 |
Sep 18 09:55:58 PM UTC 24 |
22199389748 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3246558513 |
|
|
Sep 18 09:52:45 PM UTC 24 |
Sep 18 09:55:59 PM UTC 24 |
460861265 ps |
| T1440 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.1991544286 |
|
|
Sep 18 09:50:15 PM UTC 24 |
Sep 18 09:56:07 PM UTC 24 |
4429139715 ps |
| T1441 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.2947304127 |
|
|
Sep 18 09:40:59 PM UTC 24 |
Sep 18 09:56:15 PM UTC 24 |
62229985358 ps |
| T1442 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.204394648 |
|
|
Sep 18 09:55:43 PM UTC 24 |
Sep 18 09:56:18 PM UTC 24 |
354211533 ps |
| T1443 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.4217362306 |
|
|
Sep 18 09:56:29 PM UTC 24 |
Sep 18 09:56:38 PM UTC 24 |
56959077 ps |
| T1444 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.3148149238 |
|
|
Sep 18 09:56:13 PM UTC 24 |
Sep 18 09:56:49 PM UTC 24 |
759593096 ps |
| T1445 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.3756719549 |
|
|
Sep 18 09:53:45 PM UTC 24 |
Sep 18 09:56:50 PM UTC 24 |
11963990892 ps |
| T1446 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.1102226099 |
|
|
Sep 18 09:56:16 PM UTC 24 |
Sep 18 09:56:50 PM UTC 24 |
643751024 ps |
| T1447 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.2702462961 |
|
|
Sep 18 09:48:31 PM UTC 24 |
Sep 18 09:56:52 PM UTC 24 |
5188267768 ps |
| T1448 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.2567142758 |
|
|
Sep 18 09:56:28 PM UTC 24 |
Sep 18 09:56:57 PM UTC 24 |
506794357 ps |
| T1449 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.2791405847 |
|
|
Sep 18 09:55:31 PM UTC 24 |
Sep 18 09:57:02 PM UTC 24 |
8881972543 ps |
| T1450 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.3504368322 |
|
|
Sep 18 09:56:50 PM UTC 24 |
Sep 18 09:57:03 PM UTC 24 |
52117954 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.1238325661 |
|
|
Sep 18 09:55:56 PM UTC 24 |
Sep 18 09:57:04 PM UTC 24 |
1175911113 ps |
| T1451 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.2819941102 |
|
|
Sep 18 09:54:28 PM UTC 24 |
Sep 18 09:57:12 PM UTC 24 |
3970717168 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.1715447953 |
|
|
Sep 18 09:52:59 PM UTC 24 |
Sep 18 09:57:23 PM UTC 24 |
3511362255 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.1263588825 |
|
|
Sep 18 09:52:42 PM UTC 24 |
Sep 18 09:57:31 PM UTC 24 |
8630410862 ps |
| T1452 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.4173011797 |
|
|
Sep 18 09:57:26 PM UTC 24 |
Sep 18 09:57:36 PM UTC 24 |
45483015 ps |
| T1453 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.1471247011 |
|
|
Sep 18 09:48:33 PM UTC 24 |
Sep 18 09:57:36 PM UTC 24 |
5529709335 ps |
| T1454 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.4047707995 |
|
|
Sep 18 09:57:32 PM UTC 24 |
Sep 18 09:57:43 PM UTC 24 |
48864771 ps |
| T1455 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.497542041 |
|
|
Sep 18 09:49:04 PM UTC 24 |
Sep 18 09:58:02 PM UTC 24 |
52333578319 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.1101804129 |
|
|
Sep 18 09:57:43 PM UTC 24 |
Sep 18 09:58:02 PM UTC 24 |
128417153 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1935834652 |
|
|
Sep 18 09:54:31 PM UTC 24 |
Sep 18 09:58:11 PM UTC 24 |
914053199 ps |
| T1456 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2727703606 |
|
|
Sep 18 09:55:29 PM UTC 24 |
Sep 18 09:58:18 PM UTC 24 |
6603057293 ps |
| T1457 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.62912023 |
|
|
Sep 18 09:56:46 PM UTC 24 |
Sep 18 09:58:34 PM UTC 24 |
309323865 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.3303990778 |
|
|
Sep 18 09:42:45 PM UTC 24 |
Sep 18 09:58:34 PM UTC 24 |
59118348249 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.4020228186 |
|
|
Sep 18 09:54:56 PM UTC 24 |
Sep 18 09:58:42 PM UTC 24 |
3614337296 ps |
| T1458 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.3684806410 |
|
|
Sep 18 09:57:53 PM UTC 24 |
Sep 18 09:58:43 PM UTC 24 |
410766925 ps |
| T1459 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.4245818520 |
|
|
Sep 18 09:57:34 PM UTC 24 |
Sep 18 09:58:57 PM UTC 24 |
5645409712 ps |
| T1460 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.29809922 |
|
|
Sep 18 09:46:49 PM UTC 24 |
Sep 18 09:59:04 PM UTC 24 |
48251208322 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.492188060 |
|
|
Sep 18 09:56:37 PM UTC 24 |
Sep 18 09:59:13 PM UTC 24 |
1702537210 ps |
| T1461 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.1204453024 |
|
|
Sep 18 09:58:42 PM UTC 24 |
Sep 18 09:59:14 PM UTC 24 |
456775391 ps |
| T1462 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.1344078538 |
|
|
Sep 18 09:58:33 PM UTC 24 |
Sep 18 09:59:23 PM UTC 24 |
972254879 ps |
| T1463 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.3996669380 |
|
|
Sep 18 09:57:30 PM UTC 24 |
Sep 18 09:59:41 PM UTC 24 |
8657991864 ps |
| T1464 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.322962083 |
|
|
Sep 18 09:57:23 PM UTC 24 |
Sep 18 09:59:44 PM UTC 24 |
2816737588 ps |
| T1465 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.3017649276 |
|
|
Sep 18 09:58:48 PM UTC 24 |
Sep 18 09:59:47 PM UTC 24 |
976928689 ps |
| T1466 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.2407579383 |
|
|
Sep 18 09:59:50 PM UTC 24 |
Sep 18 10:00:00 PM UTC 24 |
40236005 ps |
| T1467 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.3713841229 |
|
|
Sep 18 09:58:32 PM UTC 24 |
Sep 18 10:00:10 PM UTC 24 |
2161797570 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.1012150252 |
|
|
Sep 18 09:58:07 PM UTC 24 |
Sep 18 10:00:14 PM UTC 24 |
3035279007 ps |
| T1468 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.3667688594 |
|
|
Sep 18 10:00:11 PM UTC 24 |
Sep 18 10:00:22 PM UTC 24 |
41029301 ps |
| T1469 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.1887391875 |
|
|
Sep 18 10:00:40 PM UTC 24 |
Sep 18 10:00:58 PM UTC 24 |
102581160 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.921513210 |
|
|
Sep 18 10:00:31 PM UTC 24 |
Sep 18 10:01:17 PM UTC 24 |
965734281 ps |
| T1470 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.2699858694 |
|
|
Sep 18 10:00:18 PM UTC 24 |
Sep 18 10:01:25 PM UTC 24 |
4674290210 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3901910237 |
|
|
Sep 18 09:57:07 PM UTC 24 |
Sep 18 10:01:58 PM UTC 24 |
7331991726 ps |
| T1471 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.723270364 |
|
|
Sep 18 09:59:05 PM UTC 24 |
Sep 18 10:02:13 PM UTC 24 |
2117184148 ps |
| T1472 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.4193278087 |
|
|
Sep 18 10:01:56 PM UTC 24 |
Sep 18 10:02:15 PM UTC 24 |
135907258 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.3174937148 |
|
|
Sep 18 09:57:19 PM UTC 24 |
Sep 18 10:02:30 PM UTC 24 |
4186113332 ps |
| T1473 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.1127418081 |
|
|
Sep 18 09:55:48 PM UTC 24 |
Sep 18 10:02:40 PM UTC 24 |
41017445784 ps |
| T1474 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.160177271 |
|
|
Sep 18 10:02:29 PM UTC 24 |
Sep 18 10:02:41 PM UTC 24 |
153688789 ps |
| T1475 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.3150032634 |
|
|
Sep 18 10:00:15 PM UTC 24 |
Sep 18 10:02:43 PM UTC 24 |
8840921206 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.33200474 |
|
|
Sep 18 09:47:16 PM UTC 24 |
Sep 18 10:02:46 PM UTC 24 |
53977585559 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.2604190664 |
|
|
Sep 18 10:01:28 PM UTC 24 |
Sep 18 10:02:49 PM UTC 24 |
668899194 ps |
| T1476 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.3201409620 |
|
|
Sep 18 09:55:51 PM UTC 24 |
Sep 18 10:02:49 PM UTC 24 |
26702150546 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3454523753 |
|
|
Sep 18 09:54:01 PM UTC 24 |
Sep 18 10:02:57 PM UTC 24 |
37367427245 ps |
| T1477 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.3867961822 |
|
|
Sep 18 10:02:47 PM UTC 24 |
Sep 18 10:03:04 PM UTC 24 |
322887457 ps |
| T1478 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.797768013 |
|
|
Sep 18 10:02:43 PM UTC 24 |
Sep 18 10:03:30 PM UTC 24 |
926960351 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.395726321 |
|
|
Sep 18 09:30:26 PM UTC 24 |
Sep 18 10:03:32 PM UTC 24 |
18213549924 ps |
| T1479 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.3680221229 |
|
|
Sep 18 10:03:33 PM UTC 24 |
Sep 18 10:03:46 PM UTC 24 |
209495129 ps |
| T1480 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.2642989339 |
|
|
Sep 18 10:04:02 PM UTC 24 |
Sep 18 10:04:12 PM UTC 24 |
42828207 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.2931542615 |
|
|
Sep 18 09:59:43 PM UTC 24 |
Sep 18 10:04:19 PM UTC 24 |
3965688820 ps |
| T1481 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.4131132055 |
|
|
Sep 18 09:59:14 PM UTC 24 |
Sep 18 10:04:28 PM UTC 24 |
3138012356 ps |
| T1482 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.3771306908 |
|
|
Sep 18 09:52:49 PM UTC 24 |
Sep 18 10:04:40 PM UTC 24 |
5744406040 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.3550060881 |
|
|
Sep 18 10:03:10 PM UTC 24 |
Sep 18 10:05:04 PM UTC 24 |
262280994 ps |
| T1483 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.3889352769 |
|
|
Sep 18 09:54:41 PM UTC 24 |
Sep 18 10:05:07 PM UTC 24 |
5893043095 ps |
| T1484 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.2821476627 |
|
|
Sep 18 09:52:49 PM UTC 24 |
Sep 18 10:05:35 PM UTC 24 |
10669031946 ps |
| T1485 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.258230020 |
|
|
Sep 18 10:05:36 PM UTC 24 |
Sep 18 10:05:47 PM UTC 24 |
71168714 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.3677671653 |
|
|
Sep 18 09:53:46 PM UTC 24 |
Sep 18 10:05:48 PM UTC 24 |
72647929445 ps |
| T1486 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.4136087462 |
|
|
Sep 18 09:50:20 PM UTC 24 |
Sep 18 10:05:56 PM UTC 24 |
9590059210 ps |
| T1487 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.3376872484 |
|
|
Sep 18 10:04:04 PM UTC 24 |
Sep 18 10:06:02 PM UTC 24 |
7089652974 ps |
| T1488 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.142873500 |
|
|
Sep 18 10:04:50 PM UTC 24 |
Sep 18 10:06:05 PM UTC 24 |
598368224 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2186386387 |
|
|
Sep 18 09:49:17 PM UTC 24 |
Sep 18 10:06:06 PM UTC 24 |
69604223734 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.2583462940 |
|
|
Sep 18 09:27:57 PM UTC 24 |
Sep 18 10:06:08 PM UTC 24 |
16260318416 ps |
| T1489 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.3828194674 |
|
|
Sep 18 10:04:17 PM UTC 24 |
Sep 18 10:06:18 PM UTC 24 |
5028537658 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.1157966798 |
|
|
Sep 18 09:59:04 PM UTC 24 |
Sep 18 10:06:25 PM UTC 24 |
10098754841 ps |
| T1490 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.888825837 |
|
|
Sep 18 10:06:04 PM UTC 24 |
Sep 18 10:06:31 PM UTC 24 |
511278002 ps |
| T1491 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.273973261 |
|
|
Sep 18 10:06:21 PM UTC 24 |
Sep 18 10:06:34 PM UTC 24 |
80383110 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.2444174830 |
|
|
Sep 18 09:41:10 PM UTC 24 |
Sep 18 10:06:36 PM UTC 24 |
79278093570 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.192987933 |
|
|
Sep 18 09:51:42 PM UTC 24 |
Sep 18 10:06:41 PM UTC 24 |
58317398775 ps |
| T1492 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.2928604961 |
|
|
Sep 18 10:04:42 PM UTC 24 |
Sep 18 10:06:47 PM UTC 24 |
2712016113 ps |
| T1493 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.513947692 |
|
|
Sep 18 10:06:15 PM UTC 24 |
Sep 18 10:06:59 PM UTC 24 |
550986664 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.3258664562 |
|
|
Sep 18 10:03:25 PM UTC 24 |
Sep 18 10:07:07 PM UTC 24 |
2960699735 ps |
| T1494 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.3374542900 |
|
|
Sep 18 10:07:06 PM UTC 24 |
Sep 18 10:07:16 PM UTC 24 |
52220663 ps |
| T1495 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.4273416299 |
|
|
Sep 18 10:07:10 PM UTC 24 |
Sep 18 10:07:19 PM UTC 24 |
38353733 ps |
| T1496 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.317081201 |
|
|
Sep 18 10:00:44 PM UTC 24 |
Sep 18 10:07:20 PM UTC 24 |
43700036337 ps |
| T1497 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.231558452 |
|
|
Sep 18 10:06:17 PM UTC 24 |
Sep 18 10:07:32 PM UTC 24 |
1146431930 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.3735712379 |
|
|
Sep 18 10:03:01 PM UTC 24 |
Sep 18 10:07:35 PM UTC 24 |
3263123075 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1052586214 |
|
|
Sep 18 09:59:12 PM UTC 24 |
Sep 18 10:07:46 PM UTC 24 |
4133628382 ps |
| T1498 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.500693993 |
|
|
Sep 18 10:03:07 PM UTC 24 |
Sep 18 10:08:03 PM UTC 24 |
1892028698 ps |
| T1499 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.3650345542 |
|
|
Sep 18 09:58:07 PM UTC 24 |
Sep 18 10:08:11 PM UTC 24 |
36154414719 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.630799109 |
|
|
Sep 18 09:52:43 PM UTC 24 |
Sep 18 10:08:22 PM UTC 24 |
8898401080 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.2732575310 |
|
|
Sep 18 09:37:33 PM UTC 24 |
Sep 18 10:08:28 PM UTC 24 |
112294834872 ps |
| T1500 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.820927165 |
|
|
Sep 18 10:07:28 PM UTC 24 |
Sep 18 10:08:34 PM UTC 24 |
5124086036 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.2115568449 |
|
|
Sep 18 10:07:46 PM UTC 24 |
Sep 18 10:08:36 PM UTC 24 |
525286389 ps |
| T1501 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.3589451450 |
|
|
Sep 18 10:03:17 PM UTC 24 |
Sep 18 10:08:55 PM UTC 24 |
4457993843 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.2222380657 |
|
|
Sep 18 09:35:14 PM UTC 24 |
Sep 18 10:08:57 PM UTC 24 |
15209142210 ps |
| T1502 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.1644519848 |
|
|
Sep 18 10:08:31 PM UTC 24 |
Sep 18 10:09:13 PM UTC 24 |
806375403 ps |
| T1503 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.1865038477 |
|
|
Sep 18 10:07:41 PM UTC 24 |
Sep 18 10:09:13 PM UTC 24 |
8470787156 ps |
| T1504 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.1035632458 |
|
|
Sep 18 09:51:22 PM UTC 24 |
Sep 18 10:09:24 PM UTC 24 |
115685990188 ps |
| T1505 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.306274805 |
|
|
Sep 18 10:08:52 PM UTC 24 |
Sep 18 10:09:25 PM UTC 24 |
301445173 ps |
| T1506 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.1575318930 |
|
|
Sep 18 10:07:37 PM UTC 24 |
Sep 18 10:09:28 PM UTC 24 |
2297392962 ps |
| T1507 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.4197664428 |
|
|
Sep 18 10:08:16 PM UTC 24 |
Sep 18 10:09:28 PM UTC 24 |
1719676205 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.4274306586 |
|
|
Sep 18 10:01:47 PM UTC 24 |
Sep 18 10:09:35 PM UTC 24 |
27995220099 ps |
| T1508 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.480593984 |
|
|
Sep 18 10:07:17 PM UTC 24 |
Sep 18 10:09:36 PM UTC 24 |
9533857464 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.3579888319 |
|
|
Sep 18 10:08:38 PM UTC 24 |
Sep 18 10:09:38 PM UTC 24 |
1268083391 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.2725321235 |
|
|
Sep 18 10:03:10 PM UTC 24 |
Sep 18 10:09:50 PM UTC 24 |
4472368140 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.3139697843 |
|
|
Sep 18 10:08:02 PM UTC 24 |
Sep 18 10:09:54 PM UTC 24 |
1993350716 ps |
| T1509 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.3468863581 |
|
|
Sep 18 10:09:54 PM UTC 24 |
Sep 18 10:10:04 PM UTC 24 |
43674969 ps |
| T1510 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.3636398893 |
|
|
Sep 18 09:57:20 PM UTC 24 |
Sep 18 10:10:05 PM UTC 24 |
11821154570 ps |
| T1511 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.1564979034 |
|
|
Sep 18 10:09:56 PM UTC 24 |
Sep 18 10:10:07 PM UTC 24 |
47293516 ps |
| T1512 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.1499495065 |
|
|
Sep 18 10:06:36 PM UTC 24 |
Sep 18 10:10:07 PM UTC 24 |
2871301396 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2456113845 |
|
|
Sep 18 09:51:48 PM UTC 24 |
Sep 18 10:10:09 PM UTC 24 |
73651544707 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.2644934452 |
|
|
Sep 18 10:05:39 PM UTC 24 |
Sep 18 10:10:16 PM UTC 24 |
12000828703 ps |
| T1513 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.3133230751 |
|
|
Sep 18 09:54:40 PM UTC 24 |
Sep 18 10:10:18 PM UTC 24 |
11442881473 ps |
| T1514 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.429278732 |
|
|
Sep 18 10:03:17 PM UTC 24 |
Sep 18 10:10:27 PM UTC 24 |
6314864900 ps |
| T1515 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.1082113491 |
|
|
Sep 18 10:10:05 PM UTC 24 |
Sep 18 10:10:32 PM UTC 24 |
235247270 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.849434435 |
|
|
Sep 18 10:06:36 PM UTC 24 |
Sep 18 10:10:34 PM UTC 24 |
700180526 ps |
| T1516 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.1684868518 |
|
|
Sep 18 10:10:00 PM UTC 24 |
Sep 18 10:10:39 PM UTC 24 |
355552587 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.1723514022 |
|
|
Sep 18 10:07:05 PM UTC 24 |
Sep 18 10:10:59 PM UTC 24 |
3272644272 ps |
| T1517 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.2389152164 |
|
|
Sep 18 10:10:32 PM UTC 24 |
Sep 18 10:11:07 PM UTC 24 |
852049763 ps |
| T1518 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.39208564 |
|
|
Sep 18 10:10:05 PM UTC 24 |
Sep 18 10:11:10 PM UTC 24 |
4211130119 ps |
| T1519 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.234786995 |
|
|
Sep 18 10:10:33 PM UTC 24 |
Sep 18 10:11:17 PM UTC 24 |
1074012976 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.1658799683 |
|
|
Sep 18 10:11:01 PM UTC 24 |
Sep 18 10:11:18 PM UTC 24 |
261736844 ps |
| T1520 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.2452108840 |
|
|
Sep 18 10:09:54 PM UTC 24 |
Sep 18 10:11:21 PM UTC 24 |
8903803962 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.2572877419 |
|
|
Sep 18 10:10:38 PM UTC 24 |
Sep 18 10:11:30 PM UTC 24 |
821668744 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.1045663226 |
|
|
Sep 18 09:42:57 PM UTC 24 |
Sep 18 10:11:28 PM UTC 24 |
111230732951 ps |
| T1521 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.527785070 |
|
|
Sep 18 10:10:34 PM UTC 24 |
Sep 18 10:11:40 PM UTC 24 |
603851483 ps |
| T1522 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.2104175879 |
|
|
Sep 18 10:10:43 PM UTC 24 |
Sep 18 10:11:42 PM UTC 24 |
1348954108 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.2353161152 |
|
|
Sep 18 09:40:10 PM UTC 24 |
Sep 18 10:11:46 PM UTC 24 |
15484799747 ps |
| T1523 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.2988602725 |
|
|
Sep 18 10:11:39 PM UTC 24 |
Sep 18 10:11:50 PM UTC 24 |
52647273 ps |
| T1524 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.253297661 |
|
|
Sep 18 10:11:46 PM UTC 24 |
Sep 18 10:11:56 PM UTC 24 |
46321265 ps |
| T1525 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.164700242 |
|
|
Sep 18 09:59:28 PM UTC 24 |
Sep 18 10:12:03 PM UTC 24 |
5652795415 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.3367448600 |
|
|
Sep 18 09:42:09 PM UTC 24 |
Sep 18 10:12:17 PM UTC 24 |
15214018306 ps |
| T1526 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.3791815594 |
|
|
Sep 18 10:12:00 PM UTC 24 |
Sep 18 10:12:20 PM UTC 24 |
117731294 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.1124174524 |
|
|
Sep 18 09:38:23 PM UTC 24 |
Sep 18 10:12:20 PM UTC 24 |
15916574935 ps |
| T1527 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.1728894435 |
|
|
Sep 18 10:11:58 PM UTC 24 |
Sep 18 10:12:30 PM UTC 24 |
771044844 ps |
| T1528 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.1803129302 |
|
|
Sep 18 10:09:06 PM UTC 24 |
Sep 18 10:12:45 PM UTC 24 |
6217409668 ps |
| T1529 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.1140277499 |
|
|
Sep 18 10:12:47 PM UTC 24 |
Sep 18 10:12:59 PM UTC 24 |
83513048 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.107099844 |
|
|
Sep 18 10:12:18 PM UTC 24 |
Sep 18 10:13:00 PM UTC 24 |
643536686 ps |
| T1530 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.3537962418 |
|
|
Sep 18 10:12:32 PM UTC 24 |
Sep 18 10:13:04 PM UTC 24 |
287267817 ps |
| T1531 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.3172447388 |
|
|
Sep 18 10:11:47 PM UTC 24 |
Sep 18 10:13:06 PM UTC 24 |
6002423554 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.3134261838 |
|
|
Sep 18 10:08:52 PM UTC 24 |
Sep 18 10:13:06 PM UTC 24 |
6308239322 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.322114870 |
|
|
Sep 18 10:11:01 PM UTC 24 |
Sep 18 10:13:08 PM UTC 24 |
290903337 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.562120530 |
|
|
Sep 18 10:09:25 PM UTC 24 |
Sep 18 10:13:16 PM UTC 24 |
978467379 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.2877537106 |
|
|
Sep 18 09:54:22 PM UTC 24 |
Sep 18 10:13:27 PM UTC 24 |
8658488456 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.3240723850 |
|
|
Sep 18 10:09:54 PM UTC 24 |
Sep 18 10:13:27 PM UTC 24 |
2747116520 ps |
| T1532 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.540140680 |
|
|
Sep 18 10:13:35 PM UTC 24 |
Sep 18 10:13:42 PM UTC 24 |
46154416 ps |
| T1533 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.3324807071 |
|
|
Sep 18 10:13:37 PM UTC 24 |
Sep 18 10:13:46 PM UTC 24 |
50377833 ps |
| T1534 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.3628518849 |
|
|
Sep 18 10:11:52 PM UTC 24 |
Sep 18 10:13:49 PM UTC 24 |
6256264029 ps |
| T1535 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.771933226 |
|
|
Sep 18 10:12:48 PM UTC 24 |
Sep 18 10:13:54 PM UTC 24 |
1110029719 ps |
| T1536 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.131520656 |
|
|
Sep 18 10:10:32 PM UTC 24 |
Sep 18 10:14:04 PM UTC 24 |
9378117171 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.2020043845 |
|
|
Sep 18 10:12:27 PM UTC 24 |
Sep 18 10:14:05 PM UTC 24 |
2322228117 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.2418853057 |
|
|
Sep 18 10:11:38 PM UTC 24 |
Sep 18 10:14:17 PM UTC 24 |
3345233700 ps |
| T1537 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.3349492119 |
|
|
Sep 18 10:13:56 PM UTC 24 |
Sep 18 10:14:37 PM UTC 24 |
417608567 ps |
| T1538 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.740536875 |
|
|
Sep 18 10:09:26 PM UTC 24 |
Sep 18 10:14:40 PM UTC 24 |
4197332290 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.1937683414 |
|
|
Sep 18 09:59:33 PM UTC 24 |
Sep 18 10:14:47 PM UTC 24 |
11322239738 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.1320773971 |
|
|
Sep 18 10:12:50 PM UTC 24 |
Sep 18 10:14:50 PM UTC 24 |
1471931193 ps |
| T1539 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.2096613696 |
|
|
Sep 18 10:12:10 PM UTC 24 |
Sep 18 10:14:53 PM UTC 24 |
17776371661 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.3490712457 |
|
|
Sep 18 10:10:49 PM UTC 24 |
Sep 18 10:15:08 PM UTC 24 |
2725445992 ps |
| T1540 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.945444948 |
|
|
Sep 18 10:13:38 PM UTC 24 |
Sep 18 10:15:09 PM UTC 24 |
8797859992 ps |
| T1541 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.4131349860 |
|
|
Sep 18 10:13:38 PM UTC 24 |
Sep 18 10:15:12 PM UTC 24 |
4116825734 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.275854847 |
|
|
Sep 18 10:09:05 PM UTC 24 |
Sep 18 10:15:12 PM UTC 24 |
913478781 ps |
| T1542 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.3768723594 |
|
|
Sep 18 10:13:45 PM UTC 24 |
Sep 18 10:15:16 PM UTC 24 |
1904810543 ps |
| T1543 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.955733505 |
|
|
Sep 18 09:43:34 PM UTC 24 |
Sep 18 10:15:20 PM UTC 24 |
14388319904 ps |
| T1544 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.2811139538 |
|
|
Sep 18 10:14:37 PM UTC 24 |
Sep 18 10:15:22 PM UTC 24 |
740857364 ps |
| T1545 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.1435369012 |
|
|
Sep 18 10:14:33 PM UTC 24 |
Sep 18 10:15:23 PM UTC 24 |
1248236411 ps |
| T1546 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.3225114007 |
|
|
Sep 18 10:14:47 PM UTC 24 |
Sep 18 10:15:35 PM UTC 24 |
1015310494 ps |
| T1547 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.1699867855 |
|
|
Sep 18 10:15:35 PM UTC 24 |
Sep 18 10:15:43 PM UTC 24 |
52550471 ps |
| T1548 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.1429286012 |
|
|
Sep 18 10:14:21 PM UTC 24 |
Sep 18 10:15:50 PM UTC 24 |
2661209473 ps |
| T1549 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.4239707718 |
|
|
Sep 18 10:15:37 PM UTC 24 |
Sep 18 10:15:52 PM UTC 24 |
247212891 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.2613224659 |
|
|
Sep 18 09:55:56 PM UTC 24 |
Sep 18 10:15:55 PM UTC 24 |
75391706475 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.2604192347 |
|
|
Sep 18 10:14:16 PM UTC 24 |
Sep 18 10:16:00 PM UTC 24 |
2170310625 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.3115730381 |
|
|
Sep 18 10:06:31 PM UTC 24 |
Sep 18 10:16:14 PM UTC 24 |
15075547803 ps |
| T1550 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.1875877947 |
|
|
Sep 18 10:14:11 PM UTC 24 |
Sep 18 10:16:22 PM UTC 24 |
10217245996 ps |
| T1551 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.205738550 |
|
|
Sep 18 10:00:53 PM UTC 24 |
Sep 18 10:16:26 PM UTC 24 |
56853837225 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.4286406095 |
|
|
Sep 18 10:16:05 PM UTC 24 |
Sep 18 10:16:32 PM UTC 24 |
689048848 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.2766178238 |
|
|
Sep 18 10:06:36 PM UTC 24 |
Sep 18 10:16:37 PM UTC 24 |
5284794360 ps |
| T1552 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.2400102793 |
|
|
Sep 18 10:15:52 PM UTC 24 |
Sep 18 10:16:42 PM UTC 24 |
437279469 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.384693574 |
|
|
Sep 18 10:13:30 PM UTC 24 |
Sep 18 10:16:46 PM UTC 24 |
2988796532 ps |
| T1553 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.116902607 |
|
|
Sep 18 10:15:47 PM UTC 24 |
Sep 18 10:16:48 PM UTC 24 |
1273824271 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.225586664 |
|
|
Sep 18 10:16:21 PM UTC 24 |
Sep 18 10:16:57 PM UTC 24 |
514452156 ps |
| T1554 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.621802488 |
|
|
Sep 18 10:16:32 PM UTC 24 |
Sep 18 10:16:57 PM UTC 24 |
156887068 ps |
| T1555 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.4184051279 |
|
|
Sep 18 10:05:07 PM UTC 24 |
Sep 18 10:16:58 PM UTC 24 |
45109946256 ps |
| T1556 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.2059379322 |
|
|
Sep 18 10:09:43 PM UTC 24 |
Sep 18 10:17:04 PM UTC 24 |
7101434235 ps |
| T1557 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.1013556253 |
|
|
Sep 18 10:16:27 PM UTC 24 |
Sep 18 10:17:15 PM UTC 24 |
993587643 ps |
| T1558 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.1836396088 |
|
|
Sep 18 10:15:15 PM UTC 24 |
Sep 18 10:17:17 PM UTC 24 |
483343748 ps |
| T1559 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.246503813 |
|
|
Sep 18 10:15:42 PM UTC 24 |
Sep 18 10:17:17 PM UTC 24 |
8863403410 ps |
| T1560 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.1011519020 |
|
|
Sep 18 10:17:12 PM UTC 24 |
Sep 18 10:17:20 PM UTC 24 |
39290962 ps |
| T1561 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.332205417 |
|
|
Sep 18 10:17:13 PM UTC 24 |
Sep 18 10:17:20 PM UTC 24 |
43665751 ps |
| T1562 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.666205685 |
|
|
Sep 18 10:15:43 PM UTC 24 |
Sep 18 10:17:22 PM UTC 24 |
4924570591 ps |
| T1563 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.1188481731 |
|
|
Sep 18 10:16:42 PM UTC 24 |
Sep 18 10:17:24 PM UTC 24 |
322005001 ps |
| T1564 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.4213596748 |
|
|
Sep 18 10:16:23 PM UTC 24 |
Sep 18 10:17:32 PM UTC 24 |
2041821006 ps |
| T1565 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.2746930520 |
|
|
Sep 18 10:17:47 PM UTC 24 |
Sep 18 10:17:55 PM UTC 24 |
59981493 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.1071515086 |
|
|
Sep 18 10:10:57 PM UTC 24 |
Sep 18 10:17:56 PM UTC 24 |
4799969574 ps |
| T1566 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.1724478319 |
|
|
Sep 18 10:17:45 PM UTC 24 |
Sep 18 10:18:05 PM UTC 24 |
333547529 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2672018602 |
|
|
Sep 18 09:44:25 PM UTC 24 |
Sep 18 10:18:16 PM UTC 24 |
139128120873 ps |
| T1567 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.1952558676 |
|
|
Sep 18 10:17:25 PM UTC 24 |
Sep 18 10:18:22 PM UTC 24 |
491220936 ps |
| T1568 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.1375977243 |
|
|
Sep 18 10:17:54 PM UTC 24 |
Sep 18 10:18:37 PM UTC 24 |
1044238173 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.1129213267 |
|
|
Sep 18 10:17:18 PM UTC 24 |
Sep 18 10:18:41 PM UTC 24 |
10174273781 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.1297283379 |
|
|
Sep 18 10:06:49 PM UTC 24 |
Sep 18 10:18:42 PM UTC 24 |
6142711774 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.2746618734 |
|
|
Sep 18 10:17:26 PM UTC 24 |
Sep 18 10:18:47 PM UTC 24 |
2273245306 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.1799139469 |
|
|
Sep 18 10:17:25 PM UTC 24 |
Sep 18 10:18:57 PM UTC 24 |
6014570806 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.3598825009 |
|
|
Sep 18 10:15:17 PM UTC 24 |
Sep 18 10:19:01 PM UTC 24 |
2897652687 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.1118263371 |
|
|
Sep 18 10:18:51 PM UTC 24 |
Sep 18 10:19:02 PM UTC 24 |
204625463 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.3395251569 |
|
|
Sep 18 10:16:59 PM UTC 24 |
Sep 18 10:19:02 PM UTC 24 |
361663325 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.322448520 |
|
|
Sep 18 10:17:45 PM UTC 24 |
Sep 18 10:19:04 PM UTC 24 |
1859351159 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.2123174505 |
|
|
Sep 18 10:19:07 PM UTC 24 |
Sep 18 10:19:16 PM UTC 24 |
49356116 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.2937056412 |
|
|
Sep 18 10:17:44 PM UTC 24 |
Sep 18 10:19:30 PM UTC 24 |
2759540174 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.2355799278 |
|
|
Sep 18 10:19:26 PM UTC 24 |
Sep 18 10:19:53 PM UTC 24 |
193894958 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.4041642009 |
|
|
Sep 18 10:13:59 PM UTC 24 |
Sep 18 10:19:55 PM UTC 24 |
32877681594 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.1218469881 |
|
|
Sep 18 10:11:30 PM UTC 24 |
Sep 18 10:20:14 PM UTC 24 |
6414123101 ps |