| T2267 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.2447629043 |
|
|
Sep 18 11:10:35 PM UTC 24 |
Sep 18 11:12:11 PM UTC 24 |
2090039996 ps |
| T2268 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.3205091674 |
|
|
Sep 18 11:10:25 PM UTC 24 |
Sep 18 11:12:13 PM UTC 24 |
8363971525 ps |
| T2269 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.2268471753 |
|
|
Sep 18 11:12:03 PM UTC 24 |
Sep 18 11:12:16 PM UTC 24 |
137072282 ps |
| T2270 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.2804001833 |
|
|
Sep 18 11:11:41 PM UTC 24 |
Sep 18 11:12:23 PM UTC 24 |
1214320407 ps |
| T2271 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.397943917 |
|
|
Sep 18 11:11:43 PM UTC 24 |
Sep 18 11:12:27 PM UTC 24 |
451853697 ps |
| T2272 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.3710244761 |
|
|
Sep 18 11:11:59 PM UTC 24 |
Sep 18 11:12:37 PM UTC 24 |
626089447 ps |
| T2273 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.1109051708 |
|
|
Sep 18 11:03:08 PM UTC 24 |
Sep 18 11:12:39 PM UTC 24 |
17792737581 ps |
| T2274 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.1579389577 |
|
|
Sep 18 11:12:33 PM UTC 24 |
Sep 18 11:12:43 PM UTC 24 |
45039562 ps |
| T2275 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.2379659444 |
|
|
Sep 18 11:12:09 PM UTC 24 |
Sep 18 11:12:44 PM UTC 24 |
754343415 ps |
| T2276 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.905222328 |
|
|
Sep 18 11:12:32 PM UTC 24 |
Sep 18 11:12:46 PM UTC 24 |
217346084 ps |
| T2277 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.2380998285 |
|
|
Sep 18 11:11:35 PM UTC 24 |
Sep 18 11:12:49 PM UTC 24 |
7167880545 ps |
| T2278 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.4070427389 |
|
|
Sep 18 11:02:45 PM UTC 24 |
Sep 18 11:12:51 PM UTC 24 |
39296463004 ps |
| T2279 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.925957119 |
|
|
Sep 18 11:10:19 PM UTC 24 |
Sep 18 11:12:52 PM UTC 24 |
16428127862 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.2362605484 |
|
|
Sep 18 11:06:32 PM UTC 24 |
Sep 18 11:12:57 PM UTC 24 |
5342703826 ps |
| T2280 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.3916796451 |
|
|
Sep 18 11:12:40 PM UTC 24 |
Sep 18 11:13:00 PM UTC 24 |
528726921 ps |
| T2281 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.1322852602 |
|
|
Sep 18 11:12:18 PM UTC 24 |
Sep 18 11:13:02 PM UTC 24 |
48681544 ps |
| T2282 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.3932569883 |
|
|
Sep 18 10:54:45 PM UTC 24 |
Sep 18 11:13:05 PM UTC 24 |
75969452242 ps |
| T2283 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.1166381162 |
|
|
Sep 18 11:12:44 PM UTC 24 |
Sep 18 11:13:10 PM UTC 24 |
224143544 ps |
| T2284 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.2293237443 |
|
|
Sep 18 11:09:32 PM UTC 24 |
Sep 18 11:13:11 PM UTC 24 |
3255791223 ps |
| T2285 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.2321003065 |
|
|
Sep 18 11:11:40 PM UTC 24 |
Sep 18 11:13:14 PM UTC 24 |
6038864880 ps |
| T2286 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.778487382 |
|
|
Sep 18 10:56:32 PM UTC 24 |
Sep 18 11:13:14 PM UTC 24 |
97337349006 ps |
| T2287 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.2706116658 |
|
|
Sep 18 11:12:02 PM UTC 24 |
Sep 18 11:13:14 PM UTC 24 |
1920258558 ps |
| T2288 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.182357632 |
|
|
Sep 18 11:07:32 PM UTC 24 |
Sep 18 11:13:20 PM UTC 24 |
729301930 ps |
| T2289 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.2306129248 |
|
|
Sep 18 11:13:13 PM UTC 24 |
Sep 18 11:13:26 PM UTC 24 |
208827038 ps |
| T2290 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.3954839041 |
|
|
Sep 18 11:08:33 PM UTC 24 |
Sep 18 11:13:34 PM UTC 24 |
9320442113 ps |
| T2291 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.1069051429 |
|
|
Sep 18 11:13:14 PM UTC 24 |
Sep 18 11:13:34 PM UTC 24 |
325254506 ps |
| T2292 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.3246648848 |
|
|
Sep 18 11:13:08 PM UTC 24 |
Sep 18 11:13:35 PM UTC 24 |
340975937 ps |
| T2293 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.3981193448 |
|
|
Sep 18 11:04:28 PM UTC 24 |
Sep 18 11:13:35 PM UTC 24 |
11328751474 ps |
| T2294 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.4123403093 |
|
|
Sep 18 11:12:38 PM UTC 24 |
Sep 18 11:13:38 PM UTC 24 |
5912445556 ps |
| T2295 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.1420875302 |
|
|
Sep 18 11:13:29 PM UTC 24 |
Sep 18 11:13:39 PM UTC 24 |
41875778 ps |
| T2296 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.3215001961 |
|
|
Sep 18 11:13:30 PM UTC 24 |
Sep 18 11:13:43 PM UTC 24 |
183769233 ps |
| T2297 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.485265459 |
|
|
Sep 18 11:12:53 PM UTC 24 |
Sep 18 11:13:44 PM UTC 24 |
1402528921 ps |
| T2298 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.4001675497 |
|
|
Sep 18 11:12:36 PM UTC 24 |
Sep 18 11:13:47 PM UTC 24 |
4961950964 ps |
| T2299 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.4251956178 |
|
|
Sep 18 11:13:15 PM UTC 24 |
Sep 18 11:13:59 PM UTC 24 |
746495549 ps |
| T2300 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.2926371683 |
|
|
Sep 18 11:13:37 PM UTC 24 |
Sep 18 11:14:07 PM UTC 24 |
319928330 ps |
| T2301 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.3097922187 |
|
|
Sep 18 10:47:17 PM UTC 24 |
Sep 18 11:14:15 PM UTC 24 |
94099530517 ps |
| T2302 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.3673640755 |
|
|
Sep 18 11:14:05 PM UTC 24 |
Sep 18 11:14:16 PM UTC 24 |
84761789 ps |
| T2303 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3464203329 |
|
|
Sep 18 11:11:11 PM UTC 24 |
Sep 18 11:14:19 PM UTC 24 |
785227024 ps |
| T2304 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.897753318 |
|
|
Sep 18 11:13:51 PM UTC 24 |
Sep 18 11:14:23 PM UTC 24 |
350555603 ps |
| T2305 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.1281183613 |
|
|
Sep 18 11:14:18 PM UTC 24 |
Sep 18 11:14:28 PM UTC 24 |
47588598 ps |
| T2306 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.3994763993 |
|
|
Sep 18 11:06:32 PM UTC 24 |
Sep 18 11:14:32 PM UTC 24 |
12333430537 ps |
| T2307 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.3513018289 |
|
|
Sep 18 11:13:42 PM UTC 24 |
Sep 18 11:14:33 PM UTC 24 |
476918163 ps |
| T2308 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.3472697512 |
|
|
Sep 18 11:06:22 PM UTC 24 |
Sep 18 11:14:34 PM UTC 24 |
32508546732 ps |
| T2309 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.2789703279 |
|
|
Sep 18 11:14:01 PM UTC 24 |
Sep 18 11:14:37 PM UTC 24 |
352126118 ps |
| T2310 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.1639618407 |
|
|
Sep 18 11:14:30 PM UTC 24 |
Sep 18 11:14:40 PM UTC 24 |
43813109 ps |
| T2311 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.1597178857 |
|
|
Sep 18 11:10:54 PM UTC 24 |
Sep 18 11:14:43 PM UTC 24 |
7913629613 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.3090737180 |
|
|
Sep 18 11:13:28 PM UTC 24 |
Sep 18 11:14:51 PM UTC 24 |
190638515 ps |
| T2312 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.2411760911 |
|
|
Sep 18 11:13:38 PM UTC 24 |
Sep 18 11:14:58 PM UTC 24 |
3412799510 ps |
| T2313 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.951716740 |
|
|
Sep 18 11:14:46 PM UTC 24 |
Sep 18 11:15:01 PM UTC 24 |
310272231 ps |
| T2314 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.1630514259 |
|
|
Sep 18 11:05:08 PM UTC 24 |
Sep 18 11:15:05 PM UTC 24 |
38794129588 ps |
| T2315 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.484470522 |
|
|
Sep 18 11:14:03 PM UTC 24 |
Sep 18 11:15:06 PM UTC 24 |
1226979743 ps |
| T2316 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.1091842696 |
|
|
Sep 18 11:12:22 PM UTC 24 |
Sep 18 11:15:06 PM UTC 24 |
1971010436 ps |
| T2317 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.2242183234 |
|
|
Sep 18 11:14:01 PM UTC 24 |
Sep 18 11:15:14 PM UTC 24 |
2523168350 ps |
| T2318 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.402695601 |
|
|
Sep 18 10:59:42 PM UTC 24 |
Sep 18 11:15:20 PM UTC 24 |
99052124483 ps |
| T2319 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.391040793 |
|
|
Sep 18 11:14:48 PM UTC 24 |
Sep 18 11:15:23 PM UTC 24 |
335170208 ps |
| T2320 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.2363255503 |
|
|
Sep 18 11:15:03 PM UTC 24 |
Sep 18 11:15:28 PM UTC 24 |
614608145 ps |
| T2321 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.1333249513 |
|
|
Sep 18 11:08:16 PM UTC 24 |
Sep 18 11:15:30 PM UTC 24 |
29731235297 ps |
| T2322 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.3466693747 |
|
|
Sep 18 11:15:08 PM UTC 24 |
Sep 18 11:15:31 PM UTC 24 |
288546636 ps |
| T2323 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.715324754 |
|
|
Sep 18 11:15:11 PM UTC 24 |
Sep 18 11:15:34 PM UTC 24 |
186290860 ps |
| T2324 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.472565117 |
|
|
Sep 18 11:07:38 PM UTC 24 |
Sep 18 11:15:35 PM UTC 24 |
8549580917 ps |
| T2325 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.469663542 |
|
|
Sep 18 11:08:38 PM UTC 24 |
Sep 18 11:15:36 PM UTC 24 |
14858511907 ps |
| T2326 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.2249149781 |
|
|
Sep 18 11:15:33 PM UTC 24 |
Sep 18 11:15:43 PM UTC 24 |
222922417 ps |
| T2327 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.3412127688 |
|
|
Sep 18 11:15:36 PM UTC 24 |
Sep 18 11:15:45 PM UTC 24 |
44625593 ps |
| T2328 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.3764025751 |
|
|
Sep 18 11:15:12 PM UTC 24 |
Sep 18 11:15:48 PM UTC 24 |
1009508874 ps |
| T2329 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.3240562793 |
|
|
Sep 18 11:13:35 PM UTC 24 |
Sep 18 11:15:55 PM UTC 24 |
10910733488 ps |
| T2330 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.1831874176 |
|
|
Sep 18 11:14:38 PM UTC 24 |
Sep 18 11:15:58 PM UTC 24 |
7333790570 ps |
| T2331 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.2793216321 |
|
|
Sep 18 11:15:30 PM UTC 24 |
Sep 18 11:15:58 PM UTC 24 |
49767809 ps |
| T2332 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.3940811474 |
|
|
Sep 18 11:14:59 PM UTC 24 |
Sep 18 11:16:09 PM UTC 24 |
893284018 ps |
| T2333 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.3572887225 |
|
|
Sep 18 11:14:45 PM UTC 24 |
Sep 18 11:16:20 PM UTC 24 |
4840177730 ps |
| T2334 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.800195105 |
|
|
Sep 18 11:01:01 PM UTC 24 |
Sep 18 11:16:23 PM UTC 24 |
60708736655 ps |
| T2335 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.1695041721 |
|
|
Sep 18 11:15:54 PM UTC 24 |
Sep 18 11:16:23 PM UTC 24 |
353800007 ps |
| T2336 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.1431449414 |
|
|
Sep 18 11:16:18 PM UTC 24 |
Sep 18 11:16:27 PM UTC 24 |
26312132 ps |
| T2337 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.3108329095 |
|
|
Sep 18 11:16:11 PM UTC 24 |
Sep 18 11:16:33 PM UTC 24 |
265721758 ps |
| T2338 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.3127413890 |
|
|
Sep 18 11:15:55 PM UTC 24 |
Sep 18 11:16:34 PM UTC 24 |
418557549 ps |
| T2339 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.2175179703 |
|
|
Sep 18 11:12:18 PM UTC 24 |
Sep 18 11:16:34 PM UTC 24 |
3263769205 ps |
| T2340 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.3829643411 |
|
|
Sep 18 11:15:26 PM UTC 24 |
Sep 18 11:16:36 PM UTC 24 |
168389028 ps |
| T2341 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.1283458112 |
|
|
Sep 18 11:16:02 PM UTC 24 |
Sep 18 11:16:39 PM UTC 24 |
1080381606 ps |
| T2342 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.1737353300 |
|
|
Sep 18 11:15:39 PM UTC 24 |
Sep 18 11:16:44 PM UTC 24 |
6740940117 ps |
| T2343 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.529753289 |
|
|
Sep 18 11:16:12 PM UTC 24 |
Sep 18 11:16:53 PM UTC 24 |
957694141 ps |
| T2344 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.3350382323 |
|
|
Sep 18 11:16:49 PM UTC 24 |
Sep 18 11:16:59 PM UTC 24 |
220530866 ps |
| T2345 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.509976136 |
|
|
Sep 18 11:16:03 PM UTC 24 |
Sep 18 11:17:02 PM UTC 24 |
702826434 ps |
| T2346 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.2529608144 |
|
|
Sep 18 11:16:55 PM UTC 24 |
Sep 18 11:17:02 PM UTC 24 |
44901215 ps |
| T2347 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.2820205598 |
|
|
Sep 18 11:03:55 PM UTC 24 |
Sep 18 11:17:05 PM UTC 24 |
76483808388 ps |
| T2348 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.445790936 |
|
|
Sep 18 11:15:49 PM UTC 24 |
Sep 18 11:17:13 PM UTC 24 |
5161990995 ps |
| T2349 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.1542054127 |
|
|
Sep 18 11:14:13 PM UTC 24 |
Sep 18 11:17:18 PM UTC 24 |
2205300774 ps |
| T2350 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.3866482203 |
|
|
Sep 18 11:14:49 PM UTC 24 |
Sep 18 11:17:24 PM UTC 24 |
16983731340 ps |
| T2351 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.2625936103 |
|
|
Sep 18 11:17:30 PM UTC 24 |
Sep 18 11:17:42 PM UTC 24 |
66980790 ps |
| T2352 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.2233413360 |
|
|
Sep 18 11:17:30 PM UTC 24 |
Sep 18 11:17:49 PM UTC 24 |
260980719 ps |
| T2353 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.592539346 |
|
|
Sep 18 11:17:11 PM UTC 24 |
Sep 18 11:17:52 PM UTC 24 |
3091506551 ps |
| T2354 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.2989945325 |
|
|
Sep 18 11:09:33 PM UTC 24 |
Sep 18 11:17:54 PM UTC 24 |
12885367484 ps |
| T2355 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.1431833634 |
|
|
Sep 18 11:17:04 PM UTC 24 |
Sep 18 11:17:57 PM UTC 24 |
460317890 ps |
| T2356 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.3769935523 |
|
|
Sep 18 11:17:01 PM UTC 24 |
Sep 18 11:18:03 PM UTC 24 |
1622811452 ps |
| T2357 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.1869928485 |
|
|
Sep 18 11:17:27 PM UTC 24 |
Sep 18 11:18:07 PM UTC 24 |
376507077 ps |
| T2358 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.3997182795 |
|
|
Sep 18 11:16:50 PM UTC 24 |
Sep 18 11:18:14 PM UTC 24 |
7406922515 ps |
| T2359 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.520498446 |
|
|
Sep 18 11:17:06 PM UTC 24 |
Sep 18 11:18:16 PM UTC 24 |
3898745393 ps |
| T2360 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.1044187769 |
|
|
Sep 18 11:13:22 PM UTC 24 |
Sep 18 11:18:20 PM UTC 24 |
7621352853 ps |
| T2361 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.274867531 |
|
|
Sep 18 11:12:45 PM UTC 24 |
Sep 18 11:18:23 PM UTC 24 |
33105767397 ps |
| T2362 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.3950212754 |
|
|
Sep 18 11:18:14 PM UTC 24 |
Sep 18 11:18:28 PM UTC 24 |
213265522 ps |
| T2363 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.334892678 |
|
|
Sep 18 11:18:20 PM UTC 24 |
Sep 18 11:18:30 PM UTC 24 |
44862891 ps |
| T2364 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.669193281 |
|
|
Sep 18 11:17:09 PM UTC 24 |
Sep 18 11:18:36 PM UTC 24 |
1458947812 ps |
| T2365 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.1551695848 |
|
|
Sep 18 11:17:22 PM UTC 24 |
Sep 18 11:18:36 PM UTC 24 |
2125597226 ps |
| T2366 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.2330279289 |
|
|
Sep 18 11:18:33 PM UTC 24 |
Sep 18 11:18:44 PM UTC 24 |
67051588 ps |
| T2367 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.2475237353 |
|
|
Sep 18 11:13:16 PM UTC 24 |
Sep 18 11:18:45 PM UTC 24 |
4155541006 ps |
| T2368 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.3737163812 |
|
|
Sep 18 11:15:21 PM UTC 24 |
Sep 18 11:18:46 PM UTC 24 |
2909076198 ps |
| T2369 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.3717788808 |
|
|
Sep 18 11:17:47 PM UTC 24 |
Sep 18 11:18:46 PM UTC 24 |
1032674947 ps |
| T2370 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.4179151040 |
|
|
Sep 18 11:14:07 PM UTC 24 |
Sep 18 11:18:50 PM UTC 24 |
1317216993 ps |
| T2371 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.3310243370 |
|
|
Sep 18 11:08:35 PM UTC 24 |
Sep 18 11:18:51 PM UTC 24 |
7255085934 ps |
| T2372 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.3568373858 |
|
|
Sep 18 11:16:56 PM UTC 24 |
Sep 18 11:18:53 PM UTC 24 |
6261886301 ps |
| T2373 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.2025505666 |
|
|
Sep 18 11:18:49 PM UTC 24 |
Sep 18 11:19:03 PM UTC 24 |
211727997 ps |
| T2374 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.3921642635 |
|
|
Sep 18 11:09:44 PM UTC 24 |
Sep 18 11:19:04 PM UTC 24 |
17207547288 ps |
| T2375 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.3340524958 |
|
|
Sep 18 11:10:50 PM UTC 24 |
Sep 18 11:19:10 PM UTC 24 |
2719790276 ps |
| T2376 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.3854438460 |
|
|
Sep 18 11:18:59 PM UTC 24 |
Sep 18 11:19:14 PM UTC 24 |
196823471 ps |
| T2377 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.877603668 |
|
|
Sep 18 11:19:14 PM UTC 24 |
Sep 18 11:19:25 PM UTC 24 |
230936408 ps |
| T2378 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.296186838 |
|
|
Sep 18 11:19:17 PM UTC 24 |
Sep 18 11:19:27 PM UTC 24 |
46233061 ps |
| T2379 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.1616163205 |
|
|
Sep 18 11:18:54 PM UTC 24 |
Sep 18 11:19:28 PM UTC 24 |
397072043 ps |
| T2380 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.3910339750 |
|
|
Sep 18 11:18:59 PM UTC 24 |
Sep 18 11:19:29 PM UTC 24 |
505544197 ps |
| T2381 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.3774919854 |
|
|
Sep 18 11:14:11 PM UTC 24 |
Sep 18 11:19:35 PM UTC 24 |
8333892317 ps |
| T2382 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.2189922857 |
|
|
Sep 18 11:18:25 PM UTC 24 |
Sep 18 11:19:41 PM UTC 24 |
4022752941 ps |
| T2383 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.1913347722 |
|
|
Sep 18 11:14:07 PM UTC 24 |
Sep 18 11:19:46 PM UTC 24 |
10045178861 ps |
| T2384 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.1921303533 |
|
|
Sep 18 11:18:46 PM UTC 24 |
Sep 18 11:19:55 PM UTC 24 |
2233366244 ps |
| T2385 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.1535257324 |
|
|
Sep 18 11:13:19 PM UTC 24 |
Sep 18 11:19:58 PM UTC 24 |
4544510080 ps |
| T2386 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.1170332310 |
|
|
Sep 18 11:18:24 PM UTC 24 |
Sep 18 11:20:02 PM UTC 24 |
7760915158 ps |
| T2387 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.1962764776 |
|
|
Sep 18 11:18:29 PM UTC 24 |
Sep 18 11:20:02 PM UTC 24 |
1778889252 ps |
| T2388 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.1646075138 |
|
|
Sep 18 11:19:32 PM UTC 24 |
Sep 18 11:20:07 PM UTC 24 |
329747357 ps |
| T2389 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.4071975857 |
|
|
Sep 18 11:19:12 PM UTC 24 |
Sep 18 11:20:08 PM UTC 24 |
152929043 ps |
| T2390 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.3402201108 |
|
|
Sep 18 11:19:27 PM UTC 24 |
Sep 18 11:20:14 PM UTC 24 |
526482912 ps |
| T2391 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.2176741249 |
|
|
Sep 18 11:09:21 PM UTC 24 |
Sep 18 11:20:16 PM UTC 24 |
47767736033 ps |
| T2392 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.3157290369 |
|
|
Sep 18 11:20:11 PM UTC 24 |
Sep 18 11:20:22 PM UTC 24 |
100387378 ps |
| T2393 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.457933197 |
|
|
Sep 18 10:57:46 PM UTC 24 |
Sep 18 11:20:23 PM UTC 24 |
89093928470 ps |
| T2394 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.2979002421 |
|
|
Sep 18 11:19:17 PM UTC 24 |
Sep 18 11:20:26 PM UTC 24 |
6162365852 ps |
| T2395 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.3968232994 |
|
|
Sep 18 11:19:59 PM UTC 24 |
Sep 18 11:20:38 PM UTC 24 |
1067499733 ps |
| T2396 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.1316495203 |
|
|
Sep 18 11:19:58 PM UTC 24 |
Sep 18 11:20:40 PM UTC 24 |
1080747992 ps |
| T2397 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.1449908569 |
|
|
Sep 18 11:20:03 PM UTC 24 |
Sep 18 11:20:41 PM UTC 24 |
734280719 ps |
| T2398 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.443143940 |
|
|
Sep 18 11:20:33 PM UTC 24 |
Sep 18 11:20:43 PM UTC 24 |
54317421 ps |
| T2399 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.619411976 |
|
|
Sep 18 11:20:37 PM UTC 24 |
Sep 18 11:20:47 PM UTC 24 |
37179600 ps |
| T2400 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.3030287833 |
|
|
Sep 18 11:19:24 PM UTC 24 |
Sep 18 11:20:54 PM UTC 24 |
5053091618 ps |
| T2401 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.4040443874 |
|
|
Sep 18 11:15:29 PM UTC 24 |
Sep 18 11:20:58 PM UTC 24 |
10164716083 ps |
| T2402 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.3842599813 |
|
|
Sep 18 11:14:54 PM UTC 24 |
Sep 18 11:20:58 PM UTC 24 |
23684434599 ps |
| T2403 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.2436548706 |
|
|
Sep 18 11:20:23 PM UTC 24 |
Sep 18 11:21:00 PM UTC 24 |
14720223 ps |
| T2404 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.1544826321 |
|
|
Sep 18 11:06:09 PM UTC 24 |
Sep 18 11:21:21 PM UTC 24 |
58223295792 ps |
| T2405 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.778629109 |
|
|
Sep 18 11:21:09 PM UTC 24 |
Sep 18 11:21:31 PM UTC 24 |
167665907 ps |
| T2406 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.1326586486 |
|
|
Sep 18 11:20:45 PM UTC 24 |
Sep 18 11:21:33 PM UTC 24 |
1014799664 ps |
| T2407 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.3151682730 |
|
|
Sep 18 11:21:21 PM UTC 24 |
Sep 18 11:21:37 PM UTC 24 |
117823371 ps |
| T2408 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.4144884235 |
|
|
Sep 18 11:21:16 PM UTC 24 |
Sep 18 11:21:47 PM UTC 24 |
198451128 ps |
| T2409 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.4244449239 |
|
|
Sep 18 11:20:50 PM UTC 24 |
Sep 18 11:22:01 PM UTC 24 |
623476466 ps |
| T2410 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.3345534234 |
|
|
Sep 18 11:20:42 PM UTC 24 |
Sep 18 11:22:02 PM UTC 24 |
4563224965 ps |
| T2411 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.2706563131 |
|
|
Sep 18 11:21:10 PM UTC 24 |
Sep 18 11:22:03 PM UTC 24 |
1691145190 ps |
| T2412 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.1966694376 |
|
|
Sep 18 11:22:00 PM UTC 24 |
Sep 18 11:22:13 PM UTC 24 |
158836778 ps |
| T2413 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.24678937 |
|
|
Sep 18 11:22:03 PM UTC 24 |
Sep 18 11:22:14 PM UTC 24 |
48245989 ps |
| T2414 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.583299794 |
|
|
Sep 18 11:19:11 PM UTC 24 |
Sep 18 11:22:18 PM UTC 24 |
595317264 ps |
| T2415 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.3140595490 |
|
|
Sep 18 11:19:52 PM UTC 24 |
Sep 18 11:22:42 PM UTC 24 |
3231936649 ps |
| T2416 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.2052327808 |
|
|
Sep 18 11:16:23 PM UTC 24 |
Sep 18 11:22:42 PM UTC 24 |
11941505186 ps |
| T2417 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.291297533 |
|
|
Sep 18 11:20:37 PM UTC 24 |
Sep 18 11:22:47 PM UTC 24 |
10599061297 ps |
| T2418 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.1111813422 |
|
|
Sep 18 11:22:30 PM UTC 24 |
Sep 18 11:22:54 PM UTC 24 |
712617970 ps |
| T2419 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.324787612 |
|
|
Sep 18 11:19:42 PM UTC 24 |
Sep 18 11:22:55 PM UTC 24 |
12709989598 ps |
| T2420 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.2839574006 |
|
|
Sep 18 11:11:44 PM UTC 24 |
Sep 18 11:22:56 PM UTC 24 |
67591755760 ps |
| T2421 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.2517971282 |
|
|
Sep 18 11:20:56 PM UTC 24 |
Sep 18 11:22:57 PM UTC 24 |
8492320039 ps |
| T2422 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.1522919377 |
|
|
Sep 18 11:06:01 PM UTC 24 |
Sep 18 11:22:58 PM UTC 24 |
91714368980 ps |
| T2423 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.2919334426 |
|
|
Sep 18 11:17:51 PM UTC 24 |
Sep 18 11:23:02 PM UTC 24 |
2012979066 ps |
| T2424 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.761308882 |
|
|
Sep 18 11:22:30 PM UTC 24 |
Sep 18 11:23:04 PM UTC 24 |
309371834 ps |
| T2425 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.1086631478 |
|
|
Sep 18 11:12:30 PM UTC 24 |
Sep 18 11:23:06 PM UTC 24 |
7022521082 ps |
| T2426 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.2210098464 |
|
|
Sep 18 11:22:45 PM UTC 24 |
Sep 18 11:23:08 PM UTC 24 |
589798119 ps |
| T2427 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.3696716597 |
|
|
Sep 18 11:17:37 PM UTC 24 |
Sep 18 11:23:11 PM UTC 24 |
2114166305 ps |
| T2428 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.2211306269 |
|
|
Sep 18 11:21:32 PM UTC 24 |
Sep 18 11:23:14 PM UTC 24 |
1329753526 ps |
| T2429 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.1577627756 |
|
|
Sep 18 11:16:22 PM UTC 24 |
Sep 18 11:23:22 PM UTC 24 |
9743085424 ps |
| T2430 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.1025368096 |
|
|
Sep 18 11:23:11 PM UTC 24 |
Sep 18 11:23:23 PM UTC 24 |
221036157 ps |
| T2431 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.2767848425 |
|
|
Sep 18 11:23:15 PM UTC 24 |
Sep 18 11:23:30 PM UTC 24 |
87815863 ps |
| T2432 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.2375751214 |
|
|
Sep 18 11:22:06 PM UTC 24 |
Sep 18 11:23:35 PM UTC 24 |
6815662869 ps |
| T2433 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.388975130 |
|
|
Sep 18 11:16:01 PM UTC 24 |
Sep 18 11:23:39 PM UTC 24 |
50176581487 ps |
| T2434 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.889171497 |
|
|
Sep 18 11:22:18 PM UTC 24 |
Sep 18 11:23:41 PM UTC 24 |
6373669552 ps |
| T2435 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.3051896792 |
|
|
Sep 18 11:23:14 PM UTC 24 |
Sep 18 11:23:42 PM UTC 24 |
206222850 ps |
| T2436 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.1032961843 |
|
|
Sep 18 11:23:28 PM UTC 24 |
Sep 18 11:23:43 PM UTC 24 |
222833693 ps |
| T2437 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.2548997208 |
|
|
Sep 18 11:23:34 PM UTC 24 |
Sep 18 11:23:44 PM UTC 24 |
46486578 ps |
| T2438 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.2595551845 |
|
|
Sep 18 11:22:43 PM UTC 24 |
Sep 18 11:23:50 PM UTC 24 |
4204970230 ps |
| T2439 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.623712666 |
|
|
Sep 18 11:11:49 PM UTC 24 |
Sep 18 11:23:58 PM UTC 24 |
53270863689 ps |
| T2440 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.1458130989 |
|
|
Sep 18 11:23:41 PM UTC 24 |
Sep 18 11:24:03 PM UTC 24 |
369270345 ps |
| T2441 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3985949889 |
|
|
Sep 18 11:23:29 PM UTC 24 |
Sep 18 11:24:05 PM UTC 24 |
104575545 ps |
| T2442 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.471669066 |
|
|
Sep 18 11:21:10 PM UTC 24 |
Sep 18 11:24:10 PM UTC 24 |
3765237199 ps |
| T2443 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.2549255300 |
|
|
Sep 18 11:08:32 PM UTC 24 |
Sep 18 11:24:11 PM UTC 24 |
27977117800 ps |
| T2444 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.2467091157 |
|
|
Sep 18 11:10:04 PM UTC 24 |
Sep 18 11:24:24 PM UTC 24 |
16108265984 ps |
| T2445 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.1663446786 |
|
|
Sep 18 11:24:11 PM UTC 24 |
Sep 18 11:24:27 PM UTC 24 |
154180136 ps |
| T2446 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.3942234629 |
|
|
Sep 18 11:23:23 PM UTC 24 |
Sep 18 11:24:28 PM UTC 24 |
1424242934 ps |
| T2447 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.1931041065 |
|
|
Sep 18 10:49:36 PM UTC 24 |
Sep 18 11:24:29 PM UTC 24 |
133430093171 ps |
| T2448 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.416949837 |
|
|
Sep 18 11:24:01 PM UTC 24 |
Sep 18 11:24:41 PM UTC 24 |
846562321 ps |
| T2449 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.2040207839 |
|
|
Sep 18 11:23:41 PM UTC 24 |
Sep 18 11:24:42 PM UTC 24 |
524133234 ps |
| T2450 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.4000672997 |
|
|
Sep 18 11:24:34 PM UTC 24 |
Sep 18 11:24:43 PM UTC 24 |
53844873 ps |
| T2451 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.3769952683 |
|
|
Sep 18 11:21:52 PM UTC 24 |
Sep 18 11:24:43 PM UTC 24 |
636645152 ps |
| T2452 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.1847399661 |
|
|
Sep 18 11:24:39 PM UTC 24 |
Sep 18 11:24:50 PM UTC 24 |
50871165 ps |
| T2453 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.2749918194 |
|
|
Sep 18 11:15:57 PM UTC 24 |
Sep 18 11:24:52 PM UTC 24 |
39185489039 ps |
| T2454 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.7282285 |
|
|
Sep 18 11:23:34 PM UTC 24 |
Sep 18 11:24:55 PM UTC 24 |
8262651048 ps |
| T2455 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.3054787136 |
|
|
Sep 18 11:24:11 PM UTC 24 |
Sep 18 11:24:59 PM UTC 24 |
1171408066 ps |
| T2456 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.3459535256 |
|
|
Sep 18 11:23:36 PM UTC 24 |
Sep 18 11:24:59 PM UTC 24 |
5663144346 ps |
| T2457 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.2984669435 |
|
|
Sep 18 11:09:17 PM UTC 24 |
Sep 18 11:25:00 PM UTC 24 |
91847053603 ps |
| T2458 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.586298340 |
|
|
Sep 18 11:24:09 PM UTC 24 |
Sep 18 11:25:02 PM UTC 24 |
1454144768 ps |
| T2459 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.873956259 |
|
|
Sep 18 11:24:11 PM UTC 24 |
Sep 18 11:25:12 PM UTC 24 |
1221824920 ps |
| T2460 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.3677215235 |
|
|
Sep 18 11:24:59 PM UTC 24 |
Sep 18 11:25:15 PM UTC 24 |
223482124 ps |
| T2461 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.4012988170 |
|
|
Sep 18 11:17:03 PM UTC 24 |
Sep 18 11:25:20 PM UTC 24 |
51090296859 ps |
| T2462 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.2692330479 |
|
|
Sep 18 11:19:02 PM UTC 24 |
Sep 18 11:25:30 PM UTC 24 |
5746257311 ps |
| T2463 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.292201315 |
|
|
Sep 18 11:25:14 PM UTC 24 |
Sep 18 11:25:39 PM UTC 24 |
264485326 ps |
| T2464 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.58773627 |
|
|
Sep 18 11:24:43 PM UTC 24 |
Sep 18 11:25:40 PM UTC 24 |
5825236421 ps |
| T2465 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.172456834 |
|
|
Sep 18 11:25:19 PM UTC 24 |
Sep 18 11:25:41 PM UTC 24 |
433204851 ps |
| T2466 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.1901600291 |
|
|
Sep 18 11:25:19 PM UTC 24 |
Sep 18 11:25:45 PM UTC 24 |
219725329 ps |
| T2467 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.151134516 |
|
|
Sep 18 11:25:37 PM UTC 24 |
Sep 18 11:25:45 PM UTC 24 |
159682621 ps |
| T2468 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.620656247 |
|
|
Sep 18 11:25:00 PM UTC 24 |
Sep 18 11:25:48 PM UTC 24 |
481031431 ps |
| T2469 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.3838395240 |
|
|
Sep 18 11:25:42 PM UTC 24 |
Sep 18 11:25:49 PM UTC 24 |
58478253 ps |
| T2470 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.4259169086 |
|
|
Sep 18 11:23:22 PM UTC 24 |
Sep 18 11:25:57 PM UTC 24 |
1938429423 ps |
| T2471 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.3567966052 |
|
|
Sep 18 11:20:29 PM UTC 24 |
Sep 18 11:25:58 PM UTC 24 |
3294337880 ps |
| T2472 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.3007649199 |
|
|
Sep 18 11:20:53 PM UTC 24 |
Sep 18 11:26:00 PM UTC 24 |
33080825257 ps |
| T2473 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.2760443231 |
|
|
Sep 18 11:23:25 PM UTC 24 |
Sep 18 11:26:02 PM UTC 24 |
5218891047 ps |
| T2474 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.3426289256 |
|
|
Sep 18 11:25:22 PM UTC 24 |
Sep 18 11:26:04 PM UTC 24 |
865496210 ps |
| T2475 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.3686875287 |
|
|
Sep 18 11:23:26 PM UTC 24 |
Sep 18 11:26:09 PM UTC 24 |
815721376 ps |
| T2476 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.4122831327 |
|
|
Sep 18 11:20:15 PM UTC 24 |
Sep 18 11:26:18 PM UTC 24 |
10812295496 ps |
| T2477 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.1024596916 |
|
|
Sep 18 11:18:38 PM UTC 24 |
Sep 18 11:26:23 PM UTC 24 |
47689991039 ps |
| T2478 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.3463727487 |
|
|
Sep 18 11:24:54 PM UTC 24 |
Sep 18 11:26:25 PM UTC 24 |
5053598683 ps |
| T2479 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.1578441056 |
|
|
Sep 18 11:25:11 PM UTC 24 |
Sep 18 11:26:27 PM UTC 24 |
1342142424 ps |
| T2480 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.545960528 |
|
|
Sep 18 11:21:28 PM UTC 24 |
Sep 18 11:26:30 PM UTC 24 |
7243602826 ps |
| T2481 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.2440267852 |
|
|
Sep 18 11:26:14 PM UTC 24 |
Sep 18 11:26:34 PM UTC 24 |
145278531 ps |
| T2482 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.3745160456 |
|
|
Sep 18 11:19:36 PM UTC 24 |
Sep 18 11:26:37 PM UTC 24 |
47779834610 ps |
| T2483 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.4067178024 |
|
|
Sep 18 11:26:14 PM UTC 24 |
Sep 18 11:26:40 PM UTC 24 |
463875732 ps |
| T2484 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.308052436 |
|
|
Sep 18 11:26:25 PM UTC 24 |
Sep 18 11:26:42 PM UTC 24 |
357090067 ps |
| T2485 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.416835533 |
|
|
Sep 18 11:26:09 PM UTC 24 |
Sep 18 11:26:47 PM UTC 24 |
452382776 ps |
| T2486 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.476394547 |
|
|
Sep 18 11:26:12 PM UTC 24 |
Sep 18 11:26:49 PM UTC 24 |
432807266 ps |
| T2487 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.2331556363 |
|
|
Sep 18 11:26:24 PM UTC 24 |
Sep 18 11:26:56 PM UTC 24 |
364741739 ps |
| T2488 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.2844552690 |
|
|
Sep 18 11:26:55 PM UTC 24 |
Sep 18 11:27:04 PM UTC 24 |
49038461 ps |
| T2489 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.2589566734 |
|
|
Sep 18 11:26:52 PM UTC 24 |
Sep 18 11:27:06 PM UTC 24 |
224834751 ps |
| T2490 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.343180929 |
|
|
Sep 18 11:23:51 PM UTC 24 |
Sep 18 11:27:08 PM UTC 24 |
14358302911 ps |
| T2491 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.3020418364 |
|
|
Sep 18 11:17:29 PM UTC 24 |
Sep 18 11:27:14 PM UTC 24 |
15116223239 ps |
| T2492 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.2573632740 |
|
|
Sep 18 11:09:22 PM UTC 24 |
Sep 18 11:27:16 PM UTC 24 |
64897451935 ps |
| T2493 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.1593273000 |
|
|
Sep 18 11:26:29 PM UTC 24 |
Sep 18 11:27:20 PM UTC 24 |
988743819 ps |
| T2494 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.3424762998 |
|
|
Sep 18 11:26:11 PM UTC 24 |
Sep 18 11:27:20 PM UTC 24 |
4628075454 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.3206939226 |
|
|
Sep 18 11:16:25 PM UTC 24 |
Sep 18 11:27:28 PM UTC 24 |
11810948742 ps |
| T2495 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.2186647447 |
|
|
Sep 18 11:25:44 PM UTC 24 |
Sep 18 11:27:30 PM UTC 24 |
10387212713 ps |
| T2496 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.2668064159 |
|
|
Sep 18 11:27:07 PM UTC 24 |
Sep 18 11:27:31 PM UTC 24 |
293134258 ps |
| T2497 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.1555277120 |
|
|
Sep 18 11:27:03 PM UTC 24 |
Sep 18 11:27:32 PM UTC 24 |
310883427 ps |
| T2498 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.16697426 |
|
|
Sep 18 11:27:16 PM UTC 24 |
Sep 18 11:27:44 PM UTC 24 |
323712061 ps |
| T2499 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.2134456135 |
|
|
Sep 18 11:12:55 PM UTC 24 |
Sep 18 11:27:50 PM UTC 24 |
65216691431 ps |
| T2500 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.565680330 |
|
|
Sep 18 11:27:24 PM UTC 24 |
Sep 18 11:27:57 PM UTC 24 |
335777243 ps |
| T2501 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.2790987697 |
|
|
Sep 18 11:27:36 PM UTC 24 |
Sep 18 11:28:00 PM UTC 24 |
560470259 ps |
| T2502 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.338602502 |
|
|
Sep 18 11:26:53 PM UTC 24 |
Sep 18 11:28:03 PM UTC 24 |
7004755246 ps |
| T2503 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.75207271 |
|
|
Sep 18 11:27:56 PM UTC 24 |
Sep 18 11:28:06 PM UTC 24 |
49498864 ps |
| T2504 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.3894957878 |
|
|
Sep 18 11:24:17 PM UTC 24 |
Sep 18 11:28:07 PM UTC 24 |
3268410651 ps |
| T2505 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.239777360 |
|
|
Sep 18 11:27:58 PM UTC 24 |
Sep 18 11:28:10 PM UTC 24 |
183445770 ps |
| T2506 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.2687786507 |
|
|
Sep 18 11:26:00 PM UTC 24 |
Sep 18 11:28:10 PM UTC 24 |
6691435856 ps |
| T2507 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.100987738 |
|
|
Sep 18 11:27:47 PM UTC 24 |
Sep 18 11:28:10 PM UTC 24 |
71706432 ps |
| T2508 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.4287371256 |
|
|
Sep 18 11:27:00 PM UTC 24 |
Sep 18 11:28:13 PM UTC 24 |
5141623288 ps |
| T2509 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.2138798986 |
|
|
Sep 18 11:25:13 PM UTC 24 |
Sep 18 11:28:13 PM UTC 24 |
11807223210 ps |
| T2510 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.1658556704 |
|
|
Sep 18 11:27:44 PM UTC 24 |
Sep 18 11:28:23 PM UTC 24 |
1063680596 ps |
| T2511 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.3545372990 |
|
|
Sep 18 11:27:36 PM UTC 24 |
Sep 18 11:28:27 PM UTC 24 |
313139940 ps |
| T2512 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.3810967852 |
|
|
Sep 18 11:28:17 PM UTC 24 |
Sep 18 11:28:38 PM UTC 24 |
237658026 ps |
| T2513 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.4099367327 |
|
|
Sep 18 11:27:33 PM UTC 24 |
Sep 18 11:28:45 PM UTC 24 |
2302347331 ps |