| T1580 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.176229504 |
|
|
Sep 18 10:20:01 PM UTC 24 |
Sep 18 10:20:17 PM UTC 24 |
286521960 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.2421721898 |
|
|
Sep 18 10:19:32 PM UTC 24 |
Sep 18 10:20:20 PM UTC 24 |
965162029 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.1638420154 |
|
|
Sep 18 10:11:00 PM UTC 24 |
Sep 18 10:20:28 PM UTC 24 |
5957663590 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.4074756086 |
|
|
Sep 18 10:19:30 PM UTC 24 |
Sep 18 10:20:31 PM UTC 24 |
2455540172 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.3913198673 |
|
|
Sep 18 10:06:50 PM UTC 24 |
Sep 18 10:20:31 PM UTC 24 |
8065382048 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.2219006237 |
|
|
Sep 18 10:20:25 PM UTC 24 |
Sep 18 10:20:35 PM UTC 24 |
69337575 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.3958181192 |
|
|
Sep 18 10:19:17 PM UTC 24 |
Sep 18 10:20:37 PM UTC 24 |
2007969620 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.2713709047 |
|
|
Sep 18 10:15:22 PM UTC 24 |
Sep 18 10:20:42 PM UTC 24 |
4579233920 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.2764451952 |
|
|
Sep 18 10:20:25 PM UTC 24 |
Sep 18 10:20:51 PM UTC 24 |
433730365 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.606326422 |
|
|
Sep 18 10:15:06 PM UTC 24 |
Sep 18 10:20:52 PM UTC 24 |
4229063202 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.703969816 |
|
|
Sep 18 10:16:57 PM UTC 24 |
Sep 18 10:20:54 PM UTC 24 |
5854708603 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.2345128148 |
|
|
Sep 18 10:19:47 PM UTC 24 |
Sep 18 10:21:01 PM UTC 24 |
2093040682 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.1338193102 |
|
|
Sep 18 10:19:10 PM UTC 24 |
Sep 18 10:21:08 PM UTC 24 |
6556630275 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.887952812 |
|
|
Sep 18 10:10:23 PM UTC 24 |
Sep 18 10:21:09 PM UTC 24 |
35915136146 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.856950575 |
|
|
Sep 18 10:21:03 PM UTC 24 |
Sep 18 10:21:14 PM UTC 24 |
211799730 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.700799656 |
|
|
Sep 18 10:21:06 PM UTC 24 |
Sep 18 10:21:16 PM UTC 24 |
52006959 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.4257463543 |
|
|
Sep 18 10:15:08 PM UTC 24 |
Sep 18 10:21:18 PM UTC 24 |
3366458123 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.512658511 |
|
|
Sep 18 10:20:57 PM UTC 24 |
Sep 18 10:21:20 PM UTC 24 |
43736587 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.3094134617 |
|
|
Sep 18 10:19:10 PM UTC 24 |
Sep 18 10:21:21 PM UTC 24 |
8535769975 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.2139862596 |
|
|
Sep 18 09:58:02 PM UTC 24 |
Sep 18 10:21:28 PM UTC 24 |
113543756913 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.336294168 |
|
|
Sep 18 10:18:27 PM UTC 24 |
Sep 18 10:21:38 PM UTC 24 |
526975793 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.2255215421 |
|
|
Sep 18 10:18:35 PM UTC 24 |
Sep 18 10:21:41 PM UTC 24 |
1636705285 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.3294976696 |
|
|
Sep 18 10:21:22 PM UTC 24 |
Sep 18 10:21:52 PM UTC 24 |
291219339 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.114613757 |
|
|
Sep 18 10:21:43 PM UTC 24 |
Sep 18 10:21:57 PM UTC 24 |
94129409 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.1176561612 |
|
|
Sep 18 10:18:42 PM UTC 24 |
Sep 18 10:22:04 PM UTC 24 |
3835076892 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.4282642037 |
|
|
Sep 18 10:21:45 PM UTC 24 |
Sep 18 10:22:07 PM UTC 24 |
358188254 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.2054664155 |
|
|
Sep 18 10:21:48 PM UTC 24 |
Sep 18 10:22:12 PM UTC 24 |
191672315 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.878961791 |
|
|
Sep 18 10:13:14 PM UTC 24 |
Sep 18 10:22:14 PM UTC 24 |
16421041081 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.2216573872 |
|
|
Sep 18 10:15:53 PM UTC 24 |
Sep 18 10:22:14 PM UTC 24 |
25652920275 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.2796651523 |
|
|
Sep 18 10:21:21 PM UTC 24 |
Sep 18 10:22:18 PM UTC 24 |
1294131398 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.2707747911 |
|
|
Sep 18 10:22:09 PM UTC 24 |
Sep 18 10:22:23 PM UTC 24 |
244174300 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.1814724511 |
|
|
Sep 18 10:17:07 PM UTC 24 |
Sep 18 10:22:26 PM UTC 24 |
3725233905 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.212057692 |
|
|
Sep 18 10:13:31 PM UTC 24 |
Sep 18 10:22:27 PM UTC 24 |
4082419036 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.2592621459 |
|
|
Sep 18 10:21:52 PM UTC 24 |
Sep 18 10:22:29 PM UTC 24 |
289738484 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.1908541061 |
|
|
Sep 18 10:21:38 PM UTC 24 |
Sep 18 10:22:29 PM UTC 24 |
434477732 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.526489949 |
|
|
Sep 18 10:22:24 PM UTC 24 |
Sep 18 10:22:32 PM UTC 24 |
189420583 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.588410867 |
|
|
Sep 18 10:20:51 PM UTC 24 |
Sep 18 10:22:39 PM UTC 24 |
1438327732 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.825131364 |
|
|
Sep 18 10:22:32 PM UTC 24 |
Sep 18 10:22:42 PM UTC 24 |
45191917 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.682718245 |
|
|
Sep 18 10:17:30 PM UTC 24 |
Sep 18 10:22:51 PM UTC 24 |
33102238552 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.160617944 |
|
|
Sep 18 10:21:14 PM UTC 24 |
Sep 18 10:23:02 PM UTC 24 |
5574519147 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.2830337473 |
|
|
Sep 18 10:18:27 PM UTC 24 |
Sep 18 10:23:05 PM UTC 24 |
3688840753 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.3841120526 |
|
|
Sep 18 10:21:08 PM UTC 24 |
Sep 18 10:23:07 PM UTC 24 |
10263951043 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.789592337 |
|
|
Sep 18 10:22:59 PM UTC 24 |
Sep 18 10:23:11 PM UTC 24 |
145575123 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.1071399316 |
|
|
Sep 18 10:18:03 PM UTC 24 |
Sep 18 10:23:25 PM UTC 24 |
8982879218 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.4178346718 |
|
|
Sep 18 10:13:00 PM UTC 24 |
Sep 18 10:23:33 PM UTC 24 |
3825491524 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.2768234582 |
|
|
Sep 18 09:58:13 PM UTC 24 |
Sep 18 10:23:34 PM UTC 24 |
94304404645 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.1477647676 |
|
|
Sep 18 10:22:44 PM UTC 24 |
Sep 18 10:23:39 PM UTC 24 |
541057739 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.2407969530 |
|
|
Sep 18 10:23:10 PM UTC 24 |
Sep 18 10:23:42 PM UTC 24 |
254175183 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.1540156563 |
|
|
Sep 18 10:22:44 PM UTC 24 |
Sep 18 10:23:45 PM UTC 24 |
1136003457 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.3126112218 |
|
|
Sep 18 10:23:04 PM UTC 24 |
Sep 18 10:23:48 PM UTC 24 |
266294773 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.2888405158 |
|
|
Sep 18 10:22:39 PM UTC 24 |
Sep 18 10:23:50 PM UTC 24 |
7452175275 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.3832238464 |
|
|
Sep 18 10:22:43 PM UTC 24 |
Sep 18 10:23:51 PM UTC 24 |
4087675304 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.3508693552 |
|
|
Sep 18 10:23:42 PM UTC 24 |
Sep 18 10:23:52 PM UTC 24 |
45775667 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.3318421494 |
|
|
Sep 18 10:23:01 PM UTC 24 |
Sep 18 10:23:55 PM UTC 24 |
515556252 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.3955243897 |
|
|
Sep 18 10:23:56 PM UTC 24 |
Sep 18 10:24:06 PM UTC 24 |
45097844 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.3053212914 |
|
|
Sep 18 10:22:56 PM UTC 24 |
Sep 18 10:24:09 PM UTC 24 |
1934906055 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.1631150584 |
|
|
Sep 18 10:22:55 PM UTC 24 |
Sep 18 10:24:12 PM UTC 24 |
3778975041 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.1740609837 |
|
|
Sep 18 10:07:49 PM UTC 24 |
Sep 18 10:24:14 PM UTC 24 |
52619510551 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.2638253354 |
|
|
Sep 18 10:24:12 PM UTC 24 |
Sep 18 10:24:22 PM UTC 24 |
58447678 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.2860441943 |
|
|
Sep 18 10:04:58 PM UTC 24 |
Sep 18 10:24:24 PM UTC 24 |
93280440983 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.3907209406 |
|
|
Sep 18 10:24:08 PM UTC 24 |
Sep 18 10:24:35 PM UTC 24 |
612503581 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.99665364 |
|
|
Sep 18 10:24:20 PM UTC 24 |
Sep 18 10:24:53 PM UTC 24 |
384800224 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.1486080905 |
|
|
Sep 18 10:24:40 PM UTC 24 |
Sep 18 10:24:55 PM UTC 24 |
210064524 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3356754425 |
|
|
Sep 18 10:23:35 PM UTC 24 |
Sep 18 10:24:58 PM UTC 24 |
185045028 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.1082868747 |
|
|
Sep 18 10:24:23 PM UTC 24 |
Sep 18 10:25:09 PM UTC 24 |
389139431 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.2733624755 |
|
|
Sep 18 09:29:01 PM UTC 24 |
Sep 18 10:25:17 PM UTC 24 |
31287841124 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.2660192911 |
|
|
Sep 18 10:24:05 PM UTC 24 |
Sep 18 10:25:20 PM UTC 24 |
5317060694 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.413120524 |
|
|
Sep 18 10:25:26 PM UTC 24 |
Sep 18 10:25:36 PM UTC 24 |
51000322 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.556537707 |
|
|
Sep 18 10:25:22 PM UTC 24 |
Sep 18 10:25:36 PM UTC 24 |
190587131 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.638278394 |
|
|
Sep 18 10:24:04 PM UTC 24 |
Sep 18 10:25:38 PM UTC 24 |
8912615274 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.4076765496 |
|
|
Sep 18 10:24:21 PM UTC 24 |
Sep 18 10:25:47 PM UTC 24 |
2095345080 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.2909550219 |
|
|
Sep 18 09:32:32 PM UTC 24 |
Sep 18 10:25:48 PM UTC 24 |
30888846774 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.4155260835 |
|
|
Sep 18 10:24:36 PM UTC 24 |
Sep 18 10:25:50 PM UTC 24 |
1233268031 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.1531099603 |
|
|
Sep 18 10:25:49 PM UTC 24 |
Sep 18 10:26:03 PM UTC 24 |
73930861 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.1307626732 |
|
|
Sep 18 10:25:45 PM UTC 24 |
Sep 18 10:26:26 PM UTC 24 |
1172392502 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.2732989684 |
|
|
Sep 18 10:22:49 PM UTC 24 |
Sep 18 10:26:33 PM UTC 24 |
18928554019 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.30575481 |
|
|
Sep 18 10:25:41 PM UTC 24 |
Sep 18 10:26:34 PM UTC 24 |
3831803237 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.113278589 |
|
|
Sep 18 10:24:56 PM UTC 24 |
Sep 18 10:26:39 PM UTC 24 |
838557294 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.3869815874 |
|
|
Sep 18 10:12:13 PM UTC 24 |
Sep 18 10:26:42 PM UTC 24 |
61594133024 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.3966742568 |
|
|
Sep 18 10:26:34 PM UTC 24 |
Sep 18 10:26:47 PM UTC 24 |
58052808 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.345808957 |
|
|
Sep 18 10:25:28 PM UTC 24 |
Sep 18 10:26:49 PM UTC 24 |
7575611151 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.2305320503 |
|
|
Sep 18 10:16:53 PM UTC 24 |
Sep 18 10:26:50 PM UTC 24 |
10434078120 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.2665557342 |
|
|
Sep 18 10:23:13 PM UTC 24 |
Sep 18 10:26:51 PM UTC 24 |
1981040593 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.2138417373 |
|
|
Sep 18 10:26:19 PM UTC 24 |
Sep 18 10:26:56 PM UTC 24 |
444167471 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.1560672288 |
|
|
Sep 18 10:26:22 PM UTC 24 |
Sep 18 10:27:03 PM UTC 24 |
481418238 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.2690642479 |
|
|
Sep 18 09:54:48 PM UTC 24 |
Sep 18 10:27:27 PM UTC 24 |
16592821807 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.1745582598 |
|
|
Sep 18 10:20:59 PM UTC 24 |
Sep 18 10:27:27 PM UTC 24 |
4846367696 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.2586533010 |
|
|
Sep 18 10:26:54 PM UTC 24 |
Sep 18 10:27:27 PM UTC 24 |
288246730 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.1243739633 |
|
|
Sep 18 10:26:03 PM UTC 24 |
Sep 18 10:27:28 PM UTC 24 |
1033182374 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.2459480122 |
|
|
Sep 18 10:27:19 PM UTC 24 |
Sep 18 10:27:29 PM UTC 24 |
44848435 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.316740157 |
|
|
Sep 18 10:27:17 PM UTC 24 |
Sep 18 10:27:31 PM UTC 24 |
222047795 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.3590576370 |
|
|
Sep 18 10:23:39 PM UTC 24 |
Sep 18 10:27:46 PM UTC 24 |
3309454819 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.1494892216 |
|
|
Sep 18 10:21:44 PM UTC 24 |
Sep 18 10:27:51 PM UTC 24 |
8006859644 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.2915675458 |
|
|
Sep 18 10:21:30 PM UTC 24 |
Sep 18 10:27:58 PM UTC 24 |
28213546073 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.745445337 |
|
|
Sep 18 10:27:12 PM UTC 24 |
Sep 18 10:28:04 PM UTC 24 |
89670340 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.2519038809 |
|
|
Sep 18 09:53:00 PM UTC 24 |
Sep 18 10:28:11 PM UTC 24 |
15542558641 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.4187742746 |
|
|
Sep 18 10:22:22 PM UTC 24 |
Sep 18 10:28:16 PM UTC 24 |
4706436744 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.3181933767 |
|
|
Sep 18 10:27:33 PM UTC 24 |
Sep 18 10:28:18 PM UTC 24 |
858241845 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.1660918405 |
|
|
Sep 18 10:16:15 PM UTC 24 |
Sep 18 10:28:23 PM UTC 24 |
46382223449 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.2370408673 |
|
|
Sep 18 10:22:13 PM UTC 24 |
Sep 18 10:28:28 PM UTC 24 |
7993677614 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.2862655214 |
|
|
Sep 18 10:28:02 PM UTC 24 |
Sep 18 10:28:28 PM UTC 24 |
268362897 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.2057310201 |
|
|
Sep 18 10:27:21 PM UTC 24 |
Sep 18 10:28:29 PM UTC 24 |
7590468248 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.1390104079 |
|
|
Sep 18 10:22:00 PM UTC 24 |
Sep 18 10:28:29 PM UTC 24 |
6466148859 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.1962605688 |
|
|
Sep 18 10:27:56 PM UTC 24 |
Sep 18 10:28:30 PM UTC 24 |
313582647 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.2977776968 |
|
|
Sep 18 10:23:22 PM UTC 24 |
Sep 18 10:28:32 PM UTC 24 |
3250482848 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.173301948 |
|
|
Sep 18 10:24:49 PM UTC 24 |
Sep 18 10:28:38 PM UTC 24 |
6290146599 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.4000727392 |
|
|
Sep 18 09:50:27 PM UTC 24 |
Sep 18 10:28:39 PM UTC 24 |
16599356240 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.1803292570 |
|
|
Sep 18 10:28:21 PM UTC 24 |
Sep 18 10:28:39 PM UTC 24 |
243281999 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.2016994723 |
|
|
Sep 18 10:25:05 PM UTC 24 |
Sep 18 10:28:44 PM UTC 24 |
2934618450 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.2732913941 |
|
|
Sep 18 10:27:04 PM UTC 24 |
Sep 18 10:28:49 PM UTC 24 |
2597293482 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.809944444 |
|
|
Sep 18 10:20:43 PM UTC 24 |
Sep 18 10:28:59 PM UTC 24 |
13996019068 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.1353940256 |
|
|
Sep 18 10:28:51 PM UTC 24 |
Sep 18 10:28:59 PM UTC 24 |
131980342 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.2485151625 |
|
|
Sep 18 10:15:53 PM UTC 24 |
Sep 18 10:29:01 PM UTC 24 |
67495218123 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2443523285 |
|
|
Sep 18 10:28:54 PM UTC 24 |
Sep 18 10:29:04 PM UTC 24 |
42857192 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.818755173 |
|
|
Sep 18 10:28:59 PM UTC 24 |
Sep 18 10:29:10 PM UTC 24 |
131243012 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.1601776143 |
|
|
Sep 18 10:24:41 PM UTC 24 |
Sep 18 10:29:11 PM UTC 24 |
6028051774 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.2083990009 |
|
|
Sep 18 10:28:26 PM UTC 24 |
Sep 18 10:29:13 PM UTC 24 |
859164123 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.2104844363 |
|
|
Sep 18 10:28:14 PM UTC 24 |
Sep 18 10:29:18 PM UTC 24 |
607093426 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.2678450868 |
|
|
Sep 18 10:27:24 PM UTC 24 |
Sep 18 10:29:22 PM UTC 24 |
6362459063 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.3536705235 |
|
|
Sep 18 10:28:58 PM UTC 24 |
Sep 18 10:29:33 PM UTC 24 |
347980874 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.2040660388 |
|
|
Sep 18 10:29:30 PM UTC 24 |
Sep 18 10:29:39 PM UTC 24 |
24929287 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.89189586 |
|
|
Sep 18 10:29:26 PM UTC 24 |
Sep 18 10:29:42 PM UTC 24 |
202420995 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.1839113060 |
|
|
Sep 18 10:29:11 PM UTC 24 |
Sep 18 10:29:49 PM UTC 24 |
762048483 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.3606916646 |
|
|
Sep 18 10:29:41 PM UTC 24 |
Sep 18 10:29:53 PM UTC 24 |
155192783 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.982757128 |
|
|
Sep 18 10:24:19 PM UTC 24 |
Sep 18 10:29:54 PM UTC 24 |
21028531683 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.3111206026 |
|
|
Sep 18 10:29:45 PM UTC 24 |
Sep 18 10:29:55 PM UTC 24 |
53833108 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.2905032246 |
|
|
Sep 18 10:27:08 PM UTC 24 |
Sep 18 10:29:57 PM UTC 24 |
4988516976 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.2197189029 |
|
|
Sep 18 10:28:33 PM UTC 24 |
Sep 18 10:30:00 PM UTC 24 |
819631741 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.2384989608 |
|
|
Sep 18 10:27:16 PM UTC 24 |
Sep 18 10:30:04 PM UTC 24 |
3593760947 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.1696100274 |
|
|
Sep 18 10:26:06 PM UTC 24 |
Sep 18 10:30:07 PM UTC 24 |
18612119948 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.1836202135 |
|
|
Sep 18 10:29:10 PM UTC 24 |
Sep 18 10:30:14 PM UTC 24 |
2170021964 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.3001810499 |
|
|
Sep 18 10:30:08 PM UTC 24 |
Sep 18 10:30:22 PM UTC 24 |
236320374 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.3763694946 |
|
|
Sep 18 10:28:57 PM UTC 24 |
Sep 18 10:30:25 PM UTC 24 |
5953210734 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.3716938112 |
|
|
Sep 18 10:28:44 PM UTC 24 |
Sep 18 10:30:27 PM UTC 24 |
2579316433 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.2588296024 |
|
|
Sep 18 10:29:08 PM UTC 24 |
Sep 18 10:30:36 PM UTC 24 |
1125458713 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.2692002719 |
|
|
Sep 18 10:27:58 PM UTC 24 |
Sep 18 10:30:39 PM UTC 24 |
3427691939 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.733987722 |
|
|
Sep 18 10:23:32 PM UTC 24 |
Sep 18 10:30:42 PM UTC 24 |
13012777998 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.2755788630 |
|
|
Sep 18 10:30:14 PM UTC 24 |
Sep 18 10:30:43 PM UTC 24 |
244691055 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.3268787706 |
|
|
Sep 18 10:30:27 PM UTC 24 |
Sep 18 10:30:48 PM UTC 24 |
463430697 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.2771420632 |
|
|
Sep 18 10:28:59 PM UTC 24 |
Sep 18 10:30:55 PM UTC 24 |
9764105393 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.3951040882 |
|
|
Sep 18 10:30:38 PM UTC 24 |
Sep 18 10:30:58 PM UTC 24 |
185398302 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.872915526 |
|
|
Sep 18 10:14:19 PM UTC 24 |
Sep 18 10:31:01 PM UTC 24 |
65963334042 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.1881929977 |
|
|
Sep 18 10:10:19 PM UTC 24 |
Sep 18 10:31:01 PM UTC 24 |
114196585544 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.2316914531 |
|
|
Sep 18 10:27:58 PM UTC 24 |
Sep 18 10:31:02 PM UTC 24 |
10627769029 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.824288717 |
|
|
Sep 18 10:30:03 PM UTC 24 |
Sep 18 10:31:04 PM UTC 24 |
4456157975 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.2973098689 |
|
|
Sep 18 10:30:30 PM UTC 24 |
Sep 18 10:31:06 PM UTC 24 |
909360907 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.1981203 |
|
|
Sep 18 10:30:24 PM UTC 24 |
Sep 18 10:31:09 PM UTC 24 |
481714045 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.1516800268 |
|
|
Sep 18 10:31:03 PM UTC 24 |
Sep 18 10:31:13 PM UTC 24 |
51994578 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.2867139191 |
|
|
Sep 18 10:31:06 PM UTC 24 |
Sep 18 10:31:13 PM UTC 24 |
45690568 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.2812577630 |
|
|
Sep 18 10:36:39 PM UTC 24 |
Sep 18 10:36:52 PM UTC 24 |
65134358 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.4220177269 |
|
|
Sep 18 10:20:44 PM UTC 24 |
Sep 18 10:31:19 PM UTC 24 |
5138873304 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.3377624994 |
|
|
Sep 18 10:30:33 PM UTC 24 |
Sep 18 10:31:27 PM UTC 24 |
1236059963 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.4227010501 |
|
|
Sep 18 10:29:51 PM UTC 24 |
Sep 18 10:31:33 PM UTC 24 |
9279242837 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.1642977784 |
|
|
Sep 18 10:31:23 PM UTC 24 |
Sep 18 10:31:35 PM UTC 24 |
100462128 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.1223738471 |
|
|
Sep 18 10:31:28 PM UTC 24 |
Sep 18 10:31:46 PM UTC 24 |
201022515 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.1716960387 |
|
|
Sep 18 10:31:37 PM UTC 24 |
Sep 18 10:32:06 PM UTC 24 |
557285847 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.282792637 |
|
|
Sep 18 10:32:05 PM UTC 24 |
Sep 18 10:32:14 PM UTC 24 |
45878358 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.3455612777 |
|
|
Sep 18 10:31:38 PM UTC 24 |
Sep 18 10:32:16 PM UTC 24 |
288529634 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.3333930804 |
|
|
Sep 18 10:27:01 PM UTC 24 |
Sep 18 10:32:19 PM UTC 24 |
6284949470 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.318431818 |
|
|
Sep 18 10:32:17 PM UTC 24 |
Sep 18 10:32:28 PM UTC 24 |
53655678 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.3276336343 |
|
|
Sep 18 10:31:19 PM UTC 24 |
Sep 18 10:32:28 PM UTC 24 |
1608792104 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.1797799817 |
|
|
Sep 18 10:26:18 PM UTC 24 |
Sep 18 10:32:29 PM UTC 24 |
23057315391 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.926436989 |
|
|
Sep 18 10:30:57 PM UTC 24 |
Sep 18 10:32:29 PM UTC 24 |
203076663 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.2753902871 |
|
|
Sep 18 10:31:38 PM UTC 24 |
Sep 18 10:32:43 PM UTC 24 |
1351090198 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.2646507839 |
|
|
Sep 18 10:31:31 PM UTC 24 |
Sep 18 10:32:44 PM UTC 24 |
882867295 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.1337488582 |
|
|
Sep 18 10:17:43 PM UTC 24 |
Sep 18 10:32:54 PM UTC 24 |
59010266235 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.1690732339 |
|
|
Sep 18 10:30:45 PM UTC 24 |
Sep 18 10:32:56 PM UTC 24 |
3673137354 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.2686974844 |
|
|
Sep 18 10:19:30 PM UTC 24 |
Sep 18 10:33:02 PM UTC 24 |
74862138873 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.710731300 |
|
|
Sep 18 10:31:09 PM UTC 24 |
Sep 18 10:33:12 PM UTC 24 |
5456829984 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.3424816467 |
|
|
Sep 18 10:31:51 PM UTC 24 |
Sep 18 10:33:17 PM UTC 24 |
90454354 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.3817541297 |
|
|
Sep 18 10:32:45 PM UTC 24 |
Sep 18 10:33:18 PM UTC 24 |
256267049 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.3640712397 |
|
|
Sep 18 10:27:58 PM UTC 24 |
Sep 18 10:33:23 PM UTC 24 |
32831690238 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.3657063542 |
|
|
Sep 18 10:33:15 PM UTC 24 |
Sep 18 10:33:32 PM UTC 24 |
269200968 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.1363097793 |
|
|
Sep 18 10:33:25 PM UTC 24 |
Sep 18 10:33:37 PM UTC 24 |
53027600 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.3412921551 |
|
|
Sep 18 10:33:12 PM UTC 24 |
Sep 18 10:33:39 PM UTC 24 |
319570635 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.3445792320 |
|
|
Sep 18 10:31:11 PM UTC 24 |
Sep 18 10:33:41 PM UTC 24 |
10192135405 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.2678178631 |
|
|
Sep 18 10:32:46 PM UTC 24 |
Sep 18 10:33:41 PM UTC 24 |
549205048 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.2280554613 |
|
|
Sep 18 10:28:48 PM UTC 24 |
Sep 18 10:33:42 PM UTC 24 |
1870639887 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.2075625114 |
|
|
Sep 18 10:30:53 PM UTC 24 |
Sep 18 10:33:48 PM UTC 24 |
2297561873 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.1697218356 |
|
|
Sep 18 10:29:38 PM UTC 24 |
Sep 18 10:33:52 PM UTC 24 |
6488810797 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.3809321559 |
|
|
Sep 18 09:46:03 PM UTC 24 |
Sep 18 10:33:54 PM UTC 24 |
29090605691 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.3685034408 |
|
|
Sep 18 10:32:03 PM UTC 24 |
Sep 18 10:33:56 PM UTC 24 |
252632996 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.3067246342 |
|
|
Sep 18 10:31:43 PM UTC 24 |
Sep 18 10:34:01 PM UTC 24 |
3485734583 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.2765322358 |
|
|
Sep 18 10:33:53 PM UTC 24 |
Sep 18 10:34:02 PM UTC 24 |
37413372 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.1669799615 |
|
|
Sep 18 10:24:42 PM UTC 24 |
Sep 18 10:34:03 PM UTC 24 |
10531548433 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.3772711365 |
|
|
Sep 18 10:32:37 PM UTC 24 |
Sep 18 10:34:08 PM UTC 24 |
6175766607 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.2349769213 |
|
|
Sep 18 10:32:58 PM UTC 24 |
Sep 18 10:34:09 PM UTC 24 |
1363239693 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.2339619581 |
|
|
Sep 18 10:34:02 PM UTC 24 |
Sep 18 10:34:10 PM UTC 24 |
39093108 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.3285893363 |
|
|
Sep 18 10:29:37 PM UTC 24 |
Sep 18 10:34:15 PM UTC 24 |
1268679511 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.2253812029 |
|
|
Sep 18 10:33:26 PM UTC 24 |
Sep 18 10:34:17 PM UTC 24 |
772365693 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.1015002764 |
|
|
Sep 18 10:32:44 PM UTC 24 |
Sep 18 10:34:17 PM UTC 24 |
5957818006 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.1029144108 |
|
|
Sep 18 10:30:53 PM UTC 24 |
Sep 18 10:34:18 PM UTC 24 |
571368584 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.146034345 |
|
|
Sep 18 10:34:09 PM UTC 24 |
Sep 18 10:34:26 PM UTC 24 |
105226237 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2827349568 |
|
|
Sep 18 10:33:45 PM UTC 24 |
Sep 18 10:34:27 PM UTC 24 |
145144891 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.3995132874 |
|
|
Sep 18 10:34:09 PM UTC 24 |
Sep 18 10:34:32 PM UTC 24 |
684547098 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.487746161 |
|
|
Sep 18 10:34:32 PM UTC 24 |
Sep 18 10:34:39 PM UTC 24 |
21538536 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.1747877699 |
|
|
Sep 18 10:17:44 PM UTC 24 |
Sep 18 10:34:42 PM UTC 24 |
74581086117 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.3453827549 |
|
|
Sep 18 10:31:58 PM UTC 24 |
Sep 18 10:34:47 PM UTC 24 |
2633607710 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.1695742359 |
|
|
Sep 18 10:34:25 PM UTC 24 |
Sep 18 10:34:52 PM UTC 24 |
212891444 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.2862193323 |
|
|
Sep 18 10:34:27 PM UTC 24 |
Sep 18 10:34:52 PM UTC 24 |
466790094 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.551924830 |
|
|
Sep 18 10:33:47 PM UTC 24 |
Sep 18 10:34:54 PM UTC 24 |
1918914646 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.3251123344 |
|
|
Sep 18 10:34:45 PM UTC 24 |
Sep 18 10:34:55 PM UTC 24 |
42899434 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.2411995071 |
|
|
Sep 18 10:34:34 PM UTC 24 |
Sep 18 10:34:59 PM UTC 24 |
215660776 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.2344443295 |
|
|
Sep 18 10:34:47 PM UTC 24 |
Sep 18 10:35:01 PM UTC 24 |
194082462 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.3399990714 |
|
|
Sep 18 10:34:55 PM UTC 24 |
Sep 18 10:35:05 PM UTC 24 |
37034839 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.2818696237 |
|
|
Sep 18 10:34:20 PM UTC 24 |
Sep 18 10:35:07 PM UTC 24 |
743894443 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.160020395 |
|
|
Sep 18 10:34:07 PM UTC 24 |
Sep 18 10:35:22 PM UTC 24 |
3706861447 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.239116827 |
|
|
Sep 18 10:34:55 PM UTC 24 |
Sep 18 10:35:23 PM UTC 24 |
225713575 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.1632366543 |
|
|
Sep 18 10:29:31 PM UTC 24 |
Sep 18 10:35:24 PM UTC 24 |
3694552923 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.2581401221 |
|
|
Sep 18 10:33:41 PM UTC 24 |
Sep 18 10:35:33 PM UTC 24 |
328011506 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.1305805364 |
|
|
Sep 18 10:28:42 PM UTC 24 |
Sep 18 10:35:44 PM UTC 24 |
2315938566 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.3629382995 |
|
|
Sep 18 10:35:23 PM UTC 24 |
Sep 18 10:35:46 PM UTC 24 |
444811858 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.2331817554 |
|
|
Sep 18 10:35:22 PM UTC 24 |
Sep 18 10:35:47 PM UTC 24 |
482734694 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.2052144140 |
|
|
Sep 18 10:34:09 PM UTC 24 |
Sep 18 10:35:48 PM UTC 24 |
11064810794 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.3643133003 |
|
|
Sep 18 10:34:43 PM UTC 24 |
Sep 18 10:35:49 PM UTC 24 |
7158479024 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.3530657353 |
|
|
Sep 18 10:35:22 PM UTC 24 |
Sep 18 10:35:53 PM UTC 24 |
887467718 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.3098507513 |
|
|
Sep 18 10:29:05 PM UTC 24 |
Sep 18 10:35:56 PM UTC 24 |
25858719143 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.3827392215 |
|
|
Sep 18 10:35:53 PM UTC 24 |
Sep 18 10:36:02 PM UTC 24 |
45945586 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.2264229097 |
|
|
Sep 18 10:35:52 PM UTC 24 |
Sep 18 10:36:06 PM UTC 24 |
199168620 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.4088314677 |
|
|
Sep 18 10:35:16 PM UTC 24 |
Sep 18 10:36:17 PM UTC 24 |
1552022538 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.2687148310 |
|
|
Sep 18 10:33:32 PM UTC 24 |
Sep 18 10:36:18 PM UTC 24 |
4436085503 ps |
| T1763 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.3348144607 |
|
|
Sep 18 10:34:38 PM UTC 24 |
Sep 18 10:36:20 PM UTC 24 |
1285047014 ps |
| T1764 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.367802252 |
|
|
Sep 18 10:35:26 PM UTC 24 |
Sep 18 10:36:20 PM UTC 24 |
1237674398 ps |
| T1765 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.3254501639 |
|
|
Sep 18 10:34:53 PM UTC 24 |
Sep 18 10:36:23 PM UTC 24 |
4604594905 ps |
| T1766 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.703712709 |
|
|
Sep 18 10:36:32 PM UTC 24 |
Sep 18 10:36:42 PM UTC 24 |
37625506 ps |
| T1767 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.3209528489 |
|
|
Sep 18 10:07:00 PM UTC 24 |
Sep 18 10:36:48 PM UTC 24 |
14823459098 ps |
| T1768 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.2755643648 |
|
|
Sep 18 10:36:13 PM UTC 24 |
Sep 18 10:36:57 PM UTC 24 |
315989571 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.848255829 |
|
|
Sep 18 10:29:31 PM UTC 24 |
Sep 18 10:36:58 PM UTC 24 |
3974931162 ps |
| T1769 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.253593202 |
|
|
Sep 18 10:34:40 PM UTC 24 |
Sep 18 10:37:00 PM UTC 24 |
303406257 ps |
| T1770 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.954621306 |
|
|
Sep 18 10:36:13 PM UTC 24 |
Sep 18 10:37:05 PM UTC 24 |
441951847 ps |
| T1771 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.344805002 |
|
|
Sep 18 10:36:46 PM UTC 24 |
Sep 18 10:37:22 PM UTC 24 |
317194881 ps |
| T1772 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.1425836501 |
|
|
Sep 18 10:37:23 PM UTC 24 |
Sep 18 10:37:34 PM UTC 24 |
52978663 ps |
| T1773 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.3955196027 |
|
|
Sep 18 10:37:19 PM UTC 24 |
Sep 18 10:37:35 PM UTC 24 |
230365130 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.616264522 |
|
|
Sep 18 10:19:33 PM UTC 24 |
Sep 18 10:37:44 PM UTC 24 |
70181159113 ps |
| T1774 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.2513363042 |
|
|
Sep 18 10:36:31 PM UTC 24 |
Sep 18 10:37:48 PM UTC 24 |
2112962686 ps |
| T1775 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.1885915950 |
|
|
Sep 18 10:36:14 PM UTC 24 |
Sep 18 10:37:51 PM UTC 24 |
5594269351 ps |
| T1776 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.1206202575 |
|
|
Sep 18 10:37:37 PM UTC 24 |
Sep 18 10:38:05 PM UTC 24 |
278080766 ps |
| T1777 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.4287960469 |
|
|
Sep 18 10:36:22 PM UTC 24 |
Sep 18 10:38:06 PM UTC 24 |
2893223610 ps |
| T1778 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.3140229927 |
|
|
Sep 18 10:36:04 PM UTC 24 |
Sep 18 10:38:11 PM UTC 24 |
8122274912 ps |
| T1779 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.1033221418 |
|
|
Sep 18 10:30:23 PM UTC 24 |
Sep 18 10:38:14 PM UTC 24 |
26776775244 ps |
| T1780 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.2986219382 |
|
|
Sep 18 10:36:19 PM UTC 24 |
Sep 18 10:38:17 PM UTC 24 |
5278185001 ps |
| T1781 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.3536615394 |
|
|
Sep 18 10:37:30 PM UTC 24 |
Sep 18 10:38:25 PM UTC 24 |
1335986147 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.1126201393 |
|
|
Sep 18 10:12:19 PM UTC 24 |
Sep 18 10:38:27 PM UTC 24 |
98939560671 ps |
| T1782 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.2406004818 |
|
|
Sep 18 10:37:29 PM UTC 24 |
Sep 18 10:38:29 PM UTC 24 |
4236449568 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.1497083409 |
|
|
Sep 18 10:36:52 PM UTC 24 |
Sep 18 10:38:33 PM UTC 24 |
1369317146 ps |
| T1783 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.2634136464 |
|
|
Sep 18 10:37:27 PM UTC 24 |
Sep 18 10:38:53 PM UTC 24 |
8414286413 ps |
| T1784 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.1486695973 |
|
|
Sep 18 10:34:31 PM UTC 24 |
Sep 18 10:38:56 PM UTC 24 |
7763103260 ps |
| T1785 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.1923572765 |
|
|
Sep 18 10:38:15 PM UTC 24 |
Sep 18 10:38:57 PM UTC 24 |
383477156 ps |
| T1786 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.256199414 |
|
|
Sep 18 10:38:36 PM UTC 24 |
Sep 18 10:39:06 PM UTC 24 |
268782222 ps |
| T1787 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.2977445821 |
|
|
Sep 18 10:38:58 PM UTC 24 |
Sep 18 10:39:08 PM UTC 24 |
41000441 ps |