| T446 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2519224881 |
|
|
Sep 19 03:14:34 AM UTC 24 |
Sep 19 03:31:45 AM UTC 24 |
5748576990 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.2672346182 |
|
|
Sep 19 03:23:58 AM UTC 24 |
Sep 19 03:33:19 AM UTC 24 |
5181133166 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2440282610 |
|
|
Sep 19 03:27:05 AM UTC 24 |
Sep 19 03:34:13 AM UTC 24 |
4617414449 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.552993112 |
|
|
Sep 19 03:24:03 AM UTC 24 |
Sep 19 03:34:40 AM UTC 24 |
6142629390 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2225006453 |
|
|
Sep 19 02:54:06 AM UTC 24 |
Sep 19 03:35:04 AM UTC 24 |
26423262418 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2935260377 |
|
|
Sep 19 03:04:24 AM UTC 24 |
Sep 19 03:35:22 AM UTC 24 |
25054563962 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx1.327326572 |
|
|
Sep 19 03:26:06 AM UTC 24 |
Sep 19 03:35:34 AM UTC 24 |
4277625884 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.2821226672 |
|
|
Sep 19 03:24:02 AM UTC 24 |
Sep 19 03:35:36 AM UTC 24 |
5377967460 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.3941314745 |
|
|
Sep 19 03:32:12 AM UTC 24 |
Sep 19 03:35:40 AM UTC 24 |
4006994680 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx.1229883722 |
|
|
Sep 19 03:26:52 AM UTC 24 |
Sep 19 03:36:09 AM UTC 24 |
3682674180 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_virus.1605940233 |
|
|
Sep 19 03:12:19 AM UTC 24 |
Sep 19 03:36:23 AM UTC 24 |
5903928696 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1241641208 |
|
|
Sep 19 03:10:07 AM UTC 24 |
Sep 19 03:36:34 AM UTC 24 |
11115236112 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_rand_baudrate.2666102348 |
|
|
Sep 19 03:27:05 AM UTC 24 |
Sep 19 03:37:05 AM UTC 24 |
4682790660 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_tpm.1999752732 |
|
|
Sep 19 03:30:54 AM UTC 24 |
Sep 19 03:37:14 AM UTC 24 |
3295016682 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx2.932532616 |
|
|
Sep 19 03:26:55 AM UTC 24 |
Sep 19 03:37:32 AM UTC 24 |
4291399910 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.2477678290 |
|
|
Sep 19 03:29:01 AM UTC 24 |
Sep 19 03:37:35 AM UTC 24 |
4117783848 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx3.2370889940 |
|
|
Sep 19 03:26:55 AM UTC 24 |
Sep 19 03:38:14 AM UTC 24 |
4682862020 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.1821874057 |
|
|
Sep 19 03:32:15 AM UTC 24 |
Sep 19 03:38:17 AM UTC 24 |
2843422216 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx.467480904 |
|
|
Sep 19 03:28:01 AM UTC 24 |
Sep 19 03:39:49 AM UTC 24 |
4688122620 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.4155040918 |
|
|
Sep 19 03:39:04 AM UTC 24 |
Sep 19 03:40:35 AM UTC 24 |
1999106662 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2562173794 |
|
|
Sep 19 03:28:17 AM UTC 24 |
Sep 19 03:40:57 AM UTC 24 |
4692042102 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.1866318477 |
|
|
Sep 19 03:34:04 AM UTC 24 |
Sep 19 03:41:05 AM UTC 24 |
4190961250 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through.4026657371 |
|
|
Sep 19 03:32:14 AM UTC 24 |
Sep 19 03:41:10 AM UTC 24 |
5769290688 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3584481198 |
|
|
Sep 19 03:36:30 AM UTC 24 |
Sep 19 03:41:17 AM UTC 24 |
3314453940 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2368702860 |
|
|
Sep 19 03:35:50 AM UTC 24 |
Sep 19 03:41:26 AM UTC 24 |
4103385550 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through_collision.1610421016 |
|
|
Sep 19 03:32:31 AM UTC 24 |
Sep 19 03:41:42 AM UTC 24 |
5028440511 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_smoketest.2414203272 |
|
|
Sep 19 03:18:45 AM UTC 24 |
Sep 19 03:41:58 AM UTC 24 |
6610313180 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.87766416 |
|
|
Sep 19 03:29:01 AM UTC 24 |
Sep 19 03:42:20 AM UTC 24 |
5341595818 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3348746358 |
|
|
Sep 19 03:37:19 AM UTC 24 |
Sep 19 03:42:33 AM UTC 24 |
3237290000 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_entropy.661944662 |
|
|
Sep 19 03:37:15 AM UTC 24 |
Sep 19 03:42:35 AM UTC 24 |
2821731670 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init_reduced_freq.1179777578 |
|
|
Sep 19 03:09:10 AM UTC 24 |
Sep 19 03:43:10 AM UTC 24 |
23191533755 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.924395945 |
|
|
Sep 19 03:39:05 AM UTC 24 |
Sep 19 03:43:46 AM UTC 24 |
2494258880 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3885367796 |
|
|
Sep 19 03:42:49 AM UTC 24 |
Sep 19 03:44:45 AM UTC 24 |
2600891020 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1325864581 |
|
|
Sep 19 03:42:43 AM UTC 24 |
Sep 19 03:44:55 AM UTC 24 |
1926236907 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3428136802 |
|
|
Sep 19 03:35:23 AM UTC 24 |
Sep 19 03:45:20 AM UTC 24 |
5021527236 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops.617865698 |
|
|
Sep 19 03:34:54 AM UTC 24 |
Sep 19 03:45:25 AM UTC 24 |
4119046474 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pwm_pulses.1246379875 |
|
|
Sep 19 03:25:43 AM UTC 24 |
Sep 19 03:45:37 AM UTC 24 |
8837888176 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1155215796 |
|
|
Sep 19 02:32:43 AM UTC 24 |
Sep 19 03:46:55 AM UTC 24 |
17012306320 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_rst.3541003176 |
|
|
Sep 19 03:43:28 AM UTC 24 |
Sep 19 03:47:25 AM UTC 24 |
3135752880 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2088147583 |
|
|
Sep 19 03:38:04 AM UTC 24 |
Sep 19 03:48:48 AM UTC 24 |
4162888102 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_transition.1696651815 |
|
|
Sep 19 03:40:34 AM UTC 24 |
Sep 19 03:49:01 AM UTC 24 |
5879808529 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_self_hash.3474767810 |
|
|
Sep 19 01:46:37 AM UTC 24 |
Sep 19 03:50:12 AM UTC 24 |
26453999522 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2512678532 |
|
|
Sep 19 02:34:03 AM UTC 24 |
Sep 19 03:50:56 AM UTC 24 |
19236428284 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_req.121794868 |
|
|
Sep 19 03:43:22 AM UTC 24 |
Sep 19 03:52:34 AM UTC 24 |
5308850084 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2373501479 |
|
|
Sep 19 03:36:29 AM UTC 24 |
Sep 19 03:53:13 AM UTC 24 |
5768316608 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1272730710 |
|
|
Sep 19 03:45:41 AM UTC 24 |
Sep 19 03:53:33 AM UTC 24 |
5032622302 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.550920938 |
|
|
Sep 19 02:14:17 AM UTC 24 |
Sep 19 03:54:04 AM UTC 24 |
44135678452 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1168135634 |
|
|
Sep 19 03:44:29 AM UTC 24 |
Sep 19 03:54:12 AM UTC 24 |
8055998080 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access.821726829 |
|
|
Sep 19 03:35:50 AM UTC 24 |
Sep 19 03:54:45 AM UTC 24 |
5613848686 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3343224939 |
|
|
Sep 19 03:48:08 AM UTC 24 |
Sep 19 03:55:56 AM UTC 24 |
8907701688 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_cpu_info.3612238609 |
|
|
Sep 19 03:43:49 AM UTC 24 |
Sep 19 03:56:01 AM UTC 24 |
6320564772 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1917472853 |
|
|
Sep 19 03:36:51 AM UTC 24 |
Sep 19 03:56:19 AM UTC 24 |
5585461060 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2531425794 |
|
|
Sep 19 03:38:31 AM UTC 24 |
Sep 19 03:57:16 AM UTC 24 |
6810832920 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_irq.698620887 |
|
|
Sep 19 03:53:53 AM UTC 24 |
Sep 19 03:57:37 AM UTC 24 |
2408358260 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1989122514 |
|
|
Sep 19 03:53:18 AM UTC 24 |
Sep 19 03:58:12 AM UTC 24 |
2777570344 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2699502739 |
|
|
Sep 19 03:50:57 AM UTC 24 |
Sep 19 03:59:44 AM UTC 24 |
6658142080 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_otbn.653931580 |
|
|
Sep 19 02:47:58 AM UTC 24 |
Sep 19 03:59:58 AM UTC 24 |
14654442952 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.956136958 |
|
|
Sep 19 03:38:31 AM UTC 24 |
Sep 19 04:00:08 AM UTC 24 |
8825243304 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_rma.3379268770 |
|
|
Sep 19 02:22:24 AM UTC 24 |
Sep 19 04:00:18 AM UTC 24 |
45783519138 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3769194115 |
|
|
Sep 19 03:45:42 AM UTC 24 |
Sep 19 04:00:28 AM UTC 24 |
7820998078 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2631114571 |
|
|
Sep 19 03:55:00 AM UTC 24 |
Sep 19 04:00:46 AM UTC 24 |
3236191114 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1366809322 |
|
|
Sep 19 03:53:39 AM UTC 24 |
Sep 19 04:01:53 AM UTC 24 |
5079177080 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.992114972 |
|
|
Sep 19 03:49:45 AM UTC 24 |
Sep 19 04:01:55 AM UTC 24 |
6170091590 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2848744798 |
|
|
Sep 19 03:55:27 AM UTC 24 |
Sep 19 04:02:02 AM UTC 24 |
6069875176 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2189530105 |
|
|
Sep 19 03:38:04 AM UTC 24 |
Sep 19 04:02:28 AM UTC 24 |
7299492100 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prodend.1905189778 |
|
|
Sep 19 03:43:18 AM UTC 24 |
Sep 19 04:03:05 AM UTC 24 |
12269263455 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1052057447 |
|
|
Sep 19 03:58:19 AM UTC 24 |
Sep 19 04:03:31 AM UTC 24 |
6783865396 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.3849920420 |
|
|
Sep 19 03:58:01 AM UTC 24 |
Sep 19 04:03:46 AM UTC 24 |
4196324782 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prod.790212924 |
|
|
Sep 19 02:19:36 AM UTC 24 |
Sep 19 04:03:51 AM UTC 24 |
49646133760 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_outputs.4253424761 |
|
|
Sep 19 03:57:03 AM UTC 24 |
Sep 19 04:03:57 AM UTC 24 |
3911958480 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_dev.2778422233 |
|
|
Sep 19 02:19:33 AM UTC 24 |
Sep 19 04:04:28 AM UTC 24 |
48401052381 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en.1772897774 |
|
|
Sep 19 04:03:46 AM UTC 24 |
Sep 19 04:06:57 AM UTC 24 |
2597662931 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1493784229 |
|
|
Sep 19 03:55:00 AM UTC 24 |
Sep 19 04:07:08 AM UTC 24 |
4280338635 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc.93224887 |
|
|
Sep 19 04:03:15 AM UTC 24 |
Sep 19 04:07:28 AM UTC 24 |
2772094492 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init.1488058674 |
|
|
Sep 19 03:36:25 AM UTC 24 |
Sep 19 04:07:38 AM UTC 24 |
20753865374 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_wdog_reset.279589837 |
|
|
Sep 19 04:00:29 AM UTC 24 |
Sep 19 04:08:17 AM UTC 24 |
4579531800 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.2604084182 |
|
|
Sep 19 03:43:27 AM UTC 24 |
Sep 19 04:08:42 AM UTC 24 |
8900877176 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_masking_off.2897145369 |
|
|
Sep 19 04:04:51 AM UTC 24 |
Sep 19 04:08:44 AM UTC 24 |
2338412681 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_idle.3644865271 |
|
|
Sep 19 04:04:14 AM UTC 24 |
Sep 19 04:09:05 AM UTC 24 |
3061299000 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1600972180 |
|
|
Sep 19 03:46:31 AM UTC 24 |
Sep 19 04:09:08 AM UTC 24 |
15897574969 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_test.1116277250 |
|
|
Sep 19 04:04:53 AM UTC 24 |
Sep 19 04:09:22 AM UTC 24 |
2491099928 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.4236491330 |
|
|
Sep 19 04:01:27 AM UTC 24 |
Sep 19 04:09:46 AM UTC 24 |
4211182894 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.80365251 |
|
|
Sep 19 03:47:41 AM UTC 24 |
Sep 19 04:10:52 AM UTC 24 |
12513417124 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_mem_scramble.1511309418 |
|
|
Sep 19 04:03:01 AM UTC 24 |
Sep 19 04:11:23 AM UTC 24 |
3183676320 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.929290206 |
|
|
Sep 19 03:58:57 AM UTC 24 |
Sep 19 04:12:30 AM UTC 24 |
7385501678 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2156253958 |
|
|
Sep 19 03:16:01 AM UTC 24 |
Sep 19 04:13:00 AM UTC 24 |
11405657604 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_escalation.16753502 |
|
|
Sep 19 04:04:54 AM UTC 24 |
Sep 19 04:13:20 AM UTC 24 |
5785341956 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.491830521 |
|
|
Sep 19 04:01:26 AM UTC 24 |
Sep 19 04:13:49 AM UTC 24 |
18522455072 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.4040156115 |
|
|
Sep 19 04:08:19 AM UTC 24 |
Sep 19 04:14:32 AM UTC 24 |
3941432166 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_kat_test.1088325360 |
|
|
Sep 19 04:10:08 AM UTC 24 |
Sep 19 04:14:34 AM UTC 24 |
3283113100 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_entropy.722592867 |
|
|
Sep 19 04:09:32 AM UTC 24 |
Sep 19 04:14:49 AM UTC 24 |
3284341806 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1159999024 |
|
|
Sep 19 03:27:03 AM UTC 24 |
Sep 19 04:15:19 AM UTC 24 |
13504063796 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_entropy.103144347 |
|
|
Sep 19 04:10:06 AM UTC 24 |
Sep 19 04:15:23 AM UTC 24 |
2333130034 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3043791672 |
|
|
Sep 19 04:03:10 AM UTC 24 |
Sep 19 04:16:19 AM UTC 24 |
5012233740 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_timeout.2459513333 |
|
|
Sep 19 04:05:12 AM UTC 24 |
Sep 19 04:16:43 AM UTC 24 |
5617624932 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_randomness.2385235894 |
|
|
Sep 19 04:01:33 AM UTC 24 |
Sep 19 04:18:07 AM UTC 24 |
6121754114 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_kat_test.4132259837 |
|
|
Sep 19 04:14:05 AM UTC 24 |
Sep 19 04:18:57 AM UTC 24 |
3194144552 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_boot_mode.2132438959 |
|
|
Sep 19 04:10:31 AM UTC 24 |
Sep 19 04:19:11 AM UTC 24 |
3122866222 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_ast_rng_req.4078651147 |
|
|
Sep 19 04:15:34 AM UTC 24 |
Sep 19 04:19:25 AM UTC 24 |
2293645640 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_rnd.3366277399 |
|
|
Sep 19 04:03:01 AM UTC 24 |
Sep 19 04:19:46 AM UTC 24 |
5507081952 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3742091617 |
|
|
Sep 19 03:46:28 AM UTC 24 |
Sep 19 04:20:17 AM UTC 24 |
13681108104 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_exception_c.1009469926 |
|
|
Sep 19 03:14:34 AM UTC 24 |
Sep 19 04:20:20 AM UTC 24 |
15247686714 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc.755710468 |
|
|
Sep 19 04:16:10 AM UTC 24 |
Sep 19 04:20:39 AM UTC 24 |
3470423600 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en.3241016287 |
|
|
Sep 19 04:17:03 AM UTC 24 |
Sep 19 04:21:29 AM UTC 24 |
3301988823 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_kat.3806329308 |
|
|
Sep 19 04:11:37 AM UTC 24 |
Sep 19 04:21:38 AM UTC 24 |
3144352870 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_idle.696578869 |
|
|
Sep 19 04:17:27 AM UTC 24 |
Sep 19 04:22:45 AM UTC 24 |
2867287512 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.294194052 |
|
|
Sep 19 03:46:30 AM UTC 24 |
Sep 19 04:23:11 AM UTC 24 |
26173629360 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_rma.739318968 |
|
|
Sep 19 03:16:05 AM UTC 24 |
Sep 19 04:24:16 AM UTC 24 |
15612185361 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_reset.3172271529 |
|
|
Sep 19 03:57:00 AM UTC 24 |
Sep 19 04:24:18 AM UTC 24 |
23794340260 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1944658260 |
|
|
Sep 19 04:14:33 AM UTC 24 |
Sep 19 04:24:22 AM UTC 24 |
4222444762 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_output.3675925719 |
|
|
Sep 19 03:15:06 AM UTC 24 |
Sep 19 04:24:22 AM UTC 24 |
33121236007 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3662666930 |
|
|
Sep 19 03:43:25 AM UTC 24 |
Sep 19 04:24:32 AM UTC 24 |
34519738120 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_oneshot.3729909612 |
|
|
Sep 19 04:18:52 AM UTC 24 |
Sep 19 04:24:41 AM UTC 24 |
3858517200 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3685675741 |
|
|
Sep 19 03:10:14 AM UTC 24 |
Sep 19 04:25:24 AM UTC 24 |
24474379491 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.596232747 |
|
|
Sep 19 04:13:14 AM UTC 24 |
Sep 19 04:25:27 AM UTC 24 |
7138847980 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_cshake.2172020188 |
|
|
Sep 19 04:21:28 AM UTC 24 |
Sep 19 04:25:36 AM UTC 24 |
3077591980 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod_end.2898368173 |
|
|
Sep 19 03:16:15 AM UTC 24 |
Sep 19 04:26:01 AM UTC 24 |
15397855556 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_auto_mode.3683068415 |
|
|
Sep 19 04:10:09 AM UTC 24 |
Sep 19 04:26:04 AM UTC 24 |
4751278832 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2020691284 |
|
|
Sep 19 03:15:38 AM UTC 24 |
Sep 19 04:26:36 AM UTC 24 |
14648210344 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_app_rom.1441487495 |
|
|
Sep 19 04:23:30 AM UTC 24 |
Sep 19 04:27:15 AM UTC 24 |
2376331768 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac.860656442 |
|
|
Sep 19 04:22:24 AM UTC 24 |
Sep 19 04:27:20 AM UTC 24 |
3698709048 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_idle.857961813 |
|
|
Sep 19 04:23:53 AM UTC 24 |
Sep 19 04:27:40 AM UTC 24 |
3166445216 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.655890711 |
|
|
Sep 19 04:22:24 AM UTC 24 |
Sep 19 04:27:53 AM UTC 24 |
3417693741 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3546574194 |
|
|
Sep 19 04:08:24 AM UTC 24 |
Sep 19 04:27:55 AM UTC 24 |
11571036052 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3954018645 |
|
|
Sep 19 03:16:14 AM UTC 24 |
Sep 19 04:28:18 AM UTC 24 |
15358241280 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod.45852824 |
|
|
Sep 19 03:16:10 AM UTC 24 |
Sep 19 04:28:29 AM UTC 24 |
15728389689 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3360947063 |
|
|
Sep 19 03:16:05 AM UTC 24 |
Sep 19 04:29:13 AM UTC 24 |
14676083640 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_dev.3757836949 |
|
|
Sep 19 03:16:11 AM UTC 24 |
Sep 19 04:29:52 AM UTC 24 |
15578742801 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2262055642 |
|
|
Sep 19 04:09:02 AM UTC 24 |
Sep 19 04:30:15 AM UTC 24 |
6229601054 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_ok.767382924 |
|
|
Sep 19 04:07:55 AM UTC 24 |
Sep 19 04:30:20 AM UTC 24 |
7999001976 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs.2979859946 |
|
|
Sep 19 04:15:34 AM UTC 24 |
Sep 19 04:30:32 AM UTC 24 |
6464093000 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_plic_sw_irq.1460663056 |
|
|
Sep 19 04:27:35 AM UTC 24 |
Sep 19 04:31:09 AM UTC 24 |
2711940684 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_smoke.3372142913 |
|
|
Sep 19 03:15:16 AM UTC 24 |
Sep 19 04:31:14 AM UTC 24 |
15067571760 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_sw_mode.1263539758 |
|
|
Sep 19 04:12:07 AM UTC 24 |
Sep 19 04:31:14 AM UTC 24 |
5672247804 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2086139484 |
|
|
Sep 19 04:09:32 AM UTC 24 |
Sep 19 04:31:44 AM UTC 24 |
7177499624 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_inject_scramble_seed.1950986141 |
|
|
Sep 19 12:01:43 AM UTC 24 |
Sep 19 04:31:50 AM UTC 24 |
68347906971 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_status.1209860670 |
|
|
Sep 19 04:26:52 AM UTC 24 |
Sep 19 04:32:15 AM UTC 24 |
2832802944 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3851227247 |
|
|
Sep 19 04:16:10 AM UTC 24 |
Sep 19 04:33:08 AM UTC 24 |
5395974944 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_aes_trans.470709663 |
|
|
Sep 19 04:28:05 AM UTC 24 |
Sep 19 04:33:13 AM UTC 24 |
3490947882 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_rst_inputs.482540158 |
|
|
Sep 19 03:10:19 AM UTC 24 |
Sep 19 04:33:52 AM UTC 24 |
27602539154 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3984510040 |
|
|
Sep 19 04:27:21 AM UTC 24 |
Sep 19 04:35:22 AM UTC 24 |
4662713790 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2278258350 |
|
|
Sep 19 04:28:21 AM UTC 24 |
Sep 19 04:35:31 AM UTC 24 |
4974393120 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.842823867 |
|
|
Sep 19 04:26:02 AM UTC 24 |
Sep 19 04:35:38 AM UTC 24 |
7743682304 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter.2237719324 |
|
|
Sep 19 04:32:26 AM UTC 24 |
Sep 19 04:35:55 AM UTC 24 |
2825221603 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1039106878 |
|
|
Sep 19 04:25:49 AM UTC 24 |
Sep 19 04:36:18 AM UTC 24 |
8894373906 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_static_critical.3117209229 |
|
|
Sep 19 03:16:09 AM UTC 24 |
Sep 19 04:36:23 AM UTC 24 |
17080825820 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3293496417 |
|
|
Sep 19 04:26:31 AM UTC 24 |
Sep 19 04:36:29 AM UTC 24 |
10022303341 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1594464744 |
|
|
Sep 19 04:26:29 AM UTC 24 |
Sep 19 04:36:34 AM UTC 24 |
4311516628 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.4169228152 |
|
|
Sep 19 04:20:29 AM UTC 24 |
Sep 19 04:36:39 AM UTC 24 |
6135330170 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.811803906 |
|
|
Sep 19 04:27:36 AM UTC 24 |
Sep 19 04:37:12 AM UTC 24 |
3893247160 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.2418919118 |
|
|
Sep 19 04:28:44 AM UTC 24 |
Sep 19 04:37:33 AM UTC 24 |
4416736068 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.253031388 |
|
|
Sep 19 04:28:43 AM UTC 24 |
Sep 19 04:37:57 AM UTC 24 |
4416703486 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2315475519 |
|
|
Sep 19 04:32:25 AM UTC 24 |
Sep 19 04:38:51 AM UTC 24 |
3036812600 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1233058750 |
|
|
Sep 19 04:27:22 AM UTC 24 |
Sep 19 04:39:18 AM UTC 24 |
4693997372 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3109704425 |
|
|
Sep 19 04:31:24 AM UTC 24 |
Sep 19 04:39:42 AM UTC 24 |
4569278680 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.3088339959 |
|
|
Sep 19 04:26:47 AM UTC 24 |
Sep 19 04:40:07 AM UTC 24 |
7481979556 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.645646489 |
|
|
Sep 19 04:27:13 AM UTC 24 |
Sep 19 04:40:07 AM UTC 24 |
5027037210 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_testunlock0.3341578910 |
|
|
Sep 19 04:37:50 AM UTC 24 |
Sep 19 04:40:14 AM UTC 24 |
3295583379 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_reset_frequency.3310128390 |
|
|
Sep 19 04:32:14 AM UTC 24 |
Sep 19 04:40:22 AM UTC 24 |
3496008400 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_execution_main.3121659589 |
|
|
Sep 19 04:25:51 AM UTC 24 |
Sep 19 04:40:23 AM UTC 24 |
9310298571 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_program_error.2378578199 |
|
|
Sep 19 04:34:05 AM UTC 24 |
Sep 19 04:40:27 AM UTC 24 |
4185882248 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.43754011 |
|
|
Sep 19 04:29:12 AM UTC 24 |
Sep 19 04:40:30 AM UTC 24 |
4191558166 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.714265550 |
|
|
Sep 19 04:30:37 AM UTC 24 |
Sep 19 04:40:36 AM UTC 24 |
4700425542 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1897051027 |
|
|
Sep 19 04:29:59 AM UTC 24 |
Sep 19 04:40:56 AM UTC 24 |
5169483738 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4252939331 |
|
|
Sep 19 04:34:43 AM UTC 24 |
Sep 19 04:41:29 AM UTC 24 |
7597491470 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1919714489 |
|
|
Sep 19 04:34:43 AM UTC 24 |
Sep 19 04:41:36 AM UTC 24 |
3387859394 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.285453154 |
|
|
Sep 19 04:31:21 AM UTC 24 |
Sep 19 04:41:50 AM UTC 24 |
4286389236 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_prod.1805159476 |
|
|
Sep 19 04:38:35 AM UTC 24 |
Sep 19 04:41:51 AM UTC 24 |
2973092614 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3760498459 |
|
|
Sep 19 04:31:23 AM UTC 24 |
Sep 19 04:42:43 AM UTC 24 |
4782931290 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_sleep_frequency.955969200 |
|
|
Sep 19 04:32:30 AM UTC 24 |
Sep 19 04:42:49 AM UTC 24 |
4807895616 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3971582187 |
|
|
Sep 19 04:39:35 AM UTC 24 |
Sep 19 04:43:12 AM UTC 24 |
3496865608 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_csrng.2958636940 |
|
|
Sep 19 04:15:30 AM UTC 24 |
Sep 19 04:43:39 AM UTC 24 |
8055380264 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.4225473627 |
|
|
Sep 19 04:40:27 AM UTC 24 |
Sep 19 04:44:03 AM UTC 24 |
3157966830 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1071357404 |
|
|
Sep 19 04:37:39 AM UTC 24 |
Sep 19 04:44:04 AM UTC 24 |
4756657186 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2201789197 |
|
|
Sep 19 04:29:09 AM UTC 24 |
Sep 19 04:44:28 AM UTC 24 |
10670248775 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.1775662653 |
|
|
Sep 19 04:27:10 AM UTC 24 |
Sep 19 04:44:46 AM UTC 24 |
5589372644 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation.2623715975 |
|
|
Sep 19 04:19:55 AM UTC 24 |
Sep 19 04:45:07 AM UTC 24 |
9205310720 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.296165091 |
|
|
Sep 19 04:37:38 AM UTC 24 |
Sep 19 04:45:17 AM UTC 24 |
5571591662 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4084592386 |
|
|
Sep 19 04:36:47 AM UTC 24 |
Sep 19 04:45:35 AM UTC 24 |
5798641086 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.581136756 |
|
|
Sep 19 04:36:44 AM UTC 24 |
Sep 19 04:45:48 AM UTC 24 |
6891468040 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_rv_dm_ndm_reset_req.2486211286 |
|
|
Sep 19 04:37:42 AM UTC 24 |
Sep 19 04:45:53 AM UTC 24 |
4665224428 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.621139011 |
|
|
Sep 19 04:42:53 AM UTC 24 |
Sep 19 04:46:19 AM UTC 24 |
3436189880 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1439108425 |
|
|
Sep 19 04:42:52 AM UTC 24 |
Sep 19 04:46:32 AM UTC 24 |
3396175803 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_rma.1644276213 |
|
|
Sep 19 04:38:10 AM UTC 24 |
Sep 19 04:47:14 AM UTC 24 |
6072602550 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3096800187 |
|
|
Sep 19 04:43:39 AM UTC 24 |
Sep 19 04:47:23 AM UTC 24 |
2884224419 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1081795415 |
|
|
Sep 19 04:37:43 AM UTC 24 |
Sep 19 04:47:41 AM UTC 24 |
6478130917 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_scrambling_smoketest.88055679 |
|
|
Sep 19 04:45:12 AM UTC 24 |
Sep 19 04:48:01 AM UTC 24 |
2454122466 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1712099278 |
|
|
Sep 19 04:43:39 AM UTC 24 |
Sep 19 04:48:42 AM UTC 24 |
3900903456 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_write_clear.4171909693 |
|
|
Sep 19 04:43:06 AM UTC 24 |
Sep 19 04:48:43 AM UTC 24 |
2693158296 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_peri.1930702738 |
|
|
Sep 19 04:28:05 AM UTC 24 |
Sep 19 04:48:48 AM UTC 24 |
8814245254 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_sleep_load.1666693122 |
|
|
Sep 19 04:44:02 AM UTC 24 |
Sep 19 04:49:15 AM UTC 24 |
4301648698 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_volatile_raw_unlock.622942195 |
|
|
Sep 19 04:48:52 AM UTC 24 |
Sep 19 04:50:48 AM UTC 24 |
2369967161 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_multistream.558683170 |
|
|
Sep 19 04:19:50 AM UTC 24 |
Sep 19 04:51:06 AM UTC 24 |
8612768104 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_aes.142954836 |
|
|
Sep 19 04:21:22 AM UTC 24 |
Sep 19 04:51:10 AM UTC 24 |
9748218542 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3962327767 |
|
|
Sep 19 04:41:58 AM UTC 24 |
Sep 19 04:51:56 AM UTC 24 |
4533797686 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_outputs.2256093246 |
|
|
Sep 19 04:34:04 AM UTC 24 |
Sep 19 04:52:01 AM UTC 24 |
7196681758 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1835840766 |
|
|
Sep 19 04:43:07 AM UTC 24 |
Sep 19 04:52:42 AM UTC 24 |
4869135168 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_crash_alert.459903330 |
|
|
Sep 19 04:42:53 AM UTC 24 |
Sep 19 04:52:57 AM UTC 24 |
5579528400 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_raw_unlock.552709135 |
|
|
Sep 19 04:48:56 AM UTC 24 |
Sep 19 04:53:08 AM UTC 24 |
4934047172 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_idle_load.1753089382 |
|
|
Sep 19 04:43:39 AM UTC 24 |
Sep 19 04:53:45 AM UTC 24 |
4003058084 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2214357374 |
|
|
Sep 19 04:20:16 AM UTC 24 |
Sep 19 04:54:26 AM UTC 24 |
10252327588 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_smoketest.2217133795 |
|
|
Sep 19 04:49:51 AM UTC 24 |
Sep 19 04:54:46 AM UTC 24 |
2807093740 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_smoketest.1638568693 |
|
|
Sep 19 04:50:10 AM UTC 24 |
Sep 19 04:54:57 AM UTC 24 |
3063479800 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.888918103 |
|
|
Sep 19 04:32:20 AM UTC 24 |
Sep 19 04:55:05 AM UTC 24 |
14357913262 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_smoketest.3248089539 |
|
|
Sep 19 04:51:42 AM UTC 24 |
Sep 19 04:56:17 AM UTC 24 |
3280974904 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio_smoketest.3135143125 |
|
|
Sep 19 04:52:52 AM UTC 24 |
Sep 19 04:56:53 AM UTC 24 |
2782595766 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_smoketest.3372931606 |
|
|
Sep 19 04:51:55 AM UTC 24 |
Sep 19 04:57:09 AM UTC 24 |
3377184380 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_mem_access.2482740603 |
|
|
Sep 19 04:32:45 AM UTC 24 |
Sep 19 04:57:21 AM UTC 24 |
14001062100 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.4285251939 |
|
|
Sep 19 03:57:04 AM UTC 24 |
Sep 19 04:57:27 AM UTC 24 |
21006610014 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_smoketest.3506844635 |
|
|
Sep 19 04:53:51 AM UTC 24 |
Sep 19 04:58:34 AM UTC 24 |
2779834000 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_dev.1379581304 |
|
|
Sep 19 04:37:27 AM UTC 24 |
Sep 19 04:58:43 AM UTC 24 |
13116961803 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_smoketest.1983975989 |
|
|
Sep 19 04:53:37 AM UTC 24 |
Sep 19 04:58:57 AM UTC 24 |
3467213100 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_smoketest.620243826 |
|
|
Sep 19 04:51:57 AM UTC 24 |
Sep 19 04:59:18 AM UTC 24 |
3847108452 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_smoketest.2075811279 |
|
|
Sep 19 04:55:51 AM UTC 24 |
Sep 19 04:59:30 AM UTC 24 |
3173857864 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_smoketest.3769995197 |
|
|
Sep 19 04:52:53 AM UTC 24 |
Sep 19 05:00:09 AM UTC 24 |
3978411332 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1420053815 |
|
|
Sep 19 12:01:11 AM UTC 24 |
Sep 19 05:00:35 AM UTC 24 |
80801834914 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_plic_smoketest.615991531 |
|
|
Sep 19 04:55:45 AM UTC 24 |
Sep 19 05:00:42 AM UTC 24 |
3271742010 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_smoketest.698826880 |
|
|
Sep 19 04:55:51 AM UTC 24 |
Sep 19 05:00:57 AM UTC 24 |
2345858272 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3480020346 |
|
|
Sep 19 04:55:09 AM UTC 24 |
Sep 19 05:01:08 AM UTC 24 |
6160515502 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_keymgr_functest.175917197 |
|
|
Sep 19 04:50:09 AM UTC 24 |
Sep 19 05:01:46 AM UTC 24 |
3958380838 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_smoketest.334795754 |
|
|
Sep 19 04:57:01 AM UTC 24 |
Sep 19 05:01:46 AM UTC 24 |
3154013610 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4047112929 |
|
|
Sep 19 04:42:54 AM UTC 24 |
Sep 19 05:01:49 AM UTC 24 |
7677039574 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_kmac.2974111960 |
|
|
Sep 19 04:20:32 AM UTC 24 |
Sep 19 05:02:31 AM UTC 24 |
13414103072 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_smoketest.3185397357 |
|
|
Sep 19 04:54:22 AM UTC 24 |
Sep 19 05:03:05 AM UTC 24 |
6141614414 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_mem_protection.411647292 |
|
|
Sep 19 04:45:12 AM UTC 24 |
Sep 19 05:03:31 AM UTC 24 |
5856219720 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_smoketest.2572779064 |
|
|
Sep 19 04:57:37 AM UTC 24 |
Sep 19 05:03:42 AM UTC 24 |
3370598536 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2031291527 |
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|
Sep 19 04:36:47 AM UTC 24 |
Sep 19 05:05:51 AM UTC 24 |
24537622556 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.4279113506 |
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|
Sep 19 04:36:42 AM UTC 24 |
Sep 19 05:06:07 AM UTC 24 |
24490885432 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.1061785109 |
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|
Sep 19 05:02:38 AM UTC 24 |
Sep 19 05:06:35 AM UTC 24 |
3993355542 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2847542910 |
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|
Sep 19 05:01:55 AM UTC 24 |
Sep 19 05:07:50 AM UTC 24 |
4295392182 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1369948756 |
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|
Sep 19 05:01:38 AM UTC 24 |
Sep 19 05:07:51 AM UTC 24 |
6925990584 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2425284010 |
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|
Sep 19 04:27:04 AM UTC 24 |
Sep 19 05:08:00 AM UTC 24 |
27298166710 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3643607749 |
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|
Sep 19 05:00:55 AM UTC 24 |
Sep 19 05:08:21 AM UTC 24 |
4905347480 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_data_integrity_escalation.2936383845 |
|
|
Sep 19 04:58:24 AM UTC 24 |
Sep 19 05:08:33 AM UTC 24 |
4865978598 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_all_escalation_resets.2994462799 |
|
|
Sep 19 04:58:23 AM UTC 24 |
Sep 19 05:09:00 AM UTC 24 |
4834914870 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx1.103813309 |
|
|
Sep 19 04:59:28 AM UTC 24 |
Sep 19 05:09:07 AM UTC 24 |
4641133822 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx.1341894312 |
|
|
Sep 19 04:58:24 AM UTC 24 |
Sep 19 05:09:30 AM UTC 24 |
4650934840 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx3.2842262602 |
|
|
Sep 19 04:59:44 AM UTC 24 |
Sep 19 05:09:54 AM UTC 24 |
4240784926 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_virus.4202846989 |
|
|
Sep 19 04:45:02 AM UTC 24 |
Sep 19 05:10:25 AM UTC 24 |
6055534918 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx2.3153198163 |
|
|
Sep 19 04:59:42 AM UTC 24 |
Sep 19 05:10:46 AM UTC 24 |
4572372276 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_testunlock0.3187901034 |
|
|
Sep 19 05:02:37 AM UTC 24 |
Sep 19 05:11:42 AM UTC 24 |
5942654179 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.828991211 |
|
|
Sep 19 04:01:35 AM UTC 24 |
Sep 19 05:12:27 AM UTC 24 |
17327608290 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.1944168171 |
|
|
Sep 19 03:36:27 AM UTC 24 |
Sep 19 05:12:56 AM UTC 24 |
44862004064 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_rma.286272648 |
|
|
Sep 19 05:03:09 AM UTC 24 |
Sep 19 05:13:05 AM UTC 24 |
6320858413 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.1221009309 |
|
|
Sep 19 04:43:24 AM UTC 24 |
Sep 19 05:13:13 AM UTC 24 |
21254584304 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.74212658 |
|
|
Sep 19 03:42:49 AM UTC 24 |
Sep 19 05:15:23 AM UTC 24 |
47216318650 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_lc_ctrl_transition.2266598 |
|
|
Sep 19 05:01:27 AM UTC 24 |
Sep 19 05:15:52 AM UTC 24 |
11966793472 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_prod.3509864972 |
|
|
Sep 19 05:03:45 AM UTC 24 |
Sep 19 05:16:30 AM UTC 24 |
7874588470 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.1527694774 |
|
|
Sep 19 05:04:26 AM UTC 24 |
Sep 19 05:16:53 AM UTC 24 |
5045845664 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2759306428 |
|
|
Sep 19 04:42:51 AM UTC 24 |
Sep 19 05:17:03 AM UTC 24 |
13436205929 ps |