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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.44 98.11 95.91 97.44 87.30 98.22 98.17 92.94


Total test records in report: 3732
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T591 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_out_iso.2193261783 Feb 08 05:58:15 PM UTC 25 Feb 08 05:58:17 PM UTC 25 168824509 ps
T592 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_out_trans_nak.3330425563 Feb 08 05:58:16 PM UTC 25 Feb 08 05:58:19 PM UTC 25 179370963 ps
T593 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_out_stall.3230874964 Feb 08 05:58:16 PM UTC 25 Feb 08 05:58:19 PM UTC 25 182606206 ps
T179 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_pending_in_trans.1256633437 Feb 08 05:58:17 PM UTC 25 Feb 08 05:58:20 PM UTC 25 153416768 ps
T594 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_phy_config_pinflip.2218596035 Feb 08 05:58:17 PM UTC 25 Feb 08 05:58:20 PM UTC 25 212786179 ps
T595 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_phy_config_rand_bus_type.1917975267 Feb 08 05:58:18 PM UTC 25 Feb 08 05:58:21 PM UTC 25 195838893 ps
T38 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_phy_pins_sense.3588941715 Feb 08 05:58:20 PM UTC 25 Feb 08 05:58:22 PM UTC 25 42948323 ps
T596 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_phy_config_usb_ref_disable.3981185007 Feb 08 05:58:20 PM UTC 25 Feb 08 05:58:22 PM UTC 25 224227031 ps
T597 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_link_suspend.2201350090 Feb 08 05:58:05 PM UTC 25 Feb 08 05:58:23 PM UTC 25 5348847898 ps
T598 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_pkt_received.3948138060 Feb 08 05:58:21 PM UTC 25 Feb 08 05:58:23 PM UTC 25 159918983 ps
T599 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_pkt_sent.2940037716 Feb 08 05:58:21 PM UTC 25 Feb 08 05:58:23 PM UTC 25 210686806 ps
T600 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_freq_phase.564063745 Feb 08 05:54:43 PM UTC 25 Feb 08 05:58:24 PM UTC 25 96168748616 ps
T601 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_random_length_out_transaction.674478435 Feb 08 05:58:22 PM UTC 25 Feb 08 05:58:25 PM UTC 25 153819389 ps
T602 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_random_length_in_transaction.1422554731 Feb 08 05:58:22 PM UTC 25 Feb 08 05:58:25 PM UTC 25 262029137 ps
T603 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_freq_loclk_max.2277984903 Feb 08 05:54:42 PM UTC 25 Feb 08 05:58:25 PM UTC 25 114209722648 ps
T604 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_reset.860577158 Feb 08 05:57:28 PM UTC 25 Feb 08 05:58:27 PM UTC 25 20137328571 ps
T605 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_rx_crc_err.1835359790 Feb 08 05:58:25 PM UTC 25 Feb 08 05:58:28 PM UTC 25 142092037 ps
T606 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_max_inter_pkt_delay.1964286765 Feb 08 05:58:07 PM UTC 25 Feb 08 05:58:28 PM UTC 25 2227859627 ps
T58 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_rx_full.3585104044 Feb 08 05:58:26 PM UTC 25 Feb 08 05:58:28 PM UTC 25 259818147 ps
T607 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_rx_pid_err.3867587570 Feb 08 05:58:26 PM UTC 25 Feb 08 05:58:28 PM UTC 25 217337394 ps
T608 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_setup_priority.1699169624 Feb 08 05:58:26 PM UTC 25 Feb 08 05:58:29 PM UTC 25 374886465 ps
T609 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_setup_trans_ignored.3112293035 Feb 08 05:58:28 PM UTC 25 Feb 08 05:58:30 PM UTC 25 180236800 ps
T610 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_setup_stage.190929426 Feb 08 05:58:28 PM UTC 25 Feb 08 05:58:30 PM UTC 25 148125691 ps
T203 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_setup_priority_over_stall_response.3512680285 Feb 08 05:58:28 PM UTC 25 Feb 08 05:58:30 PM UTC 25 189724501 ps
T611 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_stall_priority_over_nak.710997795 Feb 08 05:58:29 PM UTC 25 Feb 08 05:58:32 PM UTC 25 165518574 ps
T612 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_stall_trans.1480948197 Feb 08 05:58:29 PM UTC 25 Feb 08 05:58:32 PM UTC 25 194481930 ps
T613 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_smoke.2290092287 Feb 08 05:58:29 PM UTC 25 Feb 08 05:58:32 PM UTC 25 230178316 ps
T614 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_max_usb_traffic.1613813107 Feb 08 05:58:10 PM UTC 25 Feb 08 05:58:34 PM UTC 25 2547573743 ps
T615 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_stream_len_max.253603047 Feb 08 05:58:32 PM UTC 25 Feb 08 05:58:35 PM UTC 25 334377840 ps
T616 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_alert_test.3594456500 Feb 08 05:58:34 PM UTC 25 Feb 08 05:58:37 PM UTC 25 116749063 ps
T617 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_tx_rx_disruption.284741391 Feb 08 05:58:33 PM UTC 25 Feb 08 05:58:37 PM UTC 25 600760923 ps
T231 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_sec_cm.2116636384 Feb 08 05:58:33 PM UTC 25 Feb 08 05:58:38 PM UTC 25 881294740 ps
T618 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_max_non_iso_usb_traffic.3483124076 Feb 08 05:58:10 PM UTC 25 Feb 08 05:58:38 PM UTC 25 2524376263 ps
T619 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_av_buffer.3850447738 Feb 08 05:58:38 PM UTC 25 Feb 08 05:58:40 PM UTC 25 153503871 ps
T620 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_av_empty.3204257983 Feb 08 05:58:38 PM UTC 25 Feb 08 05:58:41 PM UTC 25 163523141 ps
T159 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_invalid_sync.3940545417 Feb 08 05:57:56 PM UTC 25 Feb 08 05:58:41 PM UTC 25 3380427702 ps
T621 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_bitstuff_err.843775918 Feb 08 05:58:39 PM UTC 25 Feb 08 05:58:42 PM UTC 25 169252163 ps
T92 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_av_overflow.633651851 Feb 08 05:58:39 PM UTC 25 Feb 08 05:58:42 PM UTC 25 146359062 ps
T84 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_stress_usb_traffic.2059672252 Feb 08 05:57:23 PM UTC 25 Feb 08 05:58:44 PM UTC 25 5913677493 ps
T622 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_data_toggle_clear.2913597376 Feb 08 05:58:41 PM UTC 25 Feb 08 05:58:45 PM UTC 25 270592348 ps
T623 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_aon_wake_disconnect.3453987084 Feb 08 05:58:36 PM UTC 25 Feb 08 05:58:46 PM UTC 25 5014915590 ps
T316 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_data_toggle_restore.2024744535 Feb 08 05:58:41 PM UTC 25 Feb 08 05:58:46 PM UTC 25 680611948 ps
T624 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_disconnected.3004087806 Feb 08 05:58:44 PM UTC 25 Feb 08 05:58:47 PM UTC 25 141204903 ps
T625 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_min_inter_pkt_delay.754002849 Feb 08 05:58:11 PM UTC 25 Feb 08 05:58:47 PM UTC 25 3031220955 ps
T365 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_low_speed_traffic.2251889986 Feb 08 05:58:05 PM UTC 25 Feb 08 05:58:47 PM UTC 25 4436127306 ps
T340 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_disable_endpoint.101976255 Feb 08 05:58:44 PM UTC 25 Feb 08 05:58:48 PM UTC 25 610384517 ps
T626 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_enable.1955619984 Feb 08 05:58:45 PM UTC 25 Feb 08 05:58:48 PM UTC 25 47055140 ps
T627 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_freq_hiclk_max.4063358718 Feb 08 05:54:37 PM UTC 25 Feb 08 05:58:50 PM UTC 25 89260812195 ps
T462 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_endpoint_types.1148188053 Feb 08 05:58:48 PM UTC 25 Feb 08 05:58:50 PM UTC 25 335697148 ps
T628 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_fifo_rst.2200540321 Feb 08 05:58:48 PM UTC 25 Feb 08 05:58:51 PM UTC 25 172792807 ps
T500 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_endpoint_access.1506025993 Feb 08 05:58:48 PM UTC 25 Feb 08 05:58:52 PM UTC 25 932251745 ps
T629 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_in_iso.3617747299 Feb 08 05:58:52 PM UTC 25 Feb 08 05:58:55 PM UTC 25 195047074 ps
T630 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_in_stall.2354994095 Feb 08 05:58:53 PM UTC 25 Feb 08 05:58:56 PM UTC 25 150204225 ps
T631 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_in_trans.3334355562 Feb 08 05:58:55 PM UTC 25 Feb 08 05:58:58 PM UTC 25 179260753 ps
T632 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_link_in_err.752889374 Feb 08 05:58:58 PM UTC 25 Feb 08 05:59:01 PM UTC 25 208858597 ps
T103 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_link_resume.46825554 Feb 08 05:58:04 PM UTC 25 Feb 08 05:59:03 PM UTC 25 29420810819 ps
T633 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_device_timeout.3251745680 Feb 08 05:58:43 PM UTC 25 Feb 08 05:59:05 PM UTC 25 699486384 ps
T634 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_resume_link_active.3972836171 Feb 08 05:58:24 PM UTC 25 Feb 08 05:59:07 PM UTC 25 20172834909 ps
T635 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_streaming_out.1705417156 Feb 08 05:58:30 PM UTC 25 Feb 08 05:59:07 PM UTC 25 2475764654 ps
T636 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_timeout_missing_host_handshake.992601057 Feb 08 05:58:43 PM UTC 25 Feb 08 05:59:07 PM UTC 25 3565814060 ps
T637 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_spurious_pids_ignored.3418931407 Feb 08 05:58:29 PM UTC 25 Feb 08 05:59:08 PM UTC 25 3559055173 ps
T186 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_device_address.2088479483 Feb 08 05:57:41 PM UTC 25 Feb 08 05:59:09 PM UTC 25 36273195902 ps
T294 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_pkt_buffer.3753819296 Feb 08 05:58:20 PM UTC 25 Feb 08 05:59:10 PM UTC 25 15619975974 ps
T638 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_aon_wake_reset.1546334250 Feb 08 05:58:36 PM UTC 25 Feb 08 05:59:11 PM UTC 25 14750093583 ps
T639 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_max_length_out_transaction.3210526922 Feb 08 05:59:08 PM UTC 25 Feb 08 05:59:11 PM UTC 25 223963879 ps
T640 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_max_length_in_transaction.2560819797 Feb 08 05:59:08 PM UTC 25 Feb 08 05:59:11 PM UTC 25 283623141 ps
T641 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_min_length_out_transaction.81956413 Feb 08 05:59:12 PM UTC 25 Feb 08 05:59:14 PM UTC 25 149270296 ps
T642 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_min_length_in_transaction.1504980373 Feb 08 05:59:12 PM UTC 25 Feb 08 05:59:14 PM UTC 25 153047379 ps
T643 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_aon_wake_resume.2090420140 Feb 08 05:58:36 PM UTC 25 Feb 08 05:59:14 PM UTC 25 29601506169 ps
T138 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_nak_trans.1610528658 Feb 08 05:59:12 PM UTC 25 Feb 08 05:59:15 PM UTC 25 214988415 ps
T644 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_pending_in_trans.2613708839 Feb 08 05:59:15 PM UTC 25 Feb 08 05:59:18 PM UTC 25 145097408 ps
T645 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_out_trans_nak.3615522436 Feb 08 05:59:15 PM UTC 25 Feb 08 05:59:18 PM UTC 25 159200540 ps
T646 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_out_iso.2831273871 Feb 08 05:59:15 PM UTC 25 Feb 08 05:59:18 PM UTC 25 241547279 ps
T501 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_out_stall.3514876537 Feb 08 05:59:15 PM UTC 25 Feb 08 05:59:18 PM UTC 25 185232858 ps
T39 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_phy_pins_sense.2533605673 Feb 08 05:59:19 PM UTC 25 Feb 08 05:59:21 PM UTC 25 36328505 ps
T647 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_phy_config_usb_ref_disable.2120660240 Feb 08 05:59:19 PM UTC 25 Feb 08 05:59:21 PM UTC 25 141457465 ps
T648 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_phy_config_rand_bus_type.2451721347 Feb 08 05:59:19 PM UTC 25 Feb 08 05:59:22 PM UTC 25 222827339 ps
T649 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_phy_config_pinflip.2096406873 Feb 08 05:59:19 PM UTC 25 Feb 08 05:59:22 PM UTC 25 199447670 ps
T650 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_iso_retraction.1553207118 Feb 08 05:58:02 PM UTC 25 Feb 08 05:59:25 PM UTC 25 11415383805 ps
T651 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_pkt_received.754512226 Feb 08 05:59:22 PM UTC 25 Feb 08 05:59:25 PM UTC 25 167037596 ps
T652 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_pkt_sent.2039110488 Feb 08 05:59:22 PM UTC 25 Feb 08 05:59:25 PM UTC 25 219400985 ps
T653 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_random_length_in_transaction.1960653506 Feb 08 05:59:22 PM UTC 25 Feb 08 05:59:25 PM UTC 25 182090536 ps
T654 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_freq_loclk.1089524817 Feb 08 05:54:39 PM UTC 25 Feb 08 05:59:28 PM UTC 25 110099931696 ps
T655 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_random_length_out_transaction.3181804942 Feb 08 05:59:26 PM UTC 25 Feb 08 05:59:28 PM UTC 25 166943877 ps
T656 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_max_inter_pkt_delay.1827990362 Feb 08 05:59:08 PM UTC 25 Feb 08 05:59:30 PM UTC 25 1970062119 ps
T104 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_link_suspend.2857213277 Feb 08 05:59:04 PM UTC 25 Feb 08 05:59:32 PM UTC 25 8702235324 ps
T657 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_rx_crc_err.3873743961 Feb 08 05:59:30 PM UTC 25 Feb 08 05:59:32 PM UTC 25 160803889 ps
T658 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_link_resume.2420501181 Feb 08 05:59:02 PM UTC 25 Feb 08 05:59:32 PM UTC 25 7635916852 ps
T659 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_rx_full.2000557734 Feb 08 05:59:31 PM UTC 25 Feb 08 05:59:34 PM UTC 25 368110618 ps
T660 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_rand_bus_resets.2215647 Feb 08 05:58:24 PM UTC 25 Feb 08 05:59:35 PM UTC 25 7677351574 ps
T661 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_max_usb_traffic.703811410 Feb 08 05:59:12 PM UTC 25 Feb 08 05:59:35 PM UTC 25 2332809664 ps
T662 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_rx_pid_err.3989898080 Feb 08 05:59:33 PM UTC 25 Feb 08 05:59:36 PM UTC 25 199639197 ps
T663 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_setup_priority_over_stall_response.1093290244 Feb 08 05:59:33 PM UTC 25 Feb 08 05:59:36 PM UTC 25 203292259 ps
T664 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_setup_priority.3789600651 Feb 08 05:59:33 PM UTC 25 Feb 08 05:59:36 PM UTC 25 338444389 ps
T665 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_min_inter_pkt_delay.2165132023 Feb 08 05:59:12 PM UTC 25 Feb 08 05:59:37 PM UTC 25 2896128984 ps
T666 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_max_non_iso_usb_traffic.221420509 Feb 08 05:59:09 PM UTC 25 Feb 08 05:59:37 PM UTC 25 2775993059 ps
T667 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_setup_stage.1666381145 Feb 08 05:59:35 PM UTC 25 Feb 08 05:59:38 PM UTC 25 178118997 ps
T668 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_setup_trans_ignored.839869164 Feb 08 05:59:37 PM UTC 25 Feb 08 05:59:39 PM UTC 25 145180144 ps
T669 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_stall_trans.1637260074 Feb 08 05:59:37 PM UTC 25 Feb 08 05:59:39 PM UTC 25 159181444 ps
T670 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_stall_priority_over_nak.3367705785 Feb 08 05:59:37 PM UTC 25 Feb 08 05:59:39 PM UTC 25 194395717 ps
T671 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_smoke.1753535828 Feb 08 05:59:37 PM UTC 25 Feb 08 05:59:40 PM UTC 25 240461745 ps
T672 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_stream_len_max.1959481784 Feb 08 05:59:38 PM UTC 25 Feb 08 05:59:42 PM UTC 25 572972418 ps
T673 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_alert_test.3793670538 Feb 08 05:59:41 PM UTC 25 Feb 08 05:59:43 PM UTC 25 42387856 ps
T674 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_tx_rx_disruption.26454234 Feb 08 05:59:41 PM UTC 25 Feb 08 05:59:45 PM UTC 25 455249380 ps
T232 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_sec_cm.3195434814 Feb 08 05:59:41 PM UTC 25 Feb 08 05:59:45 PM UTC 25 919878409 ps
T675 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_av_buffer.1929790917 Feb 08 05:59:46 PM UTC 25 Feb 08 05:59:48 PM UTC 25 168511164 ps
T676 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_bitstuff_err.221986616 Feb 08 05:59:46 PM UTC 25 Feb 08 05:59:48 PM UTC 25 191597615 ps
T176 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_rand_bus_disconnects.2276645372 Feb 08 05:58:24 PM UTC 25 Feb 08 05:59:53 PM UTC 25 2899313836 ps
T677 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_data_toggle_clear.531678020 Feb 08 05:59:49 PM UTC 25 Feb 08 05:59:53 PM UTC 25 505564074 ps
T310 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_data_toggle_restore.3331216075 Feb 08 05:59:49 PM UTC 25 Feb 08 05:59:54 PM UTC 25 879777336 ps
T247 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_stress_usb_traffic.3280972374 Feb 08 05:58:32 PM UTC 25 Feb 08 06:00:00 PM UTC 25 11946089620 ps
T678 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_rand_bus_disconnects.3969899505 Feb 08 05:59:26 PM UTC 25 Feb 08 06:00:02 PM UTC 25 2712774448 ps
T679 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_resume_link_active.249500302 Feb 08 05:59:30 PM UTC 25 Feb 08 06:00:02 PM UTC 25 20179348861 ps
T680 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_iso_retraction.2905139045 Feb 08 05:58:56 PM UTC 25 Feb 08 06:00:03 PM UTC 25 7582213525 ps
T681 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_freq_phase.3565284195 Feb 08 05:56:28 PM UTC 25 Feb 08 06:00:03 PM UTC 25 110170949545 ps
T682 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_freq_loclk.2270123269 Feb 08 05:56:28 PM UTC 25 Feb 08 06:00:08 PM UTC 25 111097604404 ps
T683 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_aon_wake_disconnect.548447571 Feb 08 05:59:43 PM UTC 25 Feb 08 06:00:08 PM UTC 25 9270413640 ps
T684 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_timeout_missing_host_handshake.64908752 Feb 08 05:59:55 PM UTC 25 Feb 08 06:00:09 PM UTC 25 1078857828 ps
T685 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_aon_wake_reset.3593525491 Feb 08 05:59:43 PM UTC 25 Feb 08 06:00:11 PM UTC 25 14574539881 ps
T686 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_spurious_pids_ignored.2060584005 Feb 08 05:59:37 PM UTC 25 Feb 08 06:00:12 PM UTC 25 3713072288 ps
T687 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_rand_suspends.711855420 Feb 08 05:58:24 PM UTC 25 Feb 08 06:00:14 PM UTC 25 13999096091 ps
T688 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_freq_hiclk_max.2130388735 Feb 08 05:56:27 PM UTC 25 Feb 08 06:00:19 PM UTC 25 106318188630 ps
T689 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_device_timeout.3191584215 Feb 08 05:59:54 PM UTC 25 Feb 08 06:00:19 PM UTC 25 2919749565 ps
T690 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_disconnected.1242656706 Feb 08 06:00:03 PM UTC 25 Feb 08 06:00:20 PM UTC 25 155850202 ps
T691 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_freq_loclk_max.1365063731 Feb 08 05:56:28 PM UTC 25 Feb 08 06:00:23 PM UTC 25 89981355854 ps
T692 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_disable_endpoint.2393779345 Feb 08 06:00:01 PM UTC 25 Feb 08 06:00:23 PM UTC 25 895184567 ps
T693 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_enable.3241536968 Feb 08 06:00:20 PM UTC 25 Feb 08 06:00:23 PM UTC 25 60651644 ps
T694 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_link_in_err.379577457 Feb 08 06:00:20 PM UTC 25 Feb 08 06:00:24 PM UTC 25 170107809 ps
T695 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_in_stall.2605948756 Feb 08 06:00:20 PM UTC 25 Feb 08 06:00:24 PM UTC 25 151824057 ps
T197 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_device_address.950537220 Feb 08 05:58:42 PM UTC 25 Feb 08 06:00:24 PM UTC 25 43966059844 ps
T696 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_in_iso.3090326963 Feb 08 06:00:20 PM UTC 25 Feb 08 06:00:24 PM UTC 25 227067141 ps
T697 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_in_trans.2905993869 Feb 08 06:00:20 PM UTC 25 Feb 08 06:00:24 PM UTC 25 286922945 ps
T366 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_endpoint_types.3143196142 Feb 08 06:00:20 PM UTC 25 Feb 08 06:00:24 PM UTC 25 512925380 ps
T295 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_pkt_buffer.3331457217 Feb 08 05:59:22 PM UTC 25 Feb 08 06:00:25 PM UTC 25 15849792795 ps
T698 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_fifo_rst.955346430 Feb 08 06:00:20 PM UTC 25 Feb 08 06:00:25 PM UTC 25 271545656 ps
T390 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_device_address.3668066388 Feb 08 05:59:54 PM UTC 25 Feb 08 06:00:25 PM UTC 25 14198954021 ps
T699 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_endpoint_access.2921596374 Feb 08 06:00:20 PM UTC 25 Feb 08 06:00:26 PM UTC 25 872408368 ps
T205 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_aon_wake_resume.3616991635 Feb 08 05:59:44 PM UTC 25 Feb 08 06:00:29 PM UTC 25 24923308933 ps
T700 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_min_length_out_transaction.3594116670 Feb 08 06:00:27 PM UTC 25 Feb 08 06:00:30 PM UTC 25 148610343 ps
T701 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_max_length_out_transaction.1052396855 Feb 08 06:00:27 PM UTC 25 Feb 08 06:00:30 PM UTC 25 203375899 ps
T702 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_min_length_in_transaction.3437991255 Feb 08 06:00:27 PM UTC 25 Feb 08 06:00:30 PM UTC 25 167777937 ps
T703 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_max_length_in_transaction.2921345066 Feb 08 06:00:27 PM UTC 25 Feb 08 06:00:30 PM UTC 25 234767405 ps
T126 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_nak_trans.4164838025 Feb 08 06:00:27 PM UTC 25 Feb 08 06:00:30 PM UTC 25 202328371 ps
T704 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_out_trans_nak.3718021863 Feb 08 06:00:27 PM UTC 25 Feb 08 06:00:30 PM UTC 25 145876041 ps
T705 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_out_iso.4279175996 Feb 08 06:00:27 PM UTC 25 Feb 08 06:00:30 PM UTC 25 180264525 ps
T706 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_out_stall.1767355238 Feb 08 06:00:27 PM UTC 25 Feb 08 06:00:30 PM UTC 25 171173510 ps
T707 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_link_suspend.4244238370 Feb 08 06:00:22 PM UTC 25 Feb 08 06:00:31 PM UTC 25 3453134760 ps
T708 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_phy_pins_sense.939611170 Feb 08 06:00:31 PM UTC 25 Feb 08 06:00:33 PM UTC 25 39344175 ps
T709 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_phy_config_usb_ref_disable.1145879006 Feb 08 06:00:31 PM UTC 25 Feb 08 06:00:34 PM UTC 25 140307751 ps
T710 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_pending_in_trans.940390940 Feb 08 06:00:31 PM UTC 25 Feb 08 06:00:34 PM UTC 25 187827383 ps
T711 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_low_speed_traffic.3095063272 Feb 08 05:59:06 PM UTC 25 Feb 08 06:00:34 PM UTC 25 3020540194 ps
T712 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_pkt_received.1313618551 Feb 08 06:00:31 PM UTC 25 Feb 08 06:00:34 PM UTC 25 167744423 ps
T713 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_phy_config_pinflip.2258034460 Feb 08 06:00:31 PM UTC 25 Feb 08 06:00:34 PM UTC 25 268494494 ps
T714 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_pkt_sent.82469513 Feb 08 06:00:31 PM UTC 25 Feb 08 06:00:34 PM UTC 25 199152648 ps
T715 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_random_length_in_transaction.821979961 Feb 08 06:00:31 PM UTC 25 Feb 08 06:00:34 PM UTC 25 226025987 ps
T716 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_random_length_out_transaction.3333939672 Feb 08 06:00:31 PM UTC 25 Feb 08 06:00:34 PM UTC 25 206054367 ps
T717 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_streaming_out.1118710654 Feb 08 05:59:38 PM UTC 25 Feb 08 06:00:38 PM UTC 25 1740552628 ps
T718 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_setup_stage.380314483 Feb 08 06:00:35 PM UTC 25 Feb 08 06:00:38 PM UTC 25 147776823 ps
T719 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_rx_crc_err.3218636042 Feb 08 06:00:35 PM UTC 25 Feb 08 06:00:38 PM UTC 25 148011372 ps
T720 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_setup_trans_ignored.4087415104 Feb 08 06:00:35 PM UTC 25 Feb 08 06:00:38 PM UTC 25 149604442 ps
T721 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_smoke.812675260 Feb 08 06:00:35 PM UTC 25 Feb 08 06:00:39 PM UTC 25 213763297 ps
T722 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_rx_full.1431894152 Feb 08 06:00:35 PM UTC 25 Feb 08 06:00:39 PM UTC 25 345706239 ps
T723 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_stall_priority_over_nak.946672142 Feb 08 06:00:39 PM UTC 25 Feb 08 06:00:41 PM UTC 25 172372247 ps
T724 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_max_non_iso_usb_traffic.3799891536 Feb 08 06:00:27 PM UTC 25 Feb 08 06:00:42 PM UTC 25 1829708987 ps
T725 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_smoke.1646214186 Feb 08 06:01:33 PM UTC 25 Feb 08 06:01:36 PM UTC 25 212120681 ps
T726 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_stall_trans.3451815907 Feb 08 06:00:40 PM UTC 25 Feb 08 06:00:44 PM UTC 25 184290682 ps
T238 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_tx_rx_disruption.3937544595 Feb 08 06:00:40 PM UTC 25 Feb 08 06:00:45 PM UTC 25 645890128 ps
T727 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_alert_test.351090394 Feb 08 06:00:43 PM UTC 25 Feb 08 06:00:45 PM UTC 25 42639598 ps
T728 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_stream_len_max.3405729898 Feb 08 06:00:40 PM UTC 25 Feb 08 06:00:46 PM UTC 25 711201605 ps
T729 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_rand_bus_resets.2527081559 Feb 08 05:59:26 PM UTC 25 Feb 08 06:00:47 PM UTC 25 3345377383 ps
T730 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_av_buffer.2064925419 Feb 08 06:00:46 PM UTC 25 Feb 08 06:00:48 PM UTC 25 195045049 ps
T731 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_bitstuff_err.2388205309 Feb 08 06:00:46 PM UTC 25 Feb 08 06:00:48 PM UTC 25 204437838 ps
T732 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_freq_phase.2706314897 Feb 08 05:57:56 PM UTC 25 Feb 08 06:00:49 PM UTC 25 84177845240 ps
T733 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_data_toggle_clear.3487431130 Feb 08 06:00:47 PM UTC 25 Feb 08 06:00:50 PM UTC 25 359037858 ps
T734 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_data_toggle_restore.3954468135 Feb 08 06:00:48 PM UTC 25 Feb 08 06:00:52 PM UTC 25 527458675 ps
T476 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_disable_endpoint.1734460394 Feb 08 06:00:51 PM UTC 25 Feb 08 06:00:55 PM UTC 25 630820422 ps
T735 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_disconnected.2286819792 Feb 08 06:00:53 PM UTC 25 Feb 08 06:00:55 PM UTC 25 144144715 ps
T736 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_aon_wake_disconnect.1374217137 Feb 08 06:00:45 PM UTC 25 Feb 08 06:00:56 PM UTC 25 5668040020 ps
T737 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_enable.3851296147 Feb 08 06:00:55 PM UTC 25 Feb 08 06:00:57 PM UTC 25 82935275 ps
T738 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_max_usb_traffic.4259537295 Feb 08 06:00:27 PM UTC 25 Feb 08 06:00:58 PM UTC 25 2877852527 ps
T739 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_rand_bus_disconnects.3692660893 Feb 08 06:00:32 PM UTC 25 Feb 08 06:00:58 PM UTC 25 5648076310 ps
T740 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_endpoint_types.2962477163 Feb 08 06:00:57 PM UTC 25 Feb 08 06:00:59 PM UTC 25 160636434 ps
T741 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_endpoint_access.105719449 Feb 08 06:00:56 PM UTC 25 Feb 08 06:00:59 PM UTC 25 882482175 ps
T742 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_fifo_rst.1394326351 Feb 08 06:00:57 PM UTC 25 Feb 08 06:01:01 PM UTC 25 211487061 ps
T743 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_in_iso.3994128544 Feb 08 06:00:59 PM UTC 25 Feb 08 06:01:02 PM UTC 25 156823181 ps
T744 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_in_stall.484763391 Feb 08 06:00:59 PM UTC 25 Feb 08 06:01:02 PM UTC 25 166740002 ps
T745 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_in_trans.217837447 Feb 08 06:01:00 PM UTC 25 Feb 08 06:01:03 PM UTC 25 188975184 ps
T746 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_device_timeout.796492213 Feb 08 06:00:49 PM UTC 25 Feb 08 06:01:04 PM UTC 25 1520443528 ps
T747 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_link_in_err.560233400 Feb 08 06:01:02 PM UTC 25 Feb 08 06:01:05 PM UTC 25 244570840 ps
T748 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_max_length_in_transaction.1873401908 Feb 08 06:01:05 PM UTC 25 Feb 08 06:01:08 PM UTC 25 240762383 ps
T749 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_timeout_missing_host_handshake.778624251 Feb 08 06:00:51 PM UTC 25 Feb 08 06:01:10 PM UTC 25 1527842044 ps
T750 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_resume_link_active.1595354935 Feb 08 06:00:35 PM UTC 25 Feb 08 06:01:10 PM UTC 25 20165784879 ps
T751 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_max_length_out_transaction.491317190 Feb 08 06:01:08 PM UTC 25 Feb 08 06:01:11 PM UTC 25 197699654 ps
T752 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_invalid_sync.3962537321 Feb 08 06:00:20 PM UTC 25 Feb 08 06:01:16 PM UTC 25 4753577748 ps
T753 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_aon_wake_reset.3664261645 Feb 08 06:00:45 PM UTC 25 Feb 08 06:01:18 PM UTC 25 13657133588 ps
T496 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_invalid_sync.2583293192 Feb 08 06:00:58 PM UTC 25 Feb 08 06:01:19 PM UTC 25 2810645275 ps
T754 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_max_inter_pkt_delay.3795006387 Feb 08 06:00:27 PM UTC 25 Feb 08 06:01:19 PM UTC 25 1961052551 ps
T755 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_min_length_in_transaction.1247965276 Feb 08 06:01:17 PM UTC 25 Feb 08 06:01:19 PM UTC 25 194372694 ps
T756 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_min_length_out_transaction.4222243013 Feb 08 06:01:19 PM UTC 25 Feb 08 06:01:21 PM UTC 25 146822509 ps
T757 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_freq_loclk_max.2429963621 Feb 08 05:57:56 PM UTC 25 Feb 08 06:01:22 PM UTC 25 103200752277 ps
T758 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_spurious_pids_ignored.3238027056 Feb 08 06:00:35 PM UTC 25 Feb 08 06:01:22 PM UTC 25 3198356505 ps
T149 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_nak_trans.1290362621 Feb 08 06:01:20 PM UTC 25 Feb 08 06:01:23 PM UTC 25 171486054 ps
T759 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_out_stall.1361682093 Feb 08 06:01:21 PM UTC 25 Feb 08 06:01:23 PM UTC 25 199802464 ps
T760 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_out_iso.4193249960 Feb 08 06:01:20 PM UTC 25 Feb 08 06:01:23 PM UTC 25 245550712 ps
T761 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_link_resume.877127210 Feb 08 06:00:22 PM UTC 25 Feb 08 06:01:23 PM UTC 25 30921401867 ps
T40 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_phy_pins_sense.177228772 Feb 08 06:01:24 PM UTC 25 Feb 08 06:01:26 PM UTC 25 35043055 ps
T762 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_phy_config_usb_ref_disable.2784617353 Feb 08 06:01:24 PM UTC 25 Feb 08 06:01:26 PM UTC 25 186724859 ps
T198 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_pending_in_trans.586202237 Feb 08 06:01:24 PM UTC 25 Feb 08 06:01:26 PM UTC 25 165925162 ps
T763 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_phy_config_pinflip.2403099363 Feb 08 06:01:24 PM UTC 25 Feb 08 06:01:26 PM UTC 25 184871013 ps
T764 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_out_trans_nak.649810503 Feb 08 06:01:24 PM UTC 25 Feb 08 06:01:26 PM UTC 25 181590627 ps
T765 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_pkt_received.2953665282 Feb 08 06:01:25 PM UTC 25 Feb 08 06:01:28 PM UTC 25 182633804 ps
T766 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_aon_wake_resume.3857306986 Feb 08 06:00:45 PM UTC 25 Feb 08 06:01:28 PM UTC 25 30097095410 ps
T177 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_stress_usb_traffic.2403405752 Feb 08 05:59:40 PM UTC 25 Feb 08 06:01:29 PM UTC 25 9133390306 ps
T767 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_pkt_sent.1437845214 Feb 08 06:01:27 PM UTC 25 Feb 08 06:01:30 PM UTC 25 271332045 ps
T768 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_random_length_in_transaction.2959873929 Feb 08 06:01:27 PM UTC 25 Feb 08 06:01:30 PM UTC 25 207346608 ps
T769 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_random_length_out_transaction.1890270668 Feb 08 06:01:27 PM UTC 25 Feb 08 06:01:30 PM UTC 25 187094996 ps
T770 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_rx_crc_err.964355150 Feb 08 06:01:30 PM UTC 25 Feb 08 06:01:32 PM UTC 25 133209884 ps
T771 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_setup_trans_ignored.689426479 Feb 08 06:01:31 PM UTC 25 Feb 08 06:01:33 PM UTC 25 160741367 ps
T772 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_setup_stage.3074304072 Feb 08 06:01:31 PM UTC 25 Feb 08 06:01:34 PM UTC 25 183517443 ps
T59 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_rx_full.3321117367 Feb 08 06:01:31 PM UTC 25 Feb 08 06:01:34 PM UTC 25 255404998 ps
T773 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_max_non_iso_usb_traffic.1327141201 Feb 08 06:01:10 PM UTC 25 Feb 08 06:01:34 PM UTC 25 2618179494 ps
T774 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_freq_hiclk.2592624794 Feb 08 05:57:53 PM UTC 25 Feb 08 06:01:34 PM UTC 25 121188500452 ps
T775 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_freq_loclk.1400629153 Feb 08 05:57:55 PM UTC 25 Feb 08 06:01:34 PM UTC 25 99105988770 ps
T776 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_freq_hiclk.574725267 Feb 08 05:56:25 PM UTC 25 Feb 08 06:01:35 PM UTC 25 121181840384 ps
T777 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_link_suspend.1795486650 Feb 08 06:01:03 PM UTC 25 Feb 08 06:01:35 PM UTC 25 10431853396 ps
T778 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_min_inter_pkt_delay.796488775 Feb 08 06:00:27 PM UTC 25 Feb 08 06:01:36 PM UTC 25 2464201494 ps
T779 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_freq_hiclk_max.3070294989 Feb 08 05:57:54 PM UTC 25 Feb 08 06:01:37 PM UTC 25 99163458842 ps
T780 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_stall_trans.3528270172 Feb 08 06:01:35 PM UTC 25 Feb 08 06:01:37 PM UTC 25 171508194 ps
T781 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_stall_priority_over_nak.1357503881 Feb 08 06:01:34 PM UTC 25 Feb 08 06:01:37 PM UTC 25 168101231 ps
T782 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_enable.833425429 Feb 08 06:02:17 PM UTC 25 Feb 08 06:02:20 PM UTC 25 37152648 ps
T783 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_disable_endpoint.846688336 Feb 08 06:02:16 PM UTC 25 Feb 08 06:02:20 PM UTC 25 741716511 ps
T784 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_alert_test.728987841 Feb 08 06:01:39 PM UTC 25 Feb 08 06:01:41 PM UTC 25 40811638 ps
T785 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_min_inter_pkt_delay.620926589 Feb 08 06:01:12 PM UTC 25 Feb 08 06:01:41 PM UTC 25 2759464620 ps
T222 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_tx_rx_disruption.2525784891 Feb 08 06:01:39 PM UTC 25 Feb 08 06:01:42 PM UTC 25 572200381 ps
T786 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_stream_len_max.960362986 Feb 08 06:01:39 PM UTC 25 Feb 08 06:01:42 PM UTC 25 948505807 ps
T787 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_av_buffer.2342056282 Feb 08 06:01:40 PM UTC 25 Feb 08 06:01:43 PM UTC 25 168375384 ps
T267 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_pkt_buffer.2754419601 Feb 08 06:00:31 PM UTC 25 Feb 08 06:01:43 PM UTC 25 21059704686 ps
T182 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_rand_bus_resets.1733772172 Feb 08 06:00:35 PM UTC 25 Feb 08 06:01:43 PM UTC 25 3139021583 ps
T788 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_bitstuff_err.528270604 Feb 08 06:01:42 PM UTC 25 Feb 08 06:01:44 PM UTC 25 142771158 ps
T789 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_iso_retraction.1979792559 Feb 08 06:01:01 PM UTC 25 Feb 08 06:01:45 PM UTC 25 5385393445 ps
T311 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_data_toggle_restore.3079828093 Feb 08 06:01:42 PM UTC 25 Feb 08 06:01:45 PM UTC 25 361563584 ps
T790 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_max_usb_traffic.2697722378 Feb 08 06:01:11 PM UTC 25 Feb 08 06:01:45 PM UTC 25 2512315853 ps
T791 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_data_toggle_clear.1655603000 Feb 08 06:01:42 PM UTC 25 Feb 08 06:01:46 PM UTC 25 387068521 ps
T792 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_enable.351817027 Feb 08 06:01:45 PM UTC 25 Feb 08 06:01:47 PM UTC 25 33139118 ps
T507 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_disconnected.3297285492 Feb 08 06:01:45 PM UTC 25 Feb 08 06:01:48 PM UTC 25 140080983 ps
T348 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_endpoint_types.1934581299 Feb 08 06:01:46 PM UTC 25 Feb 08 06:01:49 PM UTC 25 407823681 ps
T793 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_disable_endpoint.1332399458 Feb 08 06:01:45 PM UTC 25 Feb 08 06:01:49 PM UTC 25 640423844 ps
T794 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_fifo_rst.3659266731 Feb 08 06:01:46 PM UTC 25 Feb 08 06:01:50 PM UTC 25 192710646 ps
T795 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_endpoint_access.505959335 Feb 08 06:01:45 PM UTC 25 Feb 08 06:01:50 PM UTC 25 760045335 ps
T796 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_in_iso.621890963 Feb 08 06:01:47 PM UTC 25 Feb 08 06:01:50 PM UTC 25 221356108 ps