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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.44 98.11 95.91 97.44 87.30 98.22 98.17 92.94


Total test records in report: 3732
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T2925 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_random_length_in_transaction.4263288416 Feb 08 06:16:55 PM UTC 25 Feb 08 06:16:58 PM UTC 25 218167296 ps
T2926 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_setup_trans_ignored.1989071173 Feb 08 06:16:58 PM UTC 25 Feb 08 06:17:01 PM UTC 25 152928027 ps
T2927 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_invalid_sync.631353000 Feb 08 06:15:11 PM UTC 25 Feb 08 06:17:29 PM UTC 25 4915354499 ps
T2928 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_rx_crc_err.3791237024 Feb 08 06:16:58 PM UTC 25 Feb 08 06:17:01 PM UTC 25 157282107 ps
T2929 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_random_length_out_transaction.3967474505 Feb 08 06:16:58 PM UTC 25 Feb 08 06:17:01 PM UTC 25 166251958 ps
T2930 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_setup_stage.3048095693 Feb 08 06:16:58 PM UTC 25 Feb 08 06:17:01 PM UTC 25 170457555 ps
T2931 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_alert_test.1088202911 Feb 08 06:16:59 PM UTC 25 Feb 08 06:17:01 PM UTC 25 38021388 ps
T2932 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_stall_priority_over_nak.468900057 Feb 08 06:16:58 PM UTC 25 Feb 08 06:17:01 PM UTC 25 149085924 ps
T2933 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_stall_trans.2839037039 Feb 08 06:16:58 PM UTC 25 Feb 08 06:17:01 PM UTC 25 188056752 ps
T2934 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_smoke.2629351335 Feb 08 06:16:58 PM UTC 25 Feb 08 06:17:01 PM UTC 25 231878737 ps
T2935 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_rx_full.3437037799 Feb 08 06:16:58 PM UTC 25 Feb 08 06:17:02 PM UTC 25 373627402 ps
T2936 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_stream_len_max.1413515944 Feb 08 06:16:59 PM UTC 25 Feb 08 06:17:03 PM UTC 25 871413193 ps
T2937 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_aon_wake_disconnect.2409430216 Feb 08 06:16:43 PM UTC 25 Feb 08 06:17:03 PM UTC 25 11343705516 ps
T2938 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_tx_rx_disruption.2587062784 Feb 08 06:16:59 PM UTC 25 Feb 08 06:17:03 PM UTC 25 648026066 ps
T2939 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_bitstuff_err.3392303107 Feb 08 06:17:02 PM UTC 25 Feb 08 06:17:04 PM UTC 25 149653465 ps
T2940 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_av_buffer.3729524347 Feb 08 06:17:02 PM UTC 25 Feb 08 06:17:05 PM UTC 25 143403130 ps
T2941 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_link_suspend.998109308 Feb 08 06:16:51 PM UTC 25 Feb 08 06:17:05 PM UTC 25 5493154932 ps
T2942 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_data_toggle_clear.2921112813 Feb 08 06:17:02 PM UTC 25 Feb 08 06:17:05 PM UTC 25 397479243 ps
T2943 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_data_toggle_restore.1876982037 Feb 08 06:17:02 PM UTC 25 Feb 08 06:17:06 PM UTC 25 476352438 ps
T2944 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_enable.715174112 Feb 08 06:17:04 PM UTC 25 Feb 08 06:17:06 PM UTC 25 119172294 ps
T2945 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_disconnected.1178421379 Feb 08 06:17:04 PM UTC 25 Feb 08 06:17:06 PM UTC 25 205681798 ps
T2946 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_disable_endpoint.2094363950 Feb 08 06:17:02 PM UTC 25 Feb 08 06:17:06 PM UTC 25 586736056 ps
T376 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_endpoint_types.2423306058 Feb 08 06:17:04 PM UTC 25 Feb 08 06:17:07 PM UTC 25 400590871 ps
T2947 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_in_stall.2850251453 Feb 08 06:17:06 PM UTC 25 Feb 08 06:17:08 PM UTC 25 141540827 ps
T2948 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_fifo_rst.1905904219 Feb 08 06:17:05 PM UTC 25 Feb 08 06:17:09 PM UTC 25 372662318 ps
T2949 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_invalid_sync.2170201539 Feb 08 06:16:27 PM UTC 25 Feb 08 06:17:09 PM UTC 25 4122204608 ps
T2950 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_endpoint_access.754638071 Feb 08 06:17:04 PM UTC 25 Feb 08 06:17:09 PM UTC 25 874258673 ps
T2951 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_in_iso.2881464398 Feb 08 06:17:06 PM UTC 25 Feb 08 06:17:09 PM UTC 25 250018729 ps
T2952 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_link_in_err.1443036214 Feb 08 06:17:08 PM UTC 25 Feb 08 06:17:10 PM UTC 25 199165502 ps
T2953 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_in_trans.2836520246 Feb 08 06:17:07 PM UTC 25 Feb 08 06:17:10 PM UTC 25 212902874 ps
T2954 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_timeout_missing_host_handshake.1377953283 Feb 08 06:16:45 PM UTC 25 Feb 08 06:17:12 PM UTC 25 2940189180 ps
T2955 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_max_length_in_transaction.727687041 Feb 08 06:17:10 PM UTC 25 Feb 08 06:17:12 PM UTC 25 304915121 ps
T2956 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_aon_wake_reset.1508253119 Feb 08 06:16:43 PM UTC 25 Feb 08 06:17:13 PM UTC 25 19566146103 ps
T2957 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_max_length_out_transaction.3674275519 Feb 08 06:17:10 PM UTC 25 Feb 08 06:17:13 PM UTC 25 232320671 ps
T2958 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_aon_wake_resume.3659347387 Feb 08 06:16:24 PM UTC 25 Feb 08 06:17:14 PM UTC 25 29110847226 ps
T2959 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_min_length_in_transaction.497131437 Feb 08 06:17:11 PM UTC 25 Feb 08 06:17:14 PM UTC 25 151936716 ps
T2960 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_min_length_out_transaction.2552432252 Feb 08 06:17:11 PM UTC 25 Feb 08 06:17:14 PM UTC 25 149019044 ps
T2961 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_timeout_missing_host_handshake.526864158 Feb 08 06:16:25 PM UTC 25 Feb 08 06:17:14 PM UTC 25 1983143362 ps
T2962 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_iso_retraction.301890710 Feb 08 06:14:52 PM UTC 25 Feb 08 06:17:14 PM UTC 25 10778830703 ps
T2963 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_out_stall.143048417 Feb 08 06:17:13 PM UTC 25 Feb 08 06:17:15 PM UTC 25 181376594 ps
T2964 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_nak_trans.2343139912 Feb 08 06:17:13 PM UTC 25 Feb 08 06:17:16 PM UTC 25 186843513 ps
T2965 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_out_iso.1882079278 Feb 08 06:17:13 PM UTC 25 Feb 08 06:17:16 PM UTC 25 171011316 ps
T2966 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_phy_pins_sense.4279146175 Feb 08 06:17:14 PM UTC 25 Feb 08 06:17:17 PM UTC 25 38608968 ps
T2967 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_phy_config_pinflip.1734925915 Feb 08 06:17:14 PM UTC 25 Feb 08 06:17:17 PM UTC 25 217659727 ps
T2968 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_pending_in_trans.823487935 Feb 08 06:17:14 PM UTC 25 Feb 08 06:17:17 PM UTC 25 155197408 ps
T2969 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_invalid_sync.1993389850 Feb 08 06:16:10 PM UTC 25 Feb 08 06:17:17 PM UTC 25 2470637794 ps
T2970 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_max_inter_pkt_delay.1408445788 Feb 08 06:16:12 PM UTC 25 Feb 08 06:17:17 PM UTC 25 2342293774 ps
T2971 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_out_trans_nak.3249699266 Feb 08 06:17:14 PM UTC 25 Feb 08 06:17:17 PM UTC 25 214615627 ps
T2972 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_phy_config_usb_ref_disable.3926670146 Feb 08 06:17:14 PM UTC 25 Feb 08 06:17:17 PM UTC 25 211648293 ps
T2973 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_aon_wake_disconnect.1725817073 Feb 08 06:17:00 PM UTC 25 Feb 08 06:17:18 PM UTC 25 4654072146 ps
T2974 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_pkt_received.173580829 Feb 08 06:17:16 PM UTC 25 Feb 08 06:17:18 PM UTC 25 202238774 ps
T2975 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_pkt_sent.2221942660 Feb 08 06:17:16 PM UTC 25 Feb 08 06:17:18 PM UTC 25 212086458 ps
T2976 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_random_length_out_transaction.1059841119 Feb 08 06:17:17 PM UTC 25 Feb 08 06:17:19 PM UTC 25 160174680 ps
T2977 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_random_length_in_transaction.964322187 Feb 08 06:17:17 PM UTC 25 Feb 08 06:17:20 PM UTC 25 202412219 ps
T2978 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_setup_stage.4291241697 Feb 08 06:17:18 PM UTC 25 Feb 08 06:17:21 PM UTC 25 159406501 ps
T2979 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_rx_crc_err.1308356597 Feb 08 06:17:18 PM UTC 25 Feb 08 06:17:21 PM UTC 25 188252151 ps
T2980 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_setup_trans_ignored.3680836994 Feb 08 06:17:18 PM UTC 25 Feb 08 06:17:21 PM UTC 25 184538696 ps
T2981 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_rx_full.1934145114 Feb 08 06:17:18 PM UTC 25 Feb 08 06:17:21 PM UTC 25 359118952 ps
T2982 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_stall_priority_over_nak.1386271511 Feb 08 06:17:19 PM UTC 25 Feb 08 06:17:21 PM UTC 25 175895038 ps
T2983 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_smoke.2416270336 Feb 08 06:17:18 PM UTC 25 Feb 08 06:17:21 PM UTC 25 239296263 ps
T2984 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_stall_trans.3254621344 Feb 08 06:17:20 PM UTC 25 Feb 08 06:17:22 PM UTC 25 160293460 ps
T2985 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_pkt_buffer.2240556923 Feb 08 06:16:38 PM UTC 25 Feb 08 06:17:23 PM UTC 25 13686548251 ps
T2986 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_tx_rx_disruption.2776048243 Feb 08 06:17:20 PM UTC 25 Feb 08 06:17:24 PM UTC 25 577597612 ps
T2987 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_device_timeout.3223693872 Feb 08 06:17:02 PM UTC 25 Feb 08 06:17:24 PM UTC 25 884453031 ps
T2988 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_alert_test.2548268668 Feb 08 06:17:22 PM UTC 25 Feb 08 06:17:25 PM UTC 25 53428357 ps
T2989 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_bitstuff_err.3809869266 Feb 08 06:17:23 PM UTC 25 Feb 08 06:17:25 PM UTC 25 168766135 ps
T2990 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_av_buffer.673053667 Feb 08 06:17:23 PM UTC 25 Feb 08 06:17:25 PM UTC 25 222963626 ps
T2991 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_invalid_sync.2635484888 Feb 08 06:16:48 PM UTC 25 Feb 08 06:17:25 PM UTC 25 3514992285 ps
T2992 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_stream_len_max.743680163 Feb 08 06:17:20 PM UTC 25 Feb 08 06:17:25 PM UTC 25 899750035 ps
T2993 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_data_toggle_clear.1168229405 Feb 08 06:17:24 PM UTC 25 Feb 08 06:17:27 PM UTC 25 293012870 ps
T2994 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_device_timeout.3551925667 Feb 08 06:16:45 PM UTC 25 Feb 08 06:17:28 PM UTC 25 4755870379 ps
T2995 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_disconnected.3232750907 Feb 08 06:17:26 PM UTC 25 Feb 08 06:17:28 PM UTC 25 153017437 ps
T2996 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_enable.126812758 Feb 08 06:17:26 PM UTC 25 Feb 08 06:17:28 PM UTC 25 36034627 ps
T2997 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_link_resume.3854676686 Feb 08 06:17:08 PM UTC 25 Feb 08 06:17:28 PM UTC 25 11956269138 ps
T2998 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_disable_endpoint.2879895438 Feb 08 06:17:26 PM UTC 25 Feb 08 06:17:30 PM UTC 25 851694332 ps
T2999 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_min_inter_pkt_delay.3441613783 Feb 08 06:15:54 PM UTC 25 Feb 08 06:17:30 PM UTC 25 3577838482 ps
T3000 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_aon_wake_resume.1934988321 Feb 08 06:16:45 PM UTC 25 Feb 08 06:17:30 PM UTC 25 30059349857 ps
T3001 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_aon_wake_reset.1253664540 Feb 08 06:17:00 PM UTC 25 Feb 08 06:17:30 PM UTC 25 15459298942 ps
T3002 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_data_toggle_restore.785885838 Feb 08 06:17:24 PM UTC 25 Feb 08 06:17:30 PM UTC 25 1043044251 ps
T342 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_endpoint_types.2272145578 Feb 08 06:17:27 PM UTC 25 Feb 08 06:17:31 PM UTC 25 719130912 ps
T3003 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_endpoint_access.3352860178 Feb 08 06:17:27 PM UTC 25 Feb 08 06:17:31 PM UTC 25 815215231 ps
T3004 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_in_stall.2757818504 Feb 08 06:17:30 PM UTC 25 Feb 08 06:17:32 PM UTC 25 157763218 ps
T3005 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_iso_retraction.3520879411 Feb 08 06:15:50 PM UTC 25 Feb 08 06:17:32 PM UTC 25 14277362730 ps
T3006 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_in_trans.3808367222 Feb 08 06:17:30 PM UTC 25 Feb 08 06:17:32 PM UTC 25 173291831 ps
T3007 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_link_suspend.1669266485 Feb 08 06:17:08 PM UTC 25 Feb 08 06:17:33 PM UTC 25 11083485924 ps
T3008 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_in_iso.245649894 Feb 08 06:17:30 PM UTC 25 Feb 08 06:17:33 PM UTC 25 209717154 ps
T3009 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_fifo_rst.1659488384 Feb 08 06:17:28 PM UTC 25 Feb 08 06:17:33 PM UTC 25 306494960 ps
T3010 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_link_in_err.2936233957 Feb 08 06:17:31 PM UTC 25 Feb 08 06:17:34 PM UTC 25 214782510 ps
T3011 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_max_length_in_transaction.2084369158 Feb 08 06:17:31 PM UTC 25 Feb 08 06:17:34 PM UTC 25 239369502 ps
T3012 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_min_length_in_transaction.2118919006 Feb 08 06:17:33 PM UTC 25 Feb 08 06:17:35 PM UTC 25 164806962 ps
T3013 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_max_length_out_transaction.1501744192 Feb 08 06:17:33 PM UTC 25 Feb 08 06:17:36 PM UTC 25 208445034 ps
T3014 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_min_length_out_transaction.1174441806 Feb 08 06:17:33 PM UTC 25 Feb 08 06:17:36 PM UTC 25 157744822 ps
T3015 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_min_inter_pkt_delay.940289476 Feb 08 06:17:10 PM UTC 25 Feb 08 06:17:37 PM UTC 25 2994403260 ps
T3016 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_out_stall.289063939 Feb 08 06:17:34 PM UTC 25 Feb 08 06:17:37 PM UTC 25 218447121 ps
T3017 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_nak_trans.301803311 Feb 08 06:17:34 PM UTC 25 Feb 08 06:17:37 PM UTC 25 232442259 ps
T3018 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_out_iso.745632840 Feb 08 06:17:34 PM UTC 25 Feb 08 06:17:37 PM UTC 25 188493583 ps
T3019 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_link_resume.966085140 Feb 08 06:16:51 PM UTC 25 Feb 08 06:17:38 PM UTC 25 24141607229 ps
T3020 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_device_address.1454281193 Feb 08 06:16:24 PM UTC 25 Feb 08 06:17:38 PM UTC 25 34550290796 ps
T3021 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_pending_in_trans.3744448175 Feb 08 06:17:36 PM UTC 25 Feb 08 06:17:38 PM UTC 25 146262854 ps
T3022 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_out_trans_nak.1492259533 Feb 08 06:17:36 PM UTC 25 Feb 08 06:17:38 PM UTC 25 171156276 ps
T3023 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_phy_config_pinflip.2654772908 Feb 08 06:17:36 PM UTC 25 Feb 08 06:17:39 PM UTC 25 215521086 ps
T3024 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_spurious_pids_ignored.3459551464 Feb 08 06:16:03 PM UTC 25 Feb 08 06:17:39 PM UTC 25 2772318119 ps
T3025 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_phy_pins_sense.439445487 Feb 08 06:17:37 PM UTC 25 Feb 08 06:17:39 PM UTC 25 40868190 ps
T3026 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_phy_config_usb_ref_disable.1861251029 Feb 08 06:17:37 PM UTC 25 Feb 08 06:17:39 PM UTC 25 139165289 ps
T3027 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_iso_retraction.1830576600 Feb 08 06:16:12 PM UTC 25 Feb 08 06:17:40 PM UTC 25 13203215824 ps
T3028 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_pkt_received.3049545395 Feb 08 06:17:38 PM UTC 25 Feb 08 06:17:41 PM UTC 25 211974342 ps
T3029 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_pkt_sent.757237980 Feb 08 06:17:38 PM UTC 25 Feb 08 06:17:41 PM UTC 25 182078245 ps
T3030 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_random_length_in_transaction.3899268609 Feb 08 06:17:38 PM UTC 25 Feb 08 06:17:41 PM UTC 25 177708233 ps
T3031 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_streaming_out.1145625539 Feb 08 06:17:20 PM UTC 25 Feb 08 06:17:42 PM UTC 25 2281205128 ps
T3032 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_rx_crc_err.819759977 Feb 08 06:17:40 PM UTC 25 Feb 08 06:17:43 PM UTC 25 239699869 ps
T3033 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_setup_stage.3548864376 Feb 08 06:17:41 PM UTC 25 Feb 08 06:17:43 PM UTC 25 154104563 ps
T3034 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_setup_trans_ignored.1771562576 Feb 08 06:17:41 PM UTC 25 Feb 08 06:17:43 PM UTC 25 146860098 ps
T3035 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_aon_wake_disconnect.481615284 Feb 08 06:17:22 PM UTC 25 Feb 08 06:17:43 PM UTC 25 11211127868 ps
T3036 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_random_length_out_transaction.3827569248 Feb 08 06:17:40 PM UTC 25 Feb 08 06:17:43 PM UTC 25 191089306 ps
T3037 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_smoke.3569914585 Feb 08 06:17:41 PM UTC 25 Feb 08 06:17:43 PM UTC 25 211845155 ps
T3038 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_stall_priority_over_nak.546643731 Feb 08 06:17:41 PM UTC 25 Feb 08 06:17:43 PM UTC 25 230495429 ps
T3039 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_rx_full.3943788753 Feb 08 06:17:40 PM UTC 25 Feb 08 06:17:44 PM UTC 25 245603503 ps
T3040 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_max_inter_pkt_delay.3647985381 Feb 08 06:16:51 PM UTC 25 Feb 08 06:17:44 PM UTC 25 2018703266 ps
T3041 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_stall_trans.405099317 Feb 08 06:17:42 PM UTC 25 Feb 08 06:17:45 PM UTC 25 180739410 ps
T3042 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_nak_trans.3863216590 Feb 08 06:17:54 PM UTC 25 Feb 08 06:17:56 PM UTC 25 216305240 ps
T3043 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_pkt_buffer.1065759319 Feb 08 06:16:54 PM UTC 25 Feb 08 06:17:46 PM UTC 25 18145284452 ps
T3044 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_alert_test.4064955723 Feb 08 06:17:44 PM UTC 25 Feb 08 06:17:46 PM UTC 25 56427047 ps
T3045 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_stream_len_max.4128755520 Feb 08 06:17:42 PM UTC 25 Feb 08 06:17:46 PM UTC 25 805005155 ps
T3046 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_tx_rx_disruption.3630563642 Feb 08 06:17:42 PM UTC 25 Feb 08 06:17:46 PM UTC 25 498553664 ps
T3047 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_invalid_sync.4072922542 Feb 08 06:17:06 PM UTC 25 Feb 08 06:17:48 PM UTC 25 5040622651 ps
T3048 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_link_suspend.774997122 Feb 08 06:17:31 PM UTC 25 Feb 08 06:17:48 PM UTC 25 8462889251 ps
T3049 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_spurious_pids_ignored.2867887883 Feb 08 06:16:40 PM UTC 25 Feb 08 06:17:48 PM UTC 25 2521002655 ps
T3050 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_data_toggle_clear.3522490063 Feb 08 06:17:45 PM UTC 25 Feb 08 06:17:48 PM UTC 25 141873568 ps
T3051 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_bitstuff_err.1080879462 Feb 08 06:17:45 PM UTC 25 Feb 08 06:17:48 PM UTC 25 180967319 ps
T3052 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_av_buffer.2488047330 Feb 08 06:17:45 PM UTC 25 Feb 08 06:17:48 PM UTC 25 183112699 ps
T3053 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_link_resume.3706618870 Feb 08 06:17:31 PM UTC 25 Feb 08 06:17:49 PM UTC 25 7368988548 ps
T3054 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_enable.2628056598 Feb 08 06:17:48 PM UTC 25 Feb 08 06:17:50 PM UTC 25 43923199 ps
T3055 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_disconnected.1658963543 Feb 08 06:17:48 PM UTC 25 Feb 08 06:17:50 PM UTC 25 141142887 ps
T3056 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_invalid_sync.1039083969 Feb 08 06:17:28 PM UTC 25 Feb 08 06:17:50 PM UTC 25 2525196009 ps
T3057 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_timeout_missing_host_handshake.1154035367 Feb 08 06:17:02 PM UTC 25 Feb 08 06:17:50 PM UTC 25 4810875108 ps
T3058 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_data_toggle_restore.915611871 Feb 08 06:17:45 PM UTC 25 Feb 08 06:17:51 PM UTC 25 1158324044 ps
T3059 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_aon_wake_resume.1592571474 Feb 08 06:17:02 PM UTC 25 Feb 08 06:17:51 PM UTC 25 30907385920 ps
T3060 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_disable_endpoint.1870704939 Feb 08 06:17:47 PM UTC 25 Feb 08 06:17:51 PM UTC 25 797219403 ps
T3061 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_in_stall.2412934393 Feb 08 06:17:49 PM UTC 25 Feb 08 06:17:52 PM UTC 25 147878039 ps
T3062 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_spurious_pids_ignored.124858576 Feb 08 06:17:19 PM UTC 25 Feb 08 06:17:52 PM UTC 25 3720825644 ps
T3063 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_in_iso.2177079759 Feb 08 06:17:49 PM UTC 25 Feb 08 06:17:52 PM UTC 25 180502762 ps
T3064 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_in_trans.2974953860 Feb 08 06:17:49 PM UTC 25 Feb 08 06:17:52 PM UTC 25 179470932 ps
T3065 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_endpoint_access.3602185832 Feb 08 06:17:48 PM UTC 25 Feb 08 06:17:52 PM UTC 25 843524741 ps
T389 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_endpoint_types.2632422052 Feb 08 06:17:49 PM UTC 25 Feb 08 06:17:52 PM UTC 25 284221380 ps
T3066 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_link_in_err.2171463031 Feb 08 06:17:51 PM UTC 25 Feb 08 06:17:53 PM UTC 25 208607107 ps
T3067 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_fifo_rst.2974614058 Feb 08 06:17:49 PM UTC 25 Feb 08 06:17:53 PM UTC 25 184577861 ps
T3068 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_aon_wake_reset.904016675 Feb 08 06:17:23 PM UTC 25 Feb 08 06:17:54 PM UTC 25 18778709269 ps
T3069 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_aon_wake_disconnect.776105213 Feb 08 06:17:44 PM UTC 25 Feb 08 06:17:55 PM UTC 25 3818928540 ps
T3070 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_max_length_out_transaction.165741878 Feb 08 06:17:52 PM UTC 25 Feb 08 06:17:55 PM UTC 25 198606526 ps
T3071 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_max_length_in_transaction.3295451924 Feb 08 06:17:52 PM UTC 25 Feb 08 06:17:55 PM UTC 25 253800419 ps
T3072 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_invalid_sync.1316970254 Feb 08 06:15:50 PM UTC 25 Feb 08 06:17:55 PM UTC 25 4389028981 ps
T3073 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_streaming_out.2769678019 Feb 08 06:16:42 PM UTC 25 Feb 08 06:17:56 PM UTC 25 2722779132 ps
T3074 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_min_length_in_transaction.3559918240 Feb 08 06:17:54 PM UTC 25 Feb 08 06:17:56 PM UTC 25 153950002 ps
T3075 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_out_stall.867895720 Feb 08 06:17:54 PM UTC 25 Feb 08 06:17:57 PM UTC 25 187208492 ps
T3076 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_out_iso.3043589495 Feb 08 06:17:54 PM UTC 25 Feb 08 06:17:57 PM UTC 25 187324739 ps
T3077 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_min_length_out_transaction.3490241575 Feb 08 06:17:54 PM UTC 25 Feb 08 06:17:57 PM UTC 25 226207496 ps
T3078 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_iso_retraction.166521240 Feb 08 06:16:29 PM UTC 25 Feb 08 06:17:57 PM UTC 25 6412127595 ps
T3079 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_phy_pins_sense.2666250009 Feb 08 06:17:55 PM UTC 25 Feb 08 06:17:57 PM UTC 25 41514069 ps
T3080 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_pending_in_trans.1032341912 Feb 08 06:17:55 PM UTC 25 Feb 08 06:17:58 PM UTC 25 217431033 ps
T3081 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_phy_config_usb_ref_disable.3847494141 Feb 08 06:17:55 PM UTC 25 Feb 08 06:17:58 PM UTC 25 162726608 ps
T3082 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_phy_config_pinflip.4203579997 Feb 08 06:17:55 PM UTC 25 Feb 08 06:17:58 PM UTC 25 238121948 ps
T3083 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_pkt_sent.601394665 Feb 08 06:17:57 PM UTC 25 Feb 08 06:17:59 PM UTC 25 234824087 ps
T3084 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_pkt_received.3638692466 Feb 08 06:17:57 PM UTC 25 Feb 08 06:18:00 PM UTC 25 191452322 ps
T3085 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_random_length_out_transaction.80297305 Feb 08 06:17:57 PM UTC 25 Feb 08 06:18:00 PM UTC 25 181065516 ps
T3086 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_random_length_in_transaction.3343648650 Feb 08 06:17:57 PM UTC 25 Feb 08 06:18:00 PM UTC 25 192143122 ps
T3087 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_low_speed_traffic.3610880837 Feb 08 06:17:31 PM UTC 25 Feb 08 06:18:01 PM UTC 25 3051188082 ps
T3088 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_device_timeout.3111645680 Feb 08 06:17:26 PM UTC 25 Feb 08 06:18:01 PM UTC 25 4375131912 ps
T3089 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_link_suspend.622229105 Feb 08 06:17:52 PM UTC 25 Feb 08 06:18:01 PM UTC 25 3813900539 ps
T3090 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_rx_crc_err.1674939112 Feb 08 06:17:59 PM UTC 25 Feb 08 06:18:01 PM UTC 25 177853172 ps
T3091 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_setup_stage.3262203382 Feb 08 06:17:59 PM UTC 25 Feb 08 06:18:01 PM UTC 25 200402724 ps
T3092 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_setup_trans_ignored.1889179809 Feb 08 06:17:59 PM UTC 25 Feb 08 06:18:01 PM UTC 25 197263647 ps
T3093 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_smoke.507892591 Feb 08 06:17:59 PM UTC 25 Feb 08 06:18:02 PM UTC 25 201098945 ps
T3094 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_pkt_buffer.3873082418 Feb 08 06:17:38 PM UTC 25 Feb 08 06:18:02 PM UTC 25 7389560039 ps
T3095 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_stall_priority_over_nak.2563048774 Feb 08 06:17:59 PM UTC 25 Feb 08 06:18:02 PM UTC 25 199740849 ps
T3096 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_device_address.2832462126 Feb 08 06:16:45 PM UTC 25 Feb 08 06:18:02 PM UTC 25 35873552057 ps
T3097 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_rx_full.1887144921 Feb 08 06:17:59 PM UTC 25 Feb 08 06:18:02 PM UTC 25 385184055 ps
T3098 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_stall_trans.3718542566 Feb 08 06:17:59 PM UTC 25 Feb 08 06:18:02 PM UTC 25 213381639 ps
T3099 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_low_speed_traffic.2567856433 Feb 08 06:15:52 PM UTC 25 Feb 08 06:18:02 PM UTC 25 4555303972 ps
T3100 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_timeout_missing_host_handshake.3389996143 Feb 08 06:17:47 PM UTC 25 Feb 08 06:18:02 PM UTC 25 1540341460 ps
T363 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/65.usbdev_endpoint_types.2847067904 Feb 08 06:18:09 PM UTC 25 Feb 08 06:18:12 PM UTC 25 454845423 ps
T3101 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_aon_wake_reset.2682569813 Feb 08 06:17:44 PM UTC 25 Feb 08 06:18:02 PM UTC 25 14172669115 ps
T3102 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_alert_test.2179595624 Feb 08 06:18:00 PM UTC 25 Feb 08 06:18:02 PM UTC 25 69967021 ps
T3103 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_timeout_missing_host_handshake.1643186200 Feb 08 06:17:26 PM UTC 25 Feb 08 06:18:03 PM UTC 25 4371380888 ps
T3104 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_tx_rx_disruption.4216391428 Feb 08 06:18:00 PM UTC 25 Feb 08 06:18:03 PM UTC 25 495893599 ps
T3105 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_stream_len_max.2578227900 Feb 08 06:18:00 PM UTC 25 Feb 08 06:18:04 PM UTC 25 814004984 ps
T3106 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_aon_wake_resume.2180003631 Feb 08 06:17:23 PM UTC 25 Feb 08 06:18:04 PM UTC 25 25853785720 ps
T3107 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/51.usbdev_endpoint_types.3041182653 Feb 08 06:18:02 PM UTC 25 Feb 08 06:18:04 PM UTC 25 219733889 ps
T3108 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/50.usbdev_tx_rx_disruption.3066682166 Feb 08 06:18:02 PM UTC 25 Feb 08 06:18:04 PM UTC 25 485181690 ps
T424 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/52.usbdev_endpoint_types.2908038769 Feb 08 06:18:02 PM UTC 25 Feb 08 06:18:05 PM UTC 25 463225211 ps
T3109 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/50.usbdev_endpoint_types.2707629514 Feb 08 06:18:02 PM UTC 25 Feb 08 06:18:05 PM UTC 25 232109051 ps
T236 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/51.usbdev_tx_rx_disruption.3444029244 Feb 08 06:18:02 PM UTC 25 Feb 08 06:18:05 PM UTC 25 563318179 ps
T427 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/54.usbdev_endpoint_types.2775472567 Feb 08 06:18:04 PM UTC 25 Feb 08 06:18:07 PM UTC 25 299899321 ps
T3110 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/52.usbdev_tx_rx_disruption.4271021418 Feb 08 06:18:04 PM UTC 25 Feb 08 06:18:07 PM UTC 25 437127290 ps
T3111 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/54.usbdev_tx_rx_disruption.1489783053 Feb 08 06:18:04 PM UTC 25 Feb 08 06:18:07 PM UTC 25 482017476 ps
T396 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/55.usbdev_endpoint_types.1720041581 Feb 08 06:18:04 PM UTC 25 Feb 08 06:18:07 PM UTC 25 425166156 ps
T201 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/53.usbdev_tx_rx_disruption.4108322468 Feb 08 06:18:04 PM UTC 25 Feb 08 06:18:07 PM UTC 25 513361188 ps
T3112 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/53.usbdev_endpoint_types.3360739260 Feb 08 06:18:04 PM UTC 25 Feb 08 06:18:07 PM UTC 25 527676775 ps
T3113 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/55.usbdev_tx_rx_disruption.3347417325 Feb 08 06:18:04 PM UTC 25 Feb 08 06:18:07 PM UTC 25 440564216 ps
T468 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/58.usbdev_endpoint_types.3331939405 Feb 08 06:18:04 PM UTC 25 Feb 08 06:18:07 PM UTC 25 447583657 ps
T397 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/57.usbdev_endpoint_types.1358344221 Feb 08 06:18:04 PM UTC 25 Feb 08 06:18:07 PM UTC 25 413809685 ps
T358 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/69.usbdev_endpoint_types.3621543898 Feb 08 06:18:09 PM UTC 25 Feb 08 06:18:12 PM UTC 25 528397660 ps
T398 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/56.usbdev_endpoint_types.4031975535 Feb 08 06:18:04 PM UTC 25 Feb 08 06:18:08 PM UTC 25 351651683 ps
T3114 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/56.usbdev_tx_rx_disruption.914411096 Feb 08 06:18:04 PM UTC 25 Feb 08 06:18:08 PM UTC 25 726571933 ps
T3115 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/58.usbdev_tx_rx_disruption.889951229 Feb 08 06:18:04 PM UTC 25 Feb 08 06:18:08 PM UTC 25 573879246 ps
T3116 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/57.usbdev_tx_rx_disruption.767931759 Feb 08 06:18:04 PM UTC 25 Feb 08 06:18:08 PM UTC 25 535064207 ps
T3117 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_iso_retraction.889153288 Feb 08 06:16:49 PM UTC 25 Feb 08 06:18:08 PM UTC 25 10575061924 ps
T3118 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_max_inter_pkt_delay.764893 Feb 08 06:17:10 PM UTC 25 Feb 08 06:18:08 PM UTC 25 1923907775 ps
T445 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/62.usbdev_endpoint_types.3613901908 Feb 08 06:18:06 PM UTC 25 Feb 08 06:18:08 PM UTC 25 184333768 ps
T442 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/59.usbdev_endpoint_types.3400751199 Feb 08 06:18:06 PM UTC 25 Feb 08 06:18:08 PM UTC 25 214949525 ps
T3119 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_device_address.2151676069 Feb 08 06:17:02 PM UTC 25 Feb 08 06:18:09 PM UTC 25 30811567689 ps
T425 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/61.usbdev_endpoint_types.1984864540 Feb 08 06:18:06 PM UTC 25 Feb 08 06:18:09 PM UTC 25 513140506 ps
T3120 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/59.usbdev_tx_rx_disruption.1171326384 Feb 08 06:18:06 PM UTC 25 Feb 08 06:18:09 PM UTC 25 646177737 ps
T3121 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/60.usbdev_tx_rx_disruption.28186306 Feb 08 06:18:06 PM UTC 25 Feb 08 06:18:09 PM UTC 25 478690804 ps
T367 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/60.usbdev_endpoint_types.1317879409 Feb 08 06:18:06 PM UTC 25 Feb 08 06:18:09 PM UTC 25 560274429 ps
T3122 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/61.usbdev_tx_rx_disruption.2092853696 Feb 08 06:18:06 PM UTC 25 Feb 08 06:18:09 PM UTC 25 563947475 ps
T3123 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/62.usbdev_tx_rx_disruption.4220716517 Feb 08 06:18:06 PM UTC 25 Feb 08 06:18:09 PM UTC 25 488111543 ps
T443 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/63.usbdev_endpoint_types.1690479722 Feb 08 06:18:07 PM UTC 25 Feb 08 06:18:10 PM UTC 25 262798628 ps
T3124 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_pkt_buffer.2554839066 Feb 08 06:17:16 PM UTC 25 Feb 08 06:18:10 PM UTC 25 21795631426 ps
T3125 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_low_speed_traffic.1893938095 Feb 08 06:16:12 PM UTC 25 Feb 08 06:18:10 PM UTC 25 4356418900 ps
T3126 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_iso_retraction.433932686 Feb 08 06:17:08 PM UTC 25 Feb 08 06:18:11 PM UTC 25 7834168233 ps
T196 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/65.usbdev_tx_rx_disruption.354609508 Feb 08 06:18:09 PM UTC 25 Feb 08 06:18:12 PM UTC 25 468776299 ps
T3127 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/63.usbdev_tx_rx_disruption.3245336008 Feb 08 06:18:09 PM UTC 25 Feb 08 06:18:12 PM UTC 25 433162025 ps
T3128 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/64.usbdev_tx_rx_disruption.897128683 Feb 08 06:18:09 PM UTC 25 Feb 08 06:18:12 PM UTC 25 474636942 ps
T414 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/64.usbdev_endpoint_types.2089402156 Feb 08 06:18:09 PM UTC 25 Feb 08 06:18:12 PM UTC 25 652803792 ps
T399 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/66.usbdev_endpoint_types.2456494963 Feb 08 06:18:09 PM UTC 25 Feb 08 06:18:12 PM UTC 25 350982093 ps
T3129 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/67.usbdev_tx_rx_disruption.3291912412 Feb 08 06:18:09 PM UTC 25 Feb 08 06:18:12 PM UTC 25 591771742 ps
T3130 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/68.usbdev_tx_rx_disruption.2168681994 Feb 08 06:18:09 PM UTC 25 Feb 08 06:18:12 PM UTC 25 518359027 ps
T431 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/67.usbdev_endpoint_types.427025748 Feb 08 06:18:09 PM UTC 25 Feb 08 06:18:12 PM UTC 25 321767774 ps
T385 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/68.usbdev_endpoint_types.1818795189 Feb 08 06:18:09 PM UTC 25 Feb 08 06:18:12 PM UTC 25 567151902 ps
T3131 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/66.usbdev_tx_rx_disruption.3533691984 Feb 08 06:18:09 PM UTC 25 Feb 08 06:18:12 PM UTC 25 709431527 ps
T3132 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/69.usbdev_tx_rx_disruption.4280998340 Feb 08 06:18:09 PM UTC 25 Feb 08 06:18:12 PM UTC 25 554331011 ps
T345 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/70.usbdev_endpoint_types.2014398534 Feb 08 06:18:09 PM UTC 25 Feb 08 06:18:13 PM UTC 25 558379085 ps
T3133 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_spurious_pids_ignored.3919391092 Feb 08 06:16:58 PM UTC 25 Feb 08 06:18:13 PM UTC 25 2482394787 ps
T3134 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_spurious_pids_ignored.4065324985 Feb 08 06:17:41 PM UTC 25 Feb 08 06:18:13 PM UTC 25 3872241357 ps
T3135 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/72.usbdev_endpoint_types.2845109177 Feb 08 06:18:12 PM UTC 25 Feb 08 06:18:14 PM UTC 25 258162642 ps
T3136 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/71.usbdev_tx_rx_disruption.1221425293 Feb 08 06:18:12 PM UTC 25 Feb 08 06:18:15 PM UTC 25 470601990 ps
T459 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/74.usbdev_endpoint_types.3609905549 Feb 08 06:18:12 PM UTC 25 Feb 08 06:18:15 PM UTC 25 409517883 ps
T489 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/73.usbdev_endpoint_types.3931011645 Feb 08 06:18:12 PM UTC 25 Feb 08 06:18:15 PM UTC 25 257234252 ps
T426 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/71.usbdev_endpoint_types.957861759 Feb 08 06:18:12 PM UTC 25 Feb 08 06:18:15 PM UTC 25 523358657 ps
T3137 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/72.usbdev_tx_rx_disruption.258735181 Feb 08 06:18:12 PM UTC 25 Feb 08 06:18:15 PM UTC 25 492957684 ps
T369 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/75.usbdev_endpoint_types.2619384863 Feb 08 06:18:12 PM UTC 25 Feb 08 06:18:15 PM UTC 25 424369133 ps
T188 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/75.usbdev_tx_rx_disruption.3529517714 Feb 08 06:18:12 PM UTC 25 Feb 08 06:18:15 PM UTC 25 436297563 ps
T3138 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/74.usbdev_tx_rx_disruption.1893070933 Feb 08 06:18:12 PM UTC 25 Feb 08 06:18:15 PM UTC 25 447333084 ps
T3139 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/70.usbdev_tx_rx_disruption.972855774 Feb 08 06:18:12 PM UTC 25 Feb 08 06:18:15 PM UTC 25 658306201 ps
T3140 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/73.usbdev_tx_rx_disruption.1581420351 Feb 08 06:18:12 PM UTC 25 Feb 08 06:18:15 PM UTC 25 636789182 ps
T429 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/76.usbdev_endpoint_types.3148471859 Feb 08 06:18:14 PM UTC 25 Feb 08 06:18:16 PM UTC 25 190522948 ps
T3141 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/79.usbdev_endpoint_types.1112653191 Feb 08 06:18:14 PM UTC 25 Feb 08 06:18:16 PM UTC 25 195207626 ps
T3142 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_min_inter_pkt_delay.1186846915 Feb 08 06:16:54 PM UTC 25 Feb 08 06:18:16 PM UTC 25 2845740732 ps
T349 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/78.usbdev_endpoint_types.3275757563 Feb 08 06:18:14 PM UTC 25 Feb 08 06:18:17 PM UTC 25 363678373 ps
T434 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/82.usbdev_endpoint_types.1718578091 Feb 08 06:18:14 PM UTC 25 Feb 08 06:18:17 PM UTC 25 407684928 ps