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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.44 98.11 95.91 97.44 87.30 98.22 98.17 92.94


Total test records in report: 3732
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T1716 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_endpoint_access.3031879932 Feb 08 06:09:54 PM UTC 25 Feb 08 06:09:58 PM UTC 25 674009994 ps
T1717 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_streaming_out.3802877754 Feb 08 06:08:51 PM UTC 25 Feb 08 06:09:59 PM UTC 25 2054042331 ps
T1718 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_aon_wake_reset.700837162 Feb 08 06:09:18 PM UTC 25 Feb 08 06:09:59 PM UTC 25 19873914488 ps
T1719 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_fifo_rst.4201659421 Feb 08 06:09:55 PM UTC 25 Feb 08 06:09:59 PM UTC 25 335778431 ps
T1720 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_aon_wake_disconnect.3272937886 Feb 08 06:09:48 PM UTC 25 Feb 08 06:09:59 PM UTC 25 5844347001 ps
T1721 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_link_in_err.2590159524 Feb 08 06:09:57 PM UTC 25 Feb 08 06:10:00 PM UTC 25 201348243 ps
T1722 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_in_trans.430912320 Feb 08 06:09:57 PM UTC 25 Feb 08 06:10:00 PM UTC 25 200457976 ps
T1723 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_max_non_iso_usb_traffic.1725138260 Feb 08 06:09:33 PM UTC 25 Feb 08 06:10:00 PM UTC 25 2793633875 ps
T1724 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_max_length_out_transaction.3384891175 Feb 08 06:09:59 PM UTC 25 Feb 08 06:10:01 PM UTC 25 195087122 ps
T1725 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_max_length_in_transaction.967832610 Feb 08 06:09:59 PM UTC 25 Feb 08 06:10:01 PM UTC 25 237939718 ps
T1726 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_min_length_out_transaction.2488643186 Feb 08 06:10:00 PM UTC 25 Feb 08 06:10:03 PM UTC 25 148097695 ps
T1727 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_min_length_in_transaction.3399111048 Feb 08 06:10:00 PM UTC 25 Feb 08 06:10:03 PM UTC 25 164952469 ps
T1728 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_out_stall.2193891889 Feb 08 06:10:00 PM UTC 25 Feb 08 06:10:03 PM UTC 25 162943684 ps
T1729 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_out_iso.2083944792 Feb 08 06:10:00 PM UTC 25 Feb 08 06:10:03 PM UTC 25 173953633 ps
T1730 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_out_trans_nak.1722427720 Feb 08 06:10:00 PM UTC 25 Feb 08 06:10:03 PM UTC 25 169980871 ps
T1731 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_nak_trans.3368445331 Feb 08 06:10:00 PM UTC 25 Feb 08 06:10:03 PM UTC 25 218550238 ps
T1732 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_spurious_pids_ignored.1938423835 Feb 08 06:09:45 PM UTC 25 Feb 08 06:10:04 PM UTC 25 2073530363 ps
T1733 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_phy_config_pinflip.1806842162 Feb 08 06:10:02 PM UTC 25 Feb 08 06:10:04 PM UTC 25 179363387 ps
T1734 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_pending_in_trans.2027240591 Feb 08 06:10:02 PM UTC 25 Feb 08 06:10:04 PM UTC 25 237934067 ps
T1735 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_phy_config_usb_ref_disable.598867703 Feb 08 06:10:03 PM UTC 25 Feb 08 06:10:05 PM UTC 25 167409661 ps
T1736 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_timeout_missing_host_handshake.2122773035 Feb 08 06:09:22 PM UTC 25 Feb 08 06:10:05 PM UTC 25 5555912140 ps
T1737 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_spurious_pids_ignored.3350691592 Feb 08 06:08:27 PM UTC 25 Feb 08 06:10:06 PM UTC 25 2725698895 ps
T1738 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_link_resume.3799020610 Feb 08 06:09:01 PM UTC 25 Feb 08 06:10:06 PM UTC 25 32342294258 ps
T1739 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_phy_pins_sense.2585592920 Feb 08 06:10:04 PM UTC 25 Feb 08 06:10:06 PM UTC 25 31802199 ps
T1740 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_random_length_in_transaction.1047545563 Feb 08 06:10:04 PM UTC 25 Feb 08 06:10:07 PM UTC 25 206918777 ps
T1741 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_pkt_received.2474240628 Feb 08 06:10:04 PM UTC 25 Feb 08 06:10:07 PM UTC 25 168180208 ps
T1742 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_random_length_out_transaction.511151384 Feb 08 06:10:04 PM UTC 25 Feb 08 06:10:07 PM UTC 25 258867440 ps
T1743 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_pkt_sent.1658482181 Feb 08 06:10:04 PM UTC 25 Feb 08 06:10:07 PM UTC 25 216115872 ps
T1744 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_invalid_sync.3168780642 Feb 08 06:09:27 PM UTC 25 Feb 08 06:10:08 PM UTC 25 3461237317 ps
T1745 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_invalid_sync.890413654 Feb 08 06:08:12 PM UTC 25 Feb 08 06:10:08 PM UTC 25 4105650657 ps
T1746 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_setup_stage.3017648645 Feb 08 06:10:06 PM UTC 25 Feb 08 06:10:08 PM UTC 25 158072940 ps
T1747 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_rx_crc_err.539995660 Feb 08 06:10:06 PM UTC 25 Feb 08 06:10:08 PM UTC 25 167262792 ps
T1748 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_setup_trans_ignored.2505967623 Feb 08 06:10:06 PM UTC 25 Feb 08 06:10:08 PM UTC 25 160207979 ps
T1749 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_pkt_buffer.1792867207 Feb 08 06:09:11 PM UTC 25 Feb 08 06:10:09 PM UTC 25 18967199319 ps
T1750 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_smoke.2127506256 Feb 08 06:10:06 PM UTC 25 Feb 08 06:10:09 PM UTC 25 208960489 ps
T1751 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_rx_full.1012757277 Feb 08 06:10:06 PM UTC 25 Feb 08 06:10:09 PM UTC 25 442744863 ps
T1752 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_stall_trans.3608041082 Feb 08 06:10:07 PM UTC 25 Feb 08 06:10:10 PM UTC 25 179021418 ps
T1753 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_stall_priority_over_nak.2746130370 Feb 08 06:10:07 PM UTC 25 Feb 08 06:10:10 PM UTC 25 173544749 ps
T1754 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_out_iso.3878934027 Feb 08 06:10:23 PM UTC 25 Feb 08 06:10:25 PM UTC 25 163835625 ps
T1755 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_alert_test.157126565 Feb 08 06:10:09 PM UTC 25 Feb 08 06:10:11 PM UTC 25 34095711 ps
T1756 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_streaming_out.2227657035 Feb 08 06:09:15 PM UTC 25 Feb 08 06:10:26 PM UTC 25 2460142784 ps
T1757 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_timeout_missing_host_handshake.808829468 Feb 08 06:09:53 PM UTC 25 Feb 08 06:10:12 PM UTC 25 851287544 ps
T1758 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_invalid_sync.4237476155 Feb 08 06:08:56 PM UTC 25 Feb 08 06:10:13 PM UTC 25 2633753016 ps
T1759 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_tx_rx_disruption.2179267593 Feb 08 06:10:09 PM UTC 25 Feb 08 06:10:13 PM UTC 25 578660326 ps
T1760 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_bitstuff_err.2546151698 Feb 08 06:10:10 PM UTC 25 Feb 08 06:10:13 PM UTC 25 148753060 ps
T1761 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_av_buffer.3016372051 Feb 08 06:10:10 PM UTC 25 Feb 08 06:10:13 PM UTC 25 172520596 ps
T1762 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_data_toggle_clear.3940605410 Feb 08 06:10:10 PM UTC 25 Feb 08 06:10:13 PM UTC 25 189641238 ps
T1763 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_link_suspend.3371164827 Feb 08 06:09:57 PM UTC 25 Feb 08 06:10:13 PM UTC 25 10072063041 ps
T1764 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_stream_len_max.2009741850 Feb 08 06:10:09 PM UTC 25 Feb 08 06:10:15 PM UTC 25 1012450022 ps
T1765 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_disconnected.1569490064 Feb 08 06:10:13 PM UTC 25 Feb 08 06:10:15 PM UTC 25 150816369 ps
T1766 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_data_toggle_restore.1441320743 Feb 08 06:10:10 PM UTC 25 Feb 08 06:10:16 PM UTC 25 1304918763 ps
T1767 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_disable_endpoint.4288053238 Feb 08 06:10:12 PM UTC 25 Feb 08 06:10:16 PM UTC 25 859167123 ps
T1768 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_enable.1041578500 Feb 08 06:10:14 PM UTC 25 Feb 08 06:10:17 PM UTC 25 42855270 ps
T1769 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_in_iso.1945228193 Feb 08 06:10:14 PM UTC 25 Feb 08 06:10:17 PM UTC 25 184046869 ps
T444 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_endpoint_types.3883149342 Feb 08 06:10:14 PM UTC 25 Feb 08 06:10:18 PM UTC 25 375421507 ps
T1770 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_in_stall.893084882 Feb 08 06:10:16 PM UTC 25 Feb 08 06:10:18 PM UTC 25 160903072 ps
T1771 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_in_trans.3535885621 Feb 08 06:10:16 PM UTC 25 Feb 08 06:10:18 PM UTC 25 179057265 ps
T1772 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_fifo_rst.1592665980 Feb 08 06:10:14 PM UTC 25 Feb 08 06:10:18 PM UTC 25 295921490 ps
T1773 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_min_inter_pkt_delay.1221336884 Feb 08 06:10:00 PM UTC 25 Feb 08 06:10:19 PM UTC 25 2019903639 ps
T1774 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_link_in_err.1837795982 Feb 08 06:10:17 PM UTC 25 Feb 08 06:10:20 PM UTC 25 227602895 ps
T1775 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_endpoint_access.3384112638 Feb 08 06:10:14 PM UTC 25 Feb 08 06:10:20 PM UTC 25 783609695 ps
T1776 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_min_inter_pkt_delay.3569124791 Feb 08 06:09:04 PM UTC 25 Feb 08 06:10:20 PM UTC 25 2842746359 ps
T1777 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_pkt_buffer.2067475036 Feb 08 06:09:41 PM UTC 25 Feb 08 06:10:22 PM UTC 25 14956210675 ps
T1778 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_max_length_in_transaction.4195539149 Feb 08 06:10:20 PM UTC 25 Feb 08 06:10:22 PM UTC 25 237287646 ps
T1779 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_max_length_out_transaction.688546122 Feb 08 06:10:20 PM UTC 25 Feb 08 06:10:22 PM UTC 25 191139554 ps
T1780 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_device_timeout.1202623478 Feb 08 06:09:53 PM UTC 25 Feb 08 06:10:23 PM UTC 25 4287789468 ps
T1781 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_invalid_sync.486299458 Feb 08 06:09:55 PM UTC 25 Feb 08 06:10:23 PM UTC 25 3298057507 ps
T1782 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_min_length_out_transaction.3256783449 Feb 08 06:10:21 PM UTC 25 Feb 08 06:10:23 PM UTC 25 144269964 ps
T1783 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_max_non_iso_usb_traffic.3597575734 Feb 08 06:09:59 PM UTC 25 Feb 08 06:10:23 PM UTC 25 2431601328 ps
T1784 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_min_length_in_transaction.454679185 Feb 08 06:10:21 PM UTC 25 Feb 08 06:10:24 PM UTC 25 168048061 ps
T1785 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_nak_trans.3509031875 Feb 08 06:10:21 PM UTC 25 Feb 08 06:10:24 PM UTC 25 241841631 ps
T1786 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_aon_wake_resume.4113485290 Feb 08 06:09:18 PM UTC 25 Feb 08 06:10:25 PM UTC 25 31154406106 ps
T1787 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_out_stall.3078079844 Feb 08 06:10:23 PM UTC 25 Feb 08 06:10:25 PM UTC 25 211402879 ps
T1788 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_out_trans_nak.271992946 Feb 08 06:10:23 PM UTC 25 Feb 08 06:10:25 PM UTC 25 232465927 ps
T1789 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_phy_config_usb_ref_disable.2759734272 Feb 08 06:10:24 PM UTC 25 Feb 08 06:10:27 PM UTC 25 144660759 ps
T1790 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_phy_pins_sense.1121540100 Feb 08 06:10:24 PM UTC 25 Feb 08 06:10:27 PM UTC 25 41478915 ps
T1791 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_pending_in_trans.2322711095 Feb 08 06:10:24 PM UTC 25 Feb 08 06:10:27 PM UTC 25 153159498 ps
T1792 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_pkt_received.1122521178 Feb 08 06:10:24 PM UTC 25 Feb 08 06:10:27 PM UTC 25 182849204 ps
T1793 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_phy_config_pinflip.856876695 Feb 08 06:10:24 PM UTC 25 Feb 08 06:10:27 PM UTC 25 211838651 ps
T1794 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_streaming_out.3577099502 Feb 08 06:10:07 PM UTC 25 Feb 08 06:10:28 PM UTC 25 2376818847 ps
T1795 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_aon_wake_disconnect.3035816771 Feb 08 06:10:09 PM UTC 25 Feb 08 06:10:28 PM UTC 25 10196735208 ps
T1796 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_random_length_out_transaction.2216715028 Feb 08 06:10:26 PM UTC 25 Feb 08 06:10:28 PM UTC 25 189670250 ps
T1797 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_pkt_sent.3985549317 Feb 08 06:10:26 PM UTC 25 Feb 08 06:10:28 PM UTC 25 164174751 ps
T1798 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_random_length_in_transaction.3514260737 Feb 08 06:10:26 PM UTC 25 Feb 08 06:10:28 PM UTC 25 236754006 ps
T1799 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_rx_crc_err.568913209 Feb 08 06:10:27 PM UTC 25 Feb 08 06:10:30 PM UTC 25 143265480 ps
T1800 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_rx_full.2703046013 Feb 08 06:10:27 PM UTC 25 Feb 08 06:10:30 PM UTC 25 327760669 ps
T1801 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_setup_trans_ignored.1822559744 Feb 08 06:10:27 PM UTC 25 Feb 08 06:10:30 PM UTC 25 168166429 ps
T1802 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_setup_stage.3143057004 Feb 08 06:10:27 PM UTC 25 Feb 08 06:10:30 PM UTC 25 238817427 ps
T1803 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_iso_retraction.1069076299 Feb 08 06:09:57 PM UTC 25 Feb 08 06:10:30 PM UTC 25 4690002141 ps
T1804 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_iso_retraction.149528422 Feb 08 06:09:28 PM UTC 25 Feb 08 06:10:31 PM UTC 25 7495971325 ps
T1805 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_stall_priority_over_nak.2413098567 Feb 08 06:10:29 PM UTC 25 Feb 08 06:10:31 PM UTC 25 180490073 ps
T1806 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_stall_trans.1174695819 Feb 08 06:10:29 PM UTC 25 Feb 08 06:10:32 PM UTC 25 173133044 ps
T1807 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_smoke.1228810489 Feb 08 06:10:29 PM UTC 25 Feb 08 06:10:32 PM UTC 25 232067059 ps
T1808 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_device_address.4107933542 Feb 08 06:09:21 PM UTC 25 Feb 08 06:10:54 PM UTC 25 50966009684 ps
T1809 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_aon_wake_reset.2101974789 Feb 08 06:09:48 PM UTC 25 Feb 08 06:10:32 PM UTC 25 20445681247 ps
T1810 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_tx_rx_disruption.2046974062 Feb 08 06:10:30 PM UTC 25 Feb 08 06:10:33 PM UTC 25 536547934 ps
T1811 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_max_inter_pkt_delay.3633359079 Feb 08 06:10:19 PM UTC 25 Feb 08 06:10:33 PM UTC 25 1632247226 ps
T1812 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_alert_test.4078147081 Feb 08 06:10:31 PM UTC 25 Feb 08 06:10:34 PM UTC 25 35046691 ps
T1813 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_bitstuff_err.2171597516 Feb 08 06:10:32 PM UTC 25 Feb 08 06:10:34 PM UTC 25 151497564 ps
T1814 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_av_buffer.2367838258 Feb 08 06:10:31 PM UTC 25 Feb 08 06:10:34 PM UTC 25 170021959 ps
T1815 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_link_resume.3046560117 Feb 08 06:09:30 PM UTC 25 Feb 08 06:10:35 PM UTC 25 30645429240 ps
T1816 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_data_toggle_clear.3752937445 Feb 08 06:10:33 PM UTC 25 Feb 08 06:10:36 PM UTC 25 233326987 ps
T1817 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_max_non_iso_usb_traffic.2162080692 Feb 08 06:09:04 PM UTC 25 Feb 08 06:10:36 PM UTC 25 3234268537 ps
T1818 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_data_toggle_restore.119090706 Feb 08 06:10:33 PM UTC 25 Feb 08 06:10:36 PM UTC 25 343823213 ps
T1819 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_stream_len_max.613657833 Feb 08 06:10:29 PM UTC 25 Feb 08 06:10:36 PM UTC 25 1238100035 ps
T1820 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_disconnected.2247804112 Feb 08 06:10:34 PM UTC 25 Feb 08 06:10:36 PM UTC 25 156735996 ps
T1821 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_enable.3552555219 Feb 08 06:10:34 PM UTC 25 Feb 08 06:10:36 PM UTC 25 43486240 ps
T1822 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_disable_endpoint.4037230301 Feb 08 06:10:34 PM UTC 25 Feb 08 06:10:37 PM UTC 25 533668533 ps
T1823 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_invalid_sync.3343704971 Feb 08 06:08:37 PM UTC 25 Feb 08 06:10:38 PM UTC 25 4212766814 ps
T486 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_endpoint_types.341891593 Feb 08 06:10:35 PM UTC 25 Feb 08 06:10:39 PM UTC 25 273564784 ps
T1824 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_endpoint_access.595675455 Feb 08 06:10:35 PM UTC 25 Feb 08 06:10:39 PM UTC 25 968892735 ps
T1825 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_in_trans.500484554 Feb 08 06:10:37 PM UTC 25 Feb 08 06:10:39 PM UTC 25 184740905 ps
T1826 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_in_stall.4268230605 Feb 08 06:10:37 PM UTC 25 Feb 08 06:10:40 PM UTC 25 175387527 ps
T1827 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_link_in_err.1860156261 Feb 08 06:10:37 PM UTC 25 Feb 08 06:10:40 PM UTC 25 241563461 ps
T1828 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_in_iso.3447506438 Feb 08 06:10:37 PM UTC 25 Feb 08 06:10:40 PM UTC 25 229742851 ps
T1829 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_aon_wake_resume.1095289250 Feb 08 06:09:50 PM UTC 25 Feb 08 06:10:41 PM UTC 25 30371440842 ps
T1830 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_fifo_rst.1154807709 Feb 08 06:10:37 PM UTC 25 Feb 08 06:10:41 PM UTC 25 287385608 ps
T1831 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_aon_wake_reset.1440107679 Feb 08 06:10:09 PM UTC 25 Feb 08 06:10:42 PM UTC 25 19954016600 ps
T1832 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_min_length_in_transaction.418198559 Feb 08 06:10:41 PM UTC 25 Feb 08 06:10:44 PM UTC 25 158135564 ps
T1833 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_link_suspend.1805309569 Feb 08 06:10:18 PM UTC 25 Feb 08 06:10:44 PM UTC 25 11374408706 ps
T1834 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_max_length_in_transaction.997897071 Feb 08 06:10:41 PM UTC 25 Feb 08 06:10:44 PM UTC 25 236977093 ps
T1835 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_aon_wake_disconnect.1761063640 Feb 08 06:10:31 PM UTC 25 Feb 08 06:10:44 PM UTC 25 5708358786 ps
T1836 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_max_length_out_transaction.3967504216 Feb 08 06:10:41 PM UTC 25 Feb 08 06:10:44 PM UTC 25 199192324 ps
T1837 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_spurious_pids_ignored.4244738331 Feb 08 06:10:07 PM UTC 25 Feb 08 06:10:45 PM UTC 25 3493541896 ps
T1838 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_min_length_out_transaction.3722378451 Feb 08 06:10:43 PM UTC 25 Feb 08 06:10:45 PM UTC 25 143007561 ps
T1839 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_nak_trans.3029001241 Feb 08 06:10:43 PM UTC 25 Feb 08 06:10:45 PM UTC 25 216224903 ps
T1840 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_out_iso.2475307068 Feb 08 06:10:43 PM UTC 25 Feb 08 06:10:45 PM UTC 25 166064289 ps
T1841 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_out_stall.2117791706 Feb 08 06:10:44 PM UTC 25 Feb 08 06:10:46 PM UTC 25 170488753 ps
T1842 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_timeout_missing_host_handshake.2995815724 Feb 08 06:10:12 PM UTC 25 Feb 08 06:10:47 PM UTC 25 1488072288 ps
T1843 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_phy_pins_sense.3239535842 Feb 08 06:10:45 PM UTC 25 Feb 08 06:10:48 PM UTC 25 48895201 ps
T1844 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_phy_config_pinflip.1342484006 Feb 08 06:10:45 PM UTC 25 Feb 08 06:10:48 PM UTC 25 226023691 ps
T1845 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_phy_config_usb_ref_disable.2623713053 Feb 08 06:10:45 PM UTC 25 Feb 08 06:10:48 PM UTC 25 140163964 ps
T1846 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_pending_in_trans.3147141912 Feb 08 06:10:45 PM UTC 25 Feb 08 06:10:48 PM UTC 25 187550256 ps
T1847 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_out_trans_nak.4274888737 Feb 08 06:10:45 PM UTC 25 Feb 08 06:10:48 PM UTC 25 186035907 ps
T1848 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_streaming_out.2225109343 Feb 08 06:10:29 PM UTC 25 Feb 08 06:10:48 PM UTC 25 1875539843 ps
T1849 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_device_timeout.2699856471 Feb 08 06:10:33 PM UTC 25 Feb 08 06:10:49 PM UTC 25 1518564461 ps
T1850 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_timeout_missing_host_handshake.2752954489 Feb 08 06:10:33 PM UTC 25 Feb 08 06:10:49 PM UTC 25 2229311143 ps
T1851 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_random_length_out_transaction.605174399 Feb 08 06:10:47 PM UTC 25 Feb 08 06:10:50 PM UTC 25 170656018 ps
T1852 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_pkt_received.1112374852 Feb 08 06:10:47 PM UTC 25 Feb 08 06:10:50 PM UTC 25 166649773 ps
T1853 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_pkt_sent.4022375094 Feb 08 06:10:47 PM UTC 25 Feb 08 06:10:50 PM UTC 25 236005455 ps
T1854 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_min_inter_pkt_delay.1488621914 Feb 08 06:09:36 PM UTC 25 Feb 08 06:10:50 PM UTC 25 2109752456 ps
T1855 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_random_length_in_transaction.3768203816 Feb 08 06:10:47 PM UTC 25 Feb 08 06:10:50 PM UTC 25 298379976 ps
T1856 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_rx_full.3656365542 Feb 08 06:10:48 PM UTC 25 Feb 08 06:10:51 PM UTC 25 277537265 ps
T1857 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_rx_crc_err.3086389409 Feb 08 06:10:48 PM UTC 25 Feb 08 06:10:51 PM UTC 25 179726406 ps
T1858 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_setup_trans_ignored.2990599110 Feb 08 06:10:50 PM UTC 25 Feb 08 06:10:52 PM UTC 25 151412980 ps
T1859 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_streaming_out.3230570711 Feb 08 06:09:47 PM UTC 25 Feb 08 06:10:52 PM UTC 25 2266783255 ps
T1860 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_stall_priority_over_nak.3307965400 Feb 08 06:10:50 PM UTC 25 Feb 08 06:10:52 PM UTC 25 188946460 ps
T1861 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_setup_stage.4294963144 Feb 08 06:10:50 PM UTC 25 Feb 08 06:10:52 PM UTC 25 193465358 ps
T1862 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_smoke.1732622804 Feb 08 06:10:50 PM UTC 25 Feb 08 06:10:52 PM UTC 25 232140729 ps
T1863 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_link_suspend.2576068375 Feb 08 06:10:40 PM UTC 25 Feb 08 06:10:53 PM UTC 25 5991844909 ps
T1864 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_stream_len_max.186275060 Feb 08 06:10:52 PM UTC 25 Feb 08 06:10:55 PM UTC 25 848885502 ps
T1865 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_alert_test.2753948228 Feb 08 06:10:52 PM UTC 25 Feb 08 06:10:54 PM UTC 25 38477858 ps
T1866 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_data_toggle_clear.1202514767 Feb 08 06:10:53 PM UTC 25 Feb 08 06:10:56 PM UTC 25 274665655 ps
T1867 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_invalid_sync.2548327322 Feb 08 06:10:57 PM UTC 25 Feb 08 06:11:23 PM UTC 25 3163533563 ps
T1868 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_aon_wake_resume.2225171237 Feb 08 06:10:09 PM UTC 25 Feb 08 06:10:57 PM UTC 25 30717940452 ps
T1869 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_disconnected.1274785931 Feb 08 06:10:55 PM UTC 25 Feb 08 06:10:57 PM UTC 25 152516909 ps
T466 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_endpoint_types.3438014613 Feb 08 06:10:55 PM UTC 25 Feb 08 06:10:58 PM UTC 25 145017666 ps
T1870 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_enable.124692750 Feb 08 06:10:55 PM UTC 25 Feb 08 06:10:58 PM UTC 25 83196588 ps
T1871 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_data_toggle_restore.2185663617 Feb 08 06:10:53 PM UTC 25 Feb 08 06:10:58 PM UTC 25 578434094 ps
T1872 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_max_inter_pkt_delay.495831555 Feb 08 06:09:58 PM UTC 25 Feb 08 06:10:58 PM UTC 25 1975414612 ps
T1873 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_in_trans.3063144158 Feb 08 06:10:57 PM UTC 25 Feb 08 06:10:59 PM UTC 25 208084104 ps
T1874 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_in_stall.3756407438 Feb 08 06:10:57 PM UTC 25 Feb 08 06:10:59 PM UTC 25 140931749 ps
T1875 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_disable_endpoint.2194413407 Feb 08 06:10:55 PM UTC 25 Feb 08 06:11:00 PM UTC 25 771291613 ps
T1876 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_link_resume.3403915797 Feb 08 06:09:57 PM UTC 25 Feb 08 06:11:00 PM UTC 25 33317182240 ps
T1877 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_in_iso.4157114600 Feb 08 06:10:57 PM UTC 25 Feb 08 06:11:00 PM UTC 25 238424561 ps
T1878 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_link_in_err.4060551656 Feb 08 06:10:58 PM UTC 25 Feb 08 06:11:00 PM UTC 25 166530114 ps
T1879 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_fifo_rst.1955623076 Feb 08 06:10:57 PM UTC 25 Feb 08 06:11:01 PM UTC 25 182849593 ps
T1880 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_aon_wake_reset.1961126402 Feb 08 06:10:31 PM UTC 25 Feb 08 06:11:01 PM UTC 25 20545606871 ps
T1881 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_endpoint_access.479412262 Feb 08 06:10:55 PM UTC 25 Feb 08 06:11:01 PM UTC 25 1159991634 ps
T1882 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_aon_wake_disconnect.749682510 Feb 08 06:10:52 PM UTC 25 Feb 08 06:11:02 PM UTC 25 4622168381 ps
T1883 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_device_timeout.2822061644 Feb 08 06:10:53 PM UTC 25 Feb 08 06:11:03 PM UTC 25 427595288 ps
T1884 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_min_length_in_transaction.2573267725 Feb 08 06:11:01 PM UTC 25 Feb 08 06:11:03 PM UTC 25 174216527 ps
T1885 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_min_length_out_transaction.1363568811 Feb 08 06:11:01 PM UTC 25 Feb 08 06:11:03 PM UTC 25 163046247 ps
T1886 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_max_length_out_transaction.709747124 Feb 08 06:11:01 PM UTC 25 Feb 08 06:11:03 PM UTC 25 252163763 ps
T1887 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_max_length_in_transaction.773862343 Feb 08 06:11:01 PM UTC 25 Feb 08 06:11:04 PM UTC 25 257746463 ps
T135 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_nak_trans.3175920877 Feb 08 06:11:01 PM UTC 25 Feb 08 06:11:04 PM UTC 25 228172678 ps
T1888 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_out_iso.2448049160 Feb 08 06:11:02 PM UTC 25 Feb 08 06:11:04 PM UTC 25 192421897 ps
T1889 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_out_trans_nak.1713392448 Feb 08 06:11:02 PM UTC 25 Feb 08 06:11:05 PM UTC 25 183187757 ps
T1890 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_iso_retraction.1999473521 Feb 08 06:10:17 PM UTC 25 Feb 08 06:11:05 PM UTC 25 3845516696 ps
T1891 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_out_stall.3133527034 Feb 08 06:11:02 PM UTC 25 Feb 08 06:11:05 PM UTC 25 155838260 ps
T1892 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_pending_in_trans.2123954184 Feb 08 06:11:04 PM UTC 25 Feb 08 06:11:06 PM UTC 25 154979340 ps
T1893 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_phy_config_usb_ref_disable.3792764376 Feb 08 06:11:04 PM UTC 25 Feb 08 06:11:06 PM UTC 25 156585245 ps
T1894 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_invalid_sync.4219122940 Feb 08 06:10:37 PM UTC 25 Feb 08 06:11:07 PM UTC 25 3163477086 ps
T1895 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_phy_config_pinflip.1628268816 Feb 08 06:11:04 PM UTC 25 Feb 08 06:11:07 PM UTC 25 307904558 ps
T1896 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_phy_pins_sense.137335827 Feb 08 06:11:05 PM UTC 25 Feb 08 06:11:07 PM UTC 25 57265671 ps
T1897 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_random_length_out_transaction.4071622421 Feb 08 06:11:05 PM UTC 25 Feb 08 06:11:07 PM UTC 25 179629212 ps
T1898 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_random_length_in_transaction.434935382 Feb 08 06:11:05 PM UTC 25 Feb 08 06:11:08 PM UTC 25 218411949 ps
T1899 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_pkt_sent.3101008738 Feb 08 06:11:05 PM UTC 25 Feb 08 06:11:08 PM UTC 25 168596034 ps
T1900 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_pkt_received.3825229107 Feb 08 06:11:05 PM UTC 25 Feb 08 06:11:08 PM UTC 25 167404377 ps
T1901 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_min_inter_pkt_delay.3702133349 Feb 08 06:10:41 PM UTC 25 Feb 08 06:11:09 PM UTC 25 3068859946 ps
T1902 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_setup_stage.1495711875 Feb 08 06:11:07 PM UTC 25 Feb 08 06:11:09 PM UTC 25 202574107 ps
T1903 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_rx_crc_err.3863903743 Feb 08 06:11:07 PM UTC 25 Feb 08 06:11:09 PM UTC 25 174463283 ps
T301 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_rx_full.824470732 Feb 08 06:11:07 PM UTC 25 Feb 08 06:11:09 PM UTC 25 277793948 ps
T1904 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_setup_trans_ignored.2710415469 Feb 08 06:11:07 PM UTC 25 Feb 08 06:11:09 PM UTC 25 188435022 ps
T1905 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_smoke.204470798 Feb 08 06:11:08 PM UTC 25 Feb 08 06:11:11 PM UTC 25 182548093 ps
T1906 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_stall_trans.2811233337 Feb 08 06:11:08 PM UTC 25 Feb 08 06:11:11 PM UTC 25 183623517 ps
T1907 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_stall_priority_over_nak.1766962139 Feb 08 06:11:08 PM UTC 25 Feb 08 06:11:11 PM UTC 25 210770484 ps
T1908 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_aon_wake_reset.3280255364 Feb 08 06:11:28 PM UTC 25 Feb 08 06:11:50 PM UTC 25 13395150525 ps
T1909 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_alert_test.4182205576 Feb 08 06:11:10 PM UTC 25 Feb 08 06:11:12 PM UTC 25 50244403 ps
T1910 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_link_resume.954871788 Feb 08 06:10:18 PM UTC 25 Feb 08 06:11:12 PM UTC 25 27016346898 ps
T1911 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_pkt_buffer.3212270440 Feb 08 06:10:04 PM UTC 25 Feb 08 06:11:12 PM UTC 25 22681328964 ps
T1912 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_low_speed_traffic.2928898794 Feb 08 06:10:40 PM UTC 25 Feb 08 06:11:13 PM UTC 25 3512709303 ps
T1913 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_low_speed_traffic.1393695098 Feb 08 06:08:41 PM UTC 25 Feb 08 06:11:13 PM UTC 25 4781052268 ps
T1914 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_tx_rx_disruption.2603180576 Feb 08 06:11:10 PM UTC 25 Feb 08 06:11:13 PM UTC 25 509025027 ps
T1915 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_av_buffer.2505227784 Feb 08 06:11:11 PM UTC 25 Feb 08 06:11:14 PM UTC 25 182925844 ps
T1916 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_stream_len_max.2409764365 Feb 08 06:11:10 PM UTC 25 Feb 08 06:11:14 PM UTC 25 1219567531 ps
T1917 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_bitstuff_err.1577557301 Feb 08 06:11:12 PM UTC 25 Feb 08 06:11:14 PM UTC 25 147920502 ps
T1918 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_device_address.2092870249 Feb 08 06:09:51 PM UTC 25 Feb 08 06:11:15 PM UTC 25 42060449814 ps
T1919 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_spurious_pids_ignored.1611782463 Feb 08 06:10:50 PM UTC 25 Feb 08 06:11:15 PM UTC 25 2245557151 ps
T1920 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_link_suspend.4212838273 Feb 08 06:10:58 PM UTC 25 Feb 08 06:11:15 PM UTC 25 5165972057 ps
T1921 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_data_toggle_clear.1262927403 Feb 08 06:11:12 PM UTC 25 Feb 08 06:11:15 PM UTC 25 229466900 ps
T1922 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_data_toggle_restore.1199620369 Feb 08 06:11:12 PM UTC 25 Feb 08 06:11:15 PM UTC 25 291598037 ps
T1923 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_link_resume.3910571328 Feb 08 06:10:38 PM UTC 25 Feb 08 06:11:16 PM UTC 25 23554544530 ps
T1924 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_pkt_buffer.4285374223 Feb 08 06:10:24 PM UTC 25 Feb 08 06:11:17 PM UTC 25 19198710420 ps
T1925 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_enable.4081933187 Feb 08 06:11:15 PM UTC 25 Feb 08 06:11:17 PM UTC 25 57315201 ps
T1926 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_disconnected.3756184929 Feb 08 06:11:15 PM UTC 25 Feb 08 06:11:17 PM UTC 25 138027117 ps
T1927 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_aon_wake_reset.4245670492 Feb 08 06:10:52 PM UTC 25 Feb 08 06:11:17 PM UTC 25 19688040397 ps
T378 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_endpoint_types.1407398724 Feb 08 06:11:15 PM UTC 25 Feb 08 06:11:18 PM UTC 25 424414168 ps
T1928 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_low_speed_traffic.4139283755 Feb 08 06:10:19 PM UTC 25 Feb 08 06:11:18 PM UTC 25 5466481561 ps
T1929 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_disable_endpoint.1836687063 Feb 08 06:11:15 PM UTC 25 Feb 08 06:11:18 PM UTC 25 633095968 ps
T1930 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_pkt_buffer.598306382 Feb 08 06:10:47 PM UTC 25 Feb 08 06:11:18 PM UTC 25 11132431472 ps
T1931 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_endpoint_access.433363677 Feb 08 06:11:15 PM UTC 25 Feb 08 06:11:19 PM UTC 25 752799140 ps
T1932 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_in_trans.3001732821 Feb 08 06:11:17 PM UTC 25 Feb 08 06:11:19 PM UTC 25 183523383 ps
T1933 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_aon_wake_resume.2074763313 Feb 08 06:10:31 PM UTC 25 Feb 08 06:11:19 PM UTC 25 26156911676 ps
T1934 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_in_iso.2199122320 Feb 08 06:11:17 PM UTC 25 Feb 08 06:11:19 PM UTC 25 228486727 ps
T1935 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_in_stall.2313494304 Feb 08 06:11:17 PM UTC 25 Feb 08 06:11:19 PM UTC 25 232131532 ps
T1936 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_fifo_rst.3095355857 Feb 08 06:11:17 PM UTC 25 Feb 08 06:11:20 PM UTC 25 259956739 ps
T1937 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_link_in_err.440880559 Feb 08 06:11:18 PM UTC 25 Feb 08 06:11:21 PM UTC 25 212973785 ps
T1938 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_aon_wake_disconnect.2014638528 Feb 08 06:11:10 PM UTC 25 Feb 08 06:11:21 PM UTC 25 5964157246 ps
T1939 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_max_length_out_transaction.3994777466 Feb 08 06:11:19 PM UTC 25 Feb 08 06:11:21 PM UTC 25 186884699 ps
T1940 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_max_length_in_transaction.305319752 Feb 08 06:11:19 PM UTC 25 Feb 08 06:11:22 PM UTC 25 240231205 ps
T1941 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_max_inter_pkt_delay.13331593 Feb 08 06:09:32 PM UTC 25 Feb 08 06:11:23 PM UTC 25 3573369959 ps
T1942 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_min_length_out_transaction.1632435003 Feb 08 06:11:21 PM UTC 25 Feb 08 06:11:23 PM UTC 25 160529706 ps
T1943 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_min_length_in_transaction.2716658242 Feb 08 06:11:21 PM UTC 25 Feb 08 06:11:23 PM UTC 25 163781242 ps
T1944 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_nak_trans.973842465 Feb 08 06:11:21 PM UTC 25 Feb 08 06:11:23 PM UTC 25 180333068 ps
T1945 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_out_iso.199746150 Feb 08 06:11:21 PM UTC 25 Feb 08 06:11:23 PM UTC 25 185247414 ps
T1946 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_out_trans_nak.2574394061 Feb 08 06:11:21 PM UTC 25 Feb 08 06:11:23 PM UTC 25 156101594 ps
T1947 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_out_stall.2023915491 Feb 08 06:11:21 PM UTC 25 Feb 08 06:11:23 PM UTC 25 204558262 ps
T1948 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_pending_in_trans.1870352700 Feb 08 06:11:21 PM UTC 25 Feb 08 06:11:24 PM UTC 25 210460407 ps
T1949 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_phy_pins_sense.2639489134 Feb 08 06:11:22 PM UTC 25 Feb 08 06:11:24 PM UTC 25 37340100 ps
T1950 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_phy_config_usb_ref_disable.3892865319 Feb 08 06:11:22 PM UTC 25 Feb 08 06:11:25 PM UTC 25 135906334 ps
T1951 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_phy_config_pinflip.1489333361 Feb 08 06:11:22 PM UTC 25 Feb 08 06:11:25 PM UTC 25 198861626 ps
T1952 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_pkt_received.2209785092 Feb 08 06:11:23 PM UTC 25 Feb 08 06:11:26 PM UTC 25 211197544 ps
T1953 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_random_length_out_transaction.2705328524 Feb 08 06:11:23 PM UTC 25 Feb 08 06:11:26 PM UTC 25 199799954 ps
T1954 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_invalid_sync.1469154732 Feb 08 06:10:14 PM UTC 25 Feb 08 06:11:26 PM UTC 25 2538345843 ps
T1955 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_random_length_in_transaction.2922505523 Feb 08 06:11:23 PM UTC 25 Feb 08 06:11:26 PM UTC 25 182242626 ps
T1956 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_pkt_sent.2508769862 Feb 08 06:11:23 PM UTC 25 Feb 08 06:11:26 PM UTC 25 208581430 ps
T1957 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_setup_trans_ignored.2094191775 Feb 08 06:11:25 PM UTC 25 Feb 08 06:11:27 PM UTC 25 168758463 ps
T1958 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_smoke.2528772504 Feb 08 06:11:25 PM UTC 25 Feb 08 06:11:28 PM UTC 25 233947042 ps
T1959 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_rx_crc_err.3473496023 Feb 08 06:11:25 PM UTC 25 Feb 08 06:11:28 PM UTC 25 160417757 ps